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soc/intel/xeon_sp: Use <spd.h>

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Change-Id: Ib86df42c74474ab6d0bd389073c36ca0761748af
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This commit is contained in:
Elyes Haouas 2024-05-12 11:30:35 +02:00
parent 27becf5da6
commit c2837e70b9
2 changed files with 2 additions and 2 deletions
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1
src/soc/intel/xeon_sp/include/soc/ddr.h
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@ -9,7 +9,6 @@
* currently DDR4 only supports 1.2V, DDR5 only supports 1.1V. */ * currently DDR4 only supports 1.2V, DDR5 only supports 1.1V. */
#define SPD_VDD_DDR4 3 #define SPD_VDD_DDR4 3
#define SPD_VDD_DDR5 0 #define SPD_VDD_DDR5 0
#define SPD_TYPE_DDR5 0x12
/* DDR_*_TCK_MIN are in picoseconds */ /* DDR_*_TCK_MIN are in picoseconds */
#define DDR_800_TCK_MIN 2500 #define DDR_800_TCK_MIN 2500

3
src/soc/intel/xeon_sp/spr/romstage.c
View File

@ -13,6 +13,7 @@
#include <fsp/util.h> #include <fsp/util.h>
#include <hob_iiouds.h> #include <hob_iiouds.h>
#include <hob_memmap.h> #include <hob_memmap.h>
#include <spd.h>
#include <soc/chip_common.h> #include <soc/chip_common.h>
#include <soc/romstage.h> #include <soc/romstage.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
@ -330,7 +331,7 @@ void save_dimm_info(void)
dest_dimm->soc_num = soc; dest_dimm->soc_num = soc;
if (hob->DramType == SPD_TYPE_DDR5) { if (hob->DramType == SPD_MEMORY_TYPE_DDR5_SDRAM) {
/* hard-coded memory device type as DDR5 */ /* hard-coded memory device type as DDR5 */
mem_dev_type = 0x22; mem_dev_type = 0x22;
data_width = 64; data_width = 64;