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mb/google/octopus: Enable TPM on GSPI

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BUG=b:73133848
BRANCH=None
TEST=Build coreboot for Octopus board. Tested the GSPI interface
with a SPI EEPROM and got correct response to a RDID command

Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/24907
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ravi Sarawadi
2018-02-27 13:57:01 -08:00
committed by Martin Roth
parent 794d097072
commit c293496f41
3 changed files with 43 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/mainboard/google/octopus/Kconfig
View File

@@ -14,7 +14,10 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS
select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_TPM2
select MAINBOARD_HAS_SPI_TPM_CR50
select SOC_ESPI
select SPI_TPM
select TPM2
if BOARD_GOOGLE_BASEBOARD_OCTOPUS
@@ -71,4 +74,11 @@ config INCLUDE_NHLT_BLOBS
select NHLT_DA7219
select NHLT_MAX98357
config DRIVER_TPM_SPI_BUS
default 0x1
config TPM_TIS_ACPI_INTERRUPT
int
default 63 # GPE0_DW1_31 (GPIO_63)
endif # BOARD_GOOGLE_OCTOPUS

16
src/mainboard/google/octopus/variants/baseboard/devicetree.cb
View File

@@ -97,6 +97,13 @@ chip soc/intel/apollolake
.fall_time_ns = 164,
}"
# Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
# communication before memory is up.
register "gspi[0]" = "{
.speed_mhz = 1,
.early_init = 1,
}"
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF
@@ -190,7 +197,14 @@ chip soc/intel/apollolake
device pci 18.1 off end # - UART 1
device pci 18.2 on end # - UART 2
device pci 18.3 off end # - UART 3
device pci 19.0 on end # - SPI 0
device pci 19.0 on
chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cr50""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_63_IRQ)"
device spi 0 on end
end
end # - GSPI 0
device pci 19.1 off end # - SPI 1
device pci 19.2 on end # - SPI 2
device pci 1a.0 on end # - PWM

25
src/mainboard/google/octopus/variants/baseboard/gpio.c
View File

@@ -82,12 +82,12 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_55, 0, DEEP, NONE, HIZCRx0, ENPU), /* LPSS_I2C2_SCL */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C3_SDA */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C2_SCL */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_58, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C4_SDA */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_59, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C4_SCL */
PAD_CFG_GPIO_HI_Z(GPIO_58, NONE, DEEP, HIZCRx0, DISPUPD), /* LPSS_I2C4_SDA - unused */
PAD_CFG_GPIO_HI_Z(GPIO_59, NONE, DEEP, HIZCRx0, DISPUPD), /* LPSS_I2C4_SCL - unused */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */
PAD_CFG_GPI_APIC_IOS(GPIO_62, UP_20K, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* UART0-RTS_B */
PAD_CFG_GPI_APIC_IOS(GPIO_63, UP_20K, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* UART0-CTS_B */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* UART2-RTS_B */
@@ -113,11 +113,11 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPIO_HI_Z(GPIO_78, NONE, DEEP, HIZCRx0, DISPUPD),/* SVID Clk - unused */
/* LPSS */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_79, NONE, DEEP, NF1, HIZCRx0, ENPD), /* LPSS_SPI_0_CLK */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_80, NONE, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_SPI_0_FS0 */
PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */
PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L_R */
PAD_CFG_GPIO_HI_Z(GPIO_81, UP_20K, DEEP, HIZCRx0, DISPUPD), /* GPIO_81_DEBUG (Boot halt) -- MIPI60 DEBUG */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_82, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* LPSS_SPI_0_RXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_83, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* LPSS_SPI_0_TXD */
PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */
PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_84, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* LPSS_SPI_2_CLK */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_85, DN_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_SPI_2_FS0 */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_86, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* stest_CNTRL -- stest */
@@ -264,6 +264,17 @@ const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num)
/* GPIOs needed prior to ramstage. */
static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */
/* GSPI0_INT */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE,
DISPUPD), /* H1_PCH_INT_ODL */
/* GSPI0_CLK */
PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */
/* GSPI0_CS# */
PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L_R */
/* GSPI0_MISO */
PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */
/* GSPI0_MOSI */
PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */
};
const struct pad_config *__attribute__((weak))