sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/sb/cpu: Drop Intel Rangeley support

Browse Source 
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: I41589118579988617677cf48af5401bc35b23e05
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This commit is contained in:
Arthur Heymans
2019-11-19 18:37:28 +01:00
committed by Kyösti Mälkki
parent 298619f6d9
commit c2c634a089
68 changed files with 2 additions and 9280 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/cpu/intel/Makefile.inc
View File

@ -13,7 +13,6 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx
subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775

63
src/cpu/intel/fsp_model_406dx/Kconfig
View File

@ -1,63 +0,0 @@
##
## This file is part of the coreboot project.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config CPU_INTEL_FSP_MODEL_406DX
bool
if CPU_INTEL_FSP_MODEL_406DX
config CPU_SPECIFIC_OPTIONS
def_bool y
select PLATFORM_USES_FSP1_0
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select MMX
select SSE2
select UDELAY_TSC
select SUPPORT_CPU_UCODE_IN_CBFS
select MICROCODE_BLOB_NOT_IN_BLOB_REPO
select PARALLEL_CPU_INIT
select TSC_SYNC_MFENCE
select TSC_MONOTONIC_TIMER
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select NO_SMM
# Microcode header files are delivered in FSP package
select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN
choice
prompt "Rangeley CPU Stepping"
default FSP_MODEL_406DX_B0
config FSP_MODEL_406DX_A1
bool "A1"
config FSP_MODEL_406DX_B0
bool "B0"
endchoice
config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/fsp_model_406dx/bootblock.c"
#set up microcode for rangeley POSTGOLD4 release
config CPU_MICROCODE_HEADER_FILES
string
default "../intel/cpu/rangeley/microcode/microcode-m01406d000e.h ../intel/cpu/rangeley/microcode/microcode-m01406d8128.h"
endif #CPU_INTEL_FSP_MODEL_406DX

27
src/cpu/intel/fsp_model_406dx/Makefile.inc
View File

@ -1,27 +0,0 @@
#
# This file is part of the coreboot project.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
ramstage-y += model_406dx_init.c
subdirs-y += ../../x86/name
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../turbo
ramstage-y += acpi.c
CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx

321
src/cpu/intel/fsp_model_406dx/acpi.c
View File

@ -1,321 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <types.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/turbo.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include "model_406dx.h"
#include "chip.h"
static int get_cores_per_package(void)
{
struct cpuinfo_x86 c;
struct cpuid_result result;
int cores = 1;
get_fms(&c, cpuid_eax(1));
if (c.x86 != 6)
return 1;
result = cpuid_ext(0xb, 1);
cores = result.ebx & 0xff;
return cores;
}
static void generate_C_state_entries(void)
{
struct cpu_info *info;
struct cpu_driver *cpu;
struct device *lapic;
struct cpu_intel_model_406dx_config *conf = NULL;
/* Find the SpeedStep CPU in the device tree using magic APIC ID */
lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
if (!lapic)
return;
conf = lapic->chip_info;
if (!conf)
return;
/* Find CPU map of supported C-states */
info = cpu_info();
if (!info)
return;
cpu = find_cpu_driver(info->cpu);
if (!cpu || !cpu->cstates)
return;
acpigen_emit_byte(0x14); /* MethodOp */
acpigen_write_len_f(); /* PkgLength */
acpigen_emit_namestring("_CST");
acpigen_emit_byte(0x00); /* No Arguments */
/* If running on AC power */
acpigen_emit_byte(0xa0); /* IfOp */
acpigen_write_len_f(); /* PkgLength */
acpigen_emit_namestring("PWRS");
acpigen_emit_byte(0xa4); /* ReturnOp */
acpigen_pop_len();
/* Else on battery power */
acpigen_emit_byte(0xa4); /* ReturnOp */
acpigen_pop_len();
}
static acpi_tstate_t tss_table_fine[] = {
{ 100, 1000, 0, 0x00, 0 },
{ 94, 940, 0, 0x1f, 0 },
{ 88, 880, 0, 0x1e, 0 },
{ 82, 820, 0, 0x1d, 0 },
{ 75, 760, 0, 0x1c, 0 },
{ 69, 700, 0, 0x1b, 0 },
{ 63, 640, 0, 0x1a, 0 },
{ 57, 580, 0, 0x19, 0 },
{ 50, 520, 0, 0x18, 0 },
{ 44, 460, 0, 0x17, 0 },
{ 38, 400, 0, 0x16, 0 },
{ 32, 340, 0, 0x15, 0 },
{ 25, 280, 0, 0x14, 0 },
{ 19, 220, 0, 0x13, 0 },
{ 13, 160, 0, 0x12, 0 },
};
static acpi_tstate_t tss_table_coarse[] = {
{ 100, 1000, 0, 0x00, 0 },
{ 88, 875, 0, 0x1f, 0 },
{ 75, 750, 0, 0x1e, 0 },
{ 63, 625, 0, 0x1d, 0 },
{ 50, 500, 0, 0x1c, 0 },
{ 38, 375, 0, 0x1b, 0 },
{ 25, 250, 0, 0x1a, 0 },
{ 13, 125, 0, 0x19, 0 },
};
static void generate_T_state_entries(int core, int cores_per_package)
{
/* Indicate SW_ALL coordination for T-states */
acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
/* Indicate FFixedHW so OS will use MSR */
acpigen_write_empty_PTC();
/* Set a T-state limit that can be modified in NVS */
acpigen_write_TPC("\\TLVL");
/*
* CPUID.(EAX=6):EAX[5] indicates support
* for extended throttle levels.
*/
if (cpuid_eax(6) & (1 << 5))
acpigen_write_TSS_package(
ARRAY_SIZE(tss_table_fine), tss_table_fine);
else
acpigen_write_TSS_package(
ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
}
static int calculate_power(int tdp, int p1_ratio, int ratio)
{
u32 m;
u32 power;
/*
* M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
*
* Power = (ratio / p1_ratio) * m * tdp
*/
m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
m = (m * m) / 1000;
power = ((ratio * 100000 / p1_ratio) / 100);
power *= (m / 100) * (tdp / 1000);
power /= 1000;
return (int)power;
}
static int get_core_frequency_mhz(int ratio)
{
int fsb, core_freq;
/* Get BCLK - different SKUs can have different BCLK */
fsb = get_timer_fsb();
printk(BIOS_DEBUG, "BCLK:%d MHz ratio:%d\n", fsb, ratio);
core_freq = DIV_ROUND_CLOSEST(fsb * ratio, 100) * 100;
printk(BIOS_DEBUG, "core frequency for ratio(%d) %dMHz\n", ratio, core_freq);
return core_freq;
}
static void generate_P_state_entries(int core, int cores_per_package)
{
int ratio_min, ratio_max, ratio_turbo, ratio_step;
int coord_type, power_max, num_entries;
int ratio, power, clock, clock_max;
msr_t msr;
/* Rangeley uses hardware only control */
coord_type = HW_ALL;
/* Get bus ratio limits and calculate clock speeds */
msr = rdmsr(MSR_PLATFORM_INFO);
ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
/* Determine if this CPU has configurable TDP */
if (cpu_config_tdp_levels()) {
/* Set max ratio to nominal TDP ratio */
msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
ratio_max = msr.lo & 0xff;
} else {
/* Max Non-Turbo Ratio */
ratio_max = (msr.lo >> 8) & 0xff;
}
clock_max = get_core_frequency_mhz(ratio_max);
/* Calculate CPU TDP in mW */
msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
power_max = 2 << ((msr.lo & 0xf) - 1);
/* Write _PCT indicating use of FFixedHW */
acpigen_write_empty_PCT();
/* Write _PPC with no limit on supported P-state */
acpigen_write_PPC_NVS();
/* Write PSD indicating configured coordination type */
acpigen_write_PSD_package(core, cores_per_package, coord_type);
/* Add P-state entries in _PSS table */
acpigen_write_name("_PSS");
/* Determine ratio points */
ratio_step = PSS_RATIO_STEP;
num_entries = (ratio_max - ratio_min) / ratio_step;
while (num_entries > PSS_MAX_ENTRIES-1) {
ratio_step <<= 1;
num_entries >>= 1;
}
/* P[T] is Turbo state if enabled */
if (get_turbo_state() == TURBO_ENABLED) {
/* _PSS package count including Turbo */
acpigen_write_package(num_entries + 2);
msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
ratio_turbo = msr.lo & 0xff;
/* Add entry for Turbo ratio */
acpigen_write_PSS_package(
clock_max + 1, /*MHz*/
power_max, /*mW*/
PSS_LATENCY_TRANSITION, /*lat1*/
PSS_LATENCY_BUSMASTER, /*lat2*/
ratio_turbo << 8, /*control*/
ratio_turbo << 8); /*status*/
} else {
/* _PSS package count without Turbo */
acpigen_write_package(num_entries + 1);
}
/* First regular entry is max non-turbo ratio */
acpigen_write_PSS_package(
clock_max, /*MHz*/
power_max, /*mW*/
PSS_LATENCY_TRANSITION, /*lat1*/
PSS_LATENCY_BUSMASTER, /*lat2*/
ratio_max << 8, /*control*/
ratio_max << 8); /*status*/
/* Generate the remaining entries */
for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
ratio >= ratio_min; ratio -= ratio_step) {
/* Calculate power at this ratio */
power = calculate_power(power_max, ratio_max, ratio);
clock = get_core_frequency_mhz(ratio);
acpigen_write_PSS_package(
clock, /*MHz*/
power, /*mW*/
PSS_LATENCY_TRANSITION, /*lat1*/
PSS_LATENCY_BUSMASTER, /*lat2*/
ratio << 8, /*control*/
ratio << 8); /*status*/
}
/* Fix package length */
acpigen_pop_len();
}
void generate_cpu_entries(struct device *device)
{
int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
int totalcores = dev_count_cpu();
int cores_per_package = get_cores_per_package();
int numcpus = totalcores/cores_per_package;
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
numcpus, cores_per_package);
for (cpuID = 1; cpuID <= numcpus; cpuID++) {
for (coreID = 1; coreID <= cores_per_package; coreID++) {
if (coreID > 1) {
pcontrol_blk = 0;
plen = 0;
}
/* Generate processor \_PR.CPUx */
acpigen_write_processor(
(cpuID-1)*cores_per_package+coreID-1,
pcontrol_blk, plen);
/* Generate P-state tables */
generate_P_state_entries(
cpuID-1, cores_per_package);
/* Generate C-state tables */
generate_C_state_entries();
/* Generate T-state tables */
generate_T_state_entries(
cpuID-1, cores_per_package);
acpigen_pop_len();
}
}
/* PPKG is usually used for thermal management
of the first and only package. */
acpigen_write_processor_package("PPKG", 0, cores_per_package);
/* Add a method to notify processor nodes */
acpigen_write_processor_cnot(cores_per_package);
}
struct chip_operations cpu_intel_model_406dx_ops = {
CHIP_NAME("Intel Rangeley CPU")
};

89
src/cpu/intel/fsp_model_406dx/bootblock.c
View File

@ -1,89 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <cpu/x86/cache.h>
#include <cpu/intel/microcode/microcode.c>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <southbridge/intel/fsp_rangeley/soc.h>
#include "model_406dx.h"
/*
* check for a warm reset and do a hard reset instead.
*/
static void check_for_warm_reset(void)
{
/*
* Check if INIT# is asserted by port 0xCF9 and whether RCBA has been
* set. If either is true, then this is a warm reset so execute a
* Hard Reset
*/
if ((inb(0xcf9) == 0x04) ||
(pci_io_read_config32(SOC_LPC_DEV, RCBA)
& RCBA_ENABLE)) {
outb(0x00, 0xcf9);
outb(0x06, 0xcf9);
}
}
static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type)
{
/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
msr_t basem, maskm;
basem.lo = base | type;
basem.hi = 0;
wrmsr(MTRR_PHYS_BASE(reg), basem);
maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
wrmsr(MTRR_PHYS_MASK(reg), maskm);
}
static void enable_rom_caching(void)
{
msr_t msr;
disable_cache();
set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
enable_cache();
/* Enable Variable MTRRs */
msr.hi = 0x00000000;
msr.lo = 0x00000800;
wrmsr(MTRR_DEF_TYPE_MSR, msr);
}
static void set_no_evict_mode_msr(void)
{
msr_t msr;
msr.hi = 0x00000000;
msr.lo = 0x00000000;
wrmsr(MSR_NO_EVICT_MODE, msr);
}
static void bootblock_cpu_init(void)
{
/* Check for Warm Reset */
check_for_warm_reset();
/* Load microcode before any caching. */
intel_update_microcode_from_cbfs();
enable_rom_caching();
set_no_evict_mode_msr();
}

30
src/cpu/intel/fsp_model_406dx/chip.h
View File

@ -1,30 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef CPU_FSP_MODEL406DX_CHIP_H
#define CPU_FSP_MODEL406DX_CHIP_H
/* Magic value used to locate this chip in the device tree */
#define SPEEDSTEP_APIC_MAGIC 0xACAC
struct cpu_intel_fsp_model_406dx_config {
int c1_battery; /* ACPI C1 on Battery Power */
int c2_battery; /* ACPI C2 on Battery Power */
int c3_battery; /* ACPI C3 on Battery Power */
int c1_acpower; /* ACPI C1 on AC Power */
int c2_acpower; /* ACPI C2 on AC Power */
int c3_acpower; /* ACPI C3 on AC Power */
};
#endif /* CPU_FSP_MODEL406DX_CHIP_H */

87
src/cpu/intel/fsp_model_406dx/model_406dx.h
View File

@ -1,87 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _CPU_INTEL_MODEL_406DX_H
#define _CPU_INTEL_MODEL_406DX_H
#define MSR_FEATURE_CONFIG 0x13c
#define MSR_FLEX_RATIO 0x194
#define FLEX_RATIO_LOCK (1 << 20)
#define FLEX_RATIO_EN (1 << 16)
#define MSR_TEMPERATURE_TARGET 0x1a2
#define MSR_LT_LOCK_MEMORY 0x2e7
#define MSR_NO_EVICT_MODE 0x2e0
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
#define PLATFORM_INFO_SET_TDP (1 << 29)
#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
#define MSR_PMG_IO_CAPTURE_BASE 0xe4
#define MSR_MISC_PWR_MGMT 0x1aa
#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
#define MSR_TURBO_RATIO_LIMIT 0x1ad
#define MSR_POWER_CTL 0x1fc
#define MSR_PKGC3_IRTL 0x60a
#define MSR_PKGC6_IRTL 0x60b
#define MSR_PKGC7_IRTL 0x60c
#define IRTL_VALID (1 << 15)
#define IRTL_1_NS (0 << 10)
#define IRTL_32_NS (1 << 10)
#define IRTL_1024_NS (2 << 10)
#define IRTL_32768_NS (3 << 10)
#define IRTL_1048576_NS (4 << 10)
#define IRTL_33554432_NS (5 << 10)
#define IRTL_RESPONSE_MASK (0x3ff)
/* long duration in low dword, short duration in high dword */
#define MSR_PKG_POWER_LIMIT 0x610
#define PKG_POWER_LIMIT_MASK 0x7fff
#define PKG_POWER_LIMIT_EN (1 << 15)
#define PKG_POWER_LIMIT_CLAMP (1 << 16)
#define PKG_POWER_LIMIT_TIME_SHIFT 17
#define PKG_POWER_LIMIT_TIME_MASK 0x7f
#define MSR_PP0_CURRENT_CONFIG 0x601
#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */
#define MSR_PP1_CURRENT_CONFIG 0x602
#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */
#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */
#define MSR_PKG_POWER_SKU_UNIT 0x606
#define MSR_PKG_POWER_SKU 0x614
#define MSR_PP0_POWER_LIMIT 0x638
#define MSR_PP1_POWER_LIMIT 0x640
#define IVB_CONFIG_TDP_MIN_CPUID 0x306a2
#define MSR_CONFIG_TDP_NOMINAL 0x648
#define MSR_CONFIG_TDP_LEVEL1 0x649
#define MSR_CONFIG_TDP_LEVEL2 0x64a
#define MSR_CONFIG_TDP_CONTROL 0x64b
#define MSR_TURBO_ACTIVATION_RATIO 0x64c
/* P-state configuration */
#define PSS_MAX_ENTRIES 8
#define PSS_RATIO_STEP 2
#define PSS_LATENCY_TRANSITION 10
#define PSS_LATENCY_BUSMASTER 10
#ifndef __ROMCC__
/* Lock MSRs */
void intel_model_406dx_finalize_smm(void);
int cpu_config_tdp_levels(void);
#endif
#endif /* _CPU_INTEL_MODEL_406DX_H */

169
src/cpu/intel/fsp_model_406dx/model_406dx_init.c
View File

@ -1,169 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/pci.h>
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <cpu/intel/common/common.h>
#include "model_406dx.h"
#include "chip.h"
int cpu_config_tdp_levels(void)
{
msr_t platform_info;
/* Minimum CPU revision */
if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
return 0;
/* Bits 34:33 indicate how many levels supported */
platform_info = rdmsr(MSR_PLATFORM_INFO);
return (platform_info.hi >> 1) & 3;
}
static void configure_misc(void)
{
msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */
msr.lo = 0;
msr.hi = 0;
wrmsr(IA32_THERM_INTERRUPT, msr);
}
static void configure_mca(void)
{
msr_t msr;
int i;
msr.lo = msr.hi = 0;
/* This should only be done on a cold boot */
for (i = 0; i < 6; i++)
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
}
/*
* Initialize any extra cores/threads in this package.
*/
static void intel_cores_init(struct device *cpu)
{
struct cpuid_result result;
unsigned int threads_per_package, threads_per_core, i;
/* Logical processors (threads) per core */
result = cpuid_ext(0xb, 0);
threads_per_core = result.ebx & 0xffff;
/* Logical processors (threads) per package */
result = cpuid_ext(0xb, 1);
threads_per_package = result.ebx & 0xffff;
/* Only initialize extra cores from BSP */
if (cpu->path.apic.apic_id)
return;
printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n",
cpu->path.apic.apic_id, threads_per_package/threads_per_core,
threads_per_core);
for (i = 1; i < threads_per_package; ++i) {
struct device_path cpu_path;
struct device *new;
/* Build the CPU device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id =
cpu->path.apic.apic_id + i;
/* Update APIC ID if no hyperthreading */
if (threads_per_core == 1)
cpu_path.apic.apic_id <<= 1;
/* Allocate the new CPU device structure */
new = alloc_dev(cpu->bus, &cpu_path);
if (!new)
continue;
printk(BIOS_DEBUG, "CPU: %u has core %u\n",
cpu->path.apic.apic_id,
new->path.apic.apic_id);
/* Start the new CPU */
if (is_smp_boot() && !start_cpu(new)) {
/* Record the error in cpu? */
printk(BIOS_ERR, "CPU %u would not start!\n",
new->path.apic.apic_id);
}
}
}
static void model_406dx_init(struct device *cpu)
{
char processor_name[49];
/* Turn on caching if we haven't already */
x86_enable_cache();
/* Load microcode */
if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS))
intel_update_microcode_from_cbfs();
/* Clear out pending MCEs */
configure_mca();
/* Print processor name */
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
x86_mtrr_check();
/* Enable the local CPU APICs */
setup_lapic();
/* Set virtualization based on Kconfig option */
set_vmx_and_lock();
/* Configure Enhanced SpeedStep and Thermal Sensors */
configure_misc();
/* Start up extra cores */
intel_cores_init(cpu);
}
static struct device_operations cpu_dev_ops = {
.init = model_406dx_init,
};
static const struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_INTEL, 0x406d0 }, /* Intel Avoton/Rangeley A1 */
{ X86_VENDOR_INTEL, 0x406d8 }, /* Intel Avoton/Rangeley B0 */
{ 0, 0 },
};
static const struct cpu_driver driver __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
};

2
src/include/device/pci_ids.h
View File

@ -2583,8 +2583,6 @@
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f
#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41
#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f
#define PCI_DEVICE_ID_INTEL_RANGELEY_LPC_MIN 0x1f38
#define PCI_DEVICE_ID_INTEL_RANGELEY_LPC_MAX 0x1f3b
#define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc #define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc
/* Intel 82801E (C-ICH) */ /* Intel 82801E (C-ICH) */

88
src/northbridge/intel/fsp_rangeley/Kconfig
View File

@ -1,88 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Google Inc.
## Copyright (C) 2013 Sage Electronic Engineering, LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config NORTHBRIDGE_INTEL_FSP_RANGELEY
bool
select CPU_INTEL_FSP_MODEL_406DX
if NORTHBRIDGE_INTEL_FSP_RANGELEY
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
choice
prompt "Set TSEG Size"
default SET_TSEG_1MB if SET_DEFAULT_TSEG_1MB
default SET_TSEG_2MB if SET_DEFAULT_TSEG_2MB
default SET_TSEG_4MB if SET_DEFAULT_TSEG_4MB
default SET_TSEG_8MB if SET_DEFAULT_TSEG_8MB
config SET_TSEG_1MB
bool "1 MB"
help
Set the TSEG area to 1 MB.
config SET_TSEG_2MB
bool "2 MB"
help
Set the TSEG area to 2 MB.
config SET_TSEG_4MB
bool "4 MB"
help
Set the TSEG area to 4 MB.
config SET_TSEG_8MB
bool "8 MB"
help
Set the TSEG area to 8 MB.
endchoice
config SMM_TSEG_SIZE
hex
default 0x200000 if SET_TSEG_2MB
default 0x400000 if SET_TSEG_4MB
default 0x800000 if SET_TSEG_8MB
default 0x100000 # SET_TSEG_1MB
config SMM_RESERVED_SIZE
hex
default 0x200000 if SET_TSEG_2MB
default 0x400000 if SET_TSEG_4MB
default 0x800000 if SET_TSEG_8MB
default 0x100000 # SET_TSEG_1MB
config SET_DEFAULT_TSEG_1MB
bool
default n
config SET_DEFAULT_TSEG_2MB
bool
default n
config SET_DEFAULT_TSEG_4MB
bool
default n
config SET_DEFAULT_TSEG_8MB
bool
default n
# Rangeley Specific FSP Kconfig
source src/northbridge/intel/fsp_rangeley/fsp/Kconfig
endif # NORTHBRIDGE_INTEL_FSP_RANGELEY

34
src/northbridge/intel/fsp_rangeley/Makefile.inc
View File

@ -1,34 +0,0 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2010 Google Inc.
# Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY),y)
subdirs-y += fsp
ramstage-y += northbridge.c
ramstage-y += acpi.c
ramstage-y += port_access.c
romstage-y += memmap.c
romstage-y += ../../../arch/x86/walkcbfs.S
romstage-y += port_access.c
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)
CPPFLAGS_common += -I$(src)/northbridge/intel/fsp_rangeley/
CPPFLAGS_common += -I$(src)/northbridge/intel/fsp_rangeley/fsp
endif

71
src/northbridge/intel/fsp_rangeley/acpi.c
View File

@ -1,71 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2012 The Chromium OS Authors
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <types.h>
#include <arch/acpi.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <arch/acpigen.h>
#include "northbridge.h"
unsigned long acpi_fill_mcfg(unsigned long current)
{
struct device *dev;
u32 pciexbar = 0;
u32 pciexbar_reg;
int max_buses;
int pci_dev_id;
for (pci_dev_id = PCI_DEVICE_ID_RG_MIN; pci_dev_id <= PCI_DEVICE_ID_RG_MAX; pci_dev_id++) {
dev = dev_find_device(PCI_VENDOR_ID_INTEL, pci_dev_id, 0);
if (dev)
break;
}
if (!dev)
return current;
pciexbar_reg = sideband_read(B_UNIT, BECREG);
/* MMCFG not supported or not enabled. */
if (!(pciexbar_reg & (1 << 0)))
return current;
/* 256MB ECAM range */
pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
max_buses = 256;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
pciexbar, 0x0, 0x0, max_buses - 1);
return current;
}
void northbridge_acpi_fill_ssdt_generator(struct device *device)
{
u32 bmbound;
char pscope[] = "\\_SB.PCI0";
bmbound = sideband_read(B_UNIT, BMBOUND);
acpigen_write_scope(pscope);
acpigen_write_name_dword("BMBD", bmbound);
acpigen_pop_len();
generate_cpu_entries(device);
}

131
src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl
View File

@ -1,131 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Name(_HID,EISAID("PNP0A08")) // PCIe
Name(_CID,EISAID("PNP0A03")) // PCI
Name(_BBN, 0)
// This is in the SSDT and can be accessed by the DSDT
External (BMBD)
// Current Resource Settings
Name (MCRS, ResourceTemplate()
{
// Bus Numbers
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
// IO Region 0
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
// PCI Config Space
Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
// IO Region 1
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
// VGA memory (0xa0000-0xbffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
0x00020000,,, ASEG)
// OPROM reserved (0xd0000-0xd3fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
0x00004000,,, OPR0)
// OPROM reserved (0xd4000-0xd7fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
0x00004000,,, OPR1)
// OPROM reserved (0xd8000-0xdbfff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
0x00004000,,, OPR2)
// OPROM reserved (0xdc000-0xdffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
0x00004000,,, OPR3)
// BIOS Extension (0xe0000-0xe3fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
0x00004000,,, ESG0)
// BIOS Extension (0xe4000-0xe7fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
0x00004000,,, ESG1)
// BIOS Extension (0xe8000-0xebfff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
0x00004000,,, ESG2)
// BIOS Extension (0xec000-0xeffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000ec000, 0x000effff, 0x00000000,
0x00004000,,, ESG3)
// System BIOS (0xf0000-0xfffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0, 0x00000000,
0,,, PM01)
// TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
0x00005000,,, TPMR)
}) // End MCRS
Method (_CRS, 0, Serialized)
{
// Find PCI resource area in MCRS
CreateDwordField(MCRS, ^PM01._MIN, PMIN)
CreateDwordField(MCRS, ^PM01._MAX, PMAX)
CreateDwordField(MCRS, ^PM01._LEN, PLEN)
// Fix up PCI memory region
// Start with Top of Lower Usable DRAM
// Memory goes from BMBOUND to CONFIG_MMCONF_BASE_ADDRESS (PM01 above)
Store (BMBD, PMIN)
Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
Add(Subtract(PMAX, PMIN), 1, PLEN) // Store Memory Size
Return (MCRS)
} // End _CRS

36
src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl
View File

@ -1,36 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "../northbridge.h"
#include "hostbridge.asl"
/* PCI Device Resource Consumption */
Device (PDRC)
{
Name (_HID, EISAID("PNP0C02"))
Name (_UID, 1)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, DEFAULT_ECBASE, 0x10000000)
})
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
Return(PDRS)
}
}

69
src/northbridge/intel/fsp_rangeley/chip.h
View File

@ -1,69 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2015 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _FSP_RANGELEY_CHIP_H_
#define _FSP_RANGELEY_CHIP_H_
#include <arch/acpi.h>
#include <drivers/intel/fsp1_0/fsp_values.h>
struct northbridge_intel_fsp_rangeley_config {
/* Set the CPGC exp_loop_cnt field for RMT execution 2^(exp_loop_cnt -1) */
/* Valid values: 0 - 15 */
uint8_t MrcRmtCpgcExpLoopCntValue;
/* Set the CPGC num_bursts field for RMT execution 2^(num_bursts -1) */
/* Valid values: 0 - 15 */
uint8_t MrcRmtCpgcNumBursts;
/* DIMM SPD SMBus Addresses */
uint8_t SpdBaseAddress_0_0;
uint8_t SpdBaseAddress_0_1;
uint8_t SpdBaseAddress_1_0;
uint8_t SpdBaseAddress_1_1;
uint8_t EnableLan;
uint8_t EnableSata2;
uint8_t EnableSata3;
uint8_t EnableIQAT;
uint8_t EnableUsb20;
uint8_t PrintDebugMessages;
uint8_t Fastboot;
uint8_t EccSupport;
uint8_t SpdWriteProtect;
/* Enable = Memory Down, Disable = DIMM */
uint8_t MemoryDown;
/* Enable the Rank Margin Tool, needs PrintDebugMessages */
uint8_t MrcRmtSupport;
/* PCIe port bifurcation control */
uint8_t Bifurcation;
#define BIFURCATION_4_4_4_4 0
#define BIFURCATION_4_4_8 1
#define BIFURCATION_8_4_4 2
#define BIFURCATION_8_8 3
#define BIFURCATION_16 4
/* PCIe port de-emphasis control */
uint8_t PcdPcieRootPort1DeEmphasis;
uint8_t PcdPcieRootPort2DeEmphasis;
uint8_t PcdPcieRootPort3DeEmphasis;
uint8_t PcdPcieRootPort4DeEmphasis;
#define DE_EMPHASIS_DEFAULT 0
#define DE_EMPHASIS_MINUS_6_0_DB 1
#define DE_EMPHASIS_MINUS_3_5_DB 2
};
#endif

45
src/northbridge/intel/fsp_rangeley/fsp/Kconfig
View File

@ -1,45 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 Sage Electronic Engineering, LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config RANGELEY_FSP_SPECIFIC_OPTIONS
def_bool y
select PLATFORM_USES_FSP1_0
select USE_GENERIC_FSP_CAR_INC
select FSP_USES_UPD
select ENABLE_MRC_CACHE #rangeley FSP always needs MRC data
config FSP_FILE
string
default "../intel/fsp/rangeley/FvFsp.bin"
help
The path and filename of the Intel FSP binary for this platform.
config FSP_LOC
hex
default 0xfff80000
help
The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).
The Rangeley FSP is built with a preferred base address of 0xFFF80000
config DCACHE_RAM_BASE
hex
default 0xfef00000
config DCACHE_RAM_SIZE
hex
default 0x4000

17
src/northbridge/intel/fsp_rangeley/fsp/Makefile.inc
View File

@ -1,17 +0,0 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2014 Sage Electronic Engineering, LLC.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
ramstage-y += chipset_fsp_util.c
romstage-y += chipset_fsp_util.c

160
src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
View File

@ -1,160 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
* Copyright (C) 2015 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <types.h>
#include <string.h>
#include <console/console.h>
#include <bootstate.h>
#include <cbmem.h>
#include <device/device.h>
#include <southbridge/intel/fsp_rangeley/pci_devs.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <fspvpd.h>
#include <fspbootmode.h>
#include "../chip.h"
/* Copy the default UPD region and settings to a buffer for modification */
static void GetUpdDefaultFromFsp
(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData)
{
VPD_DATA_REGION *VpdDataRgnPtr;
UPD_DATA_REGION *UpdDataRgnPtr;
VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset
+ FspInfo->ImageBase);
UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)
(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase);
memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));
}
typedef struct northbridge_intel_fsp_rangeley_config config_t;
/**
* Update the UPD data based on values from devicetree.cb
*
* @param UpdData Pointer to the UPD Data structure
*/
static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
{
DEVTREE_CONST struct device *dev;
DEVTREE_CONST config_t *config;
printk(BIOS_DEBUG, "Configure Default UPD Data\n");
dev = pcidev_path_on_root(SOC_DEVFN_SOC);
config = dev->chip_info;
/* Set SPD addresses */
if (config->SpdBaseAddress_0_0) {
UpdData->PcdSpdBaseAddress_0_0 = config->SpdBaseAddress_0_0;
}
if (config->SpdBaseAddress_0_1) {
UpdData->PcdSpdBaseAddress_0_1 = config->SpdBaseAddress_0_1;
}
if (config->SpdBaseAddress_1_0) {
UpdData->PcdSpdBaseAddress_1_0 = config->SpdBaseAddress_1_0;
}
if (config->SpdBaseAddress_1_1) {
UpdData->PcdSpdBaseAddress_1_1 = config->SpdBaseAddress_1_1;
}
if (config->EccSupport) {
UpdData->PcdEccSupport = config->EccSupport;
}
if (config->PrintDebugMessages) {
UpdData->PcdPrintDebugMessages = config->PrintDebugMessages;
}
if (config->Bifurcation) {
UpdData->PcdBifurcation = config->Bifurcation;
}
if (config->MemoryDown) {
UpdData->PcdMemoryDown = config->MemoryDown;
}
UpdData->PcdMrcInitTsegSize = CONFIG_SMM_TSEG_SIZE >> 20;
if (config->MrcRmtCpgcExpLoopCntValue) {
UpdData->PcdMrcRmtCpgcExpLoopCntValue =
config->MrcRmtCpgcExpLoopCntValue;
}
if (config->MrcRmtCpgcNumBursts) {
UpdData->PcdMrcRmtCpgcNumBursts = config->MrcRmtCpgcNumBursts;
}
if (CONFIG(ENABLE_FSP_FAST_BOOT))
UpdData->PcdFastboot = UPD_ENABLE;
/*
* Loop through all the SOC devices in the devicetree
* enabling and disabling them as requested.
*/
for (; dev; dev = dev->sibling) {
if (dev->path.type != DEVICE_PATH_PCI)
continue;
switch (dev->path.pci.devfn) {
case SOC_DEVFN_GBE1:
case SOC_DEVFN_GBE2:
case SOC_DEVFN_GBE3:
case SOC_DEVFN_GBE4:
UpdData->PcdEnableLan |= dev->enabled;
printk(BIOS_DEBUG, "PcdEnableLan %d\n",
UpdData->PcdEnableLan);
break;
case SOC_DEVFN_SATA2:
UpdData->PcdEnableSata2 = dev->enabled;
printk(BIOS_DEBUG, "PcdEnableSata2 %d\n",
UpdData->PcdEnableSata2);
break;
case SOC_DEVFN_SATA3:
UpdData->PcdEnableSata3 = dev->enabled;
printk(BIOS_DEBUG, "PcdEnableSata3 %d\n",
UpdData->PcdEnableSata3);
break;
case SOC_DEVFN_IQAT:
UpdData->PcdEnableIQAT |= dev->enabled;
printk(BIOS_DEBUG, "PcdEnableIQAT %d\n",
UpdData->PcdEnableIQAT);
break;
case SOC_DEVFN_USB2:
UpdData->PcdEnableUsb20 = dev->enabled;
printk(BIOS_DEBUG, "PcdEnableUsb20 %d\n",
UpdData->PcdEnableUsb20);
break;
}
}
/* Set PCIe de-emphasis */
UPD_DEFAULT_CHECK(PcdPcieRootPort1DeEmphasis);
UPD_DEFAULT_CHECK(PcdPcieRootPort2DeEmphasis);
UPD_DEFAULT_CHECK(PcdPcieRootPort3DeEmphasis);
UPD_DEFAULT_CHECK(PcdPcieRootPort4DeEmphasis);
}
/* Set up the Rangeley specific structures for the call into the FSP */
void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
FSP_INFO_HEADER *fsp_ptr)
{
FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr;
/* Initialize the UPD Data */
GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr);
ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr);
pFspInitParams->NvsBufferPtr = NULL;
pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION;
/* Find the fastboot cache that was saved in the ROM */
pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache();
return;
}

48
src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h
View File

@ -1,48 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef CHIPSET_FSP_UTIL_H
#define CHIPSET_FSP_UTIL_H
#include <fsptypes.h>
#include <fspfv.h>
#include <fspffs.h>
#include <fspapi.h>
#include <fspplatform.h>
#include <fspinfoheader.h>
#include <fsphob.h>
#include <fspvpd.h>
#define FSP_RESERVE_MEMORY_SIZE 0x200000
#define FSP_INFO_HEADER_GUID \
{ \
0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \
}
#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \
{ \
0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0} \
}
/*
*The FSP Image ID is different for each platform's FSP and
* can be used to verify that the right FSP binary is loaded.
* For the Rangeley FSP, the Image Id is "AVN-FSP0".
*/
#define FSP_IMAGE_ID_DWORD0 0x2d4e5641 /* 'AVN-' */
#define FSP_IMAGE_ID_DWORD1 0x30505346 /* 'FSP0' */
#endif /* CHIPSET_FSP_UTIL_H */

42
src/northbridge/intel/fsp_rangeley/memmap.c
View File

@ -1,42 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cbmem.h>
#include <device/pci_def.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include "northbridge.h"
static uintptr_t smm_region_start(void)
{
/*
* Calculate the top of usable (low) DRAM.
* The FSP's reserved memory sits just below the SMM region,
* allowing calculation of the top of usable memory.
*/
uintptr_t tom = sideband_read(B_UNIT, BMBOUND);
uintptr_t bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20;
if (bsmmrrl) {
tom = bsmmrrl;
}
return tom;
}
void *cbmem_top_chipset(void)
{
return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE);
}

251
src/northbridge/intel/fsp_rangeley/northbridge.c
View File

@ -1,251 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <arch/acpi.h>
#include <device/pci_ops.h>
#include <stdint.h>
#include <cpu/intel/fsp_model_406dx/model_406dx.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <stdlib.h>
#include <cpu/cpu.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <cpu/x86/lapic.h>
#include "chip.h"
#include "northbridge.h"
static int bridge_revision_id = -1;
int bridge_silicon_revision(void)
{
if (bridge_revision_id < 0) {
uint8_t stepping = cpuid_eax(1) & 0xf;
uint8_t bridge_id = pci_read_config16(
pcidev_on_root(0, 0),
PCI_DEVICE_ID) & 0xf0;
bridge_revision_id = bridge_id | stepping;
}
return bridge_revision_id;
}
/* Reserve everything between A segment and 1MB:
*
* 0xa0000 - 0xbffff: legacy VGA
* 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
* 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
*/
static const int legacy_hole_base_k = 0xa0000 / 1024;
static const int legacy_hole_size_k = 384;
static int get_pcie_bar(u32 *base)
{
struct device *dev;
u32 pciexbar_reg;
*base = 0;
dev = pcidev_on_root(0, 0);
if (!dev)
return 0;
pciexbar_reg = sideband_read(B_UNIT, BECREG);
if (!(pciexbar_reg & (1 << 0)))
return 0;
*base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
(1 << 28));
return 256;
}
static void add_fixed_resources(struct device *dev, int index)
{
struct resource *resource;
resource = new_resource(dev, index++); /* Local APIC */
resource->base = LAPIC_DEFAULT_BASE;
resource->size = 0x00001000;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k);
}
static void mc_add_dram_resources(struct device *dev)
{
u32 tomlow, bmbound, bsmmrrl, bsmmrrh;
u64 bmbound_hi;
int index = 0;
/*
* These are the host memory ranges :
* - 0 -> SMM (SMMRRL) : cacheable
* - SMM -> LOW TOM (BMBOUND) : cacheable WP
* - 4GB -> HIGH TOM (BMBOUND_HI): cacheable
*
*/
tomlow = bmbound = sideband_read(B_UNIT, BMBOUND);
printk(BIOS_SPEW, "Top of Low Used DRAM (BMBOUND): 0x%08x\n", bmbound);
bmbound_hi = (u64)(sideband_read(B_UNIT, BMBOUND_HI)) << 4;
printk(BIOS_SPEW, "Top of Upper Used DRAM (BMBOUND_HI): 0x%llx\n", bmbound_hi);
bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20;
bsmmrrh = ((sideband_read(B_UNIT, BSMMRRH) + 1) << 20) - 1;
if (bsmmrrl) {
tomlow = bsmmrrl;
printk(BIOS_DEBUG, "SMM memory location: 0x%x SMM memory size: 0x%x\n", bsmmrrl, (bsmmrrh - bsmmrrl + 1));
printk(BIOS_DEBUG, "Subtracting %dM for SMM\n", (bmbound - bsmmrrl) >> 20);
}
tomlow -= FSP_RESERVE_MEMORY_SIZE;
printk(BIOS_SPEW, "Available memory below 4GB: 0x%08x (%dM)\n", tomlow, tomlow >> 20);
/* Report the memory regions. */
ram_resource(dev, index++, 0, legacy_hole_base_k);
ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k,
((tomlow >> 10) - (legacy_hole_base_k + legacy_hole_size_k)));
mmio_resource(dev, index++, tomlow >> 10, (bmbound - bsmmrrl) >> 10);
if (bmbound_hi > 0x100000000) {
ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10);
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (bmbound_hi - 0x100000000) >> 20);
}
add_fixed_resources(dev, index);
}
static void mc_read_resources(struct device *dev)
{
u32 pcie_config_base;
int buses;
/* Call the normal read_resources */
pci_dev_read_resources(dev);
/* We use 0xcf as an unused index for our PCIe bar so that we find it again */
buses = get_pcie_bar(&pcie_config_base);
if (buses) {
struct resource *resource = new_resource(dev, 0xcf);
mmconf_resource_init(resource, pcie_config_base, buses);
}
/* Calculate and add DRAM resources. */
mc_add_dram_resources(dev);
}
static void pci_domain_set_resources(struct device *dev)
{
/*
* Assign memory resources for PCI devices
*/
mc_add_dram_resources(dev);
assign_resources(dev->link_list);
}
static void mc_set_resources(struct device *dev)
{
/* Call the normal set_resources */
pci_dev_set_resources(dev);
}
static void northbridge_init(struct device *dev)
{
}
static void northbridge_enable(struct device *dev)
{
}
static struct pci_operations intel_pci_ops = {
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
};
static struct device_operations mc_ops = {
.read_resources = mc_read_resources,
.set_resources = mc_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
.acpi_fill_ssdt_generator = northbridge_acpi_fill_ssdt_generator,
.enable = northbridge_enable,
.scan_bus = 0,
.ops_pci = &intel_pci_ops,
};
/*
* The following entries are taken from Intel document number 510524, rev 1.6:
* Rangeley SoC External Design Specification (EDS)
* Section 10.3 PCI Configuration Space
* Table 10-6. PCI Devices and Functions
*
* These are the Device ID values for the item at bus 0, device 0, function 0.
*/
static const unsigned short pci_device_ids[] = {
0x1f00, 0x1f01, 0x1f02, 0x1f03,
0x1f04, 0x1f05, 0x1f06, 0x1f07,
0x1f08, 0x1f09, 0x1f0a, 0x1f0b,
0x1f0c, 0x1f0d, 0x1f0e, 0x1f0f,
0, /* -- END OF LIST -- */
};
static const struct pci_driver mc_driver __pci_driver = {
.ops = &mc_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};
static void cpu_bus_init(struct device *dev)
{
initialize_cpus(dev->link_list);
}
static struct device_operations cpu_bus_ops = {
.read_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP,
.enable_resources = DEVICE_NOOP,
.init = cpu_bus_init,
.scan_bus = 0,
};
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
}
struct chip_operations northbridge_intel_fsp_rangeley_ops = {
CHIP_NAME("Intel Rangeley Northbridge")
.enable_dev = enable_dev,
};

69
src/northbridge/intel/fsp_rangeley/northbridge.h
View File

@ -1,69 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2011 Google Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__
#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__
#define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS
/* Everything below this line is ignored in the DSDT */
#ifndef __ACPI__
#include <device/device.h>
/* Device 0:0.0 PCI configuration space (Host Bridge) */
/* SideBand B-UNIT */
#define B_UNIT 3
#define BNOCACHE 0x23
#define BNOCACHECTL 0x24
#define BMBOUND 0x25
#define BMBOUND_HI 0x26
#define BECREG 0x27
#define BMISC 0x28
#define BSMMRRL 0x2E
#define BSMMRRH 0x2F
#define BIMR0L 0x80
#define BIMR0H 0x81
#define BIMR0RAC 0x82
#define BIMR0WAC 0x83
/* SideBand C-UNIT */
#define C_UNIT 8
/* SideBand D-UNIT */
#define D_UNIT 1
/* SideBand P-UNIT */
#define P_UNIT 4
#ifndef __ASSEMBLER__
#define PCI_DEVICE_ID_RG_MIN 0x1F00
#define PCI_DEVICE_ID_RG_MAX 0x1F0F
#define SKPAD 0xFC
int bridge_silicon_revision(void);
void rangeley_late_initialization(void);
u32 sideband_read(int port, int reg);
void sideband_write(int port, int reg, long data);
void northbridge_acpi_fill_ssdt_generator(struct device *device);
#endif /* #ifndef __ASSEMBLER__ */
#endif /* #ifndef __ACPI__ */
#endif /* __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ */

65
src/northbridge/intel/fsp_rangeley/port_access.c
View File

@ -1,65 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009-2010 iWave Systems
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define __SIMPLE_DEVICE__
#include <stdint.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include "northbridge.h"
/*
* Restricted Access Regions:
*
* MCR - Message Control Register
* 31 24 16 8 4 0
* ----------------------------------------------------------------------------
* | | | Target | Write | |
* | Opcode | Port | register | byte | Reserved |
* | | | Address | Enables | |
* ----------------------------------------------------------------------------
*
* MDR - Message Data Register
* 31 0
* ----------------------------------------------------------------------------
* | |
* | Data |
* | |
* ----------------------------------------------------------------------------
*/
#define MSG_OPCODE_READ (0x10 << 24)
#define MSG_OPCODE_WRITE (0x11 << 24)
#define MCR 0xD0
#define MDR 0xD4
#define MCRE 0xD8
u32 sideband_read(int port, int reg)
{
pci_write_config32(PCI_DEV(0, 0, 0), MCR,
(MSG_OPCODE_READ | (port << 16) | (reg << 8)));
return pci_read_config32(PCI_DEV(0, 0, 0), MDR);
}
void sideband_write(int port, int reg, long data)
{
pci_write_config32(PCI_DEV(0, 0, 0), MDR, data);
pci_write_config32(PCI_DEV(0, 0, 0), MCR,
(MSG_OPCODE_WRITE | (port << 16) | (reg << 8) | (0xF << 4)));
pci_read_config32(PCI_DEV(0, 0, 0), MDR);
}

5
src/southbridge/intel/common/watchdog.c
View File

@ -37,13 +37,8 @@ void watchdog_off(void)
value = pci_read_config16(dev, PCI_COMMAND); value = pci_read_config16(dev, PCI_COMMAND);
if (CONFIG(SOUTHBRIDGE_INTEL_FSP_RANGELEY)) {
/* Enable I/O space. */
value |= PCI_COMMAND_IO;
} else {
/* Disable interrupt. */ /* Disable interrupt. */
value |= PCI_COMMAND_INT_DISABLE; value |= PCI_COMMAND_INT_DISABLE;
}
pci_write_config16(dev, PCI_COMMAND, value); pci_write_config16(dev, PCI_COMMAND, value);
/* Disable the watchdog timer. */ /* Disable the watchdog timer. */

60
src/southbridge/intel/fsp_rangeley/Kconfig
View File

@ -1,60 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 Google Inc.
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config SOUTHBRIDGE_INTEL_FSP_RANGELEY
bool
if SOUTHBRIDGE_INTEL_FSP_RANGELEY
config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select IOAPIC
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
select INTEL_DESCRIPTOR_MODE_CAPABLE
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
select SOUTHBRIDGE_INTEL_COMMON_RTC
select SOUTHBRIDGE_INTEL_COMMON_RESET
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
config EHCI_BAR
hex
default 0xfef00000
config SERIRQ_CONTINUOUS_MODE
bool
default n
help
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.
config HPET_MIN_TICKS
hex
default 0x80
config IFD_BIN_PATH
string
depends on HAVE_IFD_BIN
default "../intel/mainboard/intel/rangeley"
help
The path and filename to the descriptor.bin file.
endif

33
src/southbridge/intel/fsp_rangeley/Makefile.inc
View File

@ -1,33 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Google Inc.
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y)
ramstage-y += soc.c
ramstage-y += lpc.c
ramstage-y += sata.c
ramstage-y += spi.c
ramstage-y += smbus.c
ramstage-y += acpi.c
romstage-y += early_usb.c early_smbus.c gpio.c early_init.c
romstage-y += romstage.c
bootblock-$(CONFIG_USBDEBUG) += usb_debug.c
romstage-$(CONFIG_USBDEBUG) += usb_debug.c
ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
endif

195
src/southbridge/intel/fsp_rangeley/acpi.c
View File

@ -1,195 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <string.h>
#include <device/device.h>
#include <device/pci.h>
#include <arch/acpi.h>
#include <southbridge/intel/fsp_rangeley/soc.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <version.h>
#include "chip.h"
/**
* Fill in the FADT with generic values that can be overridden later.
*/
typedef struct southbridge_intel_fsp_rangeley_config config_t;
void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
struct device *lpcdev = pcidev_path_on_root(SOC_LPC_DEVFN);
u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0;
config_t *config = lpcdev->chip_info;
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
/*
* Reference section 5.2.9 Fixed ACPI Description Table (FADT)
* in the ACPI 3.0b specification.
*/
/* FADT Header Structure */
memcpy(header->signature, "FACP", 4);
header->length = sizeof(acpi_fadt_t);
header->revision = get_acpi_table_revision(FADT);
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->asl_compiler_revision = asl_revision;
/* ACPI Pointers */
fadt->firmware_ctrl = (unsigned long) facs;
fadt->dsdt = (unsigned long) dsdt;
fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */
fadt->preferred_pm_profile = config->fadt_pm_profile; /* unknown is default */
/* System Management */
fadt->sci_int = 0x09;
fadt->smi_cmd = 0x00; /* disable SMM */
fadt->acpi_enable = 0x00; /* unused if SMI_CMD = 0 */
fadt->acpi_disable = 0x00; /* unused if SMI_CMD = 0 */
/* Enable ACPI */
outl(inl(pmbase + PM1_CNT) | SCI_EN, pmbase + PM1_CNT);
/* Power Control */
fadt->s4bios_req = 0x00;
fadt->pstate_cnt = 0x00;
/* Control Registers - Base Address */
fadt->pm1a_evt_blk = pmbase + PM1_STS;
fadt->pm1b_evt_blk = 0x00; /* Not Used */
fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
fadt->pm1b_cnt_blk = 0x00; /* Not Used */
fadt->pm2_cnt_blk = pmbase + PM2A_CNT_BLK;
fadt->pm_tmr_blk = pmbase + PM1_TMR;
fadt->gpe0_blk = pmbase + GPE0_STS;
fadt->gpe1_blk = 0x00; /* Not Used */
/* Control Registers - Length */
fadt->pm1_evt_len = 4; /* 32 bits */
fadt->pm1_cnt_len = 2; /* 32 bit register, 16 bits used */
fadt->pm2_cnt_len = 1; /* 8 bits */
fadt->pm_tmr_len = 4; /* 32 bits */
fadt->gpe0_blk_len = 8; /* 64 bits */
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
fadt->cst_cnt = 0;
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->duty_offset = 1;
fadt->duty_width = 0;
/* RTC Registers */
fadt->day_alrm = 0x0D;
fadt->mon_alrm = 0x00;
fadt->century = 0x00;
fadt->iapc_boot_arch = config->fadt_boot_arch; /* legacy free default */
fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE |
ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
/* Reset Register */
fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->reset_reg.bit_width = 8;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->reset_reg.addrl = 0xCF9;
fadt->reset_reg.addrh = 0x00;
fadt->reset_value = 6;
fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */
fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */
/* Extended ACPI Pointers */
fadt->x_firmware_ctl_l = (unsigned long)facs;
fadt->x_firmware_ctl_h = 0x00;
fadt->x_dsdt_l = (unsigned long)dsdt;
fadt->x_dsdt_h = 0x00;
/* PM1 Status & PM1 Enable */
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
fadt->x_pm1a_evt_blk.addrh = 0x00;
fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1b_evt_blk.bit_width = 0;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.access_size = 0;
fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
fadt->x_pm1b_evt_blk.addrh = 0x00;
/* PM1 Control Registers */
fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
fadt->x_pm1a_cnt_blk.addrh = 0x00;
fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1b_cnt_blk.bit_width = 0;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.access_size = 0;
fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
fadt->x_pm1b_cnt_blk.addrh = 0x00;
/* PM2 Control Registers */
fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm2_cnt_blk.bit_width = 8;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
fadt->x_pm2_cnt_blk.addrh = 0x00;
/* PM1 Timer Register */
fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
fadt->x_pm_tmr_blk.addrh = 0x00;
/* General-Purpose Event Registers */
fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
fadt->x_gpe0_blk.addrh = 0x00;
fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe1_blk.bit_width = 0;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.access_size = 0;
fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
fadt->x_gpe1_blk.addrh = 0x00;
header->checksum =
acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
}

181
src/southbridge/intel/fsp_rangeley/acpi/globalnvs.asl
View File

@ -1,181 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2012 The Chromium OS Authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Global Variables */
Name(\PICM, 0) // IOAPIC/8259
Name(\DSEN, 1) // Display Output Switching Enable
/* Global ACPI memory region. This region is used for passing information
* between coreboot (aka "the system bios"), ACPI, and the SMI handler.
* Since we don't know where this will end up in memory at ACPI compile time,
* we have to fix it up in coreboot's ACPI creation phase.
*/
External(NVSA)
OperationRegion (GNVS, SystemMemory, NVSA, 0xf00)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
Offset (0x00),
OSYS, 16, // 0x00 - Operating System
SMIF, 8, // 0x02 - SMI function
PRM0, 8, // 0x03 - SMI function parameter
PRM1, 8, // 0x04 - SMI function parameter
SCIF, 8, // 0x05 - SCI function
PRM2, 8, // 0x06 - SCI function parameter
PRM3, 8, // 0x07 - SCI function parameter
LCKF, 8, // 0x08 - Global Lock function for EC
PRM4, 8, // 0x09 - Lock function parameter
PRM5, 8, // 0x0a - Lock function parameter
P80D, 32, // 0x0b - Debug port (IO 0x80) value
LIDS, 8, // 0x0f - LID state (open = 1)
PWRS, 8, // 0x10 - Power State (AC = 1)
/* Processor Identification */
Offset (0x28),
APIC, 8, // 0x28 - APIC Enabled by coreboot
MPEN, 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1
PPCM, 8, // 0x2c - Max. PPC state
PCNT, 8, // 0x2d - Processor count
/* Super I/O & CMOS config */
Offset (0x32),
NATP, 8, // 0x32 -
S5U0, 8, // 0x33 - Enable USB0 in S5
S5U1, 8, // 0x34 - Enable USB1 in S5
S3U0, 8, // 0x35 - Enable USB0 in S3
S3U1, 8, // 0x36 - Enable USB1 in S3
S33G, 8, // 0x37 - Enable 3G in S3
CMEM, 32, // 0x38 - CBMEM TOC
/* Integrated Graphics Device */
Offset (0x3c),
IGDS, 8, // 0x3c - IGD state (primary = 1)
TLST, 8, // 0x3d - Display Toggle List pointer
CADL, 8, // 0x3e - Currently Attached Devices List
PADL, 8, // 0x3f - Previously Attached Devices List
CSTE, 16, // 0x40 - Current display state
NSTE, 16, // 0x42 - Next display state
SSTE, 16, // 0x44 - Set display state
Offset (0x46),
NDID, 8, // 0x46 - Number of Device IDs
DID1, 32, // 0x47 - Device ID 1
DID2, 32, // 0x4b - Device ID 2
DID3, 32, // 0x4f - Device ID 3
DID4, 32, // 0x53 - Device ID 4
DID5, 32, // 0x57 - Device ID 5
/* Backlight Control */
Offset (0x64),
BLCS, 8, // 0x64 - Backlight control possible?
BRTL, 8, // 0x65 - Brightness Level
ODDS, 8, // 0x66
/* Ambient Light Sensors */
Offset (0x6e),
ALSE, 8, // 0x6e - ALS enable
ALAF, 8, // 0x6f - Ambient light adjustment factor
LLOW, 8, // 0x70 - LUX Low
LHIH, 8, // 0x71 - LUX High
/* EMA */
Offset (0x78),
EMAE, 8, // 0x78 - EMA enable
EMAP, 16, // 0x79 - EMA pointer
EMAL, 16, // 0x7b - EMA length
/* MEF */
Offset (0x82),
MEFE, 8, // 0x82 - MEF enable
/* TPM support */
Offset (0x8c),
TPMP, 8, // 0x8c - TPM
TPME, 8, // 0x8d - TPM enable
/* SATA */
Offset (0x96),
GTF0, 56, // 0x96 - GTF task file buffer for port 0
GTF1, 56, // 0x9d - GTF task file buffer for port 1
GTF2, 56, // 0xa4 - GTF task file buffer for port 2
IDEM, 8, // 0xab - IDE mode (compatible / enhanced)
IDET, 8, // 0xac - IDE
/* IGD OpRegion */
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
IPAT, 8, // 0xb9 - IGD panel type cmos option
ITVF, 8, // 0xba - IGD TV format cmos option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config
IBIA, 8, // 0xbe - IGD BIA config
ISSC, 8, // 0xbf - IGD SSC config
I409, 8, // 0xc0 - IGD 0409 modified settings
I509, 8, // 0xc1 - IGD 0509 modified settings
I609, 8, // 0xc2 - IGD 0609 modified settings
I709, 8, // 0xc3 - IGD 0709 modified settings
IDMM, 8, // 0xc4 - IGD Power conservation feature
IDMS, 8, // 0xc5 - IGD DVMT memory size
IF1E, 8, // 0xc6 - IGD function 1 enable
HVCO, 8, // 0xc7 - IGD HPLL VCO
NXD1, 32, // 0xc8 - IGD _DGS next DID1
NXD2, 32, // 0xcc - IGD _DGS next DID2
NXD3, 32, // 0xd0 - IGD _DGS next DID3
NXD4, 32, // 0xd4 - IGD _DGS next DID4
NXD5, 32, // 0xd8 - IGD _DGS next DID5
NXD6, 32, // 0xdc - IGD _DGS next DID6
NXD7, 32, // 0xe0 - IGD _DGS next DID7
NXD8, 32, // 0xe4 - IGD _DGS next DID8
ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI)
PAVP, 8, // 0xe9 - IGD PAVP data
Offset (0xeb),
OSCC, 8, // 0xeb - PCIe OSC control
NPCE, 8, // 0xec - native pcie support
PLFL, 8, // 0xed - platform flavor
BREV, 8, // 0xee - board revision
DPBM, 8, // 0xef - digital port b mode
DPCM, 8, // 0xf0 - digital port c mode
DPDM, 8, // 0xf1 - digital port d mode
ALFP, 8, // 0xf2 - active lfp
IMON, 8, // 0xf3 - current graphics turbo imon value
MMIO, 8, // 0xf4 - 64bit mmio support
}
/* Set flag to enable USB charging in S3 */
Method (S3UE)
{
Store (One, \S3U0)
Store (One, \S3U1)
}
/* Set flag to disable USB charging in S3 */
Method (S3UD)
{
Store (Zero, \S3U0)
Store (Zero, \S3U1)
}
/* Set flag to enable USB charging in S5 */
Method (S5UE)
{
Store (One, \S5U0)
Store (One, \S5U1)
}
/* Set flag to disable USB charging in S5 */
Method (S5UD)
{
Store (Zero, \S5U0)
Store (Zero, \S5U1)
}

57
src/southbridge/intel/fsp_rangeley/acpi/irq_helper.h
View File

@ -1,57 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2014 Sage Electronics Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* This file intentionally gets included multiple times, to set pic and apic
* modes, so should not have guard statements added.
*/
/*
* This file will use irqroute.asl and mainboard/irqroute.h
* to generate the ACPI IRQ routing for the mainboard being compiled.
* This method uses #defines in irqroute.h along with the macros contained
* in this file to generate an IRQ routing for each PCI device in the system.
*/
#undef PCI_DEV_PIRQ_ROUTES
#undef ACPI_DEV_IRQ
#undef PCI_DEV_PIRQ_ROUTE
#undef PIRQ_PIC_ROUTES
#undef PIRQ_PIC
#undef IRQROUTE_H
#if defined(PIC_MODE)
#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 }
#else /* defined(PIC_MODE) */
#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ }
#endif
#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
ACPI_DEV_IRQ(dev_, 0, a_), \
ACPI_DEV_IRQ(dev_, 1, b_), \
ACPI_DEV_IRQ(dev_, 2, c_), \
ACPI_DEV_IRQ(dev_, 3, d_)
/* Empty PIRQ_PIC definition. */
#define PIRQ_PIC(pirq_, pic_irq_)
/* Include the mainboard irq route definition */
#include "irqroute.h"

487
src/southbridge/intel/fsp_rangeley/acpi/irqlinks.asl
View File

@ -1,487 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Device (LNKA)
{
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 1)
// Disable method
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTA)
}
// Possible Resource Settings for this Link
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
// Current Resource Settings for this link
Method (_CRS, 0, Serialized)
{
Name (RTLA, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLA, 1, IRQ0)
// Clear the WordField
Store (Zero, IRQ0)
// Set the bit from PRTA
ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
Return (RTLA)
}
// Set Resource Setting for this IRQ link
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
// Which bit is set?
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTA)
}
// Status
Method (_STA, 0, Serialized)
{
If(And(PRTA, 0x80)) {
Return (0x9)
} Else {
Return (0xb)
}
}
}
Device (LNKB)
{
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 2)
// Disable method
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTB)
}
// Possible Resource Settings for this Link
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
// Current Resource Settings for this link
Method (_CRS, 0, Serialized)
{
Name (RTLB, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLB, 1, IRQ0)
// Clear the WordField
Store (Zero, IRQ0)
// Set the bit from PRTB
ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
Return (RTLB)
}
// Set Resource Setting for this IRQ link
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
// Which bit is set?
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTB)
}
// Status
Method (_STA, 0, Serialized)
{
If(And(PRTB, 0x80)) {
Return (0x9)
} Else {
Return (0xb)
}
}
}
Device (LNKC)
{
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 3)
// Disable method
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTC)
}
// Possible Resource Settings for this Link
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
// Current Resource Settings for this link
Method (_CRS, 0, Serialized)
{
Name (RTLC, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLC, 1, IRQ0)
// Clear the WordField
Store (Zero, IRQ0)
// Set the bit from PRTC
ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
Return (RTLC)
}
// Set Resource Setting for this IRQ link
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
// Which bit is set?
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTC)
}
// Status
Method (_STA, 0, Serialized)
{
If(And(PRTC, 0x80)) {
Return (0x9)
} Else {
Return (0xb)
}
}
}
Device (LNKD)
{
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 4)
// Disable method
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTD)
}
// Possible Resource Settings for this Link
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
// Current Resource Settings for this link
Method (_CRS, 0, Serialized)
{
Name (RTLD, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLD, 1, IRQ0)
// Clear the WordField
Store (Zero, IRQ0)
// Set the bit from PRTD
ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
Return (RTLD)
}
// Set Resource Setting for this IRQ link
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
// Which bit is set?
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTD)
}
// Status
Method (_STA, 0, Serialized)
{
If(And(PRTD, 0x80)) {
Return (0x9)
} Else {
Return (0xb)
}
}
}
Device (LNKE)
{
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 5)
// Disable method
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTE)
}
// Possible Resource Settings for this Link
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
// Current Resource Settings for this link
Method (_CRS, 0, Serialized)
{
Name (RTLE, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLE, 1, IRQ0)
// Clear the WordField
Store (Zero, IRQ0)
// Set the bit from PRTE
ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
Return (RTLE)
}
// Set Resource Setting for this IRQ link
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
// Which bit is set?
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTE)
}
// Status
Method (_STA, 0, Serialized)
{
If(And(PRTE, 0x80)) {
Return (0x9)
} Else {
Return (0xb)
}
}
}
Device (LNKF)
{
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 6)
// Disable method
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTF)
}
// Possible Resource Settings for this Link
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
// Current Resource Settings for this link
Method (_CRS, 0, Serialized)
{
Name (RTLF, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLF, 1, IRQ0)
// Clear the WordField
Store (Zero, IRQ0)
// Set the bit from PRTF
ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
Return (RTLF)
}
// Set Resource Setting for this IRQ link
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
// Which bit is set?
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTF)
}
// Status
Method (_STA, 0, Serialized)
{
If(And(PRTF, 0x80)) {
Return (0x9)
} Else {
Return (0xb)
}
}
}
Device (LNKG)
{
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 7)
// Disable method
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTG)
}
// Possible Resource Settings for this Link
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
// Current Resource Settings for this link
Method (_CRS, 0, Serialized)
{
Name (RTLG, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLG, 1, IRQ0)
// Clear the WordField
Store (Zero, IRQ0)
// Set the bit from PRTG
ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
Return (RTLG)
}
// Set Resource Setting for this IRQ link
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
// Which bit is set?
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTG)
}
// Status
Method (_STA, 0, Serialized)
{
If(And(PRTG, 0x80)) {
Return (0x9)
} Else {
Return (0xb)
}
}
}
Device (LNKH)
{
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 8)
// Disable method
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTH)
}
// Possible Resource Settings for this Link
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
// Current Resource Settings for this link
Method (_CRS, 0, Serialized)
{
Name (RTLH, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLH, 1, IRQ0)
// Clear the WordField
Store (Zero, IRQ0)
// Set the bit from PRTH
ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
Return (RTLH)
}
// Set Resource Setting for this IRQ link
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
// Which bit is set?
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTH)
}
// Status
Method (_STA, 0, Serialized)
{
If(And(PRTH, 0x80)) {
Return (0x9)
} Else {
Return (0xb)
}
}
}

39
src/southbridge/intel/fsp_rangeley/acpi/irqroute.asl
View File

@ -1,39 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// PCI Interrupt Routing
Method(_PRT)
{
/*
* PICM comes from _PIC, which returns the following:
* 0 - PIC mode
* 1 - APIC mode
* 2 - SAPIC mode
*/
If (PICM) {
Return (Package() {
#undef PIC_MODE
#include "irq_helper.h"
PCI_DEV_PIRQ_ROUTES
})
} Else {
Return (Package() {
#define PIC_MODE
#include "irq_helper.h"
PCI_DEV_PIRQ_ROUTES
})
}
}

226
src/southbridge/intel/fsp_rangeley/acpi/lpc.asl
View File

@ -1,226 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// Intel LPC Bus Device - 0:1f.0
Device (LPCB)
{
Name(_ADR, 0x001f0000)
OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
Field (LPC0, AnyAcc, NoLock, Preserve)
{
Offset (0x40),
PMBS, 16, // ABASE
Offset (0x60), // Interrupt Routing Registers
PRTA, 8,
PRTB, 8,
PRTC, 8,
PRTD, 8,
Offset (0x68),
PRTE, 8,
PRTF, 8,
PRTG, 8,
PRTH, 8,
Offset (0x80), // IO Decode Ranges
IOD0, 8,
IOD1, 8,
Offset (0xb8), // GPIO Routing Control
GR00, 2,
GR01, 2,
GR02, 2,
GR03, 2,
GR04, 2,
GR05, 2,
GR06, 2,
GR07, 2,
GR08, 2,
GR09, 2,
GR10, 2,
GR11, 2,
GR12, 2,
GR13, 2,
GR14, 2,
GR15, 2,
Offset (0xf0), // RCBA
RCEN, 1,
, 13,
RCBA, 18,
}
#include "irqlinks.asl"
#include "acpi/ec.asl"
Device (DMAC) // DMA Controller
{
Name(_HID, EISAID("PNP0200"))
Name(_CRS, ResourceTemplate()
{
IO (Decode16, 0x00, 0x00, 0x01, 0x20)
IO (Decode16, 0x81, 0x81, 0x01, 0x11)
IO (Decode16, 0x93, 0x93, 0x01, 0x0d)
IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)
DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }
})
}
Device (FWH) // Firmware Hub
{
Name (_HID, EISAID("INT0800"))
Name (_CRS, ResourceTemplate()
{
Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
})
}
Device (HPET)
{
Name (_HID, EISAID("PNP0103"))
Name (_CID, 0x010CD041)
Name(BUF0, ResourceTemplate()
{
Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0)
})
Method (_STA, 0) // Device Status
{
If (HPTE) {
// Note: Ancient versions of Windows don't want
// to see the HPET in order to work right
If (LGreaterEqual(OSYS, 2001)) {
Return (0xf) // Enable and show device
} Else {
Return (0xb) // Enable and don't show device
}
}
Return (0x0) // Not enabled, don't show.
}
Method (_CRS, 0, Serialized) // Current resources
{
If (HPTE) {
CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
If (Lequal(HPAS, 1)) {
Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0)
}
If (Lequal(HPAS, 2)) {
Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0)
}
If (Lequal(HPAS, 3)) {
Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0)
}
}
Return (BUF0)
}
}
Device(PIC) // 8259 Interrupt Controller
{
Name(_HID,EISAID("PNP0000"))
Name(_CRS, ResourceTemplate()
{
IO (Decode16, 0x20, 0x20, 0x01, 0x02)
IO (Decode16, 0x24, 0x24, 0x01, 0x02)
IO (Decode16, 0x28, 0x28, 0x01, 0x02)
IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
IO (Decode16, 0x30, 0x30, 0x01, 0x02)
IO (Decode16, 0x34, 0x34, 0x01, 0x02)
IO (Decode16, 0x38, 0x38, 0x01, 0x02)
IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
IO (Decode16, 0xac, 0xac, 0x01, 0x02)
IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
IRQNoFlags () { 2 }
})
}
Device(MATH) // FPU
{
Name (_HID, EISAID("PNP0C04"))
Name (_CRS, ResourceTemplate()
{
IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
IRQNoFlags() { 13 }
})
}
Device(LDRC) // LPC device: Resource consumption
{
Name (_HID, EISAID("PNP0C02"))
Name (_UID, 2)
Name (RBUF, ResourceTemplate()
{
IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
//IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap
IO (Decode16, DEFAULT_ABASE, DEFAULT_ABASE, 0x1, 0x80) // ICH7-M ACPI
IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH7-M GPIO
})
Method (_CRS, 0, NotSerialized)
{
Return (RBUF)
}
}
Device (RTC) // Real Time Clock
{
Name (_HID, EISAID("PNP0B00"))
Name (_CRS, ResourceTemplate()
{
IO (Decode16, 0x70, 0x70, 1, 8)
// Disable as Windows doesn't like it, and systems don't seem to use it.
// IRQNoFlags() { 8 }
})
}
Device (TIMR) // Intel 8254 timer
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
{
IO (Decode16, 0x40, 0x40, 0x01, 0x04)
IO (Decode16, 0x50, 0x50, 0x10, 0x04)
IRQNoFlags() {0}
})
}
// Include mainboard's superio.asl file.
#include "acpi/superio.asl"
}

165
src/southbridge/intel/fsp_rangeley/acpi/pcie.asl
View File

@ -1,165 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Intel 6/7 Series PCH PCIe support */
// PCI Express Ports
Method (IRQM, 1, Serialized) {
/* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
Name (IQAA, Package() {
Package() { 0x0000ffff, 0, 0, 16 },
Package() { 0x0000ffff, 1, 0, 17 },
Package() { 0x0000ffff, 2, 0, 18 },
Package() { 0x0000ffff, 3, 0, 19 } })
Name (IQAP, Package() {
Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } })
/* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
Name (IQBA, Package() {
Package() { 0x0000ffff, 0, 0, 17 },
Package() { 0x0000ffff, 1, 0, 18 },
Package() { 0x0000ffff, 2, 0, 19 },
Package() { 0x0000ffff, 3, 0, 16 } })
Name (IQBP, Package() {
Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } })
/* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
Name (IQCA, Package() {
Package() { 0x0000ffff, 0, 0, 18 },
Package() { 0x0000ffff, 1, 0, 19 },
Package() { 0x0000ffff, 2, 0, 16 },
Package() { 0x0000ffff, 3, 0, 17 } })
Name (IQCP, Package() {
Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } })
/* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
Name (IQDA, Package() {
Package() { 0x0000ffff, 0, 0, 19 },
Package() { 0x0000ffff, 1, 0, 16 },
Package() { 0x0000ffff, 2, 0, 17 },
Package() { 0x0000ffff, 3, 0, 18 } })
Name (IQDP, Package() {
Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } })
Switch (ToInteger (Arg0)) {
/* PCIe Root Port 1 */
Case (Package() { 1 }) {
If (PICM) {
Return (IQAA)
} Else {
Return (IQAP)
}
}
/* PCIe Root Port 2 */
Case (Package() { 2 }) {
If (PICM) {
Return (IQBA)
} Else {
Return (IQBP)
}
}
/* PCIe Root Port 3 */
Case (Package() { 3 }) {
If (PICM) {
Return (IQCA)
} Else {
Return (IQCP)
}
}
/* PCIe Root Port 4 */
Case (Package() { 4 }) {
If (PICM) {
Return (IQDA)
} Else {
Return (IQDP)
}
}
Default {
If (PICM) {
Return (IQDA)
} Else {
Return (IQDP)
}
}
}
}
Device (RP01)
{
Name (_ADR, 0x00010000)
#include "pcie_port.asl"
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP02)
{
Name (_ADR, 0x00020000)
#include "pcie_port.asl"
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP03)
{
Name (_ADR, 0x00030000)
#include "pcie_port.asl"
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP04)
{
Name (_ADR, 0x00040000)
#include "pcie_port.asl"
Method (_PRT)
{
Return (IRQM (RPPN))
}
}

25
src/southbridge/intel/fsp_rangeley/acpi/pcie_port.asl
View File

@ -1,25 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Included in each PCIe Root Port device */
OperationRegion (RPCS, PCI_Config, 0x00, 0xFF)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
Offset (0x4c), // Link Capabilities
, 24,
RPPN, 8, // Root Port Number
}

77
src/southbridge/intel/fsp_rangeley/acpi/sata.asl
View File

@ -1,77 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// Intel SATA Controller 0:17.0
// Note: Some BIOSes put the S-ATA code into an SSDT to make it easily
// pluggable
Device (SATA)
{
Name (_ADR, 0x00170000)
Device (PRID)
{
Name (_ADR, 0)
// Get Timing Mode
Method (_GTM, 0, Serialized)
{
Name(PBUF, Buffer(20) {
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00 })
CreateDwordField (PBUF, 0, PIO0)
CreateDwordField (PBUF, 4, DMA0)
CreateDwordField (PBUF, 8, PIO1)
CreateDwordField (PBUF, 12, DMA1)
CreateDwordField (PBUF, 16, FLAG)
// TODO fill return structure
Return (PBUF)
}
// Set Timing Mode
Method (_STM, 3)
{
CreateDwordField (Arg0, 0, PIO0)
CreateDwordField (Arg0, 4, DMA0)
CreateDwordField (Arg0, 8, PIO1)
CreateDwordField (Arg0, 12, DMA1)
CreateDwordField (Arg0, 16, FLAG)
// TODO: Do the deed
}
Device (DSK0)
{
Name (_ADR, 0)
// TODO: _RMV ?
// TODO: _GTF ?
}
Device (DSK1)
{
Name (_ADR, 1)
// TODO: _RMV ?
// TODO: _GTF ?
}
}
}

272
src/southbridge/intel/fsp_rangeley/acpi/soc.asl
View File

@ -1,272 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Intel Rangeley support */
#include "../soc.h"
Scope(\)
{
// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
OperationRegion(IO_T, SystemIO, 0x800, 0x10)
Field(IO_T, ByteAcc, NoLock, Preserve)
{
Offset(0x8),
TRP0, 8 // IO-Trap at 0x808
}
#ifdef ACPI_INCLUDE_PMIO
// PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
OperationRegion(PMIO, SystemIO, DEFAULT_ABASE, 0x80)
Field(PMIO, ByteAcc, NoLock, Preserve)
{
Offset(0x20), // GPE0_STS
, 16,
GS00, 1, // GPIO00 SCI/Wake Status
GS01, 1, // GPIO01 SCI/Wake Status
GS02, 1, // GPIO02 SCI/Wake Status
GS03, 1, // GPIO03 SCI/Wake Status
GS04, 1, // GPIO04 SCI/Wake Status
GS05, 1, // GPIO05 SCI/Wake Status
GS06, 1, // GPIO06 SCI/Wake Status
GS07, 1, // GPIO07 SCI/Wake Status
GS08, 1, // GPIO08 SCI/Wake Status
GS09, 1, // GPIO09 SCI/Wake Status
GS10, 1, // GPIO10 SCI/Wake Status
GS11, 1, // GPIO11 SCI/Wake Status
GS12, 1, // GPIO12 SCI/Wake Status
GS13, 1, // GPIO13 SCI/Wake Status
GS14, 1, // GPIO14 SCI/Wake Status
GS15, 1, // GPIO15 SCI/Wake Status
Offset(0x28), // GPE0_EN
, 16,
GE00, 1, // GPIO00 SCI/Wake Enable
GE01, 1, // GPIO01 SCI/Wake Enable
GE02, 1, // GPIO02 SCI/Wake Enable
GE03, 1, // GPIO03 SCI/Wake Enable
GE04, 1, // GPIO04 SCI/Wake Enable
GE05, 1, // GPIO05 SCI/Wake Enable
GE06, 1, // GPIO06 SCI/Wake Enable
GE07, 1, // GPIO07 SCI/Wake Enable
GE08, 1, // GPIO08 SCI/Wake Enable
GE09, 1, // GPIO09 SCI/Wake Enable
GE10, 1, // GPIO10 SCI/Wake Enable
GE11, 1, // GPIO11 SCI/Wake Enable
GE12, 1, // GPIO12 SCI/Wake Enable
GE13, 1, // GPIO13 SCI/Wake Enable
GE14, 1, // GPIO14 SCI/Wake Enable
GE15, 1, // GPIO15 SCI/Wake Enable
Offset(0x42), // General Purpose Control
, 1, // skip 1 bit
GPEC, 1, // SWGPE_CTRL
}
#endif
#ifdef ACPI_INCLUDE_GPIO
// GPIO IO mapped registers (0x1f.0 reg 0x48.l)
OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c)
Field(GPIO, ByteAcc, NoLock, Preserve)
{
Offset(0x00), // GPIO Use Select
GU00, 8,
GU01, 8,
GU02, 8,
GU03, 8,
Offset(0x04), // GPIO IO Select
GIO0, 8,
GIO1, 8,
GIO2, 8,
GIO3, 8,
Offset(0x0c), // GPIO Level
GP00, 1,
GP01, 1,
GP02, 1,
GP0e, 1,
GP04, 1,
GP05, 1,
GP06, 1,
GP07, 1,
GP08, 1,
GP09, 1,
GP10, 1,
GP11, 1,
GP12, 1,
GP13, 1,
GP14, 1,
GP15, 1,
GP16, 1,
GP17, 1,
GP18, 1,
GP19, 1,
GP20, 1,
GP21, 1,
GP22, 1,
GP23, 1,
GP24, 1,
GP25, 1,
GP26, 1,
GP27, 1,
GP28, 1,
GP29, 1,
GP30, 1,
GP31, 1,
Offset(0x18), // GPIO Blink
GB00, 8,
GB01, 8,
GB02, 8,
GB03, 8,
Offset(0x2c), // GPIO Invert
GIV0, 8,
GIV1, 8,
GIV2, 8,
GIV3, 8,
Offset(0x30), // GPIO Use Select 2
GU04, 8,
GU05, 8,
GU06, 8,
GU07, 8,
Offset(0x34), // GPIO IO Select 2
GIO4, 8,
GIO5, 8,
GIO6, 8,
GIO7, 8,
Offset(0x38), // GPIO Level 2
GP32, 1,
GP33, 1,
GP34, 1,
GP35, 1,
GP36, 1,
GP37, 1,
GP38, 1,
GP39, 1,
GP40, 1,
GP41, 1,
GP42, 1,
GP43, 1,
GP44, 1,
GP45, 1,
GP46, 1,
GP47, 1,
GP48, 1,
GP49, 1,
GP50, 1,
GP51, 1,
GP52, 1,
GP53, 1,
GP54, 1,
GP55, 1,
GP56, 1,
GP57, 1,
GP58, 1,
GP59, 1,
GP60, 1,
GP61, 1,
GP62, 1,
GP63, 1,
Offset(0x40), // GPIO Use Select 3
GU08, 8,
GU09, 4,
Offset(0x44), // GPIO IO Select 3
GIO8, 8,
GIO9, 4,
Offset(0x48), // GPIO Level 3
GP64, 1,
GP65, 1,
GP66, 1,
GP67, 1,
GP68, 1,
GP69, 1,
GP70, 1,
GP71, 1,
GP72, 1,
GP73, 1,
GP74, 1,
GP75, 1,
}
#endif
// ICH7 Root Complex Register Block. Memory Mapped through RCBA)
OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
Field(RCRB, DWordAcc, Lock, Preserve)
{
Offset(0x0000), // Backbone
Offset(0x1000), // Chipset
Offset(0x3000), // Legacy Configuration Registers
Offset(0x3404), // High Performance Timer Configuration
HPAS, 2, // Address Select
, 5,
HPTE, 1, // Address Enable
Offset(0x3418), // FD (Function Disable)
, 1, // Reserved
PCID, 1, // PCI bridge disable
SA1D, 1, // SATA1 disable
SMBD, 1, // SMBUS disable
HDAD, 1, // Azalia disable
, 8, // Reserved
EH2D, 1, // EHCI #2 disable
LPBD, 1, // LPC bridge disable
EH1D, 1, // EHCI #1 disable
RP1D, 1, // Root Port 1 disable
RP2D, 1, // Root Port 2 disable
RP3D, 1, // Root Port 3 disable
RP4D, 1, // Root Port 4 disable
TTRD, 1, // Thermal sensor registers disable
SA2D, 1, // SATA2 disable
Offset(0x3428), // FD2 (Function Disable 2)
BDFD, 1, // Display BDF
ME1D, 1, // ME Interface 1 disable
ME2D, 1, // ME Interface 2 disable
IDRD, 1, // IDE redirect disable
KTCT, 1, // Keyboard Text redirect disable
}
}
// PCI Express Ports 0:[1-4].0
#include "pcie.asl"
// USB 0:16.0
#include "usb.asl"
// LPC Bridge 0:1f.0
#include "lpc.asl"
// SATA 0:17.0
#include "sata.asl"
// SMBus 0:1f.3
#include <southbridge/intel/common/acpi/smbus.asl>
// IRQ routing for each PCI device
#include "irqroute.asl"
Method (_OSC, 4)
{
/* Check for proper GUID */
If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
{
/* Let OS control everything */
Return (Arg3)
}
Else
{
/* Unrecognized UUID */
CreateDWordField (Arg3, 0, CDW1)
Or (CDW1, 4, CDW1)
Return (Arg3)
}
}

48
src/southbridge/intel/fsp_rangeley/acpi/usb.asl
View File

@ -1,48 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Intel Rangeley USB support */
// EHCI Controller 0:16.0
Device (EHC1)
{
Name(_ADR, 0x00160000)
Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
// Leave USB ports on for to allow Wake from USB
Method(_S3D,0) // Highest D State in S3 State
{
Return (2)
}
Method(_S4D,0) // Highest D State in S4 State
{
Return (2)
}
Device (HUB7)
{
Name (_ADR, 0x00000000)
Device (PRT1) { Name (_ADR, 1) } // USB Port 0
Device (PRT2) { Name (_ADR, 2) } // USB Port 1
Device (PRT3) { Name (_ADR, 3) } // USB Port 2
Device (PRT4) { Name (_ADR, 4) } // USB Port 3
}
}

84
src/southbridge/intel/fsp_rangeley/chip.h
View File

@ -1,84 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H
#define SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H
#include <arch/acpi.h>
struct southbridge_intel_fsp_rangeley_config {
/**
* GPI Routing configuration
*
* Only the lower two bits have a meaning:
* 00: No effect
* 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
* 10: SCI (if corresponding GPIO_EN bit is also set)
* 11: reserved
*/
uint8_t gpi0_routing;
uint8_t gpi1_routing;
uint8_t gpi2_routing;
uint8_t gpi3_routing;
uint8_t gpi4_routing;
uint8_t gpi5_routing;
uint8_t gpi6_routing;
uint8_t gpi7_routing;
uint8_t gpi8_routing;
uint8_t gpi9_routing;
uint8_t gpi10_routing;
uint8_t gpi11_routing;
uint8_t gpi12_routing;
uint8_t gpi13_routing;
uint8_t gpi14_routing;
uint8_t gpi15_routing;
uint32_t gpe0_en;
uint16_t alt_gp_smi_en;
/* IDE configuration */
uint32_t ide_legacy_combined;
uint32_t sata_ahci;
uint8_t sata_port_map;
uint32_t sata_port0_gen3_tx;
uint32_t sata_port1_gen3_tx;
uint32_t gen1_dec;
uint32_t gen2_dec;
uint32_t gen3_dec;
uint32_t gen4_dec;
/* Enable linear PCIe Root Port function numbers starting at zero */
uint8_t pcie_port_coalesce;
/* Override PCIe ASPM */
uint8_t pcie_aspm_f0;
uint8_t pcie_aspm_f1;
uint8_t pcie_aspm_f2;
uint8_t pcie_aspm_f3;
uint8_t pcie_aspm_f4;
uint8_t pcie_aspm_f5;
uint8_t pcie_aspm_f6;
uint8_t pcie_aspm_f7;
/* ACPI configuration */
uint8_t fadt_pm_profile;
uint16_t fadt_boot_arch;
};
#endif /* SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H */

76
src/southbridge/intel/fsp_rangeley/early_init.c
View File

@ -1,76 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2010 coresystems GmbH
* Copyright (C) 2011 Google Inc
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <stdlib.h>
#include <console/console.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <pc80/mc146818rtc.h>
#include <version.h>
#include "pci_devs.h"
#include "soc.h"
static void rangeley_setup_bars(void)
{
/* Setting up Southbridge. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
pci_write_config32(LPC_BDF, RCBA, (uintptr_t)DEFAULT_RCBA | RCBA_ENABLE);
pci_write_config32(LPC_BDF, ABASE, DEFAULT_ABASE | SET_BAR_ENABLE);
pci_write_config32(LPC_BDF, PBASE, DEFAULT_PBASE | SET_BAR_ENABLE);
printk(BIOS_DEBUG, " done.\n");
printk(BIOS_DEBUG, "Disabling Watchdog timer...");
/* Disable the watchdog reboot and turn off the watchdog timer */
write8((void *)(DEFAULT_PBASE + PMC_CFG),
read8((void *)(DEFAULT_PBASE + PMC_CFG)) | NO_REBOOT); // disable reboot on timer trigger
outw(inw(DEFAULT_ABASE + TCO1_CNT) | TCO_TMR_HALT,
DEFAULT_ABASE + TCO1_CNT); // disable watchdog timer
printk(BIOS_DEBUG, " done.\n");
}
static void reset_rtc(void)
{
uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) &
0xfffffff0;
uint32_t gen_pmcon1 = read32((void *)(pbase + GEN_PMCON1));
int rtc_failed = !!(gen_pmcon1 & RPS);
if (rtc_failed) {
printk(BIOS_DEBUG,
"RTC Failure detected. Resetting Date to %s\n",
coreboot_dmi_date);
/* Clear the power failure flag */
write32((void *)(DEFAULT_PBASE + GEN_PMCON1),
gen_pmcon1 & ~RPS);
}
cmos_init(rtc_failed);
}
void rangeley_sb_early_initialization(void)
{
/* Setup all BARs required for early PCIe and raminit */
rangeley_setup_bars();
reset_rtc();
}

57
src/southbridge/intel/fsp_rangeley/early_smbus.c
View File

@ -1,57 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <southbridge/intel/common/smbus.h>
#include "soc.h"
void enable_smbus(void)
{
pci_devfn_t dev;
/* Set the SMBus device statically. */
dev = PCI_DEV(0x0, 0x1f, 0x3);
/* Check to make sure we've got the right device. */
if (pci_read_config16(dev, 0x0) != 0x8086) {
die("SMBus controller not found!");
}
/* Set SMBus I/O base. */
pci_write_config32(dev, SMB_BASE,
SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */
pci_write_config8(dev, HOSTC, HST_EN);
/* Set SMBus I/O space enable. */
pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
/* Disable interrupt generation. */
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
/* Clear any lingering errors, so transactions can run. */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}

41
src/southbridge/intel/fsp_rangeley/early_usb.c
View File

@ -1,41 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include "soc.h"
#define SOC_EHCI1_TEMP_BAR0 0xe8000000
/*
* Setup USB controller MMIO BAR to prevent the
* reference code from resetting the controller.
*
* The BAR will be re-assigned during device
* enumeration so these are only temporary.
*/
void enable_usb_bar(void)
{
pci_devfn_t usb0 = SOC_EHCI1_DEV;
u32 cmd;
/* USB Controller 0 */
pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
SOC_EHCI1_TEMP_BAR0);
cmd = pci_read_config32(usb0, PCI_COMMAND);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(usb0, PCI_COMMAND, cmd);
}

105
src/southbridge/intel/fsp_rangeley/gpio.c
View File

@ -1,105 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include "soc.h"
#include "gpio.h"
#define MAX_GPIO_NUMBER 31 /* zero based */
void setup_soc_gpios(const struct soc_gpio_map *gpio)
{
u16 gpiobase = pci_read_config16(SOC_LPC_DEV, GBASE) & ~0xf;
u32 *cfiobase = (u32 *)(pci_read_config32(SOC_LPC_DEV, IOBASE) & ~0xf);
u32 cfio_cnt = 0;
/* GPIO */
if (gpio->core.level)
outl(*((u32*)gpio->core.level), gpiobase + GPIO_SC_GP_LVL);
if (gpio->core.mode)
outl(*((u32*)gpio->core.mode), gpiobase + GPIO_SC_USE_SEL);
if (gpio->core.direction)
outl(*((u32*)gpio->core.direction), gpiobase + GPIO_SC_IO_SEL);
if (gpio->core.tpe)
outl(*((u32*)gpio->core.tpe), gpiobase + GPIO_SC_TPE);
if (gpio->core.tne)
outl(*((u32*)gpio->core.tne), gpiobase + GPIO_SC_TNE);
if (gpio->core.ts)
outl(*((u32*)gpio->core.ts), gpiobase + GPIO_SC_TS);
/* GPIO SUS Well Set 1 */
if (gpio->sus.level)
outl(*((u32*)gpio->sus.level), gpiobase + GPIO_SUS_GP_LVL);
if (gpio->sus.mode)
outl(*((u32*)gpio->sus.mode), gpiobase + GPIO_SUS_USE_SEL);
if (gpio->sus.direction)
outl(*((u32*)gpio->sus.direction), gpiobase + GPIO_SUS_IO_SEL);
if (gpio->sus.tpe)
outl(*((u32*)gpio->sus.tpe), gpiobase + GPIO_SUS_TPE);
if (gpio->sus.tne)
outl(*((u32*)gpio->sus.tne), gpiobase + GPIO_SUS_TNE);
if (gpio->sus.ts)
outl(*((u32*)gpio->sus.ts), gpiobase + GPIO_SUS_TS);
if (gpio->sus.we)
outl(*((u32*)gpio->sus.we), gpiobase + GPIO_SUS_WE);
/* GPIO PAD Settings */
/* CFIO Core Well Set 1 */
if ((gpio->core.cfio_init != NULL) && (gpio->core.cfio_entrynum != 0)) {
write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002);
for (cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) {
if (!((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0))
continue;
write32(cfiobase + ((CFIO_PAD_CONF0 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0);
write32(cfiobase + ((CFIO_PAD_CONF1 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_1);
write32(cfiobase + ((CFIO_PAD_VAL + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_val);
write32(cfiobase + ((CFIO_PAD_DFT + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_dft);
}
write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01041002);
}
/* CFIO SUS Well Set 1 */
if ((gpio->sus.cfio_init != NULL) && (gpio->sus.cfio_entrynum != 0)) {
write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01001002);
for (cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) {
if (!((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0))
continue;
write32(cfiobase + ((CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0);
write32(cfiobase + ((CFIO_PAD_CONF1 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_1);
write32(cfiobase + ((CFIO_PAD_VAL + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_val);
write32(cfiobase + ((CFIO_PAD_DFT + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_dft);
}
write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01041002);
}
}
int get_gpio(int gpio_num)
{
u16 gpio_base = pci_read_config16(SOC_LPC_DEV, GBASE) & ~0xf;
int bit;
if (gpio_num > MAX_GPIO_NUMBER)
return 0; /* Ignore wrong GPIO numbers. */
bit = gpio_num % 32;
return (inl(gpio_base + GPIO_SC_USE_SEL) >> bit) & 1;
}

124
src/southbridge/intel/fsp_rangeley/gpio.h
View File

@ -1,124 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef INTEL_RANGELEY_GPIO_H
#define INTEL_RANGELEY_GPIO_H
#define GPIO_MODE_NATIVE 0
#define GPIO_MODE_GPIO 1
#define GPIO_MODE_NONE 1
#define GPIO_DIR_OUTPUT 0
#define GPIO_DIR_INPUT 1
#define GPIO_LEVEL_LOW 0
#define GPIO_LEVEL_HIGH 1
#define GPIO_TPE_DISABLE 0
#define GPIO_TPE_ENABLE 1
#define GPIO_TNE_DISABLE 0
#define GPIO_TNE_ENABLE 1
#define GPIO_TS_DISABLE 0
#define GPIO_TS_ENABLE 1
#define GPIO_WE_DISABLE 0
#define GPIO_WE_ENABLE 1
struct soc_gpio {
u32 gpio0 : 1;
u32 gpio1 : 1;
u32 gpio2 : 1;
u32 gpio3 : 1;
u32 gpio4 : 1;
u32 gpio5 : 1;
u32 gpio6 : 1;
u32 gpio7 : 1;
u32 gpio8 : 1;
u32 gpio9 : 1;
u32 gpio10 : 1;
u32 gpio11 : 1;
u32 gpio12 : 1;
u32 gpio13 : 1;
u32 gpio14 : 1;
u32 gpio15 : 1;
u32 gpio16 : 1;
u32 gpio17 : 1;
u32 gpio18 : 1;
u32 gpio19 : 1;
u32 gpio20 : 1;
u32 gpio21 : 1;
u32 gpio22 : 1;
u32 gpio23 : 1;
u32 gpio24 : 1;
u32 gpio25 : 1;
u32 gpio26 : 1;
u32 gpio27 : 1;
u32 gpio28 : 1;
u32 gpio29 : 1;
u32 gpio30 : 1;
u32 gpio31 : 1;
} __packed;
struct soc_cfio {
u32 pad_conf_0;
u32 pad_conf_1;
u32 pad_val;
u32 pad_dft;
} __packed;
struct soc_gpio_map {
/* GPIO core */
struct {
const struct soc_gpio *mode;
const struct soc_gpio *direction;
const struct soc_gpio *level;
const struct soc_gpio *tpe;
const struct soc_gpio *tne;
const struct soc_gpio *ts;
const struct soc_cfio *cfio_init;
const u32 cfio_entrynum;
}core;
/* GPIO SUS */
struct {
const struct soc_gpio *mode;
const struct soc_gpio *direction;
const struct soc_gpio *level;
const struct soc_gpio *tpe;
const struct soc_gpio *tne;
const struct soc_gpio *ts;
const struct soc_gpio *we;
const struct soc_cfio *cfio_init;
const u32 cfio_entrynum;
}sus;
};
/* Configure GPIOs with mainboard provided settings */
void setup_soc_gpios(const struct soc_gpio_map *gpio);
/* Get GPIO pin value */
int get_gpio(int gpio_num);
/*
* Get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of GPIO pin numbers to scan, terminated by -1.
*/
unsigned int get_gpios(const int *gpio_num_array);
#endif

162
src/southbridge/intel/fsp_rangeley/irq.h
View File

@ -1,162 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _RANGELEY_IRQ_H_
#define _RANGELEY_IRQ_H_
#define PIRQA_APIC_IRQ 16
#define PIRQB_APIC_IRQ 17
#define PIRQC_APIC_IRQ 18
#define PIRQD_APIC_IRQ 19
#define PIRQE_APIC_IRQ 20
#define PIRQF_APIC_IRQ 21
#define PIRQG_APIC_IRQ 22
#define PIRQH_APIC_IRQ 23
/* The below IRQs are for when devices are in ACPI mode. Active low. */
#define LPE_DMA0_IRQ 24
#define LPE_DMA1_IRQ 25
#define LPE_SSP0_IRQ 26
#define LPE_SSP1_IRQ 27
#define LPE_SSP2_IRQ 28
#define LPE_IPC2HOST_IRQ 29
#define LPSS_I2C1_IRQ 32
#define LPSS_I2C2_IRQ 33
#define LPSS_I2C3_IRQ 34
#define LPSS_I2C4_IRQ 35
#define LPSS_I2C5_IRQ 36
#define LPSS_I2C6_IRQ 37
#define LPSS_I2C7_IRQ 38
#define LPSS_HSUART1_IRQ 39
#define LPSS_HSUART2_IRQ 40
#define LPSS_SPI_IRQ 41
#define LPSS_DMA1_IRQ 42
#define LPSS_DMA2_IRQ 43
#define SCC_EMMC_IRQ 44
#define SCC_SDIO_IRQ 46
#define SCC_SD_IRQ 47
#define GPIO_NC_IRQ 48
#define GPIO_SC_IRQ 49
#define GPIO_SUS_IRQ 50
/* GPIO direct / dedicated IRQs. */
#define GPIO_S0_DED_IRQ_0 51
#define GPIO_S0_DED_IRQ_1 52
#define GPIO_S0_DED_IRQ_2 53
#define GPIO_S0_DED_IRQ_3 54
#define GPIO_S0_DED_IRQ_4 55
#define GPIO_S0_DED_IRQ_5 56
#define GPIO_S0_DED_IRQ_6 57
#define GPIO_S0_DED_IRQ_7 58
#define GPIO_S0_DED_IRQ_8 59
#define GPIO_S0_DED_IRQ_9 60
#define GPIO_S0_DED_IRQ_10 61
#define GPIO_S0_DED_IRQ_11 62
#define GPIO_S0_DED_IRQ_12 63
#define GPIO_S0_DED_IRQ_13 64
#define GPIO_S0_DED_IRQ_14 65
#define GPIO_S0_DED_IRQ_15 66
#define GPIO_S5_DED_IRQ_0 67
#define GPIO_S5_DED_IRQ_1 68
#define GPIO_S5_DED_IRQ_2 69
#define GPIO_S5_DED_IRQ_3 70
#define GPIO_S5_DED_IRQ_4 71
#define GPIO_S5_DED_IRQ_5 72
#define GPIO_S5_DED_IRQ_6 73
#define GPIO_S5_DED_IRQ_7 74
#define GPIO_S5_DED_IRQ_8 75
#define GPIO_S5_DED_IRQ_9 76
#define GPIO_S5_DED_IRQ_10 77
#define GPIO_S5_DED_IRQ_11 78
#define GPIO_S5_DED_IRQ_12 79
#define GPIO_S5_DED_IRQ_13 80
#define GPIO_S5_DED_IRQ_14 81
#define GPIO_S5_DED_IRQ_15 82
/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL. */
#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot
#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot
#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot)
#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot)
/* PIC IRQ settings. */
#define PIRQ_PIC_IRQ3 0x3
#define PIRQ_PIC_IRQ4 0x4
#define PIRQ_PIC_IRQ5 0x5
#define PIRQ_PIC_IRQ6 0x6
#define PIRQ_PIC_IRQ7 0x7
#define PIRQ_PIC_IRQ9 0x9
#define PIRQ_PIC_IRQ10 0xa
#define PIRQ_PIC_IRQ11 0xb
#define PIRQ_PIC_IRQ12 0xc
#define PIRQ_PIC_IRQ14 0xe
#define PIRQ_PIC_IRQ15 0xf
#define PIRQ_PIC_IRQDISABLE 0x80
#define PIRQ_PIC_UNKNOWN_UNUSED 0xff
/* Overloaded term, but these values determine the per device route. */
#define PIRQA 0
#define PIRQB 1
#define PIRQC 2
#define PIRQD 3
#define PIRQE 4
#define PIRQF 5
#define PIRQG 6
#define PIRQH 7
/* These registers live behind the ILB_BASE_ADDRESS */
#define ACTL 0x00
# define SCIS_MASK 0x07
# define SCIS_IRQ9 0x00
# define SCIS_IRQ10 0x01
# define SCIS_IRQ11 0x02
# define SCIS_IRQ20 0x04
# define SCIS_IRQ21 0x05
# define SCIS_IRQ22 0x06
# define SCIS_IRQ23 0x07
/* In each mainboard directory there should exist a header file irqroute.h that
* defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which
* consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */
#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
#include <stdint.h>
#define NUM_OF_PCI_DEVS 32
#define NUM_PIRQS 8
struct rangeley_irq_route {
/* Per device configuration. */
uint16_t pcidev[NUM_OF_PCI_DEVS];
/* Route path for each internal PIRQx in PIC mode. */
uint8_t pic[NUM_PIRQS];
};
extern const struct rangeley_irq_route global_rangeley_irq_route;
#define DEFINE_IRQ_ROUTES \
const struct rangeley_irq_route global_rangeley_irq_route = { \
.pcidev = { PCI_DEV_PIRQ_ROUTES, }, \
.pic = { PIRQ_PIC_ROUTES, }, \
}
#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
[dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \
((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0)
#define PIRQ_PIC(pirq_, pic_irq_) \
[PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_
#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
#endif /* _RANGELEY_IRQ_H_ */

461
src/southbridge/intel/fsp_rangeley/lpc.c
View File

@ -1,461 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <arch/acpi.h>
#include <arch/cpu.h>
#include <cpu/x86/smm.h>
#include <string.h>
#include <cbmem.h>
#include <arch/acpigen.h>
#include "chip.h"
#include "soc.h"
#include "irq.h"
#include "nvs.h"
#define NMI_OFF 0
typedef struct southbridge_intel_fsp_rangeley_config config_t;
static void soc_enable_apic(struct device *dev)
{
int i;
u32 reg32;
volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f);
/*
* Enable ACPI I/O and power management.
* Set SCI IRQ to IRQ9
*/
write32(ilb_base + ILB_OIC, 0x100); /* AEN */
reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */
write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */
*ioapic_index = 0;
*ioapic_data = (1 << 25);
/* Affirm full set of redirection table entries ("write once") */
*ioapic_index = 1;
reg32 = *ioapic_data;
*ioapic_index = 1;
*ioapic_data = reg32;
*ioapic_index = 0;
reg32 = *ioapic_data;
printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
if (reg32 != (1 << 25))
die("APIC Error\n");
printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
for (i=0; i<3; i++) {
*ioapic_index = i;
printk(BIOS_SPEW, " reg 0x%04x:", i);
reg32 = *ioapic_data;
printk(BIOS_SPEW, " 0x%08x\n", reg32);
}
*ioapic_index = 3; /* Select Boot Configuration register. */
*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
}
static void soc_enable_serial_irqs(struct device *dev)
{
u8 *ibase;
ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
/* Set packet length and toggle silent mode bit for one frame. */
write8(ibase + ILB_SERIRQ_CNTL, (1 << 7));
#if !CONFIG(SERIRQ_CONTINUOUS_MODE)
write8(ibase + ILB_SERIRQ_CNTL, 0);
#endif
}
/*
* Write PCI config space IRQ assignments. PCI devices have the INT_LINE
* (0x3C) and INT_PIN (0x3D) registers which report interrupt routing
* information to operating systems and drivers. The INT_PIN register is
* generally read only and reports which interrupt pin A - D it uses. The
* INT_LINE register is configurable and reports which IRQ (generally the
* PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling
* on devices that are downstream on a PCI bridge into account.
*
* This function will loop through all enabled PCI devices and program the
* INT_LINE register with the correct PIC IRQ number for the INT_PIN that it
* uses. It then configures each interrupt in the pic to be level triggered.
*/
static void write_pci_config_irqs(void)
{
struct device *irq_dev;
struct device *targ_dev;
uint8_t int_line = 0;
uint8_t original_int_pin = 0;
uint8_t new_int_pin = 0;
uint16_t current_bdf = 0;
uint16_t parent_bdf = 0;
uint8_t pirq = 0;
uint8_t device_num = 0;
const struct rangeley_irq_route *ir = &global_rangeley_irq_route;
if (ir == NULL) {
printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because"
" 'global_rangeley_irq_route' structure does not exist\n");
return;
}
/*
* Loop through all enabled devices and program their
* INT_LINE, INT_PIN registers from values taken from
* the Interrupt Route registers in the ILB
*/
printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n");
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
if ((irq_dev->path.type != DEVICE_PATH_PCI) ||
(!irq_dev->enabled))
continue;
current_bdf = irq_dev->path.pci.devfn |
irq_dev->bus->secondary << 8;
/*
* Step 1: Get the INT_PIN and device structure to look for
* in the pirq_data table defined in the mainboard directory.
*/
targ_dev = NULL;
new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev);
if (targ_dev == NULL || new_int_pin < 1)
continue;
/* Get the original INT_PIN for record keeping */
original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
parent_bdf = targ_dev->path.pci.devfn
| targ_dev->bus->secondary << 8;
device_num = PCI_SLOT(parent_bdf);
if (ir->pcidev[device_num] == 0) {
printk(BIOS_WARNING,
"Warning: PCI Device %d does not have an IRQ entry, skipping it\n",
device_num);
continue;
}
/* Find the PIRQ that is attached to the INT_PIN this device uses */
pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0xF;
/* Get the INT_LINE this device/function will use */
int_line = ir->pic[pirq];
if (int_line != PIRQ_PIC_IRQDISABLE) {
/* Set this IRQ to level triggered since it is used by a PCI device */
i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED);
/* Set the Interrupt Line register in PCI config space */
pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
} else {
/* Set the Interrupt line register as "unknown or unused" */
pci_write_config8(irq_dev, PCI_INTERRUPT_LINE,
PIRQ_PIC_UNKNOWN_UNUSED);
}
printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n",
original_int_pin, pin_to_str(original_int_pin));
if (parent_bdf != current_bdf)
printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n",
new_int_pin, pin_to_str(new_int_pin));
printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n"
"\tINT_LINE\t: 0x%X (IRQ %d)\n",
'A' + pirq, int_line, int_line);
}
printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n");
}
static void soc_pirq_init(struct device *dev)
{
int i, j;
int pirq;
u8 *ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
u8 *pr_base = ibase + 0x08;
u16 *ir_base = (u16 *)(ibase + 0x20);
u32 *actl = (u32 *)ibase;
const struct rangeley_irq_route *ir = &global_rangeley_irq_route;
/* Set up the PIRQ PIC routing based on static config. */
printk(BIOS_SPEW, "Start writing IRQ assignments\n"
"PIRQ\tA\tB\tC\tD\tE\tF\tG\tH\n"
"IRQ ");
for (i = 0; i < NUM_PIRQS; i++) {
write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]);
printk(BIOS_SPEW, "\t%d", ir->pic[i]);
}
printk(BIOS_SPEW, "\n\n");
/* Set up the per device PIRQ routing based on static config. */
printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n"
"Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n");
for (i = 0; i < NUM_OF_PCI_DEVS; i++) {
write16(ir_base + i, ir->pcidev[i]);
/* If the entry is more than just 0, print it out */
if (ir->pcidev[i]) {
printk(BIOS_SPEW, " %d: ", i);
for (j = 0; j < 4; j++) {
pirq = (ir->pcidev[i] >> (j * 4)) & 0xF;
printk(BIOS_SPEW, "\t%-4c (%d)", 'A' + pirq, ir->pic[pirq]);
}
printk(BIOS_SPEW, "\n");
}
}
/* Route SCI to IRQ9 */
write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9);
printk(BIOS_SPEW, "Finished writing IRQ assignments\n");
/* Write IRQ assignments to PCI config space */
write_pci_config_irqs();
}
static void soc_power_options(struct device *dev)
{
u8 reg8;
u16 pmbase;
u32 reg32;
/* Get the chip configuration */
config_t *config = dev->chip_info;
int nmi_option;
/* Set up NMI on errors. */
reg8 = inb(0x61);
reg8 &= 0x0f; /* Higher Nibble must be 0 */
reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
// reg8 &= ~(1 << 2); /* PCI SERR# Enable */
reg8 |= (1 << 2); /* PCI SERR# Disable for now */
outb(reg8, 0x61);
reg8 = inb(0x70);
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {
printk(BIOS_INFO, "NMI sources enabled.\n");
reg8 &= ~(1 << 7); /* Set NMI. */
} else {
printk(BIOS_INFO, "NMI sources disabled.\n");
reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
}
outb(reg8, 0x70);
pmbase = pci_read_config16(dev, ABASE) & ~0xf;
outl(config->gpe0_en, pmbase + GPE0_EN);
outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
/* Set up power management block and determine sleep mode */
reg32 = inl(pmbase + PM1_CNT); // PM1_CNT
reg32 &= ~(7 << 10); // SLP_TYP
reg32 |= (1 << 0); // SCI_EN
outl(reg32, pmbase + PM1_CNT);
}
/* Disable the HPET, Clear the counter, and re-enable it. */
static void enable_hpet(void)
{
write8((u8 *)HPET_GCFG, 0x00);
write32((u32 *)HPET_MCV, 0x00000000);
write32((u32 *)(HPET_MCV + 0x04), 0x00000000);
write8((u8 *)HPET_GCFG, 0x01);
}
static void soc_disable_smm_only_flashing(struct device *dev)
{
u8 reg8;
printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
reg8 &= ~(1 << 5);
pci_write_config8(dev, 0xdc, reg8);
}
static void lpc_init(struct device *dev)
{
printk(BIOS_DEBUG, "soc: lpc_init\n");
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
/* IO APIC initialization. */
soc_enable_apic(dev);
soc_enable_serial_irqs(dev);
/* Setup the PIRQ. */
soc_pirq_init(dev);
/* Setup power options. */
soc_power_options(dev);
/* Initialize power management */
switch (soc_silicon_type()) {
case SOC_TYPE_RANGELEY:
break;
default:
printk(BIOS_DEBUG, "Unknown Chipset: 0x%04x\n", dev->device);
}
/* Initialize ISA DMA. */
isa_dma_init();
/* Initialize the High Precision Event Timers, if present. */
enable_hpet();
setup_i8259();
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
soc_disable_smm_only_flashing(dev);
}
static void soc_lpc_read_resources(struct device *dev)
{
struct resource *res;
config_t *config = dev->chip_info;
u8 io_index = 0;
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
/* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* Set SOC IO decode ranges if required.*/
if ((config->gen1_dec & 0xFFFC) > 0x1000) {
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
res->base = config->gen1_dec & 0xFFFC;
res->size = (config->gen1_dec >> 16) & 0xFC;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
if ((config->gen2_dec & 0xFFFC) > 0x1000) {
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
res->base = config->gen2_dec & 0xFFFC;
res->size = (config->gen2_dec >> 16) & 0xFC;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
if ((config->gen3_dec & 0xFFFC) > 0x1000) {
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
res->base = config->gen3_dec & 0xFFFC;
res->size = (config->gen3_dec >> 16) & 0xFC;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
if ((config->gen4_dec & 0xFFFC) > 0x1000) {
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
res->base = config->gen4_dec & 0xFFFC;
res->size = (config->gen4_dec >> 16) & 0xFC;
res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
}
static void soc_lpc_enable_resources(struct device *dev)
{
return pci_dev_enable_resources(dev);
}
static void soc_lpc_enable(struct device *dev)
{
soc_enable(dev);
}
static void southbridge_inject_dsdt(struct device *dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs) {
memset(gnvs, 0, sizeof(*gnvs));
acpi_create_gnvs(gnvs);
/* And tell SMI about it */
if (CONFIG(HAVE_SMI_HANDLER))
smm_setup_structures(gnvs, NULL, NULL);
/* Add it to DSDT. */
acpigen_write_scope("\\");
acpigen_write_name_dword("NVSA", (u32) gnvs);
acpigen_pop_len();
}
}
static struct pci_operations pci_ops = {
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations device_ops = {
.read_resources = soc_lpc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = soc_lpc_enable_resources,
.init = lpc_init,
.write_acpi_tables = acpi_write_hpet,
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
.enable = soc_lpc_enable,
.scan_bus = scan_static_bus,
.ops_pci = &pci_ops,
};
/* IDs for LPC device of Intel 89xx Series Chipset */
static const unsigned short pci_device_ids[] = { 0x1F38, 0x1F39, 0x1F3A, 0x1F3B,
0 };
static const struct pci_driver soc_lpc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};

151
src/southbridge/intel/fsp_rangeley/nvs.h
View File

@ -1,151 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2011 Google Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
typedef struct {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
u8 prm0; /* 0x03 - SMI function call parameter */
u8 prm1; /* 0x04 - SMI function call parameter */
u8 scif; /* 0x05 - SCI function call (via _L00) */
u8 prm2; /* 0x06 - SCI function call parameter */
u8 prm3; /* 0x07 - SCI function call parameter */
u8 lckf; /* 0x08 - Global Lock function for EC */
u8 prm4; /* 0x09 - Lock function parameter */
u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */
u8 pwrs; /* 0x10 - Power state (AC = 1) */
/* Thermal policy */
u8 tlvl; /* 0x11 - Throttle Level Limit */
u8 flvl; /* 0x12 - Current FAN Level */
u8 tcrt; /* 0x13 - Critical Threshold */
u8 tpsv; /* 0x14 - Passive Threshold */
u8 tmax; /* 0x15 - CPU Tj_max */
u8 f0of; /* 0x16 - FAN 0 OFF Threshold */
u8 f0on; /* 0x17 - FAN 0 ON Threshold */
u8 f0pw; /* 0x18 - FAN 0 PWM value */
u8 f1of; /* 0x19 - FAN 1 OFF Threshold */
u8 f1on; /* 0x1a - FAN 1 ON Threshold */
u8 f1pw; /* 0x1b - FAN 1 PWM value */
u8 f2of; /* 0x1c - FAN 2 OFF Threshold */
u8 f2on; /* 0x1d - FAN 2 ON Threshold */
u8 f2pw; /* 0x1e - FAN 2 PWM value */
u8 f3of; /* 0x1f - FAN 3 OFF Threshold */
u8 f3on; /* 0x20 - FAN 3 ON Threshold */
u8 f3pw; /* 0x21 - FAN 3 PWM value */
u8 f4of; /* 0x22 - FAN 4 OFF Threshold */
u8 f4on; /* 0x23 - FAN 4 ON Threshold */
u8 f4pw; /* 0x24 - FAN 4 PWM value */
u8 tmps; /* 0x25 - Temperature Sensor ID */
u8 rsvd3[2];
/* Processor Identification */
u8 apic; /* 0x28 - APIC enabled */
u8 mpen; /* 0x29 - MP capable/enabled */
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
u8 ppcm; /* 0x2c - Max. PPC state */
u8 pcnt; /* 0x2d - Processor Count */
u8 rsvd4[4];
/* Super I/O & CMOS config */
u8 natp; /* 0x32 - SIO type */
u8 s5u0; /* 0x33 - Enable USB0 in S5 */
u8 s5u1; /* 0x34 - Enable USB1 in S5 */
u8 s3u0; /* 0x35 - Enable USB0 in S3 */
u8 s3u1; /* 0x36 - Enable USB1 in S3 */
u8 s33g; /* 0x37 - Enable S3 in 3G */
u32 obsolete_cmem; /* 0x38 - CBMEM TOC */
/* Integrated Graphics Device */
u8 igds; /* 0x3c - IGD state */
u8 tlst; /* 0x3d - Display Toggle List Pointer */
u8 cadl; /* 0x3e - currently attached devices */
u8 padl; /* 0x3f - previously attached devices */
u16 cste; /* 0x40 - current display state */
u16 nste; /* 0x42 - next display state */
u16 sste; /* 0x44 - set display state */
u8 ndid; /* 0x46 - number of device ids */
u32 did[5]; /* 0x47 - 5b device id 1..5 */
u8 rsvd5[0x9];
/* Backlight Control */
u8 blcs; /* 0x64 - Backlight Control possible */
u8 brtl;
u8 odds;
u8 rsvd6[0x7];
/* Ambient Light Sensors*/
u8 alse; /* 0x6e - ALS enable */
u8 alaf;
u8 llow;
u8 lhih;
u8 rsvd7[0x6];
/* Extended Mobile Access */
u8 emae; /* 0x78 - EMA enable */
u16 emap; /* 0x79 - EMA pointer */
u16 emal; /* 0x7a - EMA Length */
u8 rsvd8[0x5];
/* MEF */
u8 mefe; /* 0x82 - MEF enable */
u8 rsvd9[0x9];
/* TPM support */
u8 tpmp; /* 0x8c - TPM */
u8 tpme;
u8 rsvd10[8];
/* SATA */
u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */
u8 gtf1[7];
u8 gtf2[7];
u8 idem;
u8 idet;
u8 rsvd11[7];
/* IGD OpRegion (not implemented yet) */
u32 aslb; /* 0xb4 - IGD OpRegion Base Address */
u8 ibtt; /* 0xb8 - IGD boot type */
u8 ipat; /* 0xb9 - IGD panel type */
u8 itvf; /* 0xba - IGD TV format */
u8 itvm; /* 0xbb - IGD TV minor format */
u8 ipsc; /* 0xbc - IGD Panel Scaling */
u8 iblc; /* 0xbd - IGD BLC configuration */
u8 ibia; /* 0xbe - IGD BIA configuration */
u8 issc; /* 0xbf - IGD SSC configuration */
u8 i409; /* 0xc0 - IGD 0409 modified settings */
u8 i509; /* 0xc1 - IGD 0509 modified settings */
u8 i609; /* 0xc2 - IGD 0609 modified settings */
u8 i709; /* 0xc3 - IGD 0709 modified settings */
u8 idmm; /* 0xc4 - IGD Power Conservation */
u8 idms; /* 0xc5 - IGD DVMT memory size */
u8 if1e; /* 0xc6 - IGD Function 1 Enable */
u8 hvco; /* 0xc7 - IGD HPLL VCO */
u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
u8 pavp; /* 0xe9 - IGD PAVP data */
u8 rsvd12; /* 0xea - rsvd */
u8 oscc; /* 0xeb - PCIe OSC control */
u8 npce; /* 0xec - native pcie support */
u8 plfl; /* 0xed - platform flavor */
u8 brev; /* 0xee - board revision */
u8 dpbm; /* 0xef - digital port b mode */
u8 dpcm; /* 0xf0 - digital port c mode */
u8 dpdm; /* 0xf1 - digital port c mode */
u8 alfp; /* 0xf2 - active lfp */
u8 imon; /* 0xf3 - current graphics turbo imon value */
u8 mmio; /* 0xf4 - 64bit mmio support */
u8 rsvd13[11]; /* 0xf5 - rsvd */
} __packed global_nvs_t;
void acpi_create_gnvs(global_nvs_t *gnvs);
/* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void);

135
src/southbridge/intel/fsp_rangeley/pci_devs.h
View File

@ -1,135 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _RANGELEY_PCI_DEVS_H_
#define _RANGELEY_PCI_DEVS_H_
#include <device/pci_def.h>
#define BUS0 0
/* All these devices live on bus 0 with the associated device and function */
/* Host Bridge */
#define SOC_DEV 0x0
#define SOC_FUNC 0
# define SOC_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC)
/* PCIE Port 1 */
#define PCIE_PORT1_DEV 0x1
#define PCIE_PORT1_FUNC 0
# define SOC_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_PORT1_DEV,PCIE_PORT1_FUNC)
/* PCIE Port 2 */
#define PCIE_PORT2_DEV 0x2
#define PCIE_PORT2_FUNC 0
# define SOC_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_PORT2_DEV,PCIE_PORT2_FUNC)
/* PCIE Port 3 */
#define PCIE_PORT3_DEV 0x3
#define PCIE_PORT3_FUNC 0
# define SOC_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_PORT3_DEV,PCIE_PORT3_FUNC)
/* PCIE Port 4 */
#define PCIE_PORT4_DEV 0x4
#define PCIE_PORT4_FUNC 0
# define SOC_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_PORT4_DEV,PCIE_PORT4_FUNC)
/* Host Bridge, Fabric, and RAS Registers */
#define HOST_BRIDGE_DEV 0xe
#define HOST_BRIDGE_FUNC 0
# define SOC_DEVFN_HOST_BRIDGE PCI_DEVFN(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC)
/* Root Complex Event Collector (RCEC) */
#define RCEC_DEV 0xf
#define RCEC_FUNC 0
# define SOC_DEVFN_RCEC PCI_DEVFN(RCEC_DEV,RCEC_FUNC)
/* SMBus 2.0 1 */
#define SMBUS1_DEV 0x13
#define SMBUS1_FUNC 0
# define SOC_DEVFN_SMBUS1 PCI_DEVFN(SMBUS1_DEV,SMBUS1_FUNC)
/* Gigabit Ethernet (GbE) */
#define GBE_DEV 0x14
#define GBE1_DEV GBE_DEV
#define GBE1_FUNC 0
# define SOC_DEVFN_GBE1 PCI_DEVFN(GBE1_DEV,GBE1_FUNC)
#define GBE2_DEV GBE_DEV
#define GBE2_FUNC 1
# define SOC_DEVFN_GBE2 PCI_DEVFN(GBE2_DEV,GBE2_FUNC)
#define GBE3_DEV GBE_DEV
#define GBE3_FUNC 2
# define SOC_DEVFN_GBE3 PCI_DEVFN(GBE3_DEV,GBE3_FUNC)
#define GBE4_DEV GBE_DEV
#define GBE4_FUNC 3
# define SOC_DEVFN_GBE4 PCI_DEVFN(GBE4_DEV,GBE4_FUNC)
/* USB 2.0 */
#define USB2_DEV 0x16
#define USB2_FUNC 0
# define SOC_DEVFN_USB2 PCI_DEVFN(USB2_DEV,USB2_FUNC)
/* SATA Gen 2 */
#define SATA2_DEV 0x17
#define SATA2_FUNC 0
# define SOC_DEVFN_SATA2 PCI_DEVFN(SATA2_DEV,SATA2_FUNC)
/* SATA Gen 3 */
#define SATA3_DEV 0x18
#define SATA3_FUNC 0
# define SOC_DEVFN_SATA3 PCI_DEVFN(SATA3_DEV,SATA3_FUNC)
/* Platform Control Unit (PCU) */
#define PCU_DEV 0x1f
/* Low Pin Count (LPC/ISA) */
#define LPC_DEV PCU_DEV
#define LPC_FUNC 0
# define SOC_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC)
# define LPC_BDF PCI_DEV(BUS0, LPC_DEV, LPC_FUNC)
/* SMBus 2.0 0 */
#define SMBUS0_DEV PCU_DEV
#define SMBUS0_FUNC 3
# define SOC_DEVFN_SMBUS0 PCI_DEVFN(SMBUS0_DEV,SMBUS0_FUNC)
/* Intel QuickAssist Integrated Accelerator (IQIA) */
#define IQAT_DEV 0xb
#define IQAT_FUNC 0
# define SOC_DEVFN_IQAT PCI_DEVFN(IQAT_DEV,IQAT_FUNC)
#define SOC_DEVID 0x1f08
#define PCIE_PORT1_DEVID 0x1f10
#define PCIE_PORT2_DEVID 0x1f11
#define PCIE_PORT3_DEVID 0x1f12
#define PCIE_PORT4_DEVID 0x1f13
#define HOST_BRIDGE_DEVID 0x1f14
#define RCEC_DEVID 0x1f16
#define SMBUS1_DEVID 0x1f15
#define GBE_DEVID 0x1f41
#define GBE1_DEVID GBE_DEVID
#define GBE2_DEVID GBE_DEVID
#define GBE3_DEVID GBE_DEVID
#define GBE4_DEVID GBE_DEVID
#define USB2_DEVID 0x1f2c
#define SATA2_DEVID 0x1f22
#define SATA3_DEVID 0x1f32
#define LPC_DEVID 0x1f38
#define SMBUS0_DEVID 0x1f3c
#define IQAT_DEVID 0x1f18
#endif /* _RANGELEY_PCI_DEVS_H_ */

137
src/southbridge/intel/fsp_rangeley/romstage.c
View File

@ -1,137 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <timestamp.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <cbmem.h>
#include <console/console.h>
#include <console/usb.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <program_loading.h>
#include <northbridge/intel/fsp_rangeley/northbridge.h>
#include "southbridge/intel/fsp_rangeley/soc.h"
#include "southbridge/intel/fsp_rangeley/gpio.h"
#include "southbridge/intel/fsp_rangeley/romstage.h"
#include <cpu/x86/msr.h>
#include <cpu/x86/smm.h>
#include "gpio.h"
void main(FSP_INFO_HEADER *fsp_info_header)
{
uint32_t fd_mask = 0;
uint32_t *func_dis = (uint32_t *)(DEFAULT_PBASE + PBASE_FUNC_DIS);
/*
* Do not use the Serial Console before it is setup.
* This causes the I/O to clog and a side effect is
* that the reset button stops functioning. So
* instead just use outb so it doesn't output to the
* console when CONFIG_CONSOLE_POST.
*/
outb(0x40, 0x80);
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
/* Rangeley UART POR state is enabled */
console_init();
post_code(0x41);
/* Enable GPIOs BAR */
pci_write_config32(SOC_LPC_DEV, GBASE, DEFAULT_GPIOBASE|0x02);
early_mainboard_romstage_entry();
post_code(0x42);
rangeley_sb_early_initialization();
post_code(0x46);
/* Program any required function disables */
get_func_disables(&fd_mask);
if (fd_mask != 0) {
write32(func_dis, read32(func_dis) | fd_mask);
/* Ensure posted write hits. */
read32(func_dis);
}
timestamp_add_now(TS_BEFORE_INITRAM);
/*
* Call early init to initialize memory and chipset. This function returns
* to the romstage_main_continue function with a pointer to the HOB
* structure.
*/
post_code(0x47);
printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n");
fsp_early_init(fsp_info_header);
die("Uh Oh! fsp_early_init should not return here.\n");
}
/*******************************************************************************
* The FSP early_init function returns to this function.
* Memory is setup and the stack is set by the FSP.
*/
void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
void *cbmem_hob_ptr;
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x48);
printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n",
__func__, (u32) status, (u32) hob_list_ptr);
/* FSP reconfigures USB, so reinit it to have debug */
if (CONFIG(USBDEBUG_IN_PRE_RAM))
usbdebug_hw_init(true);
printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);
post_code(0x4b);
late_mainboard_romstage_entry();
post_code(0x4c);
/* Decode E0000 and F0000 segment to DRAM */
sideband_write(B_UNIT, BMISC, sideband_read(B_UNIT, BMISC) | (1 << 1) | (1 << 0));
cbmem_recovery(0);
/* Save the HOB pointer in CBMEM to be used in ramstage*/
cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr));
if (cbmem_hob_ptr == NULL)
die("Could not allocate cbmem for HOB pointer");
*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
post_code(0x4e);
if (CONFIG(SMM_TSEG))
smm_list_regions();
/* Load the ramstage. */
post_code(0x4f);
run_ramstage();
while (1);
}
uint64_t get_initial_timestamp(void)
{
return 0;
}

28
src/southbridge/intel/fsp_rangeley/romstage.h
View File

@ -1,28 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _RANGELEY_ROMSTAGE_H_
#define _RANGELEY_ROMSTAGE_H_
#include <stdint.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
void main(FSP_INFO_HEADER *fsp_info_header);
void early_mainboard_romstage_entry(void);
void late_mainboard_romstage_entry(void);
void get_func_disables(uint32_t *mask);
#endif /* _RANGELEY_ROMSTAGE_H_ */

122
src/southbridge/intel/fsp_rangeley/sata.c
View File

@ -1,122 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include "chip.h"
#include "soc.h"
typedef struct southbridge_intel_fsp_rangeley_config config_t;
static void sata_init(struct device *dev)
{
u32 reg32;
u16 reg16;
u32 *abar;
/* Get the chip configuration */
config_t *config = dev->chip_info;
printk(BIOS_DEBUG, "SATA: Initializing...\n");
if (config == NULL) {
printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n");
return;
}
/* SATA configuration is handled by the FSP */
/* Enable BARs */
pci_write_config16(dev, PCI_COMMAND, 0x0007);
if (config->ide_legacy_combined) {
printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");
/* Set the controller mode */
reg16 = pci_read_config16(dev, SATA_MAP);
reg16 &= ~(3 << 6);
pci_write_config16(dev, SATA_MAP, reg16);
/* No AHCI: clear AHCI base */
pci_write_config32(dev, 0x24, 0x00000000);
/* And without AHCI BAR no memory decoding */
reg16 = pci_read_config16(dev, PCI_COMMAND);
reg16 &= ~PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, reg16);
} else if (config->sata_ahci) {
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
/* Set the controller mode */
reg16 = pci_read_config16(dev, SATA_MAP);
reg16 &= ~(3 << 6);
reg16 |= (1 << 6);
pci_write_config16(dev, SATA_MAP, reg16);
/* Initialize AHCI memory-mapped space */
abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* Enable AHCI Mode */
reg32 = read32(abar + 0x01);
reg32 |= (1 << 31);
write32(abar + 0x01, reg32);
} else {
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
}
/* Spin up the drives as early as possible via the Port Enable */
reg16 = pci_read_config16(dev, SATA_PSC);
reg16 &= ~0x3f;
pci_write_config16(dev, SATA_PSC, reg16);
reg16 = pci_read_config16(dev, SATA_PSC);
reg16 |= 0x3f;
pci_write_config16(dev, SATA_PSC, reg16);
}
static void sata_enable(struct device *dev)
{
}
static struct pci_operations sata_pci_ops = {
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations sata_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = sata_init,
.enable = sata_enable,
.scan_bus = 0,
.ops_pci = &sata_pci_ops,
};
static const unsigned short pci_device_ids[] = { 0x1f20, 0x1f21, 0x1f22, 0x1f23,
0x1f30, 0x1f31, 0x1f32, 0x1f33,
0 };
static const struct pci_driver soc_sata __pci_driver = {
.ops = &sata_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};

81
src/southbridge/intel/fsp_rangeley/smbus.c
View File

@ -1,81 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <device/path.h>
#include <device/smbus.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <southbridge/intel/common/smbus.h>
#include "soc.h"
static int lsmbus_read_byte(struct device *dev, u8 address)
{
u16 device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
return do_smbus_read_byte(res->base, device, address);
}
static struct smbus_bus_operations lops_smbus_bus = {
.read_byte = lsmbus_read_byte,
};
static struct pci_operations smbus_pci_ops = {
.set_subsystem = pci_dev_set_subsystem,
};
static void rangeley_smbus_read_resources(struct device *dev)
{
struct resource *res;
/*
* The SMBus has two BARS.
* BAR0 - MMIO, not used at boot time
* BAR4 - IO, Used to talk to the SMBUS during boot, so we maintain
* the default setting in the resource allocator.
*/
res = pci_get_resource(dev, PCI_BASE_ADDRESS_0);
res = new_resource(dev, PCI_BASE_ADDRESS_4);
res->base = SMBUS_IO_BASE;
res->size = 32;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static struct device_operations smbus_ops = {
.read_resources = rangeley_smbus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = scan_smbus,
.ops_smbus_bus = &lops_smbus_bus,
.ops_pci = &smbus_pci_ops,
};
static const struct pci_driver rangeley_smbus __pci_driver = {
.ops = &smbus_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x1F3C,
};

96
src/southbridge/intel/fsp_rangeley/soc.c
View File

@ -1,96 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include "soc.h"
static int soc_revision_id = -1;
static int soc_type = -1;
int soc_silicon_revision(void)
{
if (soc_revision_id < 0)
soc_revision_id = pci_read_config8(
pcidev_on_root(0x1f, 0),
PCI_REVISION_ID);
return soc_revision_id;
}
int soc_silicon_type(void)
{
if (soc_type < 0)
soc_type = pci_read_config8(
pcidev_on_root(0x1f, 0),
PCI_DEVICE_ID + 1);
return soc_type;
}
int soc_silicon_supported(int type, int rev)
{
int cur_type = soc_silicon_type();
int cur_rev = soc_silicon_revision();
switch (type) {
case SOC_TYPE_RANGELEY:
if (cur_type == SOC_TYPE_RANGELEY && cur_rev >= rev)
return 1;
}
return 0;
}
/* Set bit in Function Disable register to hide this device */
static void soc_hide_devfn(unsigned int devfn)
{
/* TODO Function Disable. */
}
void soc_enable(struct device *dev)
{
u32 reg32;
if (!dev->enabled) {
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* Ensure memory, IO, and bus master are all disabled */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Hide this device if possible */
soc_hide_devfn(dev->path.pci.devfn);
} else {
/* Enable SERR */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
}
}
struct chip_operations southbridge_intel_fsp_rangeley_ops = {
CHIP_NAME("Intel Rangeley Southbridge")
.enable_dev = soc_enable,
};

401
src/southbridge/intel/fsp_rangeley/soc.h
View File

@ -1,401 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOUTHBRIDGE_INTEL_RANGELEY_SOC_H
#define SOUTHBRIDGE_INTEL_RANGELEY_SOC_H
#include <arch/acpi.h>
/* SOC types */
#define SOC_TYPE_RANGELEY 0x1F
/*
* It does not matter where we put the SMBus I/O base, as long as we
* keep it consistent and don't interfere with other devices. Stage2
* will relocate this anyways.
* Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
* again. But handling static BARs is a generic problem that should be
* solved in the device allocator.
*/
/* Southbridge internal device IO BARs (Set to match FSP settings) */
#define SMBUS_IO_BASE 0xefa0
#define SMBUS_SLAVE_ADDR 0x24
#define DEFAULT_GPIOBASE 0x0500
#define DEFAULT_ABASE 0x0400
/* Southbridge internal device MEM BARs (Set to match FSP settings) */
#define DEFAULT_IBASE 0xfed08000
#define DEFAULT_PBASE 0xfed03000
#include <southbridge/intel/common/rcba.h>
#ifndef __ACPI__
#define DEBUG_PERIODIC_SMIS 0
void intel_soc_finalize_smm(void);
#if !defined(__ROMCC__)
#include <device/device.h>
void soc_enable(struct device *dev);
void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt);
#endif
int soc_silicon_revision(void);
int soc_silicon_type(void);
int soc_silicon_supported(int type, int rev);
void soc_log_state(void);
void enable_smbus(void);
void enable_usb_bar(void);
void rangeley_sb_early_initialization(void);
#if ENV_ROMSTAGE
int smbus_read_byte(unsigned int device, unsigned int address);
#endif
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
#define SOC_EHCI1_DEV PCI_DEV(0, 0x1d, 0)
#define PCIE_DEV_SLOT0 1
#define PCIE_DEV_SLOT1 2
#define PCIE_DEV_SLOT2 3
#define PCIE_DEV_SLOT3 4
/* PCI Configuration Space (D31:F0): LPC */
#define SOC_LPC_DEV PCI_DEV(0, 0x1f, 0)
#define SOC_LPC_DEVFN PCI_DEVFN(0x1f, 0)
/* Southbridge IO BARs */
#define ABASE 0x40 /* IO BAR */
#define PBASE 0x44 /* MEM BAR */
#define GBASE 0x48 /* IO BAR */
#define IOBASE 0x4C /* MEM BAR */
#define IBASE 0x50 /* MEM BAR */
#define SBASE 0x54 /* MEM BAR */
#define MPBASE 0x58 /* MEM BAR */
#define SET_BAR_ENABLE 0x02
/* Rangeley ILB defines */
#define ILB_ACTL 0
#define ILB_PIRQA_ROUT 0x8
#define ILB_PIRQB_ROUT 0x9
#define ILB_PIRQC_ROUT 0xA
#define ILB_PIRQD_ROUT 0xB
#define ILB_PIRQE_ROUT 0xC
#define ILB_PIRQF_ROUT 0xD
#define ILB_PIRQG_ROUT 0xE
#define ILB_PIRQH_ROUT 0xF
#define ILB_SERIRQ_CNTL 0x10
#define ILB_IR00 0x20
#define ILB_IR01 0x22
#define ILB_IR02 0x24
#define ILB_IR03 0x26
#define ILB_IR04 0x28
#define ILB_IR05 0x2A
#define ILB_IR06 0x2C
#define ILB_IR07 0x2E
#define ILB_IR08 0x30
#define ILB_IR09 0x32
#define ILB_IR10 0x34
#define ILB_IR11 0x36
#define ILB_IR12 0x38
#define ILB_IR13 0x3A
#define ILB_IR14 0x3C
#define ILB_IR15 0x3E
#define ILB_IR16 0x40
#define ILB_IR17 0x42
#define ILB_IR18 0x44
#define ILB_IR19 0x46
#define ILB_IR20 0x48
#define ILB_IR21 0x4A
#define ILB_IR22 0x4C
#define ILB_IR23 0x4E
#define ILB_IR24 0x50
#define ILB_IR25 0x52
#define ILB_IR26 0x54
#define ILB_IR27 0x56
#define ILB_IR28 0x58
#define ILB_IR29 0x5A
#define ILB_IR30 0x5C
#define ILB_IR31 0x5E
#define ILB_OIC 0x60
/* PCI Configuration Space (D31:F2/5) */
#define SOC_SATA_DEV PCI_DEV(0, 0x17, 0)
#define SOC_SATA2_DEV PCI_DEV(0, 0x18, 0)
#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
#define SATA_SP 0xd0 /* Scratchpad */
#define SATA_MAP 0x90
#define SATA_PSC 0x92
/* SATA IOBP Registers */
#define SATA_IOBP_SP0G3IR 0xea000151
#define SATA_IOBP_SP1G3IR 0xea000051
/* PCI Configuration Space (D31:F3): SMBus */
#define SOC_SMBUS_DEV PCI_DEV(0, 0x1f, 3)
#define SMB_BASE 0x20
#define HOSTC 0x40
#define SMB_RCV_SLVA 0x09
/* HOSTC bits */
#define I2C_EN (1 << 2)
#define SMB_SMI_EN (1 << 1)
#define HST_EN (1 << 0)
/* Root Port configuration space hide */
#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
/* Get the function number assigned to a Root Port */
#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)
/* Set the function number for a Root Port */
#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4))
/* Root Port function number mask */
#define RPFN_FNMASK(port) (7 << ((port) * 4))
#define NOINT 0
#define INTA 1
#define INTB 2
#define INTC 3
#define INTD 4
#define DIR_IDR 12 /* Interrupt D Pin Offset */
#define DIR_ICR 8 /* Interrupt C Pin Offset */
#define DIR_IBR 4 /* Interrupt B Pin Offset */
#define DIR_IAR 0 /* Interrupt A Pin Offset */
#define PIRQA 0
#define PIRQB 1
#define PIRQC 2
#define PIRQD 3
#define PIRQE 4
#define PIRQF 5
#define PIRQG 6
#define PIRQH 7
/* IO Buffer Programming */
#define IOBPIRI 0x2330
#define IOBPD 0x2334
#define IOBPS 0x2338
#define IOBPS_RW_BX ((1 << 9)|(1 << 10))
#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
#define DIR_ROUTE(x,a,b,c,d) \
RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
((b) << DIR_IBR) | ((a) << DIR_IAR))
/* PBASE Registers */
#define PMC_CFG 0x08
#define SPS (1 << 5)
#define NO_REBOOT (1 << 4)
#define SX_ENT_TO_EN (1 << 3)
#define TIMING_T581 (1 << 0)
#define GEN_PMCON1 0x20
# define DISB (1 << 23)
# define MEM_SR (1 << 21)
# define SRS (1 << 20)
# define CTS (1 << 19)
# define MS4V (1 << 18)
# define PWR_FLR (1 << 16)
# define PME_B0_S5_DIS (1 << 15)
# define SUS_PWR_FLR (1 << 14)
# define WOL_EN_OVRD (1 << 13)
# define DIS_SLP_X_STRCH_SUS_UP (1 << 12)
# define GEN_RST_STS (1 << 9)
# define RPS (1 << 2)
# define AFTERG3_EN (1 << 0)
/* Function Disable PBASE + 0x34 */
#define PBASE_FUNC_DIS 0x34
#define PBASE_DISABLE_QUICKASSIST (1 << 0)
#define PBASE_DISABLE_GBE(x) (1 << (12 + x))
#define PBASE_DISABLE_SATA2 (1 << 22)
#define PBASE_DISABLE_EHCI (1 << 23)
#define PBASE_DISABLE_SATA3 (1 << 23)
/* GPIOBASE */
#define GPIO_SC_USE_SEL 0x00
#define GPIO_SC_IO_SEL 0x04
#define GPIO_SC_GP_LVL 0x08
#define GPIO_SC_TPE 0x0c
#define GPIO_SC_TNE 0x10
#define GPIO_SC_TS 0x14
#define GPIO_SUS_USE_SEL 0x80
#define GPIO_SUS_IO_SEL 0x84
#define GPIO_SUS_GP_LVL 0x88
#define GPIO_SUS_TPE 0x8c
#define GPIO_SUS_TNE 0x90
#define GPIO_SUS_TS 0x94
#define GPIO_SUS_WE 0x98
/* IOBASE */
#define CFIO_PAD_CONF0 0x00
#define CFIO_PAD_CONF1 0x04
#define CFIO_PAD_VAL 0x08
#define CFIO_PAD_DFT 0x0C
/* ACPI BASE */
#define PM1_STS 0x00
#define WAK_STS (1 << 15)
#define PCIEXPWAK_STS (1 << 14)
#define PRBTNOR_STS (1 << 11)
#define RTC_STS (1 << 10)
#define PWRBTN_STS (1 << 8)
#define GBL_STS (1 << 5)
#define BM_STS (1 << 4)
#define TMROF_STS (1 << 0)
#define PM1_EN 0x02
#define PCIEXPWAK_DIS (1 << 14)
#define RTC_EN (1 << 10)
#define PWRBTN_EN (1 << 8)
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)
#define PM1_CNT 0x04
#define GBL_RLS (1 << 2)
#define BM_RLD (1 << 1)
#define SCI_EN (1 << 0)
#define PM1_TMR 0x08
#define PROC_CNT 0x10
#define LV2 0x14
#define LV3 0x15
#define LV4 0x16
#define PM2_CNT 0x50 // mobile only
#define GPE0_STS 0x20
#define PME_B0_STS (1 << 13)
#define PME_STS (1 << 11)
#define BATLOW_STS (1 << 10)
#define PCI_EXP_STS (1 << 9)
#define RI_STS (1 << 8)
#define SMB_WAK_STS (1 << 7)
#define TCOSCI_STS (1 << 6)
#define SWGPE_STS (1 << 2)
#define HOT_PLUG_STS (1 << 1)
#define GPE0_EN 0x28
#define PME_B0_EN (1 << 13)
#define PME_EN (1 << 11)
#define TCOSCI_EN (1 << 6)
#define SMI_EN 0x30
#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
#define MCSMI_EN (1 << 11) // Trap microcontroller range access
#define BIOS_RLS (1 << 7) // asserts SCI on bit set
#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
#define EOS (1 << 1) // End of SMI (deassert SMI#)
#define GBL_SMI_EN (1 << 0) // SMI# generation at all?
#define SMI_STS 0x34
#define ALT_GP_SMI_EN 0x38
#define ALT_GP_SMI_STS 0x3a
#define GPE_CNTL 0x42
#define DEVACT_STS 0x44
#define PM2A_CNT_BLK 0x50
#define SS_CNT 0x50
#define C3_RES 0x54
#define TCO1_STS 0x64
#define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66
#define TCO1_CNT 0x68
#define TCO_TMR_HALT (1 << 11)
#define TCO_LOCK (1 << 12)
/*
* SPI Opcode Menu setup for SPIBAR lockdown
* should support most common flash chips.
*/
#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
#define SPI_OPTYPE_0 0x01 /* Write, no address */
#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
#define SPI_OPTYPE_1 0x03 /* Write, address required */
#define SPI_OPMENU_2 0x03 /* READ: Read Data */
#define SPI_OPTYPE_2 0x02 /* Read, address required */
#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
#define SPI_OPTYPE_3 0x00 /* Read, no address */
#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
#define SPI_OPTYPE_4 0x03 /* Write, address required */
#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
#define SPI_OPTYPE_5 0x00 /* Read, no address */
#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
#define SPI_OPTYPE_6 0x03 /* Write, address required */
#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
#define SPI_OPTYPE_7 0x02 /* Read, address required */
#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
(SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
(SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
(SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
(SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
(SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */
#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */
#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */
#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
#define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */
#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */
#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */
#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */
#define SPIBAR_FADDR 0x08 /* SPI flash address */
#define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */
/* HPET Registers - Base is set in hardware to 0xFED00000 */
#define HPET_GCID 0xFED00000 /* General Capabilities and ID */
#define HPET_GCFG 0xFED00010 /* General Configuration */
#define HPET_GIS 0xFED00020 /* General Interrupt Status */
#define HPET_MCV 0xFED000F0 /* Main Counter Value */
#define HPET_T0C 0xFED00100 /* Timer 0 Configuration and Capabilities */
#define HPET_T0CV_L 0xFED00108 /* Lower Timer 0 Comparator Value */
#define HPET_T0CV_U 0xFED0010C /* Upper Timer 0 Comparator Value */
#define HPET_T1C 0xFED00120 /* Timer 1 Configuration and Capabilities */
#define HPET_T1CV 0xFED00128 /* Timer 1 Comparator Value */
#define HPET_T2C 0xFED00140 /* Timer 2 Configuration and Capabilities */
#define HPET_T2CV 0xFED00148 /* Timer 2 Comparator Value */
#endif /* __ACPI__ */
#endif /* SOUTHBRIDGE_INTEL_RANGELEY_SOC_H */

712
src/southbridge/intel/fsp_rangeley/spi.c
View File

@ -1,712 +0,0 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* Copyright (C) 2013, Intel Corporation.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* This file is derived from the flashrom project. */
#include <stdint.h>
#include <stdlib.h>
#include <commonlib/helpers.h>
#include <delay.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <spi_flash.h>
#include <spi-generic.h>
static int ich_status_poll(u16 bitmask, int wait_til_set);
typedef struct spi_slave ich_spi_slave;
static int ichspi_lock = 0;
typedef struct ich7_spi_regs {
uint16_t spis;
uint16_t spic;
uint32_t spia;
uint64_t spid[8];
uint64_t _pad;
uint32_t bbar;
uint16_t preop;
uint16_t optype;
uint8_t opmenu[8];
} __packed ich7_spi_regs;
typedef struct ich9_spi_regs {
uint32_t bfpr; // 0
uint16_t hsfs; // 4
uint16_t hsfc; // 6
uint32_t faddr; // 8
uint32_t _reserved0; // 0xC
uint32_t fdata[16]; // 0x10
uint32_t frap; // 0x50
uint32_t freg[5]; // 0x54
uint32_t _reserved1[3]; // 0x67
uint32_t pr[5]; // 0x74
uint32_t _reserved2[2]; // 0x88
uint8_t ssfs; // 0x90
uint8_t ssfc[3]; // 0x91
uint16_t preop; // 0x94
uint16_t optype; // 0x96
uint8_t opmenu[8]; // 0x98
uint32_t bbar; // 0xB0
uint8_t _reserved3[12];
uint32_t fdoc;
uint32_t fdod;
uint8_t _reserved4[8];
uint32_t afc;
uint32_t lvscc;
uint32_t uvscc;
uint8_t _reserved5[4];
uint32_t fpb;
uint8_t _reserved6[28];
uint32_t srdl;
uint32_t srdc;
uint32_t srd;
} __packed ich9_spi_regs;
typedef struct ich10_spi_regs {
uint32_t bfpr;
uint16_t hsfs;
uint16_t hsfc;
uint32_t faddr;
uint32_t _reserved0;
uint32_t fdata[16];
uint32_t fracc;
uint32_t freg[5];
uint32_t _reserved1[3];
uint32_t pr[5];
uint32_t _reserved2[2];
uint8_t ssfs;
uint8_t ssfc[3];
uint16_t preop;
uint16_t optype;
uint8_t opmenu[8];
uint8_t _reserved3[16];
uint32_t fdoc;
uint32_t fdod;
uint8_t _reserved4[8];
uint32_t afc;
uint32_t lvscc;
uint32_t uvscc;
uint8_t _reserved5[4];
uint32_t fpb;
uint8_t _reserved6[36];
uint32_t scs;
uint32_t bcr;
uint32_t tcgc;
} __packed ich10_spi_regs;
typedef struct ich_spi_controller {
int locked;
uint8_t *opmenu;
int menubytes;
uint16_t *preop;
uint16_t *optype;
uint32_t *addr;
uint8_t *data;
unsigned int databytes;
uint8_t *status;
uint16_t *control;
uint32_t *bbar;
uint8_t *bcr;
} ich_spi_controller;
static ich_spi_controller cntlr;
enum {
SPIS_SCIP = 0x0001,
SPIS_GRANT = 0x0002,
SPIS_CDS = 0x0004,
SPIS_FCERR = 0x0008,
SSFS_AEL = 0x0010,
SPIS_LOCK = 0x8000,
SPIS_RESERVED_MASK = 0x7ff0,
SSFS_RESERVED_MASK = 0x7fe2
};
enum {
SPIC_SCGO = 0x000002,
SPIC_ACS = 0x000004,
SPIC_SPOP = 0x000008,
SPIC_DBC = 0x003f00,
SPIC_DS = 0x004000,
SPIC_SME = 0x008000,
SSFC_SCF_MASK = 0x070000,
SSFC_RESERVED = 0xf80000
};
enum {
HSFS_FDONE = 0x0001,
HSFS_FCERR = 0x0002,
HSFS_AEL = 0x0004,
HSFS_BERASE_MASK = 0x0018,
HSFS_BERASE_SHIFT = 3,
HSFS_SCIP = 0x0020,
HSFS_FDOPSS = 0x2000,
HSFS_FDV = 0x4000,
HSFS_FLOCKDN = 0x8000
};
enum {
HSFC_FGO = 0x0001,
HSFC_FCYCLE_MASK = 0x0006,
HSFC_FCYCLE_SHIFT = 1,
HSFC_FDBC_MASK = 0x3f00,
HSFC_FDBC_SHIFT = 8,
HSFC_FSMIE = 0x8000
};
enum {
BCR_BIOSWE = 0x0001,
BCR_BLE = 0x0002,
BCR_SRC_MASK = 0x000c,
BCR_SRC_SHIFT = 0x0002,
BCR_SRC_NO_PREF = 0x0000,
BCR_SRC_NO_PREF_CACHE = 0x0004,
BCR_SRC_EN_PREF_CACHE = 0x0008,
BCR_TSS = 0x0010,
BCR_SMMBWP = 0x0020,
BCR_RESERVED_MASK = 0xffc0
};
enum {
SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0,
SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1,
SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2,
SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3,
};
#if CONFIG(DEBUG_SPI_FLASH)
static u8 readb_(const void *addr)
{
u8 v = read8(addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
static u16 readw_(const void *addr)
{
u16 v = read16(addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
static u32 readl_(const void *addr)
{
u32 v = read32(addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
static void writeb_(u8 b, const void *addr)
{
write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
write32((unsigned long)addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned int) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
#define readb_(a) read8(a)
#define readw_(a) read16(a)
#define readl_(a) read32(a)
#define writeb_(val, addr) write8(addr, val)
#define writew_(val, addr) write16(addr, val)
#define writel_(val, addr) write32(addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
static void write_reg(const void *value, void *dest, uint32_t size)
{
const uint8_t *bvalue = value;
uint8_t *bdest = dest;
while (size >= 4) {
writel_(*(const uint32_t *)bvalue, bdest);
bdest += 4; bvalue += 4; size -= 4;
}
while (size) {
writeb_(*bvalue, bdest);
bdest++; bvalue++; size--;
}
}
static void read_reg(const void *src, void *value, uint32_t size)
{
const uint8_t *bsrc = src;
uint8_t *bvalue = value;
while (size >= 4) {
*(uint32_t *)bvalue = readl_(bsrc);
bsrc += 4; bvalue += 4; size -= 4;
}
while (size) {
*bvalue = readb_(bsrc);
bsrc++; bvalue++; size--;
}
}
static void ich_set_bbar(uint32_t minaddr)
{
const uint32_t bbar_mask = 0x00ffff00;
uint32_t ichspi_bbar;
if (cntlr.bbar == NULL)
return;
minaddr &= bbar_mask;
ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask;
ichspi_bbar |= minaddr;
writel_(ichspi_bbar, cntlr.bbar);
}
/*
* Check if this device ID matches one of supported Intel SOC devices.
*
* Return the ICH version if there is a match, or zero otherwise.
*/
static inline int get_ich_version(uint16_t device_id)
{
if ((device_id >= PCI_DEVICE_ID_INTEL_RANGELEY_LPC_MIN &&
device_id <= PCI_DEVICE_ID_INTEL_RANGELEY_LPC_MAX))
return 10;
return 0;
}
#define MENU_BYTES member_size(struct ich10_spi_regs, opmenu)
void spi_init(void)
{
int ich_version = 0;
uint8_t bios_cntl;
uint32_t ids;
uint16_t vendor_id, device_id;
#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = PCI_DEV(0, 31, 0);
#else
struct device *dev = pcidev_on_root(31, 0);
#endif
ids = pci_read_config32(dev, 0);
vendor_id = ids;
device_id = (ids >> 16);
if (vendor_id != PCI_VENDOR_ID_INTEL) {
printk(BIOS_DEBUG, "SPI: No SOC found.\n");
return;
}
ich_version = get_ich_version(device_id);
if (!ich_version) {
printk(BIOS_DEBUG, "SPI: No known SOC found.\n");
return;
}
switch (ich_version) {
case 10:
{
uint8_t *spibase; /* SPI Base Address */
uint32_t sbase; /* SPI Base Address Register */
sbase = pci_read_config32(dev, 0x54);
/* Bits 31-9 are the base address, 8-4 are reserved, 3-0 are used. */
spibase = (uint8_t *)(sbase & 0xffffff00);
ich10_spi_regs *ich10_spi =
(ich10_spi_regs *)(spibase);
ichspi_lock = readw_(&ich10_spi->hsfs) & HSFS_FLOCKDN;
cntlr.opmenu = ich10_spi->opmenu;
cntlr.menubytes = sizeof(ich10_spi->opmenu);
cntlr.optype = &ich10_spi->optype;
cntlr.addr = &ich10_spi->faddr;
cntlr.data = (uint8_t *)ich10_spi->fdata;
cntlr.databytes = sizeof(ich10_spi->fdata);
cntlr.status = &ich10_spi->ssfs;
cntlr.control = (uint16_t *)ich10_spi->ssfc;
cntlr.bbar = NULL;
cntlr.preop = &ich10_spi->preop;
cntlr.bcr = (uint8_t *)&ich10_spi->bcr;
break;
}
default:
printk(BIOS_DEBUG, "ICH SPI: Unrecognized ICH version %d.\n", ich_version);
}
ich_set_bbar(0);
/* Disable the BIOS write protect so write commands are allowed. */
switch (ich_version) {
case 10:
{
/* Deassert SMM BIOS write protect(SMM BWP) and assert enable flash write(BIOSWE) */
bios_cntl = readb_(cntlr.bcr);
bios_cntl &= ~BCR_SMMBWP;
bios_cntl |= BCR_BIOSWE;
writeb_(bios_cntl, cntlr.bcr);
break;
}
default:
break;
}
}
typedef struct spi_transaction {
const uint8_t *out;
uint32_t bytesout;
uint8_t *in;
uint32_t bytesin;
uint8_t type;
uint8_t opcode;
uint32_t offset;
} spi_transaction;
static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
{
trans->out += bytes;
trans->bytesout -= bytes;
}
static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
{
trans->in += bytes;
trans->bytesin -= bytes;
}
static void spi_setup_type(spi_transaction *trans)
{
trans->type = 0xFF;
/* Try to guess spi type from read/write sizes. */
if (trans->bytesin == 0) {
if (trans->bytesout > 4)
/*
* If bytesin = 0 and bytesout > 4, we presume this is
* a write data operation, which is accompanied by an
* address.
*/
trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
else
trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
return;
}
if (trans->bytesout == 1) { /* and bytesin is > 0 */
trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
return;
}
if (trans->bytesout == 4) { /* and bytesin is > 0 */
trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
}
/* Fast read command is called with 5 bytes instead of 4 */
if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
--trans->bytesout;
}
}
static int spi_setup_opcode(spi_transaction *trans)
{
uint16_t optypes;
uint8_t opmenu[MENU_BYTES];
trans->opcode = trans->out[0];
spi_use_out(trans, 1);
if (!ichspi_lock) {
/* The lock is off, so just use index 0. */
writeb_(trans->opcode, cntlr.opmenu);
optypes = readw_(cntlr.optype);
optypes = (optypes & 0xfffc) | (trans->type & 0x3);
writew_(optypes, cntlr.optype);
return 0;
} else {
/* The lock is on. See if what we need is on the menu. */
uint8_t optype;
uint16_t opcode_index;
/* Write Enable is handled as atomic prefix */
if (trans->opcode == SPI_OPCODE_WREN)
return 0;
read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) {
if (opmenu[opcode_index] == trans->opcode)
break;
}
if (opcode_index == ARRAY_SIZE(opmenu)) {
printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n",
trans->opcode);
return -1;
}
optypes = readw_(cntlr.optype);
optype = (optypes >> (opcode_index * 2)) & 0x3;
if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
trans->bytesout >= 3) {
/* We guessed wrong earlier. Fix it up. */
trans->type = optype;
}
if (optype != trans->type) {
printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n",
optype);
return -1;
}
return opcode_index;
}
}
static int spi_setup_offset(spi_transaction *trans)
{
/* Separate the SPI address and data. */
switch (trans->type) {
case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
return 0;
case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
trans->offset = ((uint32_t)trans->out[0] << 16) |
((uint32_t)trans->out[1] << 8) |
((uint32_t)trans->out[2] << 0);
spi_use_out(trans, 3);
return 1;
default:
printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type);
return -1;
}
}
/*
* Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set
* below is True) or 0. In case the wait was for the bit(s) to set - write
* those bits back, which would cause resetting them.
*
* Return the last read status value on success or -1 on failure.
*/
static int ich_status_poll(u16 bitmask, int wait_til_set)
{
int timeout = 60000; /* This will result in 600 ms */
u16 status = 0;
while (timeout--) {
status = readw_(cntlr.status);
if (wait_til_set ^ ((status & bitmask) == 0)) {
if (wait_til_set)
writew_((status & bitmask), cntlr.status);
return status;
}
udelay(10);
}
printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n",
status, bitmask);
return -1;
}
static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
size_t bytesout, void *din, size_t bytesin)
{
uint16_t control;
int16_t opcode_index;
int with_address;
int status;
spi_transaction trans = {
dout, bytesout,
din, bytesin,
0xff, 0xff, 0
};
/* There has to always at least be an opcode. */
if (!bytesout || !dout) {
printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n");
return -1;
}
/* Make sure if we read something we have a place to put it. */
if (bytesin != 0 && !din) {
printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n");
return -1;
}
if (ich_status_poll(SPIS_SCIP, 0) == -1)
return -1;
writew_(SPIS_CDS | SPIS_FCERR, cntlr.status);
spi_setup_type(&trans);
if ((opcode_index = spi_setup_opcode(&trans)) < 0)
return -1;
if ((with_address = spi_setup_offset(&trans)) < 0)
return -1;
if (!ichspi_lock && trans.opcode == SPI_OPCODE_WREN) {
/*
* Treat Write Enable as Atomic Pre-Op if possible
* in order to prevent the Management Engine from
* issuing a transaction between WREN and DATA.
*/
writew_(trans.opcode, cntlr.preop);
return 0;
}
/* Preset control fields */
control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
/* Issue atomic preop cycle if needed */
if (readw_(cntlr.preop))
control |= SPIC_ACS;
if (!trans.bytesout && !trans.bytesin) {
/* SPI addresses are 24 bit only */
if (with_address)
writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
/*
* This is a 'no data' command (like Write Enable), its
* bitesout size was 1, decremented to zero while executing
* spi_setup_opcode() above. Tell the chip to send the
* command.
*/
writew_(control, cntlr.control);
/* wait for the result */
status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
if (status == -1)
return -1;
if (status & SPIS_FCERR) {
printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n");
return -1;
}
goto spi_xfer_exit;
}
/*
* Check if this is a write command attempting to transfer more bytes
* than the controller can handle. Iterations for writes are not
* supported here because each SPI write command needs to be preceded
* and followed by other SPI commands, and this sequence is controlled
* by the SPI chip driver.
*/
if (trans.bytesout > cntlr.databytes) {
printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use"
" spi_crop_chunk()?\n");
return -1;
}
/*
* Read or write up to databytes bytes at a time until everything has
* been sent.
*/
while (trans.bytesout || trans.bytesin) {
uint32_t data_length;
/* SPI addresses are 24 bit only */
writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
if (trans.bytesout)
data_length = min(trans.bytesout, cntlr.databytes);
else
data_length = min(trans.bytesin, cntlr.databytes);
/* Program data into FDATA0 to N */
if (trans.bytesout) {
write_reg(trans.out, cntlr.data, data_length);
spi_use_out(&trans, data_length);
if (with_address)
trans.offset += data_length;
}
/* Add proper control fields' values */
control &= ~((cntlr.databytes - 1) << 8);
control |= SPIC_DS;
control |= (data_length - 1) << 8;
/* write it */
writew_(control, cntlr.control);
/* Wait for Cycle Done Status or Flash Cycle Error. */
status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
if (status == -1)
return -1;
if (status & SPIS_FCERR) {
printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n");
return -1;
}
if (trans.bytesin) {
read_reg(cntlr.data, trans.in, data_length);
spi_use_in(&trans, data_length);
if (with_address)
trans.offset += data_length;
}
}
spi_xfer_exit:
/* Clear atomic preop now that xfer is done */
writew_(0, cntlr.preop);
return 0;
}
static int xfer_vectors(const struct spi_slave *slave,
struct spi_op vectors[], size_t count)
{
return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer);
}
static const struct spi_ctrlr spi_ctrlr = {
.xfer_vector = xfer_vectors,
.max_xfer_size = member_size(ich10_spi_regs, fdata),
};
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
{
.ctrlr = &spi_ctrlr,
.bus_start = 0,
.bus_end = 0,
},
};
const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);

1
src/vendorcode/intel/Kconfig
View File

@ -17,7 +17,6 @@
config FSP_VENDORCODE_HEADER_PATH config FSP_VENDORCODE_HEADER_PATH
string string
default "fsp1_0/baytrail" if SOC_INTEL_FSP_BAYTRAIL default "fsp1_0/baytrail" if SOC_INTEL_FSP_BAYTRAIL
default "fsp1_0/rangeley" if CPU_INTEL_FSP_MODEL_406DX
config UEFI_2_4_BINDING config UEFI_2_4_BINDING
def_bool n def_bool n

67
src/vendorcode/intel/fsp1_0/rangeley/include/fspapi.h
View File

@ -1,67 +0,0 @@
/**
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef _FSP_API_H_
#define _FSP_API_H_
#include <fsptypes.h>
#pragma pack(1)
typedef VOID (* CONTINUATION_PROC)(EFI_STATUS Status, VOID *HobListPtr);
typedef struct {
VOID *NvsBufferPtr;
VOID *RtBufferPtr;
CONTINUATION_PROC ContinuationFunc;
} FSP_INIT_PARAMS;
typedef struct {
UINT32 *StackTop;
UINT32 BootMode; /* Refer to boot mode defined in MdePkg\Include\Pi\PiBootMode.h */
VOID *UpdDataRgnPtr;
UINT32 Reserved[7];
} FSP_INIT_RT_COMMON_BUFFER;
typedef enum {
EnumInitPhaseAfterPciEnumeration = 0x20,
EnumInitPhaseReadyToBoot = 0x40
} FSP_INIT_PHASE;
typedef struct {
FSP_INIT_PHASE Phase;
} NOTIFY_PHASE_PARAMS;
#pragma pack()
typedef FSP_STATUS (FSPAPI *FSP_FSP_INIT) (FSP_INIT_PARAMS *FspInitParamPtr);
typedef FSP_STATUS (FSPAPI *FSP_NOTFY_PHASE) (NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr);
#endif /* _FSP_API_H_ */

54
src/vendorcode/intel/fsp1_0/rangeley/include/fspbootmode.h
View File

@ -1,54 +0,0 @@
/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __PI_BOOT_MODE_H__
#define __PI_BOOT_MODE_H__
///
/// EFI boot mode
///
typedef UINT32 EFI_BOOT_MODE;
//
// 0x21 - 0xf..f are reserved.
//
#define BOOT_WITH_FULL_CONFIGURATION 0x00
#define BOOT_WITH_MINIMAL_CONFIGURATION 0x01
#define BOOT_ASSUMING_NO_CONFIGURATION_CHANGES 0x02
#define BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS 0x03
#define BOOT_WITH_DEFAULT_SETTINGS 0x04
#define BOOT_ON_S4_RESUME 0x05
#define BOOT_ON_S5_RESUME 0x06
#define BOOT_ON_S2_RESUME 0x10
#define BOOT_ON_S3_RESUME 0x11
#define BOOT_ON_FLASH_UPDATE 0x12
#define BOOT_IN_RECOVERY_MODE 0x20
#endif

507
src/vendorcode/intel/fsp1_0/rangeley/include/fspffs.h
View File

@ -1,507 +0,0 @@
/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __PI_FIRMWARE_FILE_H__
#define __PI_FIRMWARE_FILE_H__
#include <fsptypes.h>
#pragma pack(1)
///
/// Used to verify the integrity of the file.
///
typedef union {
struct {
///
/// The IntegrityCheck.Checksum.Header field is an 8-bit checksum of the file
/// header. The State and IntegrityCheck.Checksum.File fields are assumed
/// to be zero and the checksum is calculated such that the entire header sums to zero.
///
UINT8 Header;
///
/// If the FFS_ATTRIB_CHECKSUM (see definition below) bit of the Attributes
/// field is set to one, the IntegrityCheck.Checksum.File field is an 8-bit
/// checksum of the file data.
/// If the FFS_ATTRIB_CHECKSUM bit of the Attributes field is cleared to zero,
/// the IntegrityCheck.Checksum.File field must be initialized with a value of
/// 0xAA. The IntegrityCheck.Checksum.File field is valid any time the
/// EFI_FILE_DATA_VALID bit is set in the State field.
///
UINT8 File;
} Checksum;
///
/// This is the full 16 bits of the IntegrityCheck field.
///
UINT16 Checksum16;
} EFI_FFS_INTEGRITY_CHECK;
///
/// FFS_FIXED_CHECKSUM is the checksum value used when the
/// FFS_ATTRIB_CHECKSUM attribute bit is clear.
///
#define FFS_FIXED_CHECKSUM 0xAA
typedef UINT8 EFI_FV_FILETYPE;
typedef UINT8 EFI_FFS_FILE_ATTRIBUTES;
typedef UINT8 EFI_FFS_FILE_STATE;
///
/// File Types Definitions
///
#define EFI_FV_FILETYPE_ALL 0x00
#define EFI_FV_FILETYPE_RAW 0x01
#define EFI_FV_FILETYPE_FREEFORM 0x02
#define EFI_FV_FILETYPE_SECURITY_CORE 0x03
#define EFI_FV_FILETYPE_PEI_CORE 0x04
#define EFI_FV_FILETYPE_DXE_CORE 0x05
#define EFI_FV_FILETYPE_PEIM 0x06
#define EFI_FV_FILETYPE_DRIVER 0x07
#define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08
#define EFI_FV_FILETYPE_APPLICATION 0x09
#define EFI_FV_FILETYPE_SMM 0x0A
#define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B
#define EFI_FV_FILETYPE_COMBINED_SMM_DXE 0x0C
#define EFI_FV_FILETYPE_SMM_CORE 0x0D
#define EFI_FV_FILETYPE_OEM_MIN 0xc0
#define EFI_FV_FILETYPE_OEM_MAX 0xdf
#define EFI_FV_FILETYPE_DEBUG_MIN 0xe0
#define EFI_FV_FILETYPE_DEBUG_MAX 0xef
#define EFI_FV_FILETYPE_FFS_MIN 0xf0
#define EFI_FV_FILETYPE_FFS_MAX 0xff
#define EFI_FV_FILETYPE_FFS_PAD 0xf0
///
/// FFS File Attributes.
///
#define FFS_ATTRIB_LARGE_FILE 0x01
#define FFS_ATTRIB_FIXED 0x04
#define FFS_ATTRIB_DATA_ALIGNMENT 0x38
#define FFS_ATTRIB_CHECKSUM 0x40
///
/// FFS File State Bits.
///
#define EFI_FILE_HEADER_CONSTRUCTION 0x01
#define EFI_FILE_HEADER_VALID 0x02
#define EFI_FILE_DATA_VALID 0x04
#define EFI_FILE_MARKED_FOR_UPDATE 0x08
#define EFI_FILE_DELETED 0x10
#define EFI_FILE_HEADER_INVALID 0x20
///
/// Each file begins with the header that describe the
/// contents and state of the files.
///
typedef struct {
///
/// This GUID is the file name. It is used to uniquely identify the file.
///
EFI_GUID Name;
///
/// Used to verify the integrity of the file.
///
EFI_FFS_INTEGRITY_CHECK IntegrityCheck;
///
/// Identifies the type of file.
///
EFI_FV_FILETYPE Type;
///
/// Declares various file attribute bits.
///
EFI_FFS_FILE_ATTRIBUTES Attributes;
///
/// The length of the file in bytes, including the FFS header.
///
UINT8 Size[3];
///
/// Used to track the state of the file throughout the life of the file from creation to deletion.
///
EFI_FFS_FILE_STATE State;
} EFI_FFS_FILE_HEADER;
typedef struct {
///
/// This GUID is the file name. It is used to uniquely identify the file. There may be only
/// one instance of a file with the file name GUID of Name in any given firmware
/// volume, except if the file type is EFI_FV_FILETYPE_FFS_PAD.
///
EFI_GUID Name;
///
/// Used to verify the integrity of the file.
///
EFI_FFS_INTEGRITY_CHECK IntegrityCheck;
///
/// Identifies the type of file.
///
EFI_FV_FILETYPE Type;
///
/// Declares various file attribute bits.
///
EFI_FFS_FILE_ATTRIBUTES Attributes;
///
/// The length of the file in bytes, including the FFS header.
/// The length of the file data is either (Size - sizeof(EFI_FFS_FILE_HEADER)). This calculation means a
/// zero-length file has a Size of 24 bytes, which is sizeof(EFI_FFS_FILE_HEADER).
/// Size is not required to be a multiple of 8 bytes. Given a file F, the next file header is
/// located at the next 8-byte aligned firmware volume offset following the last byte of the file F.
///
UINT8 Size[3];
///
/// Used to track the state of the file throughout the life of the file from creation to deletion.
///
EFI_FFS_FILE_STATE State;
///
/// If FFS_ATTRIB_LARGE_FILE is set in Attributes, then ExtendedSize exists and Size must be set to zero.
/// If FFS_ATTRIB_LARGE_FILE is not set then EFI_FFS_FILE_HEADER is used.
///
UINT32 ExtendedSize;
} EFI_FFS_FILE_HEADER2;
#define IS_FFS_FILE2(FfsFileHeaderPtr) \
(((((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Attributes) & FFS_ATTRIB_LARGE_FILE) == FFS_ATTRIB_LARGE_FILE)
#define FFS_FILE_SIZE(FfsFileHeaderPtr) \
((UINT32) (*((UINT32 *) ((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Size) & 0x00ffffff))
#define FFS_FILE2_SIZE(FfsFileHeaderPtr) \
(((EFI_FFS_FILE_HEADER2 *) (UINTN) FfsFileHeaderPtr)->ExtendedSize)
typedef UINT8 EFI_SECTION_TYPE;
///
/// Pseudo type. It is used as a wild card when retrieving sections.
/// The section type EFI_SECTION_ALL matches all section types.
///
#define EFI_SECTION_ALL 0x00
///
/// Encapsulation section Type values.
///
#define EFI_SECTION_COMPRESSION 0x01
#define EFI_SECTION_GUID_DEFINED 0x02
#define EFI_SECTION_DISPOSABLE 0x03
///
/// Leaf section Type values.
///
#define EFI_SECTION_PE32 0x10
#define EFI_SECTION_PIC 0x11
#define EFI_SECTION_TE 0x12
#define EFI_SECTION_DXE_DEPEX 0x13
#define EFI_SECTION_VERSION 0x14
#define EFI_SECTION_USER_INTERFACE 0x15
#define EFI_SECTION_COMPATIBILITY16 0x16
#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17
#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18
#define EFI_SECTION_RAW 0x19
#define EFI_SECTION_PEI_DEPEX 0x1B
#define EFI_SECTION_SMM_DEPEX 0x1C
///
/// Common section header.
///
typedef struct {
///
/// A 24-bit unsigned integer that contains the total size of the section in bytes,
/// including the EFI_COMMON_SECTION_HEADER.
///
UINT8 Size[3];
EFI_SECTION_TYPE Type;
///
/// Declares the section type.
///
} EFI_COMMON_SECTION_HEADER;
typedef struct {
///
/// A 24-bit unsigned integer that contains the total size of the section in bytes,
/// including the EFI_COMMON_SECTION_HEADER.
///
UINT8 Size[3];
EFI_SECTION_TYPE Type;
///
/// If Size is 0xFFFFFF, then ExtendedSize contains the size of the section. If
/// Size is not equal to 0xFFFFFF, then this field does not exist.
///
UINT32 ExtendedSize;
} EFI_COMMON_SECTION_HEADER2;
///
/// Leaf section type that contains an
/// IA-32 16-bit executable image.
///
typedef EFI_COMMON_SECTION_HEADER EFI_COMPATIBILITY16_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_COMPATIBILITY16_SECTION2;
///
/// CompressionType of EFI_COMPRESSION_SECTION.
///
#define EFI_NOT_COMPRESSED 0x00
#define EFI_STANDARD_COMPRESSION 0x01
///
/// An encapsulation section type in which the
/// section data is compressed.
///
typedef struct {
///
/// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION.
///
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// The UINT32 that indicates the size of the section data after decompression.
///
UINT32 UncompressedLength;
///
/// Indicates which compression algorithm is used.
///
UINT8 CompressionType;
} EFI_COMPRESSION_SECTION;
typedef struct {
///
/// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION.
///
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// UINT32 that indicates the size of the section data after decompression.
///
UINT32 UncompressedLength;
///
/// Indicates which compression algorithm is used.
///
UINT8 CompressionType;
} EFI_COMPRESSION_SECTION2;
///
/// An encapsulation section type in which the section data is disposable.
/// A disposable section is an encapsulation section in which the section data may be disposed of during
/// the process of creating or updating a firmware image without significant impact on the usefulness of
/// the file. The Type field in the section header is set to EFI_SECTION_DISPOSABLE. This
/// allows optional or descriptive data to be included with the firmware file which can be removed in
/// order to conserve space. The contents of this section are implementation specific, but might contain
/// debug data or detailed integration instructions.
///
typedef EFI_COMMON_SECTION_HEADER EFI_DISPOSABLE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_DISPOSABLE_SECTION2;
///
/// The leaf section which could be used to determine the dispatch order of DXEs.
///
typedef EFI_COMMON_SECTION_HEADER EFI_DXE_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_DXE_DEPEX_SECTION2;
///
/// The leaf section which contains a PI FV.
///
typedef EFI_COMMON_SECTION_HEADER EFI_FIRMWARE_VOLUME_IMAGE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_FIRMWARE_VOLUME_IMAGE_SECTION2;
///
/// The leaf section which contains a single GUID.
///
typedef struct {
///
/// Common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID.
///
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// This GUID is defined by the creator of the file. It is a vendor-defined file type.
///
EFI_GUID SubTypeGuid;
} EFI_FREEFORM_SUBTYPE_GUID_SECTION;
typedef struct {
///
/// The common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID.
///
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// This GUID is defined by the creator of the file. It is a vendor-defined file type.
///
EFI_GUID SubTypeGuid;
} EFI_FREEFORM_SUBTYPE_GUID_SECTION2;
///
/// Attributes of EFI_GUID_DEFINED_SECTION.
///
#define EFI_GUIDED_SECTION_PROCESSING_REQUIRED 0x01
#define EFI_GUIDED_SECTION_AUTH_STATUS_VALID 0x02
///
/// The leaf section which is encapsulation defined by specific GUID.
///
typedef struct {
///
/// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED.
///
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// The GUID that defines the format of the data that follows. It is a vendor-defined section type.
///
EFI_GUID SectionDefinitionGuid;
///
/// Contains the offset in bytes from the beginning of the common header to the first byte of the data.
///
UINT16 DataOffset;
///
/// The bit field that declares some specific characteristics of the section contents.
///
UINT16 Attributes;
} EFI_GUID_DEFINED_SECTION;
typedef struct {
///
/// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED.
///
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// The GUID that defines the format of the data that follows. It is a vendor-defined section type.
///
EFI_GUID SectionDefinitionGuid;
///
/// Contains the offset in bytes from the beginning of the common header to the first byte of the data.
///
UINT16 DataOffset;
///
/// The bit field that declares some specific characteristics of the section contents.
///
UINT16 Attributes;
} EFI_GUID_DEFINED_SECTION2;
///
/// The leaf section which contains PE32+ image.
///
typedef EFI_COMMON_SECTION_HEADER EFI_PE32_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PE32_SECTION2;
///
/// The leaf section used to determine the dispatch order of PEIMs.
///
typedef EFI_COMMON_SECTION_HEADER EFI_PEI_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2;
///
/// A leaf section type that contains a position-independent-code (PIC) image.
/// A PIC image section is a leaf section that contains a position-independent-code (PIC) image.
/// In addition to normal PE32+ images that contain relocation information, PEIM executables may be
/// PIC and are referred to as PIC images. A PIC image is the same as a PE32+ image except that all
/// relocation information has been stripped from the image and the image can be moved and will
/// execute correctly without performing any relocation or other fix-ups. EFI_PIC_SECTION2 must
/// be used if the section is 16MB or larger.
///
typedef EFI_COMMON_SECTION_HEADER EFI_PIC_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_PIC_SECTION2;
///
/// The leaf section which constains the position-independent-code image.
///
typedef EFI_COMMON_SECTION_HEADER EFI_TE_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_TE_SECTION2;
///
/// The leaf section which contains an array of zero or more bytes.
///
typedef EFI_COMMON_SECTION_HEADER EFI_RAW_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2;
///
/// The SMM dependency expression section is a leaf section that contains a dependency expression that
/// is used to determine the dispatch order for SMM drivers. Before the SMRAM invocation of the
/// SMM driver's entry point, this dependency expression must evaluate to TRUE. See the Platform
/// Initialization Specification, Volume 2, for details regarding the format of the dependency expression.
/// The dependency expression may refer to protocols installed in either the UEFI or the SMM protocol
/// database. EFI_SMM_DEPEX_SECTION2 must be used if the section is 16MB or larger.
///
typedef EFI_COMMON_SECTION_HEADER EFI_SMM_DEPEX_SECTION;
typedef EFI_COMMON_SECTION_HEADER2 EFI_SMM_DEPEX_SECTION2;
///
/// The leaf section which contains a unicode string that
/// is human readable file name.
///
typedef struct {
EFI_COMMON_SECTION_HEADER CommonHeader;
///
/// Array of unicode string.
///
CHAR16 FileNameString[1];
} EFI_USER_INTERFACE_SECTION;
typedef struct {
EFI_COMMON_SECTION_HEADER2 CommonHeader;
CHAR16 FileNameString[1];
} EFI_USER_INTERFACE_SECTION2;
///
/// The leaf section which contains a numeric build number and
/// an optional unicode string that represents the file revision.
///
typedef struct {
EFI_COMMON_SECTION_HEADER CommonHeader;
UINT16 BuildNumber;
///
/// Array of unicode string.
///
CHAR16 VersionString[1];
} EFI_VERSION_SECTION;
typedef struct {
EFI_COMMON_SECTION_HEADER2 CommonHeader;
///
/// A UINT16 that represents a particular build. Subsequent builds have monotonically
/// increasing build numbers relative to earlier builds.
///
UINT16 BuildNumber;
CHAR16 VersionString[1];
} EFI_VERSION_SECTION2;
#define IS_SECTION2(SectionHeaderPtr) \
((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff) == 0x00ffffff)
#define SECTION_SIZE(SectionHeaderPtr) \
((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff))
#define SECTION2_SIZE(SectionHeaderPtr) \
(((EFI_COMMON_SECTION_HEADER2 *) (UINTN) SectionHeaderPtr)->ExtendedSize)
#pragma pack()
#endif

249
src/vendorcode/intel/fsp1_0/rangeley/include/fspfv.h
View File

@ -1,249 +0,0 @@
/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __PI_FIRMWAREVOLUME_H__
#define __PI_FIRMWAREVOLUME_H__
#include <fsptypes.h>
///
/// EFI_FV_FILE_ATTRIBUTES
///
typedef UINT32 EFI_FV_FILE_ATTRIBUTES;
//
// Value of EFI_FV_FILE_ATTRIBUTES.
//
#define EFI_FV_FILE_ATTRIB_ALIGNMENT 0x0000001F
#define EFI_FV_FILE_ATTRIB_FIXED 0x00000100
#define EFI_FV_FILE_ATTRIB_MEMORY_MAPPED 0x00000200
///
/// type of EFI FVB attribute
///
typedef UINT32 EFI_FVB_ATTRIBUTES_2;
//
// Attributes bit definitions
//
#define EFI_FVB2_READ_DISABLED_CAP 0x00000001
#define EFI_FVB2_READ_ENABLED_CAP 0x00000002
#define EFI_FVB2_READ_STATUS 0x00000004
#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
#define EFI_FVB2_WRITE_STATUS 0x00000020
#define EFI_FVB2_LOCK_CAP 0x00000040
#define EFI_FVB2_LOCK_STATUS 0x00000080
#define EFI_FVB2_STICKY_WRITE 0x00000200
#define EFI_FVB2_MEMORY_MAPPED 0x00000400
#define EFI_FVB2_ERASE_POLARITY 0x00000800
#define EFI_FVB2_READ_LOCK_CAP 0x00001000
#define EFI_FVB2_READ_LOCK_STATUS 0x00002000
#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000
#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000
#define EFI_FVB2_ALIGNMENT 0x001F0000
#define EFI_FVB2_ALIGNMENT_1 0x00000000
#define EFI_FVB2_ALIGNMENT_2 0x00010000
#define EFI_FVB2_ALIGNMENT_4 0x00020000
#define EFI_FVB2_ALIGNMENT_8 0x00030000
#define EFI_FVB2_ALIGNMENT_16 0x00040000
#define EFI_FVB2_ALIGNMENT_32 0x00050000
#define EFI_FVB2_ALIGNMENT_64 0x00060000
#define EFI_FVB2_ALIGNMENT_128 0x00070000
#define EFI_FVB2_ALIGNMENT_256 0x00080000
#define EFI_FVB2_ALIGNMENT_512 0x00090000
#define EFI_FVB2_ALIGNMENT_1K 0x000A0000
#define EFI_FVB2_ALIGNMENT_2K 0x000B0000
#define EFI_FVB2_ALIGNMENT_4K 0x000C0000
#define EFI_FVB2_ALIGNMENT_8K 0x000D0000
#define EFI_FVB2_ALIGNMENT_16K 0x000E0000
#define EFI_FVB2_ALIGNMENT_32K 0x000F0000
#define EFI_FVB2_ALIGNMENT_64K 0x00100000
#define EFI_FVB2_ALIGNMENT_128K 0x00110000
#define EFI_FVB2_ALIGNMENT_256K 0x00120000
#define EFI_FVB2_ALIGNMENT_512K 0x00130000
#define EFI_FVB2_ALIGNMENT_1M 0x00140000
#define EFI_FVB2_ALIGNMENT_2M 0x00150000
#define EFI_FVB2_ALIGNMENT_4M 0x00160000
#define EFI_FVB2_ALIGNMENT_8M 0x00170000
#define EFI_FVB2_ALIGNMENT_16M 0x00180000
#define EFI_FVB2_ALIGNMENT_32M 0x00190000
#define EFI_FVB2_ALIGNMENT_64M 0x001A0000
#define EFI_FVB2_ALIGNMENT_128M 0x001B0000
#define EFI_FVB2_ALIGNMENT_256M 0x001C0000
#define EFI_FVB2_ALIGNMENT_512M 0x001D0000
#define EFI_FVB2_ALIGNMENT_1G 0x001E0000
#define EFI_FVB2_ALIGNMENT_2G 0x001F0000
typedef struct {
///
/// The number of sequential blocks which are of the same size.
///
UINT32 NumBlocks;
///
/// The size of the blocks.
///
UINT32 Length;
} EFI_FV_BLOCK_MAP_ENTRY;
///
/// Describes the features and layout of the firmware volume.
///
typedef struct {
///
/// The first 16 bytes are reserved to allow for the reset vector of
/// processors whose reset vector is at address 0.
///
UINT8 ZeroVector[16];
///
/// Declares the file system with which the firmware volume is formatted.
///
EFI_GUID FileSystemGuid;
///
/// Length in bytes of the complete firmware volume, including the header.
///
UINT64 FvLength;
///
/// Set to EFI_FVH_SIGNATURE
///
UINT32 Signature;
///
/// Declares capabilities and power-on defaults for the firmware volume.
///
EFI_FVB_ATTRIBUTES_2 Attributes;
///
/// Length in bytes of the complete firmware volume header.
///
UINT16 HeaderLength;
///
/// A 16-bit checksum of the firmware volume header. A valid header sums to zero.
///
UINT16 Checksum;
///
/// Offset, relative to the start of the header, of the extended header
/// (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is no extended header.
///
UINT16 ExtHeaderOffset;
///
/// This field must always be set to zero.
///
UINT8 Reserved[1];
///
/// Set to 2. Future versions of this specification may define new header fields and will
/// increment the Revision field accordingly.
///
UINT8 Revision;
///
/// An array of run-length encoded FvBlockMapEntry structures. The array is
/// terminated with an entry of {0,0}.
///
EFI_FV_BLOCK_MAP_ENTRY BlockMap[1];
} EFI_FIRMWARE_VOLUME_HEADER;
#define EFI_FVH_SIGNATURE SIGNATURE_32 ('_', 'F', 'V', 'H')
///
/// Firmware Volume Header Revision definition
///
#define EFI_FVH_REVISION 0x02
///
/// Extension header pointed by ExtHeaderOffset of volume header.
///
typedef struct {
///
/// Firmware volume name.
///
EFI_GUID FvName;
///
/// Size of the rest of the extension header, including this structure.
///
UINT32 ExtHeaderSize;
} EFI_FIRMWARE_VOLUME_EXT_HEADER;
///
/// Entry struture for describing FV extension header
///
typedef struct {
///
/// Size of this header extension.
///
UINT16 ExtEntrySize;
///
/// Type of the header.
///
UINT16 ExtEntryType;
} EFI_FIRMWARE_VOLUME_EXT_ENTRY;
#define EFI_FV_EXT_TYPE_OEM_TYPE 0x01
///
/// This extension header provides a mapping between a GUID and an OEM file type.
///
typedef struct {
///
/// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE.
///
EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
///
/// A bit mask, one bit for each file type between 0xC0 (bit 0) and 0xDF (bit 31). If a bit
/// is '1', then the GUID entry exists in Types. If a bit is '0' then no GUID entry exists in Types.
///
UINT32 TypeMask;
///
/// An array of GUIDs, each GUID representing an OEM file type.
///
/// EFI_GUID Types[1];
///
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_OEM_TYPE;
#define EFI_FV_EXT_TYPE_GUID_TYPE 0x0002
///
/// This extension header EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE provides a vendor specific
/// GUID FormatType type which includes a length and a successive series of data bytes.
///
typedef struct {
///
/// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE.
///
EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
///
/// Vendor-specific GUID.
///
EFI_GUID FormatType;
///
/// An arry of bytes of length Length.
///
/// UINT8 Data[1];
///
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE;
#endif

69
src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h
View File

@ -1,69 +0,0 @@
/** @file
Copyright (C) 2014, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __FSP_GUID_H__
#define __FSP_GUID_H__
/**
FSP specific GUID HOB definitions
**/
#define FSP_INFO_HEADER_GUID \
{ \
0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \
}
#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \
{ \
0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } \
}
#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \
{ \
0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } \
}
#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \
{ \
0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } \
}
#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \
{ \
0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } \
}
#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \
{ \
0x9c7c3aa7, 0x5332, 0x4917, { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \
}
#endif

544
src/vendorcode/intel/fsp1_0/rangeley/include/fsphob.h
View File

@ -1,544 +0,0 @@
/** @file
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __PI_HOB_H__
#define __PI_HOB_H__
#include <fsptypes.h>
//
// HobType of EFI_HOB_GENERIC_HEADER.
//
#define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
#define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
#define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
#define EFI_HOB_TYPE_UNUSED 0xFFFE
#define EFI_HOB_TYPE_END_OF_HOB_LIST 0xFFFF
///
/// Describes the format and size of the data inside the HOB.
/// All HOBs must contain this generic HOB header.
///
typedef struct {
///
/// Identifies the HOB data structure type.
///
UINT16 HobType;
///
/// The length in bytes of the HOB.
///
UINT16 HobLength;
///
/// This field must always be set to zero.
///
UINT32 Reserved;
} EFI_HOB_GENERIC_HEADER;
///
/// Enumeration of memory types introduced in UEFI.
///
typedef enum {
///
/// Not used.
///
EfiReservedMemoryType,
///
/// The code portions of a loaded application.
/// (Note that UEFI OS loaders are UEFI applications.)
///
EfiLoaderCode,
///
/// The data portions of a loaded application and the default data allocation
/// type used by an application to allocate pool memory.
///
EfiLoaderData,
///
/// The code portions of a loaded Boot Services Driver.
///
EfiBootServicesCode,
///
/// The data portions of a loaded Boot Serves Driver, and the default data
/// allocation type used by a Boot Services Driver to allocate pool memory.
///
EfiBootServicesData,
///
/// The code portions of a loaded Runtime Services Driver.
///
EfiRuntimeServicesCode,
///
/// The data portions of a loaded Runtime Services Driver and the default
/// data allocation type used by a Runtime Services Driver to allocate pool memory.
///
EfiRuntimeServicesData,
///
/// Free (unallocated) memory.
///
EfiConventionalMemory,
///
/// Memory in which errors have been detected.
///
EfiUnusableMemory,
///
/// Memory that holds the ACPI tables.
///
EfiACPIReclaimMemory,
///
/// Address space reserved for use by the firmware.
///
EfiACPIMemoryNVS,
///
/// Used by system firmware to request that a memory-mapped IO region
/// be mapped by the OS to a virtual address so it can be accessed by EFI runtime services.
///
EfiMemoryMappedIO,
///
/// System memory-mapped IO region that is used to translate memory
/// cycles to IO cycles by the processor.
///
EfiMemoryMappedIOPortSpace,
///
/// Address space reserved by the firmware for code that is part of the processor.
///
EfiPalCode,
EfiMaxMemoryType
} EFI_MEMORY_TYPE;
///
/// EFI_HOB_MEMORY_ALLOCATION_HEADER describes the
/// various attributes of the logical memory allocation. The type field will be used for
/// subsequent inclusion in the UEFI memory map.
///
typedef struct {
///
/// A GUID that defines the memory allocation region's type and purpose, as well as
/// other fields within the memory allocation HOB. This GUID is used to define the
/// additional data within the HOB that may be present for the memory allocation HOB.
/// Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0
/// specification.
///
EFI_GUID Name;
///
/// The base address of memory allocated by this HOB. Type
/// EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0
/// specification.
///
EFI_PHYSICAL_ADDRESS MemoryBaseAddress;
///
/// The length in bytes of memory allocated by this HOB.
///
UINT64 MemoryLength;
///
/// Defines the type of memory allocated by this HOB. The memory type definition
/// follows the EFI_MEMORY_TYPE definition. Type EFI_MEMORY_TYPE is defined
/// in AllocatePages() in the UEFI 2.0 specification.
///
EFI_MEMORY_TYPE MemoryType;
///
/// Padding for Itanium processor family
///
UINT8 Reserved[4];
} EFI_HOB_MEMORY_ALLOCATION_HEADER;
///
/// Describes all memory ranges used during the HOB producer
/// phase that exist outside the HOB list. This HOB type
/// describes how memory is used, not the physical attributes of memory.
///
typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
///
EFI_HOB_GENERIC_HEADER Header;
///
/// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
/// various attributes of the logical memory allocation.
///
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
//
// Additional data pertaining to the "Name" Guid memory
// may go here.
//
} EFI_HOB_MEMORY_ALLOCATION;
///
/// The resource type.
///
typedef UINT32 EFI_RESOURCE_TYPE;
//
// Value of ResourceType in EFI_HOB_RESOURCE_DESCRIPTOR.
//
#define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000
#define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001
#define EFI_RESOURCE_IO 0x00000002
#define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003
#define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 0x00000004
#define EFI_RESOURCE_MEMORY_RESERVED 0x00000005
#define EFI_RESOURCE_IO_RESERVED 0x00000006
#define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000007
///
/// A type of recount attribute type.
///
typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE;
//
// These types can be ORed together as needed.
//
// The first three enumerations describe settings
//
#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001
#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002
#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004
//
// The rest of the settings describe capabilities
//
#define EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC 0x00000008
#define EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC 0x00000010
#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_1 0x00000020
#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_2 0x00000040
#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080
#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100
#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200
#define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400
#define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800
#define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000
#define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000
#define EFI_RESOURCE_ATTRIBUTE_16_BIT_IO 0x00004000
#define EFI_RESOURCE_ATTRIBUTE_32_BIT_IO 0x00008000
#define EFI_RESOURCE_ATTRIBUTE_64_BIT_IO 0x00010000
#define EFI_RESOURCE_ATTRIBUTE_UNCACHED_EXPORTED 0x00020000
///
/// Describes the resource properties of all fixed,
/// nonrelocatable resource ranges found on the processor
/// host bus during the HOB producer phase.
///
typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR.
///
EFI_HOB_GENERIC_HEADER Header;
///
/// A GUID representing the owner of the resource. This GUID is used by HOB
/// consumer phase components to correlate device ownership of a resource.
///
EFI_GUID Owner;
///
/// The resource type enumeration as defined by EFI_RESOURCE_TYPE.
///
EFI_RESOURCE_TYPE ResourceType;
///
/// Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE.
///
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
///
/// The physical start address of the resource region.
///
EFI_PHYSICAL_ADDRESS PhysicalStart;
///
/// The number of bytes of the resource region.
///
UINT64 ResourceLength;
} EFI_HOB_RESOURCE_DESCRIPTOR;
///
/// Allows writers of executable content in the HOB producer phase to
/// maintain and manage HOBs with specific GUID.
///
typedef struct {
///
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION.
///
EFI_HOB_GENERIC_HEADER Header;
///
/// A GUID that defines the contents of this HOB.
///
EFI_GUID Name;
//
// Guid specific data goes here
//
} EFI_HOB_GUID_TYPE;
///
/// Union of all the possible HOB Types.
///
typedef union {
EFI_HOB_GENERIC_HEADER *Header;
EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation;
EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor;
EFI_HOB_GUID_TYPE *Guid;
UINT8 *Raw;
} EFI_PEI_HOB_POINTERS;
/**
Returns the type of a HOB.
This macro returns the HobType field from the HOB header for the
HOB specified by HobStart.
@param HobStart A pointer to a HOB.
@return HobType.
**/
#define GET_HOB_TYPE(HobStart) \
(((EFI_HOB_GENERIC_HEADER *)(HobStart))->HobType)
/**
Returns the length, in bytes, of a HOB.
This macro returns the HobLength field from the HOB header for the
HOB specified by HobStart.
@param HobStart A pointer to a HOB.
@return HobLength.
**/
#define GET_HOB_LENGTH(HobStart) \
(((EFI_HOB_GENERIC_HEADER *)(HobStart))->HobLength)
/**
Returns a pointer to the next HOB in the HOB list.
This macro returns a pointer to HOB that follows the
HOB specified by HobStart in the HOB List.
@param HobStart A pointer to a HOB.
@return A pointer to the next HOB in the HOB list.
**/
#define GET_NEXT_HOB(HobStart) \
(VOID *)((UINT8 *)(HobStart) + GET_HOB_LENGTH(HobStart))
/**
Determines if a HOB is the last HOB in the HOB list.
This macro determine if the HOB specified by HobStart is the
last HOB in the HOB list. If HobStart is last HOB in the HOB list,
then TRUE is returned. Otherwise, FALSE is returned.
@param HobStart A pointer to a HOB.
@retval TRUE The HOB specified by HobStart is the last HOB in the HOB list.
@retval FALSE The HOB specified by HobStart is not the last HOB in the HOB list.
**/
#define END_OF_HOB_LIST(HobStart) (GET_HOB_TYPE(HobStart) == (UINT16)EFI_HOB_TYPE_END_OF_HOB_LIST)
/**
Returns a pointer to data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
This macro returns a pointer to the data buffer in a HOB specified by HobStart.
HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
@param GuidHob A pointer to a HOB.
@return A pointer to the data buffer in a HOB.
**/
#define GET_GUID_HOB_DATA(HobStart) \
(VOID *)((UINT8 *)(HobStart) + sizeof(EFI_HOB_GUID_TYPE))
/**
Returns the size of the data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
This macro returns the size, in bytes, of the data buffer in a HOB specified by HobStart.
HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
@param GuidHob A pointer to a HOB.
@return The size of the data buffer.
**/
#define GET_GUID_HOB_DATA_SIZE(HobStart) \
(UINT16)(GET_HOB_LENGTH(HobStart) - sizeof(EFI_HOB_GUID_TYPE))
/**
Returns the pointer to the HOB list.
This function returns the pointer to first HOB in the list.
If the pointer to the HOB list is NULL, then ASSERT().
@return The pointer to the HOB list.
**/
VOID *
EFIAPI
GetHobList (
VOID
);
/**
Returns the next instance of a HOB type from the starting HOB.
This function searches the first instance of a HOB type from the starting HOB pointer.
If there does not exist such HOB type from the starting HOB pointer, it will return NULL.
In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer
unconditionally: it returns HobStart back if HobStart itself meets the requirement;
caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart.
If HobStart is NULL, then ASSERT().
@param Type The HOB type to return.
@param HobStart The starting HOB pointer to search from.
@return The next instance of a HOB type from the starting HOB.
**/
VOID *
EFIAPI
GetNextHob (
UINT16 Type,
CONST VOID *HobStart
);
/**
Returns the first instance of a HOB type among the whole HOB list.
This function searches the first instance of a HOB type among the whole HOB list.
If there does not exist such HOB type in the HOB list, it will return NULL.
If the pointer to the HOB list is NULL, then ASSERT().
@param Type The HOB type to return.
@return The next instance of a HOB type from the starting HOB.
**/
VOID *
EFIAPI
GetFirstHob (
UINT16 Type
);
/**
Returns the next instance of the matched GUID HOB from the starting HOB.
This function searches the first instance of a HOB from the starting HOB pointer.
Such HOB should satisfy two conditions:
its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid.
If there does not exist such HOB from the starting HOB pointer, it will return NULL.
Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE ()
to extract the data section and its size info respectively.
In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer
unconditionally: it returns HobStart back if HobStart itself meets the requirement;
caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart.
If Guid is NULL, then ASSERT().
If HobStart is NULL, then ASSERT().
@param Guid The GUID to match with in the HOB list.
@param HobStart A pointer to a Guid.
@return The next instance of the matched GUID HOB from the starting HOB.
**/
VOID *
EFIAPI
GetNextGuidHob (
CONST EFI_GUID *Guid,
CONST VOID *HobStart
);
/**
Returns the first instance of the matched GUID HOB among the whole HOB list.
This function searches the first instance of a HOB among the whole HOB list.
Such HOB should satisfy two conditions:
its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid.
If there does not exist such HOB from the starting HOB pointer, it will return NULL.
Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE ()
to extract the data section and its size info respectively.
If the pointer to the HOB list is NULL, then ASSERT().
If Guid is NULL, then ASSERT().
@param Guid The GUID to match with in the HOB list.
@return The first instance of the matched GUID HOB among the whole HOB list.
**/
VOID *
EFIAPI
GetFirstGuidHob (
CONST EFI_GUID *Guid
);
/**
Compares two GUIDs.
This function compares Guid1 to Guid2. If the GUIDs are identical then TRUE is returned.
If there are any bit differences in the two GUIDs, then FALSE is returned.
If Guid1 is NULL, then ASSERT().
If Guid2 is NULL, then ASSERT().
@param Guid1 A pointer to a 128 bit GUID.
@param Guid2 A pointer to a 128 bit GUID.
@retval TRUE Guid1 and Guid2 are identical.
@retval FALSE Guid1 and Guid2 are not identical.
**/
BOOLEAN
EFIAPI
CompareGuid (
CONST EFI_GUID *Guid1,
CONST EFI_GUID *Guid2
);
/**
Reads a 64-bit value from memory that may be unaligned.
This function returns the 64-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 64-bit value that may be unaligned.
@return The 64-bit value read from Buffer.
**/
UINT64
EFIAPI
ReadUnaligned64 (
CONST UINT64 *Buffer
);
#endif

62
src/vendorcode/intel/fsp1_0/rangeley/include/fspinfoheader.h
View File

@ -1,62 +0,0 @@
/*++
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef _FSP_INFO_HEADER_H_
#define _FSP_INFO_HEADER_H_
#pragma pack(1)
typedef struct {
UINT32 Signature; // Off 0x94
UINT32 HeaderLength;
UINT8 Reserved1[3];
UINT8 HeaderRevision;
UINT32 ImageRevision;
CHAR8 ImageId[8]; // Off 0xA4
UINT32 ImageSize;
UINT32 ImageBase;
UINT32 ImageAttribute; // Off 0xB4
UINT32 CfgRegionOffset;
UINT32 CfgRegionSize;
UINT32 ApiEntryNum;
UINT32 NemInitEntry; // Off 0xC4
UINT32 FspInitEntry;
UINT32 NotifyPhaseEntry;
UINT32 Reserved2;
} FSP_INFO_HEADER;
#pragma pack()
#endif

114
src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h
View File

@ -1,114 +0,0 @@
/**
Copyright (C) 2013 - 2015, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef _FSP_PLATFORM_H_
#define _FSP_PLATFORM_H_
#include "fsptypes.h"
#include "fspapi.h"
//
// Maximum number of SDRAM channels supported by each CPU
//
#define MAX_CHANNELS 2
//
// Maximum number of DIMM sockets supported by each channel
//
#define MAX_DIMMS 2
#pragma pack(1)
//
// SPD DDR3 structure
//
typedef struct {
UINT8 DRAMDeviceType; // 2 DRAM Device Type
UINT8 ModuleType; // 3 Module Type
UINT8 SDRAMDensityAndBanks; // 4 SDRAM Density and Banks
UINT8 SDRAMAddressing; // 5 SDRAM Addressing
UINT8 VDD; // 6 Module Nominal Voltage
UINT8 ModuleOrganization; // 7 Module Organization
UINT8 ModuleMemoryBusWidth; // 8 Module Memory Bus Width
UINT8 TimebaseDividend; // 10 Medium Timebase (MTB) Dividend
UINT8 TimebaseDivisor; // 11 Medium Timebase (MTB) Divisor
UINT8 SDRAMMinimumCycleTime; // 12 SDRAM Minimum Cycle Time (tCKmin)
UINT8 CASLatenciesLSB; // 14 CAS Latencies Supported, Least Significant Byte
UINT8 CASLatenciesMSB; // 15 CAS Latencies Supported, Most Significant Byte
UINT8 MinimumCASLatencyTime; // 16 Minimum CAS Latency Time (tAAmin)
UINT8 MinimumWriteRecoveryTime; // 17 Minimum Write Recovery Time (tWRmin)
UINT8 MinimumRASToCASDelayTime; // 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
UINT8 MinimumRowToRowDelayTime; // 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
UINT8 MinimumRowPrechargeDelayTime; // 20 Minimum Row Precharge Delay Time (tRPmin)
UINT8 UpperNibblesFortRASAndtRC; // 21 Upper Nibbles for tRAS and tRC
UINT8 tRASmin; // 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
UINT8 tRCmin; // 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
UINT8 tRFCminLeastSignificantByte; // 24 Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte
UINT8 tRFCminMostSignificantByte; // 25 Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte
UINT8 tWTRmin; // 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
UINT8 tRTPmin; // 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
UINT8 UpperNibbleFortFAW; // 28 Upper Nibble for tFAW
UINT8 tFAWmin; // 29 Minimum Four Activate Window Delay Time (tFAWmin)
UINT8 SdramThermalRefreshOption; // 31 SdramThermalRefreshOption
UINT8 ModuleThermalSensor; // 32 ModuleThermalSensor
UINT8 SDRAMDeviceType; // 33 SDRAM Device Type
UINT8 tCKminFine; // 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
UINT8 tAAminFine; // 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
UINT8 MACCount; // 41 Maximum Activate Count
UINT8 ReferenceRawCardUsed; // 62 Reference Raw Card Used
UINT8 AddressMappingEdgeConnector; // 63 Address Mapping from Edge Connector to DRAM
UINT8 ModuleManufacturerIdCodeLsb; // 117 Module Manufacturer ID Code, Least Significant Byte
UINT8 ModuleManufacturerIdCodeMsb; // 118 Module Manufacturer ID Code, Most Significant Byte
UINT8 ModuleManufacturingLocation; // 119 Module Manufacturing Location
UINT8 ModuleManufacturingDateYear; // 120 Module Manufacturing Date Year
UINT8 ModuleManufacturingDateWW; // 121 Module Manufacturing Date creation work week
UINT8 ModuleSerialNumberA; // 122 Module Serial Number A
UINT8 ModuleSerialNumberB; // 123 Module Serial Number B
UINT8 ModuleSerialNumberC; // 124 Module Serial Number C
UINT8 ModuleSerialNumberD; // 125 Module Serial Number D
UINT8 DramManufacturerIdLsb; // 148 DRAM Manufacturer ID Code, LSB
UINT8 DramManufacturerIdMsb; // 149 DRAM Manufacturer ID Code, MSB
} MEM_DOWN_DIMM_SPD_DATA;
typedef struct {
UINT32 MemoryDownDimmPopulation; // 0 - Empty, 1 - DIMM populated
MEM_DOWN_DIMM_SPD_DATA MemoryDownDimmSpdData;
} MEM_DOWN_DIMM_CONFIG;
typedef struct {
CONST MEM_DOWN_DIMM_CONFIG *MemDownDimmConfig[MAX_CHANNELS][MAX_DIMMS];
} FSP_INIT_RT_PLATFORM_BUFFER;
typedef struct {
FSP_INIT_RT_COMMON_BUFFER Common;
FSP_INIT_RT_PLATFORM_BUFFER Platform;
} FSP_INIT_RT_BUFFER;
#pragma pack()
#endif

95
src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h
View File

@ -1,95 +0,0 @@
/** @file
Copyright (C) 2013 - 2014, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef __FSP_SUPPORT_H__
#define __FSP_SUPPORT_H__
#include "fsptypes.h"
#include "fspfv.h"
#include "fspffs.h"
#include "fspapi.h"
#include "fsphob.h"
#include "fspguid.h"
#include "fspplatform.h"
#include "fspinfoheader.h"
#include "fspbootmode.h"
#include "fspvpd.h"
UINT32
GetUsableLowMemTop (
CONST VOID *HobListPtr
);
UINT64
GetUsableHighMemTop (
CONST VOID *HobListPtr
);
VOID *
GetGuidHobDataBuffer (
CONST VOID *HobListPtr,
UINT32 *Length,
EFI_GUID *Guid
);
VOID
GetFspReservedMemoryFromGuid (
CONST VOID *HobListPtr,
EFI_PHYSICAL_ADDRESS *FspMemoryBase,
UINT64 *FspMemoryLength,
EFI_GUID *FspReservedMemoryGuid
);
UINT32
GetTsegReservedMemory (
CONST VOID *HobListPtr,
UINT32 *Length
);
UINT32
GetFspReservedMemory (
CONST VOID *HobListPtr,
UINT32 *Length
);
VOID*
GetFspNvsDataBuffer (
CONST VOID *HobListPtr,
UINT32 *Length
);
VOID *
GetBootloaderTempMemoryBuffer (
CONST VOID *HobListPtr,
UINT32 *Length
);
#endif

183
src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h
View File

@ -1,183 +0,0 @@
/******************************************************************************
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
/** \file fsptypes.h
*
*
*/
#ifndef __FSP_TYPES_H__
#define __FSP_TYPES_H__
///
/// 8-byte unsigned value.
///
typedef unsigned long long UINT64;
///
/// 8-byte signed value.
///
typedef long long INT64;
///
/// 4-byte unsigned value.
///
typedef unsigned int UINT32;
///
/// 4-byte signed value.
///
typedef int INT32;
///
/// 2-byte unsigned value.
///
typedef unsigned short UINT16;
///
/// 2-byte Character. Unless otherwise specified all strings are stored in the
/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
///
typedef unsigned short CHAR16;
///
/// 2-byte signed value.
///
typedef short INT16;
///
/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
/// values are undefined.
///
typedef unsigned char BOOLEAN;
///
/// 1-byte unsigned value.
///
typedef unsigned char UINT8;
///
/// 1-byte Character
///
typedef char CHAR8;
///
/// 1-byte signed value
///
typedef char INT8;
typedef void VOID;
typedef UINT64 EFI_PHYSICAL_ADDRESS;
typedef struct {
UINT32 Data1;
UINT16 Data2;
UINT16 Data3;
UINT8 Data4[8];
} EFI_GUID;
#define CONST const
#define STATIC static
#define TRUE ((BOOLEAN)(1==1))
#define FALSE ((BOOLEAN)(0==1))
static inline void DebugDeadLoop(void) {
for (;;);
}
#define FSPAPI __attribute__((cdecl))
#define EFIAPI __attribute__((cdecl))
#define _ASSERT(Expression) DebugDeadLoop()
#define ASSERT(Expression) \
do { \
if (!(Expression)) { \
_ASSERT (Expression); \
} \
} while (FALSE)
typedef UINT32 FSP_STATUS;
typedef UINT32 EFI_STATUS;
///
/// Compatiable with EFI_STATUS defined in PI Spec.
#define FSP_SUCCESS 0
#define FSP_INVALID_PARAMETER 0x80000002
#define FSP_UNSUPPORTED 0x80000003
#define FSP_DEVICE_ERROR 0x80000007
#define FSP_NOT_FOUND 0x8000000E
#define FSP_ALREADY_STARTED 0x80000014
/**
Returns a 16-bit signature built from 2 ASCII characters.
This macro returns a 16-bit value built from the two ASCII characters specified
by A and B.
@param A The first ASCII character.
@param B The second ASCII character.
@return A 16-bit value built from the two ASCII characters specified by A and B.
**/
#define SIGNATURE_16(A, B) ((A) | (B << 8))
/**
Returns a 32-bit signature built from 4 ASCII characters.
This macro returns a 32-bit value built from the four ASCII characters specified
by A, B, C, and D.
@param A The first ASCII character.
@param B The second ASCII character.
@param C The third ASCII character.
@param D The fourth ASCII character.
@return A 32-bit value built from the two ASCII characters specified by A, B,
C and D.
**/
#define SIGNATURE_32(A, B, C, D) (SIGNATURE_16 (A, B) | (SIGNATURE_16 (C, D) << 16))
/**
Returns a 64-bit signature built from 8 ASCII characters.
This macro returns a 64-bit value built from the eight ASCII characters specified
by A, B, C, D, E, F, G,and H.
@param A The first ASCII character.
@param B The second ASCII character.
@param C The third ASCII character.
@param D The fourth ASCII character.
@param E The fifth ASCII character.
@param F The sixth ASCII character.
@param G The seventh ASCII character.
@param H The eighth ASCII character.
@return A 64-bit value built from the two ASCII characters specified by A, B,
C, D, E, F, G and H.
**/
#define SIGNATURE_64(A, B, C, D, E, F, G, H) \
(SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32))
#endif

89
src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h
View File

@ -1,89 +0,0 @@
/** @file
Copyright (C) 2015, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSP_VPD_H__
#define __FSP_VPD_H__
#pragma pack(1)
typedef struct _UPD_DATA_REGION {
UINT64 Signature; /* Offset 0x0000 */
UINT64 Reserved; /* Offset 0x0008 */
UINT8 UnusedUpdSpace0[16]; /* Offset 0x0010 */
UINT8 PcdMrcInitTsegSize; /* Offset 0x0020 */
UINT8 PcdMemoryDown; /* Offset 0x0021 */
UINT8 PcdMrcRmtSupport; /* Offset 0x0022 */
UINT8 PcdMrcRmtCpgcExpLoopCntValue; /* Offset 0x0023 */
UINT8 PcdMrcRmtCpgcNumBursts; /* Offset 0x0024 */
UINT8 PcdSpdBaseAddress_0_0; /* Offset 0x0025 */
UINT8 PcdSpdBaseAddress_0_1; /* Offset 0x0026 */
UINT8 PcdSpdBaseAddress_1_0; /* Offset 0x0027 */
UINT8 PcdSpdBaseAddress_1_1; /* Offset 0x0028 */
UINT8 PcdExtendedTemperatureEnable; /* Offset 0x0029 */
UINT8 UnusedUpdSpace1[6]; /* Offset 0x002A */
UINT8 PcdEnableLan; /* Offset 0x0030 */
UINT8 PcdEnableSata2; /* Offset 0x0031 */
UINT8 PcdEnableSata3; /* Offset 0x0032 */
UINT8 PcdEnableIQAT; /* Offset 0x0033 */
UINT8 PcdEnableUsb20; /* Offset 0x0034 */
UINT8 PcdBifurcation; /* Offset 0x0035 */
UINT8 PcdPcieRootPort1DeEmphasis; /* Offset 0x0036 */
UINT8 PcdPcieRootPort2DeEmphasis; /* Offset 0x0037 */
UINT8 PcdPcieRootPort3DeEmphasis; /* Offset 0x0038 */
UINT8 PcdPcieRootPort4DeEmphasis; /* Offset 0x0039 */
UINT8 UnusedUpdSpace2[6]; /* Offset 0x003A */
UINT8 PcdPrintDebugMessages; /* Offset 0x0040 */
UINT8 PcdFastboot; /* Offset 0x0041 */
UINT8 PcdEccSupport; /* Offset 0x0042 */
UINT8 PcdSerialPortBaudRate; /* Offset 0x0043 */
UINT8 PcdCustomerRevision[32]; /* Offset 0x0044 */
UINT8 UnusedUpdSpace3[12]; /* Offset 0x0064 */
UINT16 PcdRegionTerminator; /* Offset 0x0070 */
} UPD_DATA_REGION;
#define VPD_IMAGE_ID 0x562D474E524E5641 /* 'AVNRNG-V' */
#define VPD_IMAGE_REV 0x00000140
typedef struct _VPD_DATA_REGION {
UINT64 PcdVpdRegionSign; /* Offset 0x0000 */
UINT32 PcdImageRevision; /* Offset 0x0008 */
UINT32 PcdUpdRegionOffset; /* Offset 0x000C */
UINT8 UnusedVpdSpace0[16]; /* Offset 0x0010 */
UINT32 PcdFspReservedMemoryLength; /* Offset 0x0020 */
UINT8 PcdSpdWriteProtect; /* Offset 0x0024 */
} VPD_DATA_REGION;
#pragma pack()
#endif

288
src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c
View File

@ -1,288 +0,0 @@
/** @file
Copyright (C) 2013 - 2014, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#include <types.h>
#include <string.h>
#include "fspsupport.h"
/**
This function retrieves the top of usable low memory.
@param HobListPtr A HOB list pointer.
@retval Usable low memory top.
**/
UINT32
GetUsableLowMemTop (
CONST VOID *HobStart
)
{
EFI_PEI_HOB_POINTERS Hob;
UINT32 MemLen;
/*
* Get the HOB list for processing
*/
Hob.Raw = (VOID *)HobStart;
/*
* Collect memory ranges
*/
MemLen = 0x100000;
while (!END_OF_HOB_LIST(Hob.Raw)) {
if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {
/*
* Need memory above 1MB to be collected here
*/
if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000 &&
Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) 0x100000000) {
MemLen += (UINT32) (Hob.ResourceDescriptor->ResourceLength);
}
}
}
Hob.Raw = GET_NEXT_HOB(Hob.Raw);
}
return MemLen;
}
/**
This function retrieves the top of usable high memory.
@param HobListPtr A HOB list pointer.
@retval Usable high memory top.
**/
UINT64
GetUsableHighMemTop (
CONST VOID *HobStart
)
{
EFI_PEI_HOB_POINTERS Hob;
UINT64 MemTop;
/*
* Get the HOB list for processing
*/
Hob.Raw = (VOID *)HobStart;
/*
* Collect memory ranges
*/
MemTop = 0x100000000;
while (!END_OF_HOB_LIST(Hob.Raw)) {
if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {
/*
* Need memory above 1MB to be collected here
*/
if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS) 0x100000000) {
MemTop += (UINT32) (Hob.ResourceDescriptor->ResourceLength);
}
}
}
Hob.Raw = GET_NEXT_HOB(Hob.Raw);
}
return MemTop;
}
/**
This function retrieves a special reserved memory region.
@param HobListPtr A HOB list pointer.
@param Length A pointer to the GUID HOB data buffer length. If the GUID HOB is
located, the length will be updated.
@param OwnerGuid A pointer to the owner guild.
@retval Reserved region start address. 0 if this region does not exist.
**/
VOID
GetFspReservedMemoryFromGuid (
CONST VOID *HobListPtr,
EFI_PHYSICAL_ADDRESS *Base,
UINT64 *Length,
EFI_GUID *OwnerGuid
)
{
EFI_PEI_HOB_POINTERS Hob;
/*
* Get the HOB list for processing
*/
Hob.Raw = (VOID *)HobListPtr;
/*
* Collect memory ranges
*/
while (!END_OF_HOB_LIST(Hob.Raw)) {
if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) {
if (CompareGuid(&Hob.ResourceDescriptor->Owner, OwnerGuid)) {
*Base = (EFI_PHYSICAL_ADDRESS) (Hob.ResourceDescriptor->PhysicalStart);
*Length = (UINT64) (Hob.ResourceDescriptor->ResourceLength);
break;
}
}
}
Hob.Raw = GET_NEXT_HOB(Hob.Raw);
}
}
/**
This function retrieves the TSEG reserved normal memory.
@param HobListPtr A HOB list pointer.
@param Length A pointer to the TSEG reserved memory length buffer. If the GUID HOB is
located, the length will be updated.
@param Guid A pointer to owner HOB GUID.
@retval NULL Failed to find the TSEG reserved memory.
@retval others TSEG reserved memory base.
**/
UINT32
GetTsegReservedMemory (
CONST VOID *HobListPtr,
UINT32 *Length
)
{
const EFI_GUID TsegOwnerHobGuid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID;
UINT64 Length64 = 0;
EFI_PHYSICAL_ADDRESS Base = 0;
GetFspReservedMemoryFromGuid (HobListPtr, &Base, &Length64, (EFI_GUID *)&TsegOwnerHobGuid);
if ((Length != NULL) && (Base != 0)) {
*Length = (UINT32)Length64;
}
return (UINT32)Base;
}
/**
This function retrieves the FSP reserved normal memory.
@param HobListPtr A HOB list pointer.
@param Length A pointer to the FSP reserved memory length buffer. If the GUID HOB is
located, the length will be updated.
@param Guid A pointer to owner HOB GUID.
@retval NULL Failed to find the FSP reserved memory.
@retval others FSP reserved memory base.
**/
UINT32
GetFspReservedMemory (
CONST VOID *HobListPtr,
UINT32 *Length
)
{
const EFI_GUID FspOwnerHobGuid = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
UINT64 Length64 = 0;
EFI_PHYSICAL_ADDRESS Base = 0;
GetFspReservedMemoryFromGuid (HobListPtr, &Base, &Length64, (EFI_GUID *)&FspOwnerHobGuid);
if ((Length != NULL) && (Base != 0)) {
*Length = (UINT32)Length64;
}
return (UINT32)Base;
}
/**
This function retrieves a GUIDed HOB data buffer and size.
@param HobListPtr A HOB list pointer.
@param Length A pointer to the GUID HOB data buffer length. If the
GUID HOB is located, the length will be updated.
@param Guid A pointer to HOB GUID.
@retval NULL Failed to find the GUID HOB.
@retval others GUID HOB data buffer pointer.
**/
VOID *
GetGuidHobDataBuffer (
CONST VOID *HobListPtr,
UINT32 *Length,
EFI_GUID *Guid
)
{
UINT8 *GuidHob;
/* FSP NVS DATA HOB */
GuidHob = GetNextGuidHob(Guid, HobListPtr);
if (GuidHob == NULL) {
return NULL;
} else {
if (Length) {
*Length = GET_GUID_HOB_DATA_SIZE (GuidHob);
}
return GET_GUID_HOB_DATA (GuidHob);
}
}
/**
This function retrieves FSP Non-volatile Storage HOB buffer and size.
@param HobListPtr A HOB list pointer.
@param Length A pointer to the NVS data buffer length. If the FSP NVS
HOB is located, the length will be updated.
@retval NULL Failed to find the NVS HOB.
@retval others FSP NVS data buffer pointer.
**/
VOID *
GetFspNvsDataBuffer (
CONST VOID *HobListPtr,
UINT32 *Length
)
{
const EFI_GUID FspNvsHobGuid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
return GetGuidHobDataBuffer (HobListPtr, Length, (EFI_GUID *)&FspNvsHobGuid);
}
/**
This function retrieves Bootloader temporary stack buffer and size.
@param HobListPtr A HOB list pointer.
@param Length A pointer to the Bootloader temporary stack length.
If the HOB is located, the length will be updated.
@retval NULL Failed to find the Bootloader temporary stack HOB.
@retval others Bootloader temporary stackbuffer pointer.
**/
VOID *
GetBootloaderTempMemoryBuffer (
CONST VOID *HobListPtr,
UINT32 *Length
)
{
const EFI_GUID FspBootloaderTemporaryMemoryHobGuid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID;
return GetGuidHobDataBuffer (HobListPtr, Length, (EFI_GUID *)&FspBootloaderTemporaryMemoryHobGuid);
}

198
src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c
View File

@ -1,198 +0,0 @@
/******************************************************************************
Copyright (C) 2013, Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/***********************************************************************
*
* fsphob.c
*
* HOB infrastructure code.
*
**********************************************************************/
#include <string.h>
#include "fsptypes.h"
#include "fsphob.h"
//
// Pointer to the HOB should be initialized with the output of FSP INIT PARAMS
//
extern volatile void *FspHobListPtr;
/**
Reads a 64-bit value from memory that may be unaligned.
This function returns the 64-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 64-bit value that may be unaligned.
@return The 64-bit value read from Buffer.
**/
UINT64
EFIAPI
ReadUnaligned64 (
CONST UINT64 *Buffer
)
{
ASSERT (Buffer != NULL);
return *Buffer;
}
/**
Compares two GUIDs.
This function compares Guid1 to Guid2. If the GUIDs are identical then TRUE is returned.
If there are any bit differences in the two GUIDs, then FALSE is returned.
If Guid1 is NULL, then ASSERT().
If Guid2 is NULL, then ASSERT().
@param Guid1 A pointer to a 128 bit GUID.
@param Guid2 A pointer to a 128 bit GUID.
@retval TRUE Guid1 and Guid2 are identical.
@retval FALSE Guid1 and Guid2 are not identical.
**/
BOOLEAN
EFIAPI
CompareGuid (
CONST EFI_GUID *Guid1,
CONST EFI_GUID *Guid2
)
{
UINT64 LowPartOfGuid1;
UINT64 LowPartOfGuid2;
UINT64 HighPartOfGuid1;
UINT64 HighPartOfGuid2;
LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1);
LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2);
HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1);
HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1);
return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);
}
/**
Returns the pointer to the HOB list.
**/
VOID *
EFIAPI
GetHobList (
VOID
)
{
ASSERT (FspHobListPtr != NULL);
return ((VOID *)FspHobListPtr);
}
/**
Returns the next instance of a HOB type from the starting HOB.
**/
VOID *
EFIAPI
GetNextHob (
UINT16 Type,
CONST VOID *HobStart
)
{
EFI_PEI_HOB_POINTERS Hob;
ASSERT (HobStart != NULL);
Hob.Raw = (UINT8 *) HobStart;
//
// Parse the HOB list until end of list or matching type is found.
//
while (!END_OF_HOB_LIST(Hob.Raw)) {
if (Hob.Header->HobType == Type) {
return Hob.Raw;
}
Hob.Raw = GET_NEXT_HOB(Hob.Raw);
}
return NULL;
}
/**
Returns the first instance of a HOB type among the whole HOB list.
**/
VOID *
EFIAPI
GetFirstHob (
UINT16 Type
)
{
VOID *HobList;
HobList = GetHobList ();
return GetNextHob (Type, HobList);
}
/**
Returns the next instance of the matched GUID HOB from the starting HOB.
**/
VOID *
EFIAPI
GetNextGuidHob (
CONST EFI_GUID *Guid,
CONST VOID *HobStart
)
{
EFI_PEI_HOB_POINTERS GuidHob;
GuidHob.Raw = (UINT8 *) HobStart;
while ((GuidHob.Raw = GetNextHob (EFI_HOB_TYPE_GUID_EXTENSION, GuidHob.Raw)) != NULL) {
if (CompareGuid (Guid, &GuidHob.Guid->Name)) {
break;
}
GuidHob.Raw = GET_NEXT_HOB(GuidHob.Raw);
}
return GuidHob.Raw;
}
/**
Returns the first instance of the matched GUID HOB among the whole HOB list.
**/
VOID *
EFIAPI
GetFirstGuidHob (
CONST EFI_GUID *Guid
)
{
VOID *HobList;
HobList = GetHobList ();
return GetNextGuidHob (Guid, HobList);
}