sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

src/mainboard: remove MMIO macros

Browse Source 
This touches several mainboards. Replace the macro with C functions.
The presence of bootblock.c is assumed.

Change-Id: I583034ef0b0ed3e5a5e3dd680c57728ec5efbc8f
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Idwer Vollering
2020-01-05 01:44:25 +01:00
committed by Kyösti Mälkki
parent 7c07110923
commit c2ce370f30
8 changed files with 43 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/mainboard/biostar/a68n_5200/romstage.c
View File

@@ -21,12 +21,10 @@
#include <device/pci_ops.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <amdblocks/acpimmio.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8728f/it8728f.h>
#define SB_MMIO 0xFED80000
#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
#define CLKIN_DEV PNP_DEV(0x2e, IT8728F_GPIO)
@@ -36,14 +34,14 @@ static void sbxxx_enable_48mhzout(void)
/* most likely programming to 48MHz out signal */
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
u32 reg32;
reg32 = SB_MMIO_MISC32(0x28);
reg32 = misc_read32(0x28);
reg32 &= 0xfff8ffff;
SB_MMIO_MISC32(0x28) = reg32;
misc_write32(0x28, reg32);
/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
reg32 = SB_MMIO_MISC32(0x40);
reg32 = misc_read32(0x40);
reg32 &= 0xffffbffb;
SB_MMIO_MISC32(0x40) = reg32;
misc_write32(0x40, reg32);
}
void board_BeforeAgesa(struct sysinfo *cb)

17
src/mainboard/biostar/am1ml/bootblock.c
View File

@@ -61,23 +61,20 @@ static void ite_gpio_conf(pnp_devfn_t dev)
void bootblock_mainboard_early_init(void)
{
volatile u32 *addr32;
u32 t32;
u32 reg32;
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
pm_write8(0xea, 0x1);
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
addr32 = (u32 *)0xfed80e28;
t32 = *addr32;
t32 &= 0xfff8ffff;
*addr32 = t32;
reg32 = misc_read32(0x28);
reg32 &= 0xfff8ffff;
misc_write32(0x28, reg32);
/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
addr32 = (u32 *)0xfed80e40;
t32 = *addr32;
t32 &= 0xffffbffb;
*addr32 = t32;
reg32 = misc_read32(0x40);
reg32 &= 0xffffbffb;
misc_write32(0x49, reg32);
/* Configure SIO as made under vendor BIOS */
ite_evc_conf(ENVC_DEV);