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soc/amd/common/block/i2c: implement proper read_resource

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Before this patch the reservation of the MMIO region of the I2C
controllers was done in the LPC controller PCI device despite the I2C
controllers already being devices in the devicetree. This patch
implements this functionality as read_resources function of the I2C
device instead. This will only reserve the memory when the I2C devices
are enabled in devicetree which is a change from the previous behavior.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67c853df3be2f593ecfa113ae2f74e5df7cf74e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58307
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2021-10-12 23:35:11 +02:00 committed by Felix Held
parent 6c08b1ff81
commit c2cee06b4e
5 changed files with 6 additions and 22 deletions
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5
src/soc/amd/cezanne/include/soc/iomap.h
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@ -28,11 +28,6 @@
#define APU_I2C2_BASE 0xfedc4000 #define APU_I2C2_BASE 0xfedc4000
#define APU_I2C3_BASE 0xfedc5000 #define APU_I2C3_BASE 0xfedc5000
/* I2C parameters for lpc_read_resources */
#define I2C_BASE_ADDRESS APU_I2C2_BASE
#define I2C_DEVICE_SIZE 0x00001000
#define I2C_DEVICE_COUNT (I2C_MASTER_DEV_COUNT - I2C_MASTER_START_INDEX)
#define APU_DMAC0_BASE 0xfedc7000 #define APU_DMAC0_BASE 0xfedc7000
#define APU_DMAC1_BASE 0xfedc8000 #define APU_DMAC1_BASE 0xfedc8000
#define APU_UART0_BASE 0xfedc9000 #define APU_UART0_BASE 0xfedc9000

8
src/soc/amd/common/block/i2c/i2c.c
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@ -121,9 +121,13 @@ void i2c_soc_init(void)
dw_i2c_soc_init(false); dw_i2c_soc_init(false);
} }
static void i2c_read_resources(struct device *dev)
{
mmio_resource(dev, 0, dev->path.mmio.addr / KiB, 4);
}
struct device_operations soc_amd_i2c_mmio_ops = { struct device_operations soc_amd_i2c_mmio_ops = {
/* TODO(kramasub): Move I2C resource info here. */ .read_resources = i2c_read_resources,
.read_resources = noop_read_resources,
.set_resources = noop_set_resources, .set_resources = noop_set_resources,
.scan_bus = scan_smbus, .scan_bus = scan_smbus,
.acpi_name = i2c_acpi_name, .acpi_name = i2c_acpi_name,

8
src/soc/amd/common/block/lpc/lpc.c
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@ -119,14 +119,6 @@ static void lpc_read_resources(struct device *dev)
res->size = 0x00001000; res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
#ifdef I2C_BASE_ADDRESS
/* I2C devices */
res = new_resource(dev, 4);
res->base = I2C_BASE_ADDRESS;
res->size = I2C_DEVICE_SIZE * I2C_DEVICE_COUNT;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
#endif
compact_resources(dev); compact_resources(dev);
} }

5
src/soc/amd/picasso/include/soc/iomap.h
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@ -48,11 +48,6 @@
#define APU_I2C3_BASE 0xfedc5000 #define APU_I2C3_BASE 0xfedc5000
#define APU_I2C4_BASE 0xfedc6000 #define APU_I2C4_BASE 0xfedc6000
/* I2C parameters for lpc_read_resources */
#define I2C_BASE_ADDRESS APU_I2C2_BASE
#define I2C_DEVICE_SIZE 0x00001000
#define I2C_DEVICE_COUNT (I2C_MASTER_DEV_COUNT - I2C_MASTER_START_INDEX)
#define APU_DMAC0_BASE 0xfedc7000 #define APU_DMAC0_BASE 0xfedc7000
#define APU_DMAC1_BASE 0xfedc8000 #define APU_DMAC1_BASE 0xfedc8000
#define APU_UART0_BASE 0xfedc9000 #define APU_UART0_BASE 0xfedc9000

2
src/soc/amd/stoneyridge/include/soc/iomap.h
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@ -13,8 +13,6 @@
/* I2C fixed address */ /* I2C fixed address */
#define I2C_BASE_ADDRESS 0xfedc2000 #define I2C_BASE_ADDRESS 0xfedc2000
#define I2C_DEVICE_SIZE 0x00001000 #define I2C_DEVICE_SIZE 0x00001000
#define I2C_DEVICE_COUNT 4
#define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x)) #define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x))
#define I2CA_BASE_ADDRESS (I2C_BUS_ADDRESS(0)) #define I2CA_BASE_ADDRESS (I2C_BUS_ADDRESS(0))
#define I2CB_BASE_ADDRESS (I2C_BUS_ADDRESS(1)) #define I2CB_BASE_ADDRESS (I2C_BUS_ADDRESS(1))