soc,southbridge/intel: Control SMI related FADT entries
When no SMI is installed, FADT should not advertise a trigger mechanism that does not respond. Change-Id: Ifb4f99c11a72e75ec20b9faaf62aed5546de91fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41909 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
committed by
Patrick Georgi
parent
2e270ae297
commit
c328a680de
@@ -132,11 +132,12 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt)
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const uint16_t pmbase = ACPI_BASE_ADDRESS;
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fadt->sci_int = acpi_sci_irq();
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fadt->smi_cmd = APM_CNT;
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fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
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fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
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fadt->s4bios_req = 0x0;
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fadt->pstate_cnt = 0;
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if (CONFIG(HAVE_SMI_HANDLER)) {
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fadt->smi_cmd = APM_CNT;
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fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
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fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
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}
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fadt->pm1a_evt_blk = pmbase + PM1_STS;
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fadt->pm1b_evt_blk = 0x0;
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@@ -154,7 +155,6 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt)
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fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS);
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fadt->gpe1_blk_len = 0;
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fadt->gpe1_base = 0;
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fadt->cst_cnt = 0;
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fadt->p_lvl2_lat = 1;
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fadt->p_lvl3_lat = 87;
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fadt->flush_size = 1024;
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