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soc,southbridge/intel: Control SMI related FADT entries

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When no SMI is installed, FADT should not advertise a trigger
mechanism that does not respond.

Change-Id: Ifb4f99c11a72e75ec20b9faaf62aed5546de91fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41909
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-11-23 07:23:40 +02:00
committed by Patrick Georgi
parent 2e270ae297
commit c328a680de
14 changed files with 78 additions and 103 deletions
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14
src/southbridge/intel/i82801gx/lpc.c
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@@ -521,13 +521,15 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->reserved = 0;
fadt->sci_int = 0x9;
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = APM_CNT_PST_CONTROL;
fadt->cst_cnt = APM_CNT_CST_CONTROL;
if (CONFIG(HAVE_SMI_HANDLER)) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
fadt->pstate_cnt = APM_CNT_PST_CONTROL;
fadt->cst_cnt = APM_CNT_CST_CONTROL;
}
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = chip->c3_latency;
fadt->flush_size = 0;