soc/{amd,intel}/chip: Use local include for chip.h

Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/soc/amd/stoneyridge/chip.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <chip.h>
 #include <bootstate.h>
 #include <console/console.h>
 #include <cpu/amd/mtrr.h>
@@ -30,6 +29,8 @@
 #include <amdblocks/agesawrapper.h>
 #include <amdblocks/agesawrapper_call.h>
 
+#include "chip.h"
+
 /* Supplied by i2c.c */
 extern struct device_operations stoneyridge_i2c_mmio_ops;
 extern const char *i2c_acpi_name(const struct device *dev);

src/soc/amd/stoneyridge/northbridge.c

@@ -13,13 +13,11 @@
  * GNU General Public License for more details.
  */
 
-
 #include <device/pci_ops.h>
 #include <arch/ioapic.h>
 #include <arch/acpi.h>
 #include <arch/acpigen.h>
 #include <cbmem.h>
-#include <chip.h>
 #include <console/console.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/x86/lapic_def.h>
@@ -42,6 +40,8 @@
 #include <string.h>
 #include <arch/bert_storage.h>
 
+#include "chip.h"
+
 static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,
 			u32 io_min, u32 io_max)
 {

src/soc/amd/stoneyridge/romstage.c

@@ -24,7 +24,6 @@
 #include <commonlib/helpers.h>
 #include <console/console.h>
 #include <device/device.h>
-#include <chip.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
 #include <elog.h>
@@ -35,6 +34,8 @@
 #include <soc/southbridge.h>
 #include <amdblocks/psp.h>
 
+#include "chip.h"
+
 void __weak mainboard_romstage_entry(int s3_resume)
 {
 	/* By default, don't do anything */

src/soc/intel/braswell/chip.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <chip.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -23,6 +22,8 @@
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 
+#include "chip.h"
+
 static void pci_domain_set_resources(struct device *dev)
 {
 	printk(BIOS_SPEW, "%s/%s (%s)\n",

src/soc/intel/braswell/include/soc/ramstage.h

@@ -17,10 +17,11 @@
 #ifndef _SOC_RAMSTAGE_H_
 #define _SOC_RAMSTAGE_H_
 
-#include <chip.h>
 #include <device/device.h>
 #include <fsp/ramstage.h>
 
+#include "../../chip.h"
+
 #define V_PCH_LPC_RID_A0		0x00  // A0 Stepping
 #define V_PCH_LPC_RID_A1		0x04  // A1 Stepping
 #define V_PCH_LPC_RID_A2		0x08  // A2 Stepping

src/soc/intel/braswell/romstage/romstage.c

@@ -22,7 +22,6 @@
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <arch/cbfs.h>
-#include <chip.h>
 #include <cpu/x86/mtrr.h>
 #include <console/console.h>
 #include <device/device.h>
@@ -44,6 +43,8 @@
 #include <build.h>
 #include <pc80/mc146818rtc.h>
 
+#include "../chip.h"
+
 void program_base_addresses(void)
 {
 	uint32_t reg;

src/soc/intel/cannonlake/acpi.c

@@ -19,7 +19,6 @@
 #include <arch/acpigen.h>
 #include <arch/smp/mpspec.h>
 #include <cbmem.h>
-#include <chip.h>
 #include <console/console.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
@@ -38,6 +37,8 @@
 #include <vendorcode/google/chromeos/gnvs.h>
 #include <wrdd.h>
 
+#include "chip.h"
+
 /*
  * List of supported C-states in this processor.
  */

src/soc/intel/cannonlake/chip.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <chip.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/api.h>
@@ -27,6 +26,8 @@
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 
+#include "chip.h"
+
 #if CONFIG(HAVE_ACPI_TABLES)
 const char *soc_acpi_name(const struct device *dev)
 {

src/soc/intel/cannonlake/cpu.c

@@ -16,7 +16,6 @@
 #include <arch/cpu.h>
 #include <console/console.h>
 #include <device/pci.h>
-#include <chip.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
@@ -35,6 +34,8 @@
 #include <cpu/intel/microcode.h>
 #include <cpu/intel/common/common.h>
 
+#include "chip.h"
+
 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
 static const u8 power_limit_time_sec_to_msr[] = {
 	[0]   = 0x00,

src/soc/intel/cannonlake/finalize.c

@@ -17,7 +17,6 @@
 #include <arch/io.h>
 #include <device/mmio.h>
 #include <bootstate.h>
-#include <chip.h>
 #include <console/console.h>
 #include <console/post_codes.h>
 #include <cpu/x86/smm.h>
@@ -35,6 +34,8 @@
 #include <soc/systemagent.h>
 #include <stdlib.h>
 
+#include "chip.h"
+
 #define CAMERA1_CLK		0x8000 /* Camera 1 Clock */
 #define CAMERA2_CLK		0x8080 /* Camera 2 Clock */
 #define CAM_CLK_EN		(1 << 1)

src/soc/intel/cannonlake/fsp_params.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <chip.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -25,6 +24,8 @@
 #include <soc/ramstage.h>
 #include <string.h>
 
+#include "chip.h"
+
 static const int serial_io_dev[] = {
 	PCH_DEVFN_I2C0,
 	PCH_DEVFN_I2C1,

src/soc/intel/cannonlake/include/soc/ramstage.h

@@ -17,11 +17,12 @@
 #ifndef _SOC_RAMSTAGE_H_
 #define _SOC_RAMSTAGE_H_
 
-#include <chip.h>
 #include <device/device.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
 
+#include "../../chip.h"
+
 void mainboard_silicon_init_params(FSP_S_CONFIG *params);
 void soc_init_pre_device(void *chip_info);
 

src/soc/intel/cannonlake/memmap.c

@@ -16,7 +16,6 @@
 
 #include <arch/ebda.h>
 #include <cbmem.h>
-#include <chip.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -28,6 +27,8 @@
 #include <soc/systemagent.h>
 #include <stdlib.h>
 
+#include "chip.h"
+
 void smm_region(void **start, size_t *size)
 {
 	*start = (void *)sa_get_tseg_base();

src/soc/intel/cannonlake/pmc.c

@@ -16,7 +16,6 @@
  */
 
 #include <bootstate.h>
-#include <chip.h>
 #include <console/console.h>
 #include <device/mmio.h>
 #include <device/device.h>
@@ -27,6 +26,8 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 
+#include "chip.h"
+
 /*
  * Set which power state system will be after reapplying
  * the power (from G3 State)

src/soc/intel/cannonlake/romstage/fsp_params.c

@@ -14,7 +14,6 @@
  */
 
 #include <assert.h>
-#include <chip.h>
 #include <cpu/x86/msr.h>
 #include <console/console.h>
 #include <fsp/util.h>
@@ -25,6 +24,8 @@
 #include <soc/romstage.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
+#include "../chip.h"
+
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
 {
 	unsigned int i;

src/soc/intel/cannonlake/romstage/romstage.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <chip.h>
 #include <cpu/x86/mtrr.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -30,6 +29,8 @@
 #include <string.h>
 #include <timestamp.h>
 
+#include "../chip.h"
+
 #define FSP_SMBIOS_MEMORY_INFO_GUID	\
 {	\
 	0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e,	\

src/soc/intel/cannonlake/smihandler.c

@@ -15,7 +15,6 @@
  * GNU General Public License for more details.
  */
 
-#include <chip.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <intelblocks/fast_spi.h>
@@ -27,6 +26,8 @@
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
 
+#include "chip.h"
+
 #define CSME0_FBE	0xf
 #define CSME0_BAR	0x0
 #define CSME0_FID	0xb0

src/soc/intel/fsp_broadwell_de/acpi.c

@@ -38,9 +38,10 @@
 #include <soc/pattrs.h>
 #include <soc/pci_devs.h>
 #include <soc/broadwell_de.h>
-#include <chip.h>
 #include <version.h>
 
+#include "chip.h"
+
 uint16_t get_pmbase(void)
 {
 	return ACPI_BASE_ADDRESS;

src/soc/intel/fsp_broadwell_de/chip.c

@@ -22,7 +22,8 @@
 #include <drivers/intel/fsp1_0/fsp_util.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
-#include <chip.h>
+
+#include "chip.h"
 
 static void pci_domain_set_resources(struct device *dev)
 {

src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c

@@ -25,9 +25,10 @@
 #include <drivers/intel/fsp1_0/fsp_util.h>
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>
-#include <chip.h>
 #include <fsp.h>
 
+#include "../chip.h"
+
 /* Copy the default UPD region and settings to a buffer for modification */
 static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData)
 {

src/soc/intel/fsp_broadwell_de/southcluster.c

@@ -32,7 +32,8 @@
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
-#include <chip.h>
+
+#include "chip.h"
 
 typedef struct soc_intel_fsp_broadwell_de_config config_t;
 

src/soc/intel/icelake/acpi.c

@@ -18,7 +18,6 @@
 #include <device/mmio.h>
 #include <arch/smp/mpspec.h>
 #include <cbmem.h>
-#include <chip.h>
 #include <ec/google/chromeec/ec.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/pmclib.h>
@@ -32,6 +31,8 @@
 #include <vendorcode/google/chromeos/gnvs.h>
 #include <wrdd.h>
 
+#include "chip.h"
+
 /*
  * List of supported C-states in this processor.
  */

src/soc/intel/icelake/chip.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <chip.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/api.h>
@@ -28,6 +27,8 @@
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 
+#include "chip.h"
+
 #if CONFIG(HAVE_ACPI_TABLES)
 const char *soc_acpi_name(const struct device *dev)
 {

src/soc/intel/icelake/cpu.c

@@ -16,7 +16,6 @@
 #include <arch/cpu.h>
 #include <console/console.h>
 #include <device/pci.h>
-#include <chip.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
@@ -33,6 +32,8 @@
 #include <soc/pm.h>
 #include <soc/smm.h>
 
+#include "chip.h"
+
 static void soc_fsp_load(void)
 {
 	fsps_load(romstage_handoff_is_resume());

src/soc/intel/icelake/finalize.c

@@ -16,7 +16,6 @@
 #include <arch/io.h>
 #include <device/mmio.h>
 #include <bootstate.h>
-#include <chip.h>
 #include <console/console.h>
 #include <console/post_codes.h>
 #include <cpu/x86/smm.h>
@@ -34,6 +33,8 @@
 #include <soc/systemagent.h>
 #include <stdlib.h>
 
+#include "chip.h"
+
 #define CAMERA1_CLK		0x8000 /* Camera 1 Clock */
 #define CAMERA2_CLK		0x8080 /* Camera 2 Clock */
 #define CAM_CLK_EN		(1 << 1)

src/soc/intel/icelake/include/soc/ramstage.h

@@ -16,11 +16,12 @@
 #ifndef _SOC_RAMSTAGE_H_
 #define _SOC_RAMSTAGE_H_
 
-#include <chip.h>
 #include <device/device.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
 
+#include "../../chip.h"
+
 void mainboard_silicon_init_params(FSP_S_CONFIG *params);
 void soc_init_pre_device(void *chip_info);
 

src/soc/intel/icelake/memmap.c

@@ -15,7 +15,6 @@
 
 #include <arch/ebda.h>
 #include <cbmem.h>
-#include <chip.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -27,6 +26,8 @@
 #include <soc/systemagent.h>
 #include <stdlib.h>
 
+#include "chip.h"
+
 void smm_region(void **start, size_t *size)
 {
 	*start = (void *)sa_get_tseg_base();

src/soc/intel/icelake/pmc.c

@@ -14,7 +14,6 @@
  */
 
 #include <bootstate.h>
-#include <chip.h>
 #include <console/console.h>
 #include <device/mmio.h>
 #include <device/device.h>
@@ -25,6 +24,8 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 
+#include "chip.h"
+
 /*
  * Set which power state system will be after reapplying
  * the power (from G3 State)

src/soc/intel/icelake/romstage/romstage.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <chip.h>
 #include <cpu/x86/mtrr.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -30,6 +29,8 @@
 #include <string.h>
 #include <timestamp.h>
 
+#include "../chip.h"
+
 #define FSP_SMBIOS_MEMORY_INFO_GUID	\
 {	\
 	0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e,	\

src/soc/intel/icelake/smihandler.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <chip.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <intelblocks/fast_spi.h>
@@ -25,6 +24,8 @@
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
 
+#include "chip.h"
+
 #define CSME0_FBE	0xf
 #define CSME0_BAR	0x0
 #define CSME0_FID	0xb0

src/soc/intel/quark/include/soc/ramstage.h

@@ -18,11 +18,12 @@
 #define _SOC_RAMSTAGE_H_
 
 #include <arch/cpu.h>
-#include <chip.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
 #include <soc/QuarkNcSocId.h>
 
+#include "../../chip.h"
+
 void mainboard_gpio_i2c_init(struct device *dev);
 asmlinkage void chipset_teardown_car(void);
 

src/soc/intel/skylake/acpi.c

@@ -21,7 +21,6 @@
 #include <arch/ioapic.h>
 #include <arch/smp/mpspec.h>
 #include <cbmem.h>
-#include <chip.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <cpu/x86/msr.h>
@@ -51,6 +50,8 @@
 #include <wrdd.h>
 #include <device/pci_ops.h>
 
+#include "chip.h"
+
 /*
  * List of suported C-states in this processor.
  */

src/soc/intel/skylake/bootblock/pch.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 #include <device/pci_ops.h>
-#include <chip.h>
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <intelblocks/cse.h>
@@ -37,6 +36,8 @@
 #include <soc/pmc.h>
 #include <soc/smbus.h>
 
+#include "../chip.h"
+
 #define PCR_DMI_DMICTL		0x2234
 #define  PCR_DMI_DMICTL_SRLOCK	(1 << 31)
 #define PCR_DMI_ACPIBA		0x27B4

src/soc/intel/skylake/chip.c

@@ -15,7 +15,6 @@
  */
 
 #include <arch/acpi.h>
-#include <chip.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -33,6 +32,8 @@
 #include <soc/ramstage.h>
 #include <string.h>
 
+#include "chip.h"
+
 void soc_init_pre_device(void *chip_info)
 {
 	/* Snapshot the current GPIO IRQ polarities. FSP is setting a

src/soc/intel/skylake/chip_fsp20.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <chip.h>
 #include <bootmode.h>
 #include <bootstate.h>
 #include <device/pci.h>
@@ -42,6 +41,8 @@
 #include <soc/systemagent.h>
 #include <string.h>
 
+#include "chip.h"
+
 struct pcie_entry {
 	unsigned int devfn;
 	unsigned int func_count;

src/soc/intel/skylake/cpu.c

@@ -20,7 +20,6 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <chip.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
@@ -46,6 +45,8 @@
 #include <soc/systemagent.h>
 #include <timer.h>
 
+#include "chip.h"
+
 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
 static const u8 power_limit_time_sec_to_msr[] = {
 	[0]   = 0x00,

src/soc/intel/skylake/finalize.c

@@ -18,7 +18,6 @@
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <bootstate.h>
-#include <chip.h>
 #include <console/console.h>
 #include <console/post_codes.h>
 #include <cpu/x86/mp.h>
@@ -41,6 +40,8 @@
 #include <stdlib.h>
 #include <timer.h>
 
+#include "chip.h"
+
 #define PSF_BASE_ADDRESS	0xA00
 #define PCR_PSFX_T0_SHDW_PCIEN	0x1C
 #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS	(1 << 8)

src/soc/intel/skylake/include/fsp11/soc/ramstage.h

@@ -17,11 +17,12 @@
 #ifndef _SOC_RAMSTAGE_H_
 #define _SOC_RAMSTAGE_H_
 
-#include <chip.h>
 #include <device/device.h>
 #include <fsp/ramstage.h>
 #include <fsp/soc_binding.h>
 
+#include "../../../chip.h"
+
 #define FSP_SIL_UPD SILICON_INIT_UPD
 #define FSP_MEM_UPD MEMORY_INIT_UPD
 

src/soc/intel/skylake/include/fsp20/soc/ramstage.h

@@ -17,11 +17,12 @@
 #ifndef _SOC_RAMSTAGE_H_
 #define _SOC_RAMSTAGE_H_
 
-#include <chip.h>
 #include <device/device.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
 
+#include "../../../chip.h"
+
 #define FSP_SIL_UPD FSP_S_CONFIG
 #define FSP_MEM_UPD FSP_M_CONFIG
 

src/soc/intel/skylake/memmap.c

@@ -17,7 +17,6 @@
 #include <arch/ebda.h>
 #include <device/mmio.h>
 #include <cbmem.h>
-#include <chip.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -29,6 +28,8 @@
 #include <soc/systemagent.h>
 #include <stdlib.h>
 
+#include "chip.h"
+
 size_t mmap_region_granularity(void)
 {
 	if (CONFIG(HAVE_SMI_HANDLER))

src/soc/intel/skylake/pei_data.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <chip.h>
 #include <console/streams.h>
 #include <device/device.h>
 #include <device/pci_def.h>
@@ -25,6 +24,8 @@
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 
+#include "chip.h"
+
 static void ABI_X86 send_to_console(unsigned char b)
 {
 	console_tx_byte(b);

src/soc/intel/skylake/pmc.c

@@ -16,7 +16,6 @@
  */
 
 #include <bootstate.h>
-#include <chip.h>
 #include <console/console.h>
 #include <device/mmio.h>
 #include <device/device.h>
@@ -28,6 +27,8 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 
+#include "chip.h"
+
 void pmc_set_disb(void)
 {
 	/* Set the DISB after DRAM init */

src/soc/intel/skylake/romstage/romstage.c

@@ -17,7 +17,6 @@
 #include <arch/cbfs.h>
 #include <arch/early_variables.h>
 #include <assert.h>
-#include <chip.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
 #include <device/device.h>
@@ -37,6 +36,8 @@
 #include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
+#include "../chip.h"
+
 /* SOC initialization before RAM is enabled */
 void soc_pre_ram_init(struct romstage_params *params)
 {

src/soc/intel/skylake/romstage/romstage_fsp20.c

@@ -20,7 +20,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 #include <cbmem.h>
-#include <chip.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <fsp/util.h>
@@ -37,6 +36,8 @@
 #include <timestamp.h>
 #include <security/vboot/vboot_common.h>
 
+#include "../chip.h"
+
 #define FSP_SMBIOS_MEMORY_INFO_GUID	\
 {	\
 	0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e,	\

src/soc/intel/skylake/thermal.c

@@ -15,7 +15,6 @@
 
 #include <device/mmio.h>
 #include <device/pci_ops.h>
-#include <chip.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -23,6 +22,8 @@
 #include <soc/pci_devs.h>
 #include <soc/thermal.h>
 
+#include "chip.h"
+
 #define MAX_TRIP_TEMP 205
 #define DEFAULT_TRIP_TEMP 50