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mb/msi/ms7d25: Configure PCIe Root Ports

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Add the full PCIe root port configuration. Proper initialization of
the root ports depends on the correct GPIO programming including
virtual wires. Do not program the CLKREQ signals in coreboot to let FSP
detect and configure CLKREQ pads. Otherwise the CLKREQ pads are
reprogrammed by FSP despite having GpioOverride=1. The pads that
should not be touched by coreboot are left commented in the board GPIO
file. CLKREQ reprogramming caused undefined behavior when ASPM and
Clock PM was being enabled by coreboot on PCIe endpoints of CPU PCIe
x4 slot (coreboot printed a lot of exceptions and simply halted).

TEST=Boot the MSI PRO Z690-A DDR4 WiFi with all PCIe/M.2 slots
populated and check if they are detected and functional in Linux.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I50199d2caf54509a72c5100acb770bf766327e7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63656
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski
2022-04-15 18:19:19 +02:00
parent c2d1588623
commit c354f31b30
5 changed files with 330 additions and 36 deletions
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5
configs/config.msi_ms7d25
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@@ -3,7 +3,9 @@ CONFIG_CBFS_SIZE=0x1000000
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_TIANOCORE_BOOT_TIMEOUT=3
CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR4=y
# CONFIG_SMMSTORE is not set
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_POST_DEVICE_PCI_PCIE=y
CONFIG_POST_IO_PORT=0x80
@@ -13,4 +15,3 @@ CONFIG_TIANOCORE_TAG_OR_REV="origin/dasharo"
CONFIG_TIANOCORE_CBMEM_LOGGING=y
CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=y
CONFIG_TIANOCORE_SD_MMC_TIMEOUT=1000
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y