ACPI: Replace smm_setup_structures()

Except for whitespace and varying casts the codes were
the same when implemented.

Platforms that did not implement this are tagged with
ACPI_NO_SMI_GNVS.

Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/cpu/amd/agesa/Kconfig

@@ -17,6 +17,7 @@ config CPU_AMD_AGESA
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select SMM_ASEG
 	select SSE2
+	select ACPI_NO_SMI_GNVS
 
 if CPU_AMD_AGESA
 

src/cpu/amd/pi/Kconfig

@@ -17,6 +17,7 @@ config CPU_AMD_PI
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select SMM_ASEG
 	select SSE2
+	select ACPI_NO_SMI_GNVS
 
 if CPU_AMD_PI
 

src/cpu/x86/smm/smi_trigger.c

@@ -1,9 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi_gnvs.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 
+static void set_smm_gnvs_ptr(void);
+
 int apm_control(u8 cmd)
 {
 	if (!CONFIG(HAVE_SMI_HANDLER))
@@ -21,7 +24,8 @@ int apm_control(u8 cmd)
 		printk(BIOS_DEBUG, "Enabling ACPI via APMC.\n");
 		break;
 	case APM_CNT_GNVS_UPDATE:
-		break;
+		set_smm_gnvs_ptr();
+		return 0;
 	case APM_CNT_FINALIZE:
 		printk(BIOS_DEBUG, "Finalizing SMM.\n");
 		break;
@@ -41,3 +45,32 @@ int apm_control(u8 cmd)
 	printk(BIOS_DEBUG, "APMC done.\n");
 	return 0;
 }
+
+static void set_smm_gnvs_ptr(void)
+{
+	uintptr_t gnvs_address;
+
+	if (CONFIG(ACPI_NO_SMI_GNVS)) {
+		printk(BIOS_WARNING, "%s() is not implemented\n", __func__);
+		return;
+	}
+
+	gnvs_address = (uintptr_t)acpi_get_gnvs();
+	if (!gnvs_address)
+		return;
+
+	/*
+	 * Issue SMI to set the gnvs pointer in SMM.
+	 *
+	 * EAX = APM_CNT_GNVS_UPDATE
+	 * EBX = gnvs pointer
+	 * EDX = APM_CNT
+	 */
+	asm volatile (
+		"outb %%al, %%dx\n\t"
+		: /* ignore result */
+		: "a" (APM_CNT_GNVS_UPDATE),
+		  "b" (gnvs_address),
+		  "d" (APM_CNT)
+	);
+}