ACPI: Replace smm_setup_structures()

Except for whitespace and varying casts the codes were
the same when implemented.

Platforms that did not implement this are tagged with
ACPI_NO_SMI_GNVS.

Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
2020-06-17 10:34:26 +03:00
committed by Patrick Georgi
parent 5daa1d3898
commit c3c55210ee
34 changed files with 58 additions and 178 deletions

View File

@@ -10,11 +10,6 @@
#include "smi.h"
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
{
printk(BIOS_DEBUG, "%s STUB!!!\n", __func__);
}
/** Set the EOS bit and enable SMI generation from southbridge */
void global_smi_enable(void)
{

View File

@@ -10,11 +10,6 @@
#include "smi.h"
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
{
printk(BIOS_DEBUG, "%s STUB!!!\n", __func__);
}
/** Set the EOS bit and enable SMI generation from southbridge */
void global_smi_enable(void)
{

View File

@@ -665,7 +665,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
#endif
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */
acpigen_write_scope("\\");

View File

@@ -79,25 +79,6 @@ void global_smi_enable(void)
smm_southbridge_enable(PWRBTN_EN | GBL_EN);
}
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
{
/*
* Issue SMI to set the gnvs pointer in SMM.
* tcg and smi1 are unused.
*
* EAX = APM_CNT_GNVS_UPDATE
* EBX = gnvs pointer
* EDX = APM_CNT
*/
asm volatile (
"outb %%al, %%dx\n\t"
: /* ignore result */
: "a" (APM_CNT_GNVS_UPDATE),
"b" ((uintptr_t)gnvs),
"d" (APM_CNT)
);
}
void smm_southbridge_clear_state(void)
{
if (smi_enabled())

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@@ -622,7 +622,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
acpi_create_gnvs(gnvs);
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */
acpigen_write_scope("\\");

View File

@@ -464,7 +464,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
acpi_create_gnvs(gnvs);
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */
acpigen_write_scope("\\");

View File

@@ -623,7 +623,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
acpi_create_gnvs(gnvs);
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */
acpigen_write_scope("\\");

View File

@@ -566,7 +566,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
gnvs->pcnt = dev_count_cpu();
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */
acpigen_write_scope("\\");

View File

@@ -721,7 +721,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */
acpigen_write_scope("\\");

View File

@@ -57,22 +57,3 @@ void global_smi_enable(void)
{
smm_southbridge_enable(PWRBTN_EN | GBL_EN);
}
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
{
/*
* Issue SMI to set the gnvs pointer in SMM.
* tcg and smi1 are unused.
*
* EAX = APM_CNT_GNVS_UPDATE
* EBX = gnvs pointer
* EDX = APM_CNT
*/
asm volatile (
"outb %%al, %%dx\n\t"
: /* ignore result */
: "a" (APM_CNT_GNVS_UPDATE),
"b" ((u32)gnvs),
"d" (APM_CNT)
);
}