From c419da8394135dd472703b70f553382f742c7ff6 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Wed, 25 May 2022 15:26:06 -0600 Subject: [PATCH] mb/system76/gaze17: WIP: S0ix Change-Id: If03f92549ac76e2e0d04bdfe919048879b691f7d Signed-off-by: Tim Crawford --- src/mainboard/system76/gaze17/devicetree.cb | 26 +++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/mainboard/system76/gaze17/devicetree.cb b/src/mainboard/system76/gaze17/devicetree.cb index 9eaffd8099..6c41321d91 100644 --- a/src/mainboard/system76/gaze17/devicetree.cb +++ b/src/mainboard/system76/gaze17/devicetree.cb @@ -12,6 +12,8 @@ chip soc/intel/alderlake # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" + register "s0ix_enable" = "1" + # FSP Memory (soc/intel/alderlake/romstage/fsp_params.c) # Enable C6 DRAM register "enable_c6dram" = "1" @@ -86,6 +88,12 @@ chip soc/intel/alderlake .flags = PCIE_RP_LTR, .PcieRpL1Substates = L1_SS_FSP_DEFAULT, }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD1_RST# + register "srcclk_pin" = "0" # PEX4_SSD_CLKREQ# + device generic 0 on end + end end device ref tbt_pcie_rp0 on end device ref gna on end @@ -143,6 +151,12 @@ chip soc/intel/alderlake .flags = PCIE_RP_LTR, .PcieRpL1Substates = L1_SS_FSP_DEFAULT, }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" # M2_WLAN_RST# + register "srcclk_pin" = "2" # WLAN_CLKREQ# + device generic 0 on end + end end device ref pcie_rp6 on # PCIe root port #6 x1, Clock 5 (CARD) @@ -152,6 +166,12 @@ chip soc/intel/alderlake .flags = PCIE_RP_LTR, .PcieRpL1Substates = L1_SS_FSP_DEFAULT, }" + chip soc/intel/common/block/pcie/rtd3 + # XXX: No enable_gpio = no D3cold? + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)" # CARD_RTD3_RST# + register "srcclk_pin" = "5" # CARD_CLKREQ# + device generic 0 on end + end end device ref pcie_rp7 on # PCIe root port #7 x1, Clock 6 (GLAN) @@ -172,6 +192,12 @@ chip soc/intel/alderlake .flags = PCIE_RP_LTR, .PcieRpL1Substates = L1_SS_FSP_DEFAULT, }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # SATA_M2_PWR_EN1 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_PCH_SSD_RST# + register "srcclk_pin" = "1" # SSD_CLKREQ# + device generic 0 on end + end end device ref pch_espi on register "gen1_dec" = "0x00040069" # EC PM channel