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soc/intel/alderlake: Allow channel 0 for DDR5 memory-down

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This matches the change done for DDR4 in commit 8509c25eece8
("soc/intel/alderlake: Allow channel 0 for memory-down").

Fixes detection of the on-board RAM (Samsung M425R1GB4BB0-CQKOD) on the
System76 Lemur Pro 12 (Clevo L140AU). The Clevo L140*U are the only
boards in the tree using mixed memory topology.

Change-Id: I395f898472a9a8f857fd6b0564b95c787b96080b
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Jeremy Soller 2023-06-20 14:35:48 -06:00 committed by Felix Held
parent ee004de969
commit c4731fa9ee
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/alderlake/meminit.c
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@ -70,8 +70,8 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
* configuration.
*/
.half_channel = BIT(0),
/* In mixed topologies, channel 1 is always memory-down. */
.mixed_topo = BIT(1),
/* In mixed topologies, either channel 0 or 1 can be memory-down. */
.mixed_topo = BIT(0) | BIT(1),
},
},
[MEM_TYPE_LP4X] = {