sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/common/block: Add common chip config block

Browse Source 
Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.

For now, adding i2c, gspi and lockdown configuration which will be used
by common code.

BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.

Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
2018-05-09 14:55:09 +05:30
parent f513cebd8b
commit c4986eb7f4
52 changed files with 1022 additions and 734 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/soc/intel/cannonlake/chip.h
View File

@@ -18,6 +18,7 @@
#ifndef _SOC_CHIP_H_
#define _SOC_CHIP_H_
#include <intelblocks/chip.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <intelblocks/gspi.h>
#include <stdint.h>
@@ -30,11 +31,10 @@
#include <soc/usb.h>
#include <soc/vr_config.h>
#define CANNONLAKE_I2C_DEV_MAX 6
struct soc_intel_cannonlake_config {
/* GSPI */
struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
/* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config;
/* Interrupt Routing configuration.
* If bit7 is 1, the interrupt is disabled. */
@@ -201,11 +201,6 @@ struct soc_intel_cannonlake_config {
uint8_t TcoIrqSelect;
uint8_t TcoIrqEnable;
enum {
CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
} chipset_lockdown;
/*
* Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
@@ -281,9 +276,6 @@ struct soc_intel_cannonlake_config {
/* GPIO SD card detect pin */
unsigned int sdcard_cd_gpio;
/* I2C bus configuration */
struct dw_i2c_bus_config i2c[CANNONLAKE_I2C_DEV_MAX];
/* Enable Pch iSCLK */
uint8_t pch_isclk;