sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Remove some warnings, mainly from format strings which didn't match the

Browse Source 
arguments.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
2009-02-09 17:52:54 +00:00
parent 4505948fae
commit c4ddbff706
18 changed files with 44 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/cpu/amd/model_fxx/model_fxx_init.c
View File

@@ -231,7 +231,7 @@ static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_sta
size = (limitk - basek) << 10;
addr = map_2M_page(basek >> 11);
if (addr == MAPPING_ERROR) {
printk_err("Cannot map page: %x\n", basek >> 11);
printk_err("Cannot map page: %lx\n", basek >> 11);
return;
}
@@ -312,7 +312,7 @@ static void init_ecc_memory(unsigned node_id)
begink = CONFIG_LB_MEM_TOPK;
}
printk_debug("Clearing memory %uK - %uK: ", begink, endk);
printk_debug("Clearing memory %luK - %luK: ", begink, endk);
/* Save the normal state */
save_mtrr_state(&mtrr_state);
@@ -465,7 +465,9 @@ static inline void k8_errata(void)
extern void model_fxx_update_microcode(unsigned cpu_deviceid);
int init_processor_name(void);
#if CONFIG_USBDEBUG_DIRECT
static unsigned ehci_debug_addr;
#endif
void model_fxx_init(device_t dev)
{

2
src/cpu/x86/lapic/lapic.c
View File

@@ -55,7 +55,7 @@ void setup_lapic(void)
LAPIC_DELIVERY_MODE_NMI)
);
printk_debug(" apic_id: 0x%02x ", lapicid());
printk_debug(" apic_id: 0x%02lx ", lapicid());
#else /* !NEED_LLAPIC */
/* Only Pentium Pro and later have those MSR stuff */

10
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@@ -85,14 +85,14 @@ static int lapic_start_cpu(unsigned long apicid)
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (timeout >= 1000) {
printk_err("CPU %d: First apic write timed out. Disabling\n",
printk_err("CPU %ld: First apic write timed out. Disabling\n",
apicid);
// too bad.
printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR));
printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
if (lapic_read(LAPIC_ESR)) {
printk_err("Try to reset ESR\n");
lapic_write_around(LAPIC_ESR, 0);
printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR));
printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
}
return 0;
}
@@ -114,7 +114,7 @@ static int lapic_start_cpu(unsigned long apicid)
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (timeout >= 1000) {
printk_err("CPU %d: Second apic write timed out. Disabling\n",
printk_err("CPU %ld: Second apic write timed out. Disabling\n",
apicid);
// too bad.
return 0;
@@ -345,8 +345,6 @@ void stop_this_cpu(void)
/* C entry point of secondary cpus */
void secondary_cpu_init(void)
{
unsigned long cpunum;
atomic_inc(&active_cpus);
#if SERIAL_CPU_INIT == 1
#if CONFIG_MAX_CPUS>2

2
src/cpu/x86/mtrr/mtrr.c
View File

@@ -241,7 +241,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
align = max_align;
}
sizek = 1 << align;
printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\n",
printk_debug("Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n",
reg, range_startk >>10, sizek >> 10,
(type==MTRR_TYPE_UNCACHEABLE)?"UC":
((type==MTRR_TYPE_WRBACK)?"WB":"Other")