src: Add missing include <stdint.h>

Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/arch/x86/include/arch/registers.h

@@ -17,6 +17,8 @@
 #define __ARCH_REGISTERS_H
 
 #if !defined(__ASSEMBLER__)
+#include <stdint.h>
+
 #define DOWNTO8(A) \
 	union { \
 		struct { \

src/cpu/ti/am335x/uart.h

@@ -15,6 +15,8 @@
 #ifndef AM335X_UART_H
 #define AM335X_UART_H
 
+#include <stdint.h>
+
 #define AM335X_UART0_BASE	0x44e09000
 #define AM335X_UART1_BASE	0x48020000
 #define AM335X_UART2_BASE	0x48024000

src/drivers/i2c/max98373/chip.h

@@ -16,6 +16,9 @@
 /*
  * Maxim MAX98373 audio codec devicetree bindings
  */
+
+#include <stdint.h>
+
 struct drivers_i2c_max98373_config {
 	/* I2C Bus Frequency in Hertz (default 400kHz) */
 	uint32_t bus_speed;

src/drivers/i2c/rt5663/chip.h

@@ -16,6 +16,9 @@
 /*
  * Realtek RT5663 audio codec devicetree bindings
  */
+
+#include <stdint.h>
+
 struct drivers_i2c_rt5663_config {
 	/* I2C Bus Frequency in Hertz (default 400kHz) */
 	unsigned int bus_speed;

src/drivers/i2c/w83795/chip.h

@@ -13,6 +13,8 @@
  * GNU General Public License for more details.
  */
 
+#include <stdint.h>
+
 struct drivers_i2c_w83795_config {
 	uint8_t fanin_ctl1;
 	uint8_t fanin_ctl2;

src/drivers/intel/fsp2_0/include/fsp/upd.h

@@ -12,6 +12,8 @@
 #ifndef _FSP2_0_UPD_H_
 #define _FSP2_0_UPD_H_
 
+#include <stdint.h>
+
 struct FSP_UPD_HEADER {
 	///
 	/// UPD Region Signature. This signature will be

src/drivers/net/chip.h

@@ -14,6 +14,8 @@
 #ifndef __DRIVERS_R8168_CHIP_H__
 #define __DRIVERS_R8168_CHIP_H__
 
+#include <stdint.h>
+
 struct drivers_net_config {
 	uint16_t customized_leds;
 	unsigned wake;	/* Wake pin for ACPI _PRW */

src/drivers/parade/ps8625/ps8625.h

@@ -16,6 +16,8 @@
 #ifndef __PS8625_H__
 #define __PS8625_H__
 
+#include <stdint.h>
+
 struct parade_write {
 	uint8_t offset;
 	uint8_t reg;

src/drivers/siemens/nc_fpga/nc_fpga.h

@@ -16,6 +16,8 @@
 #ifndef _SIEMENS_NC_FPGA_H_
 #define _SIEMENS_NC_FPGA_H_
 
+#include <stdint.h>
+
 #define NC_MAGIC_OFFSET			0x020
 #define  NC_FPGA_MAGIC			0x4E433746
 #define NC_CAP1_OFFSET			0x080

src/include/cpu/amd/vr.h

@@ -7,6 +7,8 @@
 #ifndef CPU_AMD_VR_H
 #define CPU_AMD_VR_H
 
+#include <stdint.h>
+
 #define VRC_INDEX				0xAC1C	// Index register
 #define VRC_DATA				0xAC1E	// Data register
 #define VR_UNLOCK				0xFC53	// Virtual register unlock code

src/include/device/path.h

@@ -1,6 +1,8 @@
 #ifndef DEVICE_PATH_H
 #define DEVICE_PATH_H
 
+#include <stdint.h>
+
 enum device_path_type {
 	DEVICE_PATH_NONE = 0,
 	DEVICE_PATH_ROOT,

src/include/swab.h

@@ -1,6 +1,3 @@
-#ifndef _SWAB_H
-#define _SWAB_H
-
 /*
  * linux/byteorder/swab.h
  * Byte-swapping, independently from CPU endianness
@@ -18,6 +15,12 @@
 /* casts are necessary for constants, because we never know how for sure
  * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way.
  */
+
+#ifndef _SWAB_H
+#define _SWAB_H
+
+#include <stdint.h>
+
 #define swab16(x) \
 	((unsigned short)( \
 		(((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \

src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h

@@ -17,6 +17,8 @@
  * Copyed over from qemu soure tree, include/hw/nvram/fw_cfg.h
  */
 
+#include <stdint.h>
+
 #define FW_CFG_SIGNATURE        0x00
 #define FW_CFG_ID               0x01
 #define FW_CFG_UUID             0x02

src/mainboard/google/urara/urara_boardid.h

@@ -16,6 +16,8 @@
 #ifndef __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__
 #define __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__
 
+#include <stdint.h>
+
 /*
  * List of URARA derivatives board ID definitions. They are stored in uint8_t
  * across the code, using #defines here not to imply any specific size.

src/mainboard/pcengines/apu1/gpio_ftns.h

@@ -16,6 +16,8 @@
 #ifndef GPIO_FTNS_H
 #define GPIO_FTNS_H
 
+#include <stdint.h>
+
 uintptr_t find_gpio_base(void);
 void configure_gpio(uintptr_t base_addr, u32 gpio, u8 iomux_ftn, u8 setting);
 u8 read_gpio(uintptr_t base_addr, u32 gpio);

src/northbridge/intel/e7505/raminit.h

@@ -14,6 +14,8 @@
 #ifndef RAMINIT_H
 #define RAMINIT_H
 
+#include <stdint.h>
+
 #define MAX_DIMM_SOCKETS_PER_CHANNEL 4
 #define MAX_NUM_CHANNELS 2
 #define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL)

src/northbridge/intel/haswell/pei_data.h

@@ -30,6 +30,8 @@
 #ifndef PEI_DATA_H
 #define PEI_DATA_H
 
+#include <stdint.h>
+
 typedef void (*tx_byte_func)(unsigned char byte);
 #define PEI_VERSION 15
 

src/northbridge/intel/sandybridge/pei_data.h

@@ -30,6 +30,8 @@
 #ifndef PEI_DATA_H
 #define PEI_DATA_H
 
+#include <stdint.h>
+
 typedef struct {
 	uint16_t mode;                // 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto
 	uint16_t hs_port_switch_mask; // 4 bit mask, 1: switchable, 0: not switchable

src/security/tpm/tss/tcg-1.2/tss_commands.h

@@ -14,6 +14,8 @@
  * GNU General Public License for more details.
  */
 
+#include <stdint.h>
+
 const struct s_tpm_extend_cmd{
 	uint8_t buffer[34];
 	uint16_t pcrNum;

src/security/tpm/tss/tcg-1.2/tss_internal.h

@@ -6,6 +6,8 @@
 #ifndef TCG_TSS_INTERNAL_H_
 #define TCG_TSS_INTERNAL_H_
 
+#include <stdint.h>
+
 /*
  * These numbers derive from adding the sizes of command fields as shown in the
  * TPM commands manual.

src/security/tpm/tss_errors.h

@@ -12,6 +12,8 @@
 #ifndef TSS_ERRORS_H_
 #define TSS_ERRORS_H_
 
+#include <stdint.h>
+
 #define TPM_E_BASE 0x0
 #define TPM_E_NON_FATAL 0x800
 

src/soc/broadcom/cygnus/include/soc/tz.h

@@ -14,6 +14,8 @@
 #ifndef __SOC_BROADCOM_CYGNUS_TZ_H__
 #define __SOC_BROADCOM_CYGNUS_TZ_H__
 
+#include <stdint.h>
+
 #define TZ_STATE_SECURE				0
 #define TZ_STATE_NON_SECURE			1
 

src/soc/cavium/cn81xx/include/soc/cpu.h

@@ -17,6 +17,8 @@
 #ifndef __SOC_CAVIUM_CN81XX_CPU_H__
 #define __SOC_CAVIUM_CN81XX_CPU_H__
 
+#include <stdint.h>
+
 /**
  * Number of the Core on which the program is currently running.
  *

src/soc/cavium/common/include/soc/bootblock.h

@@ -16,6 +16,8 @@
 #ifndef SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_
 #define SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_
 
+#include <stdint.h>
+
 void bootblock_mainboard_early_init(void);
 void bootblock_soc_early_init(void);
 void bootblock_soc_init(void);

src/soc/intel/apollolake/include/soc/usb.h

@@ -18,6 +18,8 @@
 #ifndef _SOC_APOLLOLAKE_USB_H_
 #define _SOC_APOLLOLAKE_USB_H_
 
+#include <stdint.h>
+
 #define APOLLOLAKE_USB2_PORT_MAX 8
 
 struct usb2_eye_per_port {

src/soc/intel/broadwell/chip.h

@@ -17,6 +17,8 @@
 #ifndef _SOC_INTEL_BROADWELL_CHIP_H_
 #define _SOC_INTEL_BROADWELL_CHIP_H_
 
+#include <stdint.h>
+
 struct soc_intel_broadwell_config {
 	/*
 	 * Interrupt Routing configuration

src/soc/intel/cannonlake/include/soc/ebda.h

@@ -16,6 +16,8 @@
 #ifndef SOC_EBDA_H
 #define SOC_EBDA_H
 
+#include <stdint.h>
+
 struct ebda_config {
 	uint32_t signature; /* 0x00 - EBDA signature */
 	uint32_t tolum_base; /* 0x04 - coreboot memory start */

src/soc/intel/denverton_ns/chip.h

@@ -17,6 +17,8 @@
 #ifndef SOC_INTEL_DENVERTON_NS_CHIP_H
 #define SOC_INTEL_DENVERTON_NS_CHIP_H
 
+#include <stdint.h>
+
 struct soc_intel_denverton_ns_config {
 	/**
 	 * Interrupt Routing configuration

src/soc/intel/icelake/include/soc/ebda.h

@@ -16,6 +16,8 @@
 #ifndef SOC_EBDA_H
 #define SOC_EBDA_H
 
+#include <stdint.h>
+
 struct ebda_config {
 	uint32_t signature; /* 0x00 - EBDA signature */
 	uint32_t tolum_base; /* 0x04 - coreboot memory start */

src/soc/intel/quark/include/soc/i2c.h

@@ -16,6 +16,8 @@
 #ifndef _QUARK_I2C_H_
 #define _QUARK_I2C_H_
 
+#include <stdint.h>
+
 typedef volatile struct _I2C_REGS {
 	volatile uint32_t ic_con;  /* 00: Control Register */
 	volatile uint32_t ic_tar;  /* 04: Master Target Address */

src/soc/intel/skylake/include/soc/ebda.h

@@ -16,6 +16,8 @@
 #ifndef SOC_EBDA_H
 #define SOC_EBDA_H
 
+#include <stdint.h>
+
 struct ebda_config {
 	uint32_t signature; /* 0x00 - EBDA signature */
 	uint32_t tolum_base; /* 0x04 - coreboot memory start */

src/soc/nvidia/tegra210/include/soc/flow_ctrl.h

@@ -16,6 +16,8 @@
 #ifndef _TEGRA210_FLOW_CTRL_H_
 #define _TEGRA210_FLOW_CTRL_H_
 
+#include <stdint.h>
+
 void flowctrl_cpu_off(int cpu);
 void flowctrl_cpu_on(int cpu);
 void flowctrl_cpu_suspend(int cpu);

src/soc/qualcomm/ipq806x/include/soc/ebi2.h

@@ -19,6 +19,8 @@
 #ifndef __SOC_QUALCOMM_IPQ806X_EBI2_H_
 #define __SOC_QUALCOMM_IPQ806X_EBI2_H_
 
+#include <stdint.h>
+
 #define EBI2CR_BASE                                       (0x1A600000)
 
 struct ebi2cr_regs {

src/southbridge/intel/bd82x6x/chip.h

@@ -16,6 +16,8 @@
 #ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H
 #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H
 
+#include <stdint.h>
+
 struct southbridge_intel_bd82x6x_config {
 	/**
 	 * GPI Routing configuration

src/southbridge/intel/fsp_bd82x6x/chip.h

@@ -16,6 +16,8 @@
 #ifndef SOUTHBRIDGE_INTEL_FSP_BD82X6X_CHIP_H
 #define SOUTHBRIDGE_INTEL_FSP_BD82X6X_CHIP_H
 
+#include <stdint.h>
+
 struct southbridge_intel_fsp_bd82x6x_config {
 	/**
 	 * Interrupt Routing configuration

src/southbridge/intel/fsp_i89xx/chip.h

@@ -16,6 +16,8 @@
 #ifndef SOUTHBRIDGE_INTEL_I89XX_CHIP_H
 #define SOUTHBRIDGE_INTEL_I89XX_CHIP_H
 
+#include <stdint.h>
+
 struct southbridge_intel_fsp_i89xx_config {
 	/**
 	 * Interrupt Routing configuration

src/southbridge/intel/i82801dx/chip.h

@@ -17,6 +17,8 @@
 #ifndef I82801DX_CHIP_H
 #define I82801DX_CHIP_H
 
+#include <stdint.h>
+
 struct southbridge_intel_i82801dx_config {
 	int enable_usb;
 	int enable_native_ide;

src/southbridge/intel/i82801gx/chip.h

@@ -16,6 +16,8 @@
 #ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
 #define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
 
+#include <stdint.h>
+
 struct southbridge_intel_i82801gx_config {
 	/**
 	 * Interrupt Routing configuration

src/southbridge/intel/i82801ix/chip.h

@@ -17,6 +17,8 @@
 #ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H
 #define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H
 
+#include <stdint.h>
+
 enum {
 	THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3,
 	THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7

src/southbridge/intel/i82801jx/chip.h

@@ -17,6 +17,8 @@
 #ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H
 #define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H
 
+#include <stdint.h>
+
 enum {
 	THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3,
 	THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7

src/southbridge/intel/lynxpoint/chip.h

@@ -16,6 +16,8 @@
 #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H
 #define SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H
 
+#include <stdint.h>
+
 struct southbridge_intel_lynxpoint_config {
 	/**
 	 * Interrupt Routing configuration

src/superio/nuvoton/npcd378/npcd378.h

@@ -17,6 +17,8 @@
 #ifndef SUPERIO_NUVOTON_NPCD378_H
 #define SUPERIO_NUVOTON_NPCD378_H
 
+#include <stdint.h>
+
 /* HWM at LDN8 */
 #define NPCD837_HWM_WRITE_LOCK_CTRL 0x4
 #define NPCD837_HWM_WRITE_LOCK_BIT 0x1