soc/amd/picasso: introduce and use chipset device tree

The chipset devicetree only has the essential PCIe devices enabled that
are needed for the SoC code to work. It also defines aliases for all
PCIe devices that can be used to reference the devices in the mainboard-
specific devicetrees and devicetree overrides. To make the change easier
to review that part will be done in a follow-up patch.

Despite missing in the PPR, device pci 18.7 exists on Picasso.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b7c3fd32579a23539594672593a243172c161c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held
2021-02-13 02:36:02 +01:00
parent db4b21a1d0
commit c4eb45fa85
8 changed files with 50 additions and 94 deletions

View File

@@ -37,9 +37,7 @@ chip soc/amd/picasso
# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on
subsystemid 0x1022 0x1510 inherit
device pci 1.6 off end # GPP Bridge 5
device pci 1.7 on end # GPP Bridge 6 - NVME
device pci 14.6 off end # Non-Functional SDHCI
end # domain
device mmio 0xfedc4000 on end