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soc/amd/phoenix: Fix APOB NV size/base for non-vboot builds

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The APOB NV size/base are embedded into the amdfw binary and read by
the PSP. These need to be synchronized with the FMAP region used by
coreboot to store the APOB data. soc_update_apob_cache() will only
use RECOVERY_MRC_CACHE if supported and if vboot is enabled, so the
NV base passed to the PSP needs to reflect that as well.

This fixes the issue of RAM training running on every boot on
non-vboot builds for Myst boards.

TEST=untested, but same change as made for Mendocino

Change-Id: Ib4a78a39badf0a067e22eebe5869e5ea51723f35
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This commit is contained in:
Matt DeVillier 2024-07-09 16:54:51 -05:00 committed by Felix Held
parent baec1c858d
commit c4f735105b
1 changed files with 1 additions and 1 deletions
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2
src/soc/amd/phoenix/Makefile.mk
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@ -130,7 +130,7 @@ APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE)
APOB_NV_BASE=$(call _tohex,$(call int-subtract, \
$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) $(FMAP_FLASH_START)))
ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE),y)
ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE)$(CONFIG_VBOOT),yy)
# On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE.
# Else use RW_MRC_CACHE. This entry will be added in the RO section.
APOB_NV_RO_SIZE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE)