From c54358d8fcec1d0e18a32e9705e39d5180ab53fc Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jackpot51@gmail.com>
Date: Fri, 10 Feb 2023 09:39:08 -0700
Subject: [PATCH] gaze18-40x0: fill in overridetree

Change-Id: Ie411e9f103b07b079681a73cef11f44cd58f0976
---
 .../rpl/variants/gaze18-40x0/overridetree.cb  | 80 +++++++++++++++++++
 1 file changed, 80 insertions(+)

diff --git a/src/mainboard/system76/rpl/variants/gaze18-40x0/overridetree.cb b/src/mainboard/system76/rpl/variants/gaze18-40x0/overridetree.cb
index 10cd03d4e1..dd2d626d0f 100644
--- a/src/mainboard/system76/rpl/variants/gaze18-40x0/overridetree.cb
+++ b/src/mainboard/system76/rpl/variants/gaze18-40x0/overridetree.cb
@@ -1,5 +1,85 @@
 chip soc/intel/alderlake
 	device domain 0 on
 		subsystemid 0x1558 0xa671 inherit
+
+		#TODO: DDIB and DDID are both connected to TBT
+
+		device ref xhci on
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB-A 3.2 Gen 1 (Left)
+			register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB-A 2.0 (Left)
+			register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C 3.2 Gen 2 (Rear)
+			register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Thunderbolt (Right)
+			register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Secure Pad
+			register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A 3.2 Gen 1 (Left)
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C 3.2 Gen 2 (Rear)
+		end
+
+		#TODO: Reversed
+		device ref pcie5_1 off
+			# CPU PCIe RP#2 x8, Clock 14 (DGPU)
+			register "cpu_pcie_rp[CPU_RP(2)]" = "{
+				.clk_src = 14,
+				.clk_req = 14,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+
+		device ref pcie_rp3 on
+			# PCH RP#3 x1, Clock 13 (GLAN)
+			register "pch_pcie_rp[PCH_RP(3)]" = "{
+				.clk_src = 13,
+				.clk_req = 13,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+
+		device ref pcie_rp5 on
+			# PCH RP#5 x1, Clock 12 (CARD)
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 12,
+				.clk_req = 12,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+
+		device ref pcie_rp8 on
+			# PCH RP#8 x1, Clock 11 (WLAN)
+			register "pch_pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 11,
+				.clk_req = 11,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+
+		device ref pcie_rp13 on
+			# PCH RP#13 x4, Clock 10 (SSD1)
+			register "pch_pcie_rp[PCH_RP(13)]" = "{
+				.clk_src = 10,
+				.clk_req = 10,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+
+		device ref pcie_rp21 on
+			# PCH RP#21 x4, Clock 15 (TBT)
+			register "pch_pcie_rp[PCH_RP(21)]" = "{
+				.clk_src = 15,
+				.clk_req = 15,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+
+		device ref pcie_rp25 on
+			# PCH RP#25 x4, Clock 8 (SSD2)
+			register "pch_pcie_rp[PCH_RP(25)]" = "{
+				.clk_src = 8,
+				.clk_req = 8,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
 	end
 end