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cpu/intel/haswell: Rework acpi/cpu.asl

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Use acpigen_write_processor_cnot to implement notifications the CPU.
Generate PPKG in SSDT.

Change-Id: I126989e8737720f55f7ce113ff4e32bfe0f22620
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29885
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
2018-11-28 12:09:23 +01:00
committed by Duncan Laurie
parent 8afc1352f0
commit c54d14f5b4
5 changed files with 21 additions and 69 deletions
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7
src/cpu/intel/haswell/acpi.c
View File

@@ -339,6 +339,13 @@ void generate_cpu_entries(struct device *device)
acpigen_pop_len();
}
}
/* PPKG is usually used for thermal management
of the first and only package. */
acpigen_write_processor_package("PPKG", 0, cores_per_package);
/* Add a method to notify processor nodes */
acpigen_write_processor_cnot(cores_per_package);
}
struct chip_operations cpu_intel_haswell_ops = {

77
src/cpu/intel/haswell/acpi/cpu.asl
View File

@@ -14,84 +14,23 @@
* GNU General Public License for more details.
*/
/* These devices are created at runtime */
External (\_PR.CP00, DeviceObj)
External (\_PR.CP01, DeviceObj)
External (\_PR.CP02, DeviceObj)
External (\_PR.CP03, DeviceObj)
External (\_PR.CP04, DeviceObj)
External (\_PR.CP05, DeviceObj)
External (\_PR.CP06, DeviceObj)
External (\_PR.CP07, DeviceObj)
/* These come from the dynamically created CPU SSDT */
External (\_PR.CNOT, MethodObj)
/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
/* Notify OS to re-read CPU tables */
Method (PNOT)
{
If (LGreaterEqual (\PCNT, 2)) {
Notify (\_PR.CP00, 0x81) // _CST
Notify (\_PR.CP01, 0x81) // _CST
}
If (LGreaterEqual (\PCNT, 4)) {
Notify (\_PR.CP02, 0x81) // _CST
Notify (\_PR.CP03, 0x81) // _CST
}
If (LGreaterEqual (\PCNT, 8)) {
Notify (\_PR.CP04, 0x81) // _CST
Notify (\_PR.CP05, 0x81) // _CST
Notify (\_PR.CP06, 0x81) // _CST
Notify (\_PR.CP07, 0x81) // _CST
}
\_PR.CNOT (0x81)
}
/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */
/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
If (LGreaterEqual (\PCNT, 2)) {
Notify (\_PR.CP00, 0x80) // _PPC
Notify (\_PR.CP01, 0x80) // _PPC
}
If (LGreaterEqual (\PCNT, 4)) {
Notify (\_PR.CP02, 0x80) // _PPC
Notify (\_PR.CP03, 0x80) // _PPC
}
If (LGreaterEqual (\PCNT, 8)) {
Notify (\_PR.CP04, 0x80) // _PPC
Notify (\_PR.CP05, 0x80) // _PPC
Notify (\_PR.CP06, 0x80) // _PPC
Notify (\_PR.CP07, 0x80) // _PPC
}
\_PR.CNOT (0x80)
}
/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
If (LGreaterEqual (\PCNT, 2)) {
Notify (\_PR.CP00, 0x82) // _TPC
Notify (\_PR.CP01, 0x82) // _TPC
}
If (LGreaterEqual (\PCNT, 4)) {
Notify (\_PR.CP02, 0x82) // _TPC
Notify (\_PR.CP03, 0x82) // _TPC
}
If (LGreaterEqual (\PCNT, 8)) {
Notify (\_PR.CP04, 0x82) // _TPC
Notify (\_PR.CP05, 0x82) // _TPC
Notify (\_PR.CP06, 0x82) // _TPC
Notify (\_PR.CP07, 0x82) // _TPC
}
}
/* Return a package containing enabled processor entries */
Method (PPKG)
{
If (LGreaterEqual (\PCNT, 8)) {
Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03,
\_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07})
} ElseIf (LGreaterEqual (\PCNT, 4)) {
Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03})
} ElseIf (LGreaterEqual (\PCNT, 2)) {
Return (Package() {\_PR.CP00, \_PR.CP01})
} Else {
Return (Package() {\_PR.CP00})
}
\_PR.CNOT (0x82)
}