From c54d186717b584117c1beffda3e0beb89652eebf Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 17 Jul 2024 11:43:26 +0000 Subject: [PATCH] device/pci_ids: Add new Intel PTL device IDs for CSE0 This patch adds new CSE0 PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the CSE0 driver's `pci_device_ids` list to include these new IDs. Finally, dropped unused CSE1-3 PCI IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5656aeb8c5439c8361aeb3a3d759df1216d84f8b Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/83517 Reviewed-by: Angel Pons Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) --- src/include/device/pci_ids.h | 6 ++---- src/soc/intel/common/block/cse/cse.c | 3 ++- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 716f386830..445658f63b 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4679,10 +4679,8 @@ #define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d #define PCI_DID_INTEL_MTL_CSE0 0x7e70 #define PCI_DID_INTEL_LNL_CSE0 0xa870 -#define PCI_DID_INTEL_PTL_CSE0 0xe470 -#define PCI_DID_INTEL_PTL_CSE1 0xe471 -#define PCI_DID_INTEL_PTL_CSE2 0xe474 -#define PCI_DID_INTEL_PTL_CSE3 0xe475 +#define PCI_DID_INTEL_PTL_H_CSE0 0xe470 +#define PCI_DID_INTEL_PTL_U_H_CSE0 0xe370 /* Intel XDCI device Ids */ #define PCI_DID_INTEL_APL_XDCI 0x5aaa diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index ed07f69283..6389044428 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1479,7 +1479,8 @@ struct device_operations cse_ops = { }; static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_PTL_CSE0, + PCI_DID_INTEL_PTL_H_CSE0, + PCI_DID_INTEL_PTL_U_H_CSE0, PCI_DID_INTEL_LNL_CSE0, PCI_DID_INTEL_MTL_CSE0, PCI_DID_INTEL_APL_CSE0,