mb/google: Remove blank lines before '}' and after '{'
Change-Id: If68303cd59b287c8a5c982063b2ab75fd74898d6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
This commit is contained in:
Elyes Haouas
@@ -191,7 +191,6 @@ static void mainboard_fill_ssdt(const struct device *dev)
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mainboard_generate_s0ix_hook();
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acpigen_write_method_end(); /* Method */
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acpigen_write_scope_end(); /* Scope */
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}
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void __weak variant_fill_ssdt(const struct device *dev)
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@@ -191,7 +191,6 @@ static void mainboard_fill_ssdt(const struct device *dev)
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mainboard_generate_s0ix_hook();
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acpigen_write_method_end(); /* Method */
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acpigen_write_scope_end(); /* Scope */
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}
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void __weak variant_fill_ssdt(const struct device *dev)
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@@ -39,6 +39,5 @@ static void fw_config_handle(void *unused)
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printk(BIOS_INFO, "BT offload enabled over I2S with NAU88L25B\n");
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gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
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}
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
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@@ -39,6 +39,5 @@ static void fw_config_handle(void *unused)
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printk(BIOS_INFO, "BT offload enabled over I2S with NAU88L25B\n");
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gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
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}
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
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@@ -40,6 +40,5 @@ static void fw_config_handle(void *unused)
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printk(BIOS_INFO, "BT offload enabled over I2S with MAX98360+RT5682VS\n");
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gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
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}
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
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@@ -39,6 +39,5 @@ static void fw_config_handle(void *unused)
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printk(BIOS_INFO, "BT offload enabled over I2S with NAU88L25B\n");
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gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
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}
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
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@@ -17,5 +17,4 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
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if (fw_config_probe(FW_CONFIG(FPMCU_MASK, FPMCU_DISABLED)))
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config->serial_io_gspi_mode[PchSerialIoIndexGSPI1] = PchSerialIoDisabled;
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}
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@@ -24,5 +24,4 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
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gpio_padbased_override(padbased_table, wfc_disable_pads,
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ARRAY_SIZE(wfc_disable_pads));
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}
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}
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@@ -221,7 +221,6 @@ const struct pad_config *variant_gpio_override_table(size_t *num)
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{
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*num = ARRAY_SIZE(gpio_overrides);
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return gpio_overrides;
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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@@ -18,5 +18,4 @@ void butterfly_ec_init(void)
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/* Disable wake on USB, LAN & RTC */
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/* Enable Wake from Keyboard */
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ec_mem_write(EC_EC_PSW, EC_PSW_IKB);
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}
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@@ -126,7 +126,6 @@ static void program_keyboard_type(uintptr_t search_address, u32 search_length)
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char kbd_type = EC_KBD_EN; /* Default keyboard type is English */
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if (search_length != -1) {
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/*
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* Search for keyboard_layout identifier
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* The only options in the EC are Japanese or English.
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@@ -21,7 +21,6 @@ void setup_chromeos_gpios(void)
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gpio_output(GPIO_BEEP_ON, 0);
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else if (CONFIG(CHERRY_USE_RT1011))
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gpio_output(GPIO_RST_RT1011, 0);
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}
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void fill_lb_gpios(struct lb_gpios *gpios)
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@@ -174,7 +174,6 @@ bool mainboard_regulator_is_enabled(enum mtk_regulator regulator)
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}
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return !!enabled;
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}
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}
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printk(BIOS_ERR, "Invalid regulator ID: %d\n; assuming disabled", regulator);
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@@ -13,7 +13,6 @@ void variant_memory_init_params(MEMORY_INIT_UPD *memory_params)
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* RAMID = 12 - 2GiB Micron MT52L256M32D1PF
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*/
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if (ram_id == 4 || ram_id == 12) {
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/*
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* For new micron part, it requires read/receive
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* enable training before sending cmds to get MR8.
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@@ -5,7 +5,6 @@
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void board_silicon_USB2_override(SILICON_INIT_UPD *params)
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{
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if (SocStepping() >= SocD0) {
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//Follow Intel recommendation to set
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//BSW D-stepping PERPORTRXISET 2 (low strength)
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params->Usb2Port0PerPortPeTxiSet = 7;
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@@ -13,7 +13,6 @@ void variant_memory_init_params(MEMORY_INIT_UPD *memory_params)
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* RAMID = 7 - 2GiB Micron MT52L256M32D1PF-107
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*/
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if (ram_id == 5 || ram_id == 7) {
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/*
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* For new micron part, it requires read/receive
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* enable training before sending cmds to get MR8.
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@@ -5,7 +5,6 @@
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void board_silicon_USB2_override(SILICON_INIT_UPD *params)
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{
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if (SocStepping() >= SocD0) {
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//Follow Intel recommendation to set
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//BSW D-stepping PERPORTRXISET 2 (low strength)
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params->D0Usb2Port0PerPortRXISet = 2;
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@@ -13,7 +13,6 @@ void variant_memory_init_params(MEMORY_INIT_UPD *memory_params)
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* RAMID = 3 - 2GiB Micron MT52L256M32D1PF-107
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*/
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if (ram_id == 2 || ram_id == 3) {
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/*
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* For new micron part, it requires read/receive
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* enable training before sending cmds to get MR8.
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@@ -13,7 +13,6 @@ void variant_memory_init_params(MEMORY_INIT_UPD *memory_params)
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* RAMID = 2 - 2GiB Micron MT52L256M32D1PF-107
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*/
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if (ram_id == 2 || ram_id == 0xA) {
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/*
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* For new micron part, it requires read/receive
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* enable training before sending cmds to get MR8.
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@@ -13,7 +13,6 @@ void variant_memory_init_params(MEMORY_INIT_UPD *memory_params)
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* RAMID = 2 - 2GiB Micron MT52L256M32D1PF-107
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*/
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if (ram_id == 2 || ram_id == 0xA) {
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/*
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* For new micron part, it requires read/receive
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* enable training before sending cmds to get MR8.
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@@ -13,7 +13,6 @@ void variant_memory_init_params(MEMORY_INIT_UPD *memory_params)
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* RAMID = 5 - 2GiB Micron MT52L256M32D1PF-107
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*/
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if (ram_id == 4 || ram_id == 5) {
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/*
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* For new micron part, it requires read/receive
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* enable training before sending cmds to get MR8.
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@@ -13,7 +13,6 @@ void variant_memory_init_params(MEMORY_INIT_UPD *memory_params)
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* RAMID = 11 - 4GiB Micron MT52L256M32D1PF-107
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*/
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if (ram_id == 3 || ram_id == 11) {
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/*
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* For new micron part, it requires read/receive
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* enable training before sending cmds to get MR8.
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@@ -237,5 +237,4 @@ static struct soc_gpio_config gpio_config = {
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struct soc_gpio_config *mainboard_get_gpios(void)
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{
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return &gpio_config;
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}
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@@ -128,18 +128,15 @@ static void mainboard_generate_s0ix_hook(void)
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static void mainboard_fill_ssdt(const struct device *dev)
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{
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acpigen_write_scope("\\_SB");
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acpigen_write_method_serialized("MS0X", 1);
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mainboard_generate_s0ix_hook();
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acpigen_write_method_end(); /* Method */
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acpigen_write_scope_end(); /* Scope */
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}
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void __weak variant_generate_s0ix_hook(enum s0ix_entry entry)
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{
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/* Add board-specific MS0X entries */
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/*
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if (s0ix_entry == S0IX_ENTRY) {
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@@ -7,7 +7,6 @@
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#include <soc/romstage.h>
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static const struct mb_cfg baseboard_memcfg_cfg = {
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.dq_map[DDR_CH0] = {
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{0xf, 0xf0},
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{0xf, 0xf0},
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@@ -7,7 +7,6 @@
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#include <soc/romstage.h>
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static const struct mb_cfg board_memcfg_cfg = {
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.dq_map[DDR_CH0] = {
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{0xf, 0xf0},
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{0xf, 0xf0},
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@@ -9,14 +9,12 @@
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/* Pad configuration in ramstage */
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static const struct pad_config not_board6or8_gpio_table[] = {
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/* C12 : AP_PEN_DET_ODL */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, UP_20K, DEEP),
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};
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/* bid6: Pad configuration for board version 6 or 8 in ramstage */
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static const struct pad_config board6or8_gpio_table[] = {
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/* A10 : WWAN_EN */
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PAD_CFG_GPO(GPP_A10, 1, PWROK),
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@@ -19,7 +19,6 @@ const char *get_wifi_sar_cbfs_filename(void)
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uint32_t sku_id = google_chromeec_get_board_sku();
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if (fw_config_probe(FW_CONFIG(TABLETMODE, TABLETMODE_ENABLED))) {
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if (sku_id >= OSCINO_SKU_START && sku_id <= OSCINO_SKU_END)
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return "wifi_sar-oscino.hex";
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else
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@@ -5,7 +5,6 @@
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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/* A11 : TOUCH_RPT_EN */
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PAD_NC(GPP_A11, NONE),
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@@ -5,7 +5,6 @@
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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/* A11 : TOUCH_RPT_EN */
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PAD_NC(GPP_A11, NONE),
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@@ -6,11 +6,9 @@
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void __weak variant_nhlt_init(struct nhlt *nhlt)
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{
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/* RT5663 Headset codec */
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if (nhlt_soc_add_rt5663(nhlt, AUDIO_LINK_SSP1))
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printk(BIOS_ERR, "Couldn't add headset codec.\n");
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}
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void __weak variant_nhlt_oem_overrides(const char **oem_id,
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@@ -15,5 +15,4 @@ void variant_nhlt_oem_overrides(const char **oem_id,
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void variant_chip_display_init(void)
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{
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}
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@@ -18,7 +18,6 @@ void variant_nhlt_init(struct nhlt *nhlt)
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/* MAXIM Smart Amps for left and right speakers. */
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if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0))
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printk(BIOS_ERR, "Couldn't add Maxim_98357 codec.\n");
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}
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void variant_nhlt_oem_overrides(const char **oem_id,
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@@ -39,7 +39,6 @@ void bootblock_mainboard_init(void)
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/* Is maskrom parameter address set to a sensible value? */
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if ((maskrom_param->start_magic != UBER_SBL_SHARED_INFO_START_MAGIC) ||
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(maskrom_param->end_magic != UBER_SBL_SHARED_INFO_END_MAGIC)) {
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printk(BIOS_INFO, "Uber-sbl: invalid magic!\n");
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} else {
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printk(BIOS_INFO, "Uber-sbl version: %s\n",
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@@ -8,7 +8,6 @@
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static void ipq_setup_tpm(void)
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{
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if (CONFIG(I2C_TPM)) {
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gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO,
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GPIO_PULL_UP, GPIO_6MA, 1);
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@@ -9,7 +9,6 @@
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#include <types.h>
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static const char *sdram_configs[] = {
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/* Samsung K4E6E304EB-EGCE */
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[0] = "sdram-lpddr3-generic-4GB",
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@@ -14,5 +14,4 @@ void mb_pre_fspm(void)
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gpio_configure_pads_with_override(base_gpios, base_num_gpios,
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override_gpios, override_num_gpios);
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}
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@@ -153,7 +153,6 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
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* See https://review.coreboot.org/c/coreboot/+/32111 .
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*/
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static const struct pad_config default_sleep_gpio_table[] = {
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};
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/*
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@@ -161,7 +160,6 @@ static const struct pad_config default_sleep_gpio_table[] = {
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* default_sleep_gpio_table but also, turn off FPMCU.
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*/
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static const struct pad_config s5_sleep_gpio_table[] = {
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};
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const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num)
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@@ -135,7 +135,6 @@ static void mainboard_enable(struct device *dev)
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{
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/* Initialize the PIRQ data structures for consumption */
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pirq_setup();
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}
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int mainboard_get_xhci_oc_map(uint16_t *map)
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@@ -12,5 +12,4 @@ void bootblock_mainboard_init(void)
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2);
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gpio_set_spi_driving(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK,
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10);
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}
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@@ -4,5 +4,4 @@
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void bootblock_mainboard_init(void)
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{
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}
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@@ -5,7 +5,6 @@
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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}
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int get_ec_is_trusted(void)
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@@ -50,7 +50,6 @@ static void set_clock_sources(void)
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clrsetbits32(&clk_rst->clk_src_disp1,
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CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
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2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
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}
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static void setup_pinmux(void)
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@@ -50,7 +50,6 @@ static void set_clock_sources(void)
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clrsetbits32(&clk_rst->clk_src_disp1,
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CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
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2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
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}
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static void setup_pinmux(void)
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@@ -50,7 +50,6 @@ static void set_clock_sources(void)
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clrsetbits32(&clk_rst->clk_src_disp1,
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CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
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2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
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}
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static void setup_pinmux(void)
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@@ -62,7 +62,6 @@ void __weak variant_smi_sleep(u8 slp_typ)
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void power_off_lte_module(void)
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{
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const struct gpio_with_delay lte_power_off_gpios[] = {
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{
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GPIO_161, /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */
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@@ -5,7 +5,6 @@
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#include <gpio.h>
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static const struct pad_config default_override_table[] = {
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PAD_NC(GPIO_50, UP_20K), /* PCH_I2C_PEN_SDA -- unused */
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PAD_NC(GPIO_51, UP_20K), /* PCH_I2C_PEN_SCL -- unused */
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PAD_NC(GPIO_52, UP_20K), /* PCH_I2C_P_SENSOR_SDA -- unused */
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@@ -5,7 +5,6 @@
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#include <gpio.h>
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static const struct pad_config default_override_table[] = {
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PAD_NC(GPIO_52, UP_20K),
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PAD_NC(GPIO_53, UP_20K),
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/* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */
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@@ -194,7 +194,6 @@ static void simple_spi_test(void)
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printk(BIOS_SPEW, "RTRY at %d(%p):\nRAM %08lx\nSPI %08lx\n",
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i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in);
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||||
}
|
||||
|
||||
}
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printk(BIOS_SPEW, "%d errors\n", errors);
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||||
}
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@@ -219,7 +218,6 @@ void main(void)
|
||||
|
||||
void __noreturn romstage_main(void)
|
||||
{
|
||||
|
||||
extern struct mem_timings mem_timings;
|
||||
int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP);
|
||||
int power_init_failed;
|
||||
|
||||
@@ -18,7 +18,6 @@ void variant_nhlt_init(struct nhlt *nhlt)
|
||||
/* MAXIM Smart Amps for left and right speakers. */
|
||||
if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0))
|
||||
printk(BIOS_ERR, "Couldn't add Maxim_98357 codec.\n");
|
||||
|
||||
}
|
||||
|
||||
void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id,
|
||||
|
||||
@@ -18,7 +18,6 @@ void variant_nhlt_init(struct nhlt *nhlt)
|
||||
/* MAXIM Smart Amps for left and right speakers. */
|
||||
if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0))
|
||||
printk(BIOS_ERR, "Couldn't add Maxim_98357 codec.\n");
|
||||
|
||||
}
|
||||
|
||||
void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id,
|
||||
|
||||
@@ -19,7 +19,6 @@ void variant_nhlt_init(struct nhlt *nhlt)
|
||||
/* Render time_slot is 0 and feedback time_slot is 2 */
|
||||
if (nhlt_soc_add_max98927(nhlt, AUDIO_LINK_SSP0, 0, 2))
|
||||
printk(BIOS_ERR, "Couldn't add Maxim MAX98927\n");
|
||||
|
||||
}
|
||||
|
||||
void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id,
|
||||
|
||||
@@ -409,7 +409,6 @@ static const struct pad_config romstage_gpio_table[] = {
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
{
|
||||
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
@@ -27,11 +27,9 @@ static void hynix_dram_cmos_check(void)
|
||||
cmos_bit_set = (byte_value & CMOS_BITMAP_SKIP_RESET_TOGGLE) != 0;
|
||||
|
||||
if (CONFIG(BOARD_GOOGLE_FROSTFLOW)) {
|
||||
|
||||
printk(BIOS_SPEW, "Checking DRAM part #\n");
|
||||
if (google_chromeec_cbi_get_dram_part_num(
|
||||
cbi_part_number, sizeof(cbi_part_number)) == 0) {
|
||||
|
||||
skip_reset_toggle = strncmp(cbi_part_number, HYNIX_PART_NAME, HYNIX_PART_LEN) == 0;
|
||||
if (skip_reset_toggle) {
|
||||
printk(BIOS_SPEW, "SKIP_RESET_TOGGLE needed, checking CMOS bit is set\n");
|
||||
|
||||
@@ -5,7 +5,6 @@
|
||||
|
||||
/* GPIO configuration in ramstage */
|
||||
static const struct soc_amd_gpio override_gpio_table[] = {
|
||||
|
||||
/* SOC_PEN_DETECT_ODL => Unused */
|
||||
PAD_NC(GPIO_3),
|
||||
/* EN_PWR_FP => Unused */
|
||||
|
||||
@@ -6,7 +6,6 @@
|
||||
|
||||
/* GPIO configuration in ramstage */
|
||||
static const struct soc_amd_gpio override_gpio_table[] = {
|
||||
|
||||
/* SOC_PEN_DETECT_ODL */
|
||||
PAD_NC(GPIO_3),
|
||||
|
||||
|
||||
@@ -39,7 +39,6 @@ void bootblock_mainboard_init(void)
|
||||
/* Is maskrom parameter address set to a sensible value? */
|
||||
if ((maskrom_param->start_magic != UBER_SBL_SHARED_INFO_START_MAGIC) ||
|
||||
(maskrom_param->end_magic != UBER_SBL_SHARED_INFO_END_MAGIC)) {
|
||||
|
||||
printk(BIOS_INFO, "Uber-sbl: invalid magic!\n");
|
||||
} else {
|
||||
printk(BIOS_INFO, "Uber-sbl version: %s\n",
|
||||
|
||||
@@ -63,7 +63,6 @@ static void early_ec_init(void)
|
||||
|
||||
if (((ec_status & 0x3) == EC_IN_RO_MODE) ||
|
||||
((ec_status & 0x3) == EC_IN_RECOVERY_MODE)) {
|
||||
|
||||
printk(BIOS_DEBUG, "EC Cold Boot Detected\n");
|
||||
if (!rec_mode) {
|
||||
/*
|
||||
|
||||
@@ -11,7 +11,6 @@
|
||||
|
||||
void stout_ec_init(void)
|
||||
{
|
||||
|
||||
printk(BIOS_DEBUG,"%s: EC FW version %x%x\n", __func__,
|
||||
ec_read(EC_FW_VER), ec_read(EC_FW_VER + 1));
|
||||
|
||||
|
||||
@@ -57,7 +57,6 @@ static void update_dmic_gpio(void)
|
||||
gpio->pins[0] = GPIO_13;
|
||||
else
|
||||
gpio->pins[0] = GPIO_6;
|
||||
|
||||
}
|
||||
|
||||
void variant_audio_update(void)
|
||||
@@ -73,7 +72,6 @@ void variant_audio_update(void)
|
||||
*/
|
||||
static void remove_usb_device_reset_gpio(const struct device *usb_dev)
|
||||
{
|
||||
|
||||
struct drivers_usb_acpi_config *usb_cfg;
|
||||
/* config_of dies on failure, so a NULL check is not required */
|
||||
usb_cfg = config_of(usb_dev);
|
||||
|
||||
@@ -119,7 +119,6 @@ const fsp_dxio_descriptor *baseboard_get_dxio_descriptors(size_t *num)
|
||||
*num = ARRAY_SIZE(pco_dxio_descriptors);
|
||||
return pco_dxio_descriptors;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static const fsp_ddi_descriptor pco_ddi_descriptors[] = {
|
||||
|
||||
@@ -193,7 +193,6 @@ static void wifi_power_reset_configure_active_low_power(void)
|
||||
PAD_GPO(GPIO_42, LOW),
|
||||
};
|
||||
gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table));
|
||||
|
||||
}
|
||||
|
||||
static void wifi_power_reset_configure_active_high_power(void)
|
||||
@@ -283,7 +282,6 @@ void baseboard_pcie_gpio_configure(void)
|
||||
__weak void finalize_gpios(int slp_typ)
|
||||
{
|
||||
if (variant_has_fingerprint() && slp_typ != ACPI_S3) {
|
||||
|
||||
if (fpmcu_needs_delay())
|
||||
mdelay(550);
|
||||
|
||||
|
||||
@@ -35,7 +35,6 @@ void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs,
|
||||
const fsp_ddi_descriptor **ddi_descs,
|
||||
size_t *ddi_num)
|
||||
{
|
||||
|
||||
*dxio_descs = baseboard_get_dxio_descriptors(dxio_num);
|
||||
*ddi_descs = &non_hdmi_ddi_descriptors[0];
|
||||
*ddi_num = ARRAY_SIZE(non_hdmi_ddi_descriptors);
|
||||
|
||||
@@ -35,7 +35,6 @@ void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs,
|
||||
const fsp_ddi_descriptor **ddi_descs,
|
||||
size_t *ddi_num)
|
||||
{
|
||||
|
||||
*dxio_descs = baseboard_get_dxio_descriptors(dxio_num);
|
||||
*ddi_descs = &non_hdmi_ddi_descriptors[0];
|
||||
*ddi_num = ARRAY_SIZE(non_hdmi_ddi_descriptors);
|
||||
|
||||
Reference in New Issue
Block a user