cpu/intel: Rename socket_mPGA478MN to socket_p

These marketing names are much easier to distinguish. My
mnemonic: Socket M => up to Merom, Socket P => up to Penryn.

Change-Id: I3c2a59596cf7f3cd763bd79962ad326ab080677b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31645
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/socket_p/Kconfig

@@ -0,0 +1,18 @@
+config CPU_INTEL_SOCKET_P
+	bool
+	select CPU_INTEL_MODEL_1067X
+	select CPU_INTEL_MODEL_6FX
+	select MMX
+	select SSE
+
+if CPU_INTEL_SOCKET_P
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xfefc0000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+
+endif

src/cpu/intel/socket_p/Makefile.inc

@@ -0,0 +1,15 @@
+subdirs-y += ../model_6fx
+subdirs-y += ../model_1067x
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../hyperthreading
+subdirs-y += ../speedstep
+
+cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
+postcar-y += ../car/p4-netburst/exit_car.S
+
+romstage-y += ../car/romstage.c