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soc/amd/cezanne: Allow to specify SPL table path in Kconfig

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BUG=b:216096562

Change-Id: I4a5ee335ea8808b595dc65ebafd15baedfbdd06e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Zheng Bao
2022-02-11 11:53:32 +08:00
committed by Felix Held
parent 514965a9ce
commit c5b912f788
3 changed files with 21 additions and 1 deletions
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14
src/soc/amd/cezanne/Kconfig
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@@ -377,6 +377,20 @@ config PSP_WHITELIST_FILE
depends on HAVE_PSP_WHITELIST_FILE
default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin"
config HAVE_SPL_FILE
bool "Have a mainboard specific SPL table file"
default n
help
Have a mainboard specific SPL table file, which is created by AMD
and put to 3rdparty/blobs.
If unsure, answer 'n'
config SPL_TABLE_FILE
string "SPL table file"
depends on HAVE_SPL_FILE
default "3rdparty/amd_blobs/cezanne/PSP/TypeId0x55_SplTableBl_CZN.sbin"
config PSP_SOFTFUSE_BITS
string "PSP Soft Fuse bits to enable"
default "28 6"