skylake: fill out gen_pmcon_* bitfields

Open coding bitfields is really annoying as no one knows
what they are unless you have a doc in front of you.
Fill in the bitfields for the GEN_PMCON_A and GEN_PMCON_B
registers.

BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados.

Original-Change-Id: Id48de68eaa3896c17d5da2ffb0bcf17062f73e5e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290336
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I968be9736419e26a771e0a0c3c964d540fbb1efe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11182
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/soc/intel/skylake/pmc.c

@@ -39,12 +39,15 @@
 #endif
 
 static const struct reg_script pch_pmc_misc_init_script[] = {
-	/* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */
-	REG_PCI_RMW16(GEN_PMCON_B, ~((3 << 4)|(1 << 10)),
-			(1 << 3)|(1 << 11)|(1 << 12)),
+	/* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */
+	REG_PCI_RMW16(GEN_PMCON_B,
+			~(S4MAW_MASK | SLP_S3_MIN_ASST_WDTH_MASK),
+			S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS |
+			DIS_SLP_X_STRCH_SUS_UP),
+	/* Enable SCI and clear SLP requests. */
 	REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN),
 	/* Indicate DRAM init done for MRC */
-	REG_PCI_OR8(GEN_PMCON_A, (1 << 23)),
+	REG_PCI_OR8(GEN_PMCON_A, DISB),
 	REG_SCRIPT_END
 };
 
@@ -237,6 +240,8 @@ static void pmc_init(struct device *dev)
 	/* Initialize power management */
 	pch_power_options();
 
+	/* Note that certain bits may be cleared from running script as
+	 * certain bit fields are write 1 to clear. */
 	reg_script_run_on_dev(dev, pch_pmc_misc_init_script);
 	pch_set_acpi_mode();