sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCK

Browse Source 
Pass timestamps and BIST to romstage using the same signature
as C_ENVIRONMENT_BOOTBLOCK will.

Change-Id: Ic90da6b1b5ac3b56c69b593ba447ed8e05c8a4e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2018-12-28 16:54:54 +02:00
parent ee2e936f40
commit c641f7ed9f
11 changed files with 116 additions and 87 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
src/cpu/intel/car/p4-netburst/cache_as_ram.S
View File

@@ -28,11 +28,12 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
.global bootblock_pre_c_entry
.code32
_cache_as_ram_setup:
/* Save the BIST result. */
movl %eax, %ebp
bootblock_pre_c_entry:
cache_as_ram:
post_code(0x20)
@@ -353,22 +354,24 @@ skip_cache_rom:
movl %eax, %cr0
/* Setup the stack. */
movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
movl %eax, %esp
/* Align the stack 16 bytes */
mov $_car_stack_end, %esp
/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
andl $0xfffffff0, %esp
/* Account for pushing the BIST result */
subl $12, %esp
subl $4, %esp
/* Restore the BIST result. */
movl %ebp, %eax
movl %esp, %ebp
pushl %eax
/* push TSC and BIST to stack */
movd %mm0, %eax
pushl %eax /* BIST */
movd %mm2, %eax
pushl %eax /* tsc[63:32] */
movd %mm1, %eax
pushl %eax /* tsc[31:0] */
before_romstage:
before_c_entry:
post_code(0x2f)
/* Call romstage.c main function. */
call romstage_main
call bootblock_c_entry_bist
/* Should never see this postcode */
post_code(POST_DEAD_CODE)