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mediatek: Share MMU operation code among similar SOCs

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Refactor MMU operation code which will be reused among similar SOCs.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm

Change-Id: Id8173da0a02e57e863263fcd89c91a9c089e8a0f
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Tristan Shieh
2018-07-04 13:37:39 +08:00
committed by Patrick Georgi
parent 1a26a30a7f
commit c645a5aac4
8 changed files with 106 additions and 51 deletions
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42
src/soc/mediatek/mt8173/mmu_operations.c
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@@ -15,55 +15,23 @@
#include <arch/io.h>
#include <arch/mmu.h>
#include <console/console.h>
#include <symbols.h>
#include <stdlib.h>
#include <stdint.h>
#include <soc/addressmap.h>
#include <soc/emi.h>
#include <soc/symbols.h>
#include <soc/infracfg.h>
#include <soc/mcucfg.h>
#include <soc/mmu_operations.h>
void mt8173_mmu_init(void)
void mtk_soc_after_dram(void)
{
mmu_init();
/* Set 0x0 to the end of 2GB dram address as device memory */
mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM);
/* SRAM is cached */
mmu_config_range(_sram_l2c, _sram_l2c_size + _sram_size, CACHED_MEM);
/* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */
mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM);
/* set ttb as secure */
mmu_config_range(_ttb, _ttb_size, SECURE_MEM);
mmu_enable();
mmu_config_range(_dram_dma, _dram_dma_size, UNCACHED_MEM);
mtk_mmu_disable_l2c_sram();
}
void mt8173_mmu_after_dram(void)
void mtk_soc_disable_l2c_sram(void)
{
/* Map DRAM as cached now that it's up and running */
mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM);
/* Unmap L2C SRAM so it can be reclaimed by L2 cache */
/* TODO: Implement true unmapping, and also use it for the zero-page! */
mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM);
mmu_config_range(_dram_dma, _dram_dma_size, UNCACHED_MEM);
/* Careful: changing cache geometry while it's active is a bad idea! */
mmu_disable();
/* Return L2C SRAM back to L2 cache. Set it to 512KiB which is the max
* available L2 cache for A53 in MT8173. */
write32(&mt8173_mcucfg->mp0_ca7l_cache_config, 3 << 8);
/* turn off the l2c sram clock */
write32(&mt8173_infracfg->infra_pdn0, L2C_SRAM_PDN);
/* Reenable MMU with now enlarged L2 cache. Page tables still valid. */
mmu_enable();
}