Enable Microcode in CBFS for all SandyBridge/IvyBridge systems
Change-Id: Idee4facc18e0be60906d2a2f0e99bd39de8d7247 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1332 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
committed by
Ronald G. Minnich
parent
79bbbd9db3
commit
c65a36eb0f
@@ -12,6 +12,7 @@ config CPU_SPECIFIC_OPTIONS
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select SSE2
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select UDELAY_LAPIC
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select SMM_TSEG
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select MICROCODE_IN_CBFS
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config BOOTBLOCK_CPU_INIT
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string
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@@ -21,14 +22,11 @@ config SMM_TSEG_SIZE
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hex
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default 0x800000
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if MICROCODE_IN_CBFS
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config MICROCODE_INCLUDE_PATH
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string
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default "src/cpu/intel/model_206ax"
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endif
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endif
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if CPU_INTEL_MODEL_206AX
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config CPU_MODEL_NAME
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string
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@@ -25,12 +25,6 @@
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#if !CONFIG_MICROCODE_IN_CBFS
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static const uint32_t microcode_updates[] = {
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#include "microcode_blob.h"
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};
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#endif
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#include <cpu/intel/microcode/microcode.c>
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#include "model_206ax.h"
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@@ -125,9 +119,5 @@ static void bootblock_cpu_init(void)
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/* Set flex ratio and reset if needed */
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set_flex_ratio_to_tdp_nominal();
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enable_rom_caching();
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#if CONFIG_MICROCODE_IN_CBFS
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intel_update_microcode_from_cbfs();
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#else
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intel_update_microcode(microcode_updates);
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#endif
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}
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@@ -115,12 +115,6 @@ static acpi_cstate_t cstate_map[] = {
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{ 0 }
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};
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#if !CONFIG_MICROCODE_IN_CBFS
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static const uint32_t microcode_updates[] = {
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#include "microcode_blob.h"
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};
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#endif
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/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
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static const u8 power_limit_time_sec_to_msr[] = {
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[0] = 0x00,
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@@ -421,11 +415,7 @@ static void model_206ax_init(device_t cpu)
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/* Turn on caching if we haven't already */
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x86_enable_cache();
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#if CONFIG_MICROCODE_IN_CBFS
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intel_update_microcode_from_cbfs();
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#else
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intel_update_microcode(microcode_updates);
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#endif
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/* Clear out pending MCEs */
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configure_mca();
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