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tpm: Refactor TPM Kconfig dimensions

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Break TPM related Kconfig into the following dimensions:

TPM transport support:
config CRB_TPM
config I2C_TPM
config SPI_TPM
config MEMORY_MAPPED_TPM (new)

TPM brand, not defining any of these is valid, and result in "generic" support:
config TPM_ATMEL (new)
config TPM_GOOGLE (new)
config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE)
config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE)

What protocol the TPM chip supports:
config MAINBOARD_HAS_TPM1
config MAINBOARD_HAS_TPM2

What the user chooses to compile (restricted by the above):
config NO_TPM
config TPM1
config TPM2

The following Kconfigs will be replaced as indicated:
config TPM_CR50 -> TPM_GOOGLE
config MAINBOARD_HAS_CRB_TPM -> CRB_TPM
config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL
config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE
config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM
config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE

Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Jes B. Klinke
2022-04-19 14:00:33 -07:00
committed by Julius Werner
parent 0b71099f65
commit c6b041a12e
159 changed files with 260 additions and 289 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/vendorcode/google/chromeos/Kconfig
View File

@ -22,10 +22,6 @@ config CHROMEOS
if CHROMEOS
config CR50_IMMEDIATELY_COMMIT_FW_SECDATA
bool
default y if TPM_CR50
config CHROMEOS_RAMOOPS
bool "Reserve space for Chrome OS ramoops"
default y

2
src/vendorcode/google/chromeos/Makefile.inc
View File

@ -9,7 +9,7 @@ ramstage-$(CONFIG_CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME) += tpm2.c
ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c
ramstage-$(CONFIG_USE_SAR) += sar.c
ramstage-$(CONFIG_CHROMEOS_DSM_CALIB) += dsm_calib.c
ramstage-$(CONFIG_TPM_CR50) += cr50_enable_update.c
ramstage-$(CONFIG_TPM_GOOGLE) += cr50_enable_update.c
romstage-$(CONFIG_CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c
ramstage-$(CONFIG_CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c

6
src/vendorcode/google/chromeos/cse_board_reset.c
View File

@ -16,7 +16,7 @@ void cse_board_reset(void)
int ret;
struct cr50_firmware_version version;
if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50)) {
if (CONFIG(TPM2) && CONFIG(TPM_GOOGLE_CR50)) {
/* Initialize TPM and get the cr50 firmware version. */
ret = tlcl_lib_init();
if (ret != VB2_SUCCESS) {
@ -36,6 +36,10 @@ void cse_board_reset(void)
(version.major >= 3 && version.minor >= 20))
return;
}
if (CONFIG(TPM_GOOGLE_TI50)) {
/* All versions of Ti50 firmware support the above PLTRST wiring. */
return;
}
printk(BIOS_INFO, "Initiating request to EC to trigger cold reset\n");
/*