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soc/intel/elkhartlake: Update FSP-S storage related configs

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Further add initial Silicon UPD storage settings:
- SATA
- SD card
- eMMC

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Lean Sheng Tan
2021-05-30 09:08:35 -07:00
committed by Werner Zeh
parent 9420e2847e
commit c6c54439f8
4 changed files with 80 additions and 2 deletions
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19
src/soc/intel/elkhartlake/chip.h
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@@ -90,8 +90,22 @@ struct soc_intel_elkhartlake_config {
/* SATA related */
uint8_t SataMode;
uint8_t SataSalpSupport;
uint8_t SataPortsEnable[8];
uint8_t SataPortsDevSlp[8];
uint8_t SataPortsEnable[CONFIG_MAX_SATA_PORTS];
uint8_t SataPortsDevSlp[CONFIG_MAX_SATA_PORTS];
/*
* Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
* Default 0. Setting this to 1 disables the SATA Power Optimizer.
*/
uint8_t SataPwrOptimizeDisable;
/*
* SATA Port Enable Dito Config.
* Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
*/
uint8_t SataPortsEnableDitoConfig[CONFIG_MAX_SATA_PORTS];
/* SataPortsDmVal is the DITO multiplier. Default is 15. */
uint8_t SataPortsDmVal[CONFIG_MAX_SATA_PORTS];
/* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */
uint16_t SataPortsDitoVal[CONFIG_MAX_SATA_PORTS];
/* Audio related */
uint8_t PchHdaDspEnable;
@@ -135,6 +149,7 @@ struct soc_intel_elkhartlake_config {
/* eMMC and SD */
uint8_t ScsEmmcHs400Enabled;
uint8_t ScsEmmcDdr50Enabled;
/* Enable if SD Card Power Enable Signal is Active High */
uint8_t SdCardPowerEnableActiveHigh;