mb/starlabs/starlite_adl: Add Alder Lake N StarLite Mk V

Tested using `edk2` from
`github.com/starlabsltd/edk2/tree/uefipayload_vs`:
* Windows 11
* Ubuntu 22.04
* Manjaro 22

No known issues.

https://starlabs.systems/pages/starlite-specification

Change-Id: I8724e578c21353032b844b20b868348580ff561b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

Documentation/mainboard/index.md

@@ -330,6 +330,7 @@ LabTop Mk III <starlabs/labtop_kbl.md>
 LabTop Mk IV <starlabs/labtop_cml.md>
 StarLite Mk III <starlabs/lite_glk.md>
 StarLite Mk IV <starlabs/lite_glkr.md>
+StarLite Mk V <starlabs/lite_adl.md>
 StarBook Mk V <starlabs/starbook_tgl.md>
 StarBook Mk VI <starlabs/starbook_adl.md>
 Flashing devices <starlabs/common/flashing.md>

Documentation/mainboard/starlabs/starlite_adl.md

@@ -0,0 +1,82 @@
+# StarBook Mk V
+
+## Specs
+
+- CPU (full processor specs available at https://ark.intel.com)
+    - Intel N200 (Alder Lake)
+- EC
+    - ITE IT5570E
+    - USB-C PD Charger
+    - Suspend / resume
+- GPU
+    - Intel® Iris® Xe Graphics
+    - GOP driver is recommended, VBT is provided
+    - eDP 12.5-inch 2880x1920 or 2160x1440 LCD
+    - 2 x USB-C DisplayPort video
+- Memory
+    - 16GB on-board
+- Networking
+    - 9560 CNVi WiFi / Bluetooth
+- Sound
+    - Realtek ALC269-VB6
+    - Internal speakers
+    - Internal microphone
+    - Combined headphone / microphone 3.5-mm jack
+    - HDMI audio
+    - USB-C DisplayPort audio
+- Storage
+    - M.2 PCIe SSD
+    - RTS5129 MicroSD card reader
+- USB
+    - 2 x 5MP CCD Camera
+    - 2 x USB 3.1 Gen 2 Type-C (right)
+
+## Building coreboot
+
+Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
+
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* Intel Management Engine firmware (me.bin)
+* ITE Embedded Controller firmware (ec.bin)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_byte_adl
+make
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Vendor              | Winbond    |
++---------------------+------------+
+| Model               | W25Q256.V  |
++---------------------+------------+
+| Size                | 32 MiB     |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+| External flashing   | yes        |
++---------------------+------------+
+```
+
+Please see [here](common/flashing.md) for instructions on how to flash with fwupd.

src/mainboard/starlabs/starlite_adl/Kconfig

@@ -0,0 +1,121 @@
+config BOARD_STARLABS_STARLITE_SERIES
+	def_bool n
+	select DRIVERS_I2C_HID
+	select EC_STARLABS_ITE
+	select EC_STARLABS_MAX_CHARGE
+	select EC_STARLABS_MERLIN
+	select EC_STARLABS_NEED_ITE_BIN
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select HAVE_SPD_IN_CBFS
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SYSTEM_TYPE_DETACHABLE
+	select VALIDATE_INTEL_DESCRIPTOR
+
+config BOARD_STARLABS_LITE_ADL
+	select BOARD_ROMSIZE_KB_16384
+	select BOARD_STARLABS_STARLITE_SERIES
+	select CRB_TPM
+	select DRIVERS_INTEL_PMC
+	select HAVE_INTEL_PTT
+	select SOC_INTEL_ALDERLAKE
+	select SOC_INTEL_ALDERLAKE_PCH_N
+	select SOC_INTEL_COMMON_BLOCK_TCSS
+	select SOC_INTEL_CRASHLOG
+	select SPI_FLASH_WINBOND
+
+if BOARD_STARLABS_STARLITE_SERIES
+
+config CCD_PORT
+	int
+	default 4
+
+config CONSOLE_SERIAL
+	default n if !EDK2_DEBUG
+
+config D3COLD_SUPPORT
+	default n
+
+config DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
+config DIMM_SPD_SIZE
+	default 512
+
+config EC_GPE_SCI
+	default 0x6e
+
+config EC_STARLABS_ADD_ITE_BIN
+	default n
+
+config EC_STARLABS_BATTERY_MODEL
+	default "AEC3756153-2S1P-N"
+
+config EC_STARLABS_BATTERY_TYPE
+	default "LION"
+
+config EC_STARLABS_BATTERY_OEM
+	default "Apower Electronics"
+
+config EC_STARLABS_ITE_BIN_PATH
+	string
+	depends on EC_STARLABS_NEED_ITE_BIN
+	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
+
+config EC_VARIANT_DIR
+	default "merlin"
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/vboot.fmd" if VBOOT
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
+
+config IFD_BIN_PATH
+	string
+	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashdescriptor.bin"
+
+config MAINBOARD_DIR
+	default "starlabs/starlite_adl"
+
+config MAINBOARD_FAMILY
+	string
+	default "I5"
+
+config MAINBOARD_PART_NUMBER
+	default "StarLite Mk V"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "StarLite"
+
+config ME_BIN_PATH
+	string
+	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/intel_me.bin"
+
+config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
+	default n
+
+config EDK2_BOOTSPLASH_FILE
+	string
+	default "3rdparty/blobs/mainboard/starlabs/Logo.bmp"
+
+config SOC_INTEL_CSE_SEND_EOP_EARLY
+	default n
+
+config UART_FOR_CONSOLE
+	default 0
+
+config USE_PM_ACPI_TIMER
+	default n
+
+config VBOOT
+	select VBOOT_VBNV_FLASH
+
+config VARIANT_DIR
+	default "mk_v"
+
+endif

src/mainboard/starlabs/starlite_adl/Kconfig.name

@@ -0,0 +1,4 @@
+comment "Star Labs StarLite Series"
+
+config BOARD_STARLABS_LITE_ADL
+	bool "Star Labs Lite Mk V (N200)"

src/mainboard/starlabs/starlite_adl/Makefile.mk

@@ -0,0 +1,16 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += ./spd
+subdirs-y += variants/$(VARIANT_DIR)
+
+bootblock-y += bootblock.c
+
+verstage-$(CONFIG_VBOOT) += vboot.c
+
+romstage-$(CONFIG_VBOOT) += vboot.c
+
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
+ramstage-y += hda_verb.c
+ramstage-y += mainboard.c
+ramstage-y += smbios.c

src/mainboard/starlabs/starlite_adl/acpi/ec.asl

@@ -0,0 +1 @@
+/* SPDX-License-Identifier: GPL-2.0-only */

src/mainboard/starlabs/starlite_adl/acpi/mainboard.asl

@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB) {
+	#include "sleep.asl"
+}

src/mainboard/starlabs/starlite_adl/acpi/sleep.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method (MPTS, 1, NotSerialized)
+{
+	RPTS (Arg0)
+}
+
+Method (MWAK, 1, NotSerialized)
+{
+	RWAK (Arg0)
+}

src/mainboard/starlabs/starlite_adl/acpi/superio.asl

@@ -0,0 +1 @@
+/* SPDX-License-Identifier: GPL-2.0-only */

src/mainboard/starlabs/starlite_adl/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: Star Labs
+Board name: StarLite
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/starlabs/starlite_adl/bootblock.c

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <soc/gpio.h>
+#include <variants.h>
+
+void bootblock_mainboard_init(void)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_early_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+}

src/mainboard/starlabs/starlite_adl/cmos.default

@@ -0,0 +1,17 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# hardcoded
+boot_option=Fallback
+# console
+debug_level=Debug
+# cpu
+vtd=Enable
+power_profile=Balanced
+me_state=Disable
+# Devices
+wireless=Enable
+webcam=Enable
+camera=Enable
+microphone=Enable
+# EC
+mirror_flag=Disable

src/mainboard/starlabs/starlite_adl/cmos.layout

@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# Bank: 1
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# coreboot config options: ramtop
+304	80	h	0	ramtop
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	2	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	3	debug_level
+# coreboot config options: cpu
+#400	8	r	0	reserved for century byte
+408	1	e	1	vtd
+416	2	e	5	power_profile
+424	1	e	4	me_state
+432	4	h	0	me_state_counter
+
+# coreboot config options: Devices
+504	1	e	1	wireless
+512	1	e	1	webcam
+520	1	e	1	camera
+528	1	e	1	microphone
+
+# coreboot config options: EC
+600	2	e	6	max_charge
+608	1	e	1	mirror_flag
+6616	4	h	0	mirror_flag_counter
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# Bank: 2
+# embedded controller settings (outside the checksummed area)
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID	value	text
+1	0	Disable
+1	1	Enable
+
+2	0	Fallback
+2	1	Normal
+
+3	0	Emergency
+3	1	Alert
+3	2	Critical
+3	3	Error
+3	4	Warning
+3	5	Notice
+3	6	Info
+3	7	Debug
+3	8	Spew
+
+4	0	Enable
+4	1	Disable
+
+5	0	Power Saver
+5	1	Balanced
+5	2	Performance
+
+6	0	100%
+6	1	80%
+6	2	60%
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984

src/mainboard/starlabs/starlite_adl/dsdt.asl

@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20220930
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/alderlake/acpi/southbridge.asl>
+		#include <soc/intel/alderlake/acpi/tcss.asl>
+
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+
+		#include <soc/intel/common/block/acpi/acpi/gna.asl>
+
+		/* PS/2 Keyboard */
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	/* Star Labs EC */
+	#include <ec/starlabs/merlin/acpi/ec.asl>
+
+	Scope (\_SB)
+	{
+		/* HID Driver */
+		#include <ec/starlabs/merlin/acpi/hid.asl>
+
+		/* Suspend Methods */
+		#include <ec/starlabs/merlin/acpi/suspend.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/starlabs/starlite_adl/hda_verb.c

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/azalia_device.h>
+#include <option.h>
+#include <types.h>
+
+#define AZALIA_CODEC_ALC269	0x10ec0269
+
+static const u32 override_verb[] = {
+	AZALIA_PIN_CFG(0, 0x12, 0x00000000),
+};
+
+static void disable_microphone(u8 *base)
+{
+	azalia_program_verb_table(base, override_verb, ARRAY_SIZE(override_verb));
+}
+
+void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
+{
+	if (viddid == AZALIA_CODEC_ALC269) {
+		printk(BIOS_DEBUG, "CMOS: viddid = %08x\n", viddid);
+		if (get_uint_option("microphone", 1) == 0)
+			disable_microphone(base);
+	}
+}

src/mainboard/starlabs/starlite_adl/include/variants.h

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _BASEBOARD_VARIANTS_H_
+#define _BASEBOARD_VARIANTS_H_
+
+#include <soc/gpio.h>
+
+enum cmos_power_profile {
+	PP_POWER_SAVER = 0,
+	PP_BALANCED    = 1,
+	PP_PERFORMANCE = 2,
+};
+#define NUM_POWER_PROFILES 3
+
+enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback);
+
+/*
+ * The next set of functions return the gpio table and fill in the number of
+ * entries for each table.
+ */
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+
+void devtree_update(void);
+
+#endif /* _BASEBOARD_VARIANTS_H_ */

src/mainboard/starlabs/starlite_adl/mainboard.c

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <soc/ramstage.h>
+#include <option.h>
+#include <variants.h>
+
+enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback)
+{
+	const unsigned int power_profile = get_uint_option("power_profile", fallback);
+	return power_profile < NUM_POWER_PROFILES ? power_profile : fallback;
+}
+
+static void init_mainboard(void *chip_info)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+
+	devtree_update();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = init_mainboard,
+};

src/mainboard/starlabs/starlite_adl/smbios.c

@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <ec/starlabs/merlin/ec.h>
+#include <smbios.h>
+#include <types.h>
+#include <uuid.h>
+#include <variants.h>
+
+/* Get the Embedded Controller firmware version */
+void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision)
+{
+	u16 ec_version = ec_get_version();
+
+	*ec_major_revision = ec_version >> 8;
+	*ec_minor_revision = ec_version & 0xff;
+}
+
+const char *smbios_system_sku(void)
+{
+	return CONFIG_MAINBOARD_FAMILY;
+}
+
+u8 smbios_mainboard_feature_flags(void)
+{
+	return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE;
+}
+
+const char *smbios_chassis_version(void)
+{
+	return smbios_mainboard_version();
+}
+
+const char *smbios_chassis_serial_number(void)
+{
+	return smbios_mainboard_serial_number();
+}

src/mainboard/starlabs/starlite_adl/spd/Makefile.mk

@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+SPD_SOURCES = mt62f2g64d8

src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8.spd.hex

@@ -0,0 +1,32 @@
+23 10 15 0E 16 22 F9 08 00 00 00 00 0A 01 00 00
+00 00 09 00 00 00 00 00 AB 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 C9 00 C5 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk

@@ -0,0 +1,9 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+romstage-y += romstage.c
+
+ramstage-y += devtree.c
+ramstage-y += gpio.c
+ramstage-y += hda_verb.c

src/mainboard/starlabs/starlite_adl/variants/mk_v/board.fmd

@@ -0,0 +1,14 @@
+FLASH	0x1000000 {
+	SI_ALL	0x600000 {
+		SI_DESC			0x1000
+		SI_ME			0x412000
+	}
+	SI_BIOS 0xa00000 {
+		EC@0x0			0x20000
+		RW_MRC_CACHE@0x20000	0x10000
+		SMMSTORE@0x30000	0x40000
+		CONSOLE@0x70000		0x20000
+		FMAP@0x90000		0x1000
+		COREBOOT(CBFS)
+	}
+}

src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb

@@ -0,0 +1,228 @@
+chip soc/intel/alderlake
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	# FSP Memory
+	register "enable_c6dram"		= "1"
+	register "sagv"				= "SaGv_Enabled"
+
+	# FSP Silicon
+	register "eist_enable"			= "1"
+	register "cnvi_bt_core"			= "true"
+	register "cnvi_bt_audio_offload"	= "true"
+
+	# Serial I/O
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0]		= PchSerialIoPci,
+		[PchSerialIoIndexI2C2]		= PchSerialIoPci,
+	}"
+
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0]		= PchSerialIoSkipInit,
+	}"
+
+	# Power
+	register "pch_slp_s3_min_assertion_width"	= "2"			# 50ms
+	register "pch_slp_s4_min_assertion_width"	= "3"			# 1s
+	register "pch_slp_sus_min_assertion_width"	= "3"			# 500ms
+	register "pch_slp_a_min_assertion_width"	= "3"			# 2s
+
+	# PM Util
+	register "pmc_gpe0_dw0"			= "GPP_A"
+	register "pmc_gpe0_dw1"			= "GPP_R"
+	register "pmc_gpe0_dw2"			= "GPD"
+
+	device domain 0 on
+		device ref igpu		on
+			register "gfx"					= "GMA_DEFAULT_PANEL(0)"
+			register "ddi_portA_config"			= "1"
+			register "ddi_ports_config" = "{
+				[DDI_PORT_B]				= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			}"
+		end
+		device ref gna		on  end
+		device ref xhci		on
+			# Primary USB Type C
+			register "usb2_ports[0]"			= "USB2_PORT_MID(OC_SKIP)"
+			register "usb3_ports[2]"			= "USB3_PORT_DEFAULT(OC_SKIP)"
+
+			# Secondary USB Type C
+			register "usb2_ports[1]"			= "USB2_PORT_MID(OC_SKIP)"
+			register "usb3_ports[0]"			= "USB3_PORT_DEFAULT(OC_SKIP)"
+
+			# Keyboard
+			register "usb2_ports[2]"			= "USB2_PORT_MID(OC_SKIP)"
+
+			# Internal Webcam
+			register "usb2_ports[CONFIG_CCD_PORT]"		= "USB2_PORT_MID(OC_SKIP)"
+
+			# Camera
+			register "usb2_ports[5]"			= "USB2_PORT_MID(OC_SKIP)"
+
+			# Internal Bluetooth
+			register "usb2_ports[9]"			= "USB2_PORT_MID(OC_SKIP)"
+
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc"		= ""Top USB Type-C""
+						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"		= ""Top USB Type-C""
+						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb3_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"		= ""Bottom USB Type-C""
+						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"		= ""Bottom USB Type-C""
+						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"		= ""Detachable Keyboard""
+						register "type"		= "UPC_TYPE_INTERNAL"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"		= ""Internal Webcam""
+						register "type"		= "UPC_TYPE_INTERNAL"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"		= ""Camera""
+						register "type"		= "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"		= ""CNVi Bluetooth""
+						register "type"		= "UPC_TYPE_INTERNAL"
+						register "reset_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
+						device ref usb2_port10 on end
+					end
+				end
+
+			end
+		end
+		device ref shared_sram	on  end
+		device ref cnvi_wifi	on
+			chip drivers/wifi/generic
+				register "wake"				= "GPE0_PME_B0"
+				register "add_acpi_dma_property"	= "true"
+				register "enable_cnvi_ddr_rfim"		= "true"
+				use usb2_port10 as bluetooth_companion
+				device generic 0 on end
+			end
+		end
+		device ref i2c0		on				# Accelerometer
+			chip drivers/i2c/generic
+				register "hid"				= ""KIOX000A""
+				register "cid"				= ""KIOX000A""
+				register "desc"				= ""Accelerometer""
+				register "has_rotation_matrix"		= "1"
+				register "rotation_matrix"		= "{1, 0, 0, 0, -1, 0, 0, 0, 1}"
+				register "has_cdm"			= "1"
+				register "cdm_index"			= "6"
+				device i2c 0f on end
+			end
+		end
+		device ref i2c2		on				# Touchscreen
+			chip drivers/i2c/hid
+				register "generic.hid"			= ""GXTP7386""
+				register "generic.cid"			= ""GXTP7386""
+				register "generic.desc"			= ""Touchscreen""
+				register "generic.irq_gpio"		= "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_F18)"
+				register "generic.reset_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)"
+				register "hid_desc_reg_offset"		= "0x01"
+				device i2c 5d on end
+			end
+		end
+		device ref pcie_rp9	on				# SSD x4
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src				= 0,
+				.clk_req				= 0,
+				.flags					= PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+
+			smbios_slot_desc				"SlotTypeM2Socket3"
+									"SlotLengthLong"
+									"M.2/M 2242"
+									"SlotDataBusWidth4X"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
+				register "reset_gpio"			= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
+				register "srcclk_pin"			= "0"
+				device generic 0 on end
+			end
+		end
+		device ref uart0	on  end
+		device ref pch_espi	on
+			register "gen1_dec"				= "0x3c030070"
+			register "gen2_dec"				= "0x00fc0201"
+			register "gen3_dec"				= "0x000c0081"
+
+			chip ec/starlabs/merlin
+				# Port pair 4Eh/4Fh
+				device pnp 4e.00 on  end			# IO Interface
+				device pnp 4e.01 off end			# Com 1
+				device pnp 4e.02 off end			# Com 2
+				device pnp 4e.04 off end			# System Wake-Up
+				device pnp 4e.05 off end			# PS/2 Mouse
+				device pnp 4e.06 on				# PS/2 Keyboard
+					io 0x60				= 0x0060
+					io 0x62				= 0x0064
+					irq 0x70			= 1
+				end
+				device pnp 4e.0a off end			# Consumer IR
+				device pnp 4e.0f off end			# Shared Memory/Flash Interface
+				device pnp 4e.10 off end			# RTC-like Timer
+				device pnp 4e.11 off end			# Power Management Channel 1
+				device pnp 4e.12 off end			# Power Management Channel 2
+				device pnp 4e.13 off end			# Serial Peripheral Interface
+				device pnp 4e.14 off end			# Platform EC Interface
+				device pnp 4e.17 off end			# Power Management Channel 3
+				device pnp 4e.18 off end			# Power Management Channel 4
+				device pnp 4e.19 off end			# Power Management Channel 5
+			end
+		end
+		device ref pmc		hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use usb3_port3 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port2 as usb2_port
+						use usb3_port1 as usb3_port
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end
+		device ref hda		on
+			subsystemid 0x1e50 0x7038
+			register "pch_hda_sdi_enable[0]"		= "1"
+			register "pch_hda_audio_link_hda_enable"	= "1"
+			register "pch_hda_idisp_codec_enable"		= "1"
+			register "pch_hda_idisp_link_frequency"		= "HDA_LINKFREQ_96MHZ"
+			register "pch_hda_idisp_link_tmode"		= "HDA_TMODE_8T"
+		end
+		device ref smbus	on  end
+	end
+	chip drivers/crb
+		device mmio 0xfed40000 on end
+	end
+end

src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c

@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <cpu/intel/turbo.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <option.h>
+#include <types.h>
+#include <variants.h>
+
+void devtree_update(void)
+{
+	config_t *cfg = config_of_soc();
+
+	struct soc_intel_common_config *common_config;
+	common_config = chip_get_common_soc_structure();
+
+	struct soc_power_limits_config *soc_conf_4core =
+		&cfg->power_limits_config[ADL_N_021_6W_CORE];
+
+	struct device *nic_dev = pcidev_on_root(0x14, 3);
+	struct device *touchscreen_dev = pcidev_on_root(0x15, 2);
+	struct device *accelerometer_dev = pcidev_on_root(0x15, 0);
+
+	/* Update PL1 & PL2 based on CMOS settings */
+	switch (get_power_profile(PP_POWER_SAVER)) {
+	case PP_POWER_SAVER:
+		disable_turbo();
+		soc_conf_4core->tdp_pl1_override	= 6;
+		soc_conf_4core->tdp_pl2_override	= 10;
+		common_config->pch_thermal_trip		= 30;
+		break;
+	case PP_BALANCED:
+		soc_conf_4core->tdp_pl1_override	= 10;
+		soc_conf_4core->tdp_pl2_override	= 25;
+		common_config->pch_thermal_trip		= 25;
+		break;
+	case PP_PERFORMANCE:
+		soc_conf_4core->tdp_pl1_override	= 20;
+		soc_conf_4core->tdp_pl2_override	= 35;
+		common_config->pch_thermal_trip		= 20;
+		break;
+	}
+
+	/* Enable/Disable Bluetooth based on CMOS settings */
+	if (get_uint_option("wireless", 1) == 0) {
+		cfg->usb2_ports[9].enable = 0;
+		nic_dev->enabled = 0;
+	}
+
+	/* Enable/Disable Webcam based on CMOS settings */
+	if (get_uint_option("webcam", 1) == 0)
+		cfg->usb2_ports[CONFIG_CCD_PORT].enable = 0;
+
+	/* Enable/Disable Camera based on CMOS settings */
+	if (get_uint_option("camera", 1) == 0)
+		cfg->usb2_ports[5].enable = 0;
+
+	/* Enable/Disable Touchscreen based on CMOS settings */
+	if (get_uint_option("touchscreen", 1) == 0)
+		touchscreen_dev->enabled = 0;
+
+	/* Enable/Disable Accelerometer based on CMOS settings */
+	if (get_uint_option("accelerometer", 1) == 0)
+		accelerometer_dev->enabled = 0;
+}

src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c

@@ -0,0 +1,460 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <variants.h>
+
+/* Early pad configuration in bootblock */
+const struct pad_config early_gpio_table[] = {
+	/* H10:		UART0 RXD		Debug Connector		*/
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11:		UART0 TXD		Debug Connector		*/
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+
+	/* F0:		CNV BRI Data					*/
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+	/* F1:		CNV BRI Response				*/
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+	/* F2:		CNV RGI Data					*/
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+	/* F3:		CNV RGI Response				*/
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+	/* F4:		CNV RF Reset					*/
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+	/* F5:		Not used		MODEM_CLKREQ		*/
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
+	/* F6:		CNV PA Blanking					*/
+	PAD_NC(GPP_F6, NONE),
+
+	/* A13:		BlueTooth RF Kill				*/
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),
+	/* E3:		WiFi RF Kill					*/
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Pad configuration in ramstage. */
+const struct pad_config gpio_table[] = {
+	/* GPD0:	Battery Low					*/
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+	/* GPD1:	Charger Connected				*/
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+	/* GPD2:	LAN Wake					*/
+	PAD_NC(GPD2, NONE),
+	/* GPD3:	Power Button					*/
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+	/* GPD4:	Sleep S3					*/
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+	/* GPD5:	Sleep S4					*/
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+	/* GPD6:	Sleep A						*/
+	PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+	/* GPD7:	Power Adapter Disable				*/
+	PAD_CFG_GPO(GPD7, 0, PWROK),
+	/* GPD8:	Suspend Clock					*/
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+	/* GPD9:	Wireless LAN Sleep				*/
+	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+	/* GPD10:	Sleep S5					*/
+	PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+	/* GPD11:	LAN PHY Enable					*/
+	PAD_CFG_GPO(GPD11, 0, PWROK),
+
+	/* A0:		ESPI IO 0					*/
+	/* A1:		ESPI IO 1					*/
+	/* A2:		ESPI IO 2					*/
+	/* A3:		ESPI IO 3					*/
+	/* A4:		ESPI CS 0					*/
+	/* A5:		Not Connected					*/
+	PAD_NC(GPP_A5, NONE),
+	/* A6:		Not Connected					*/
+	PAD_NC(GPP_A6, NONE),
+	/* A7:		Embedded Controller SCI				*/
+	PAD_NC(GPP_A7, NONE),
+	/* A8:		Not Connected					*/
+	PAD_NC(GPP_A8, NONE),
+	/* A9:		ESPI Clock					*/
+	/* A10:		ESPI Reset					*/
+	/* A11:		Webcam Camera Reset				*/
+	PAD_NC(GPP_A11, NONE),
+	/* A12:		PCH M.2 SSD PEDET				*/
+	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+	/* A14:		Camera Power Enable				*/
+	PAD_NC(GPP_A14, NONE),
+	/* A15:		Camera Reset					*/
+	PAD_NC(GPP_A15, NONE),
+	/* A16:		USB OverCurrent 3				*/
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	/* A17:		Not Connected					*/
+	PAD_NC(GPP_A17, NONE),
+	/* A18:		DDI B DP HPD					*/
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	/* A19:		TCP0 HPD					*/
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
+	/* A20:		TCP1 HPD					*/
+	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
+	/* A21:		Fingerprint Reader Interrupt			*/
+	PAD_NC(GPP_A21, NONE),
+	/* A22:		Fingerprint Reader Reset			*/
+	PAD_NC(GPP_A22, NONE),
+	/* A23:		Not Connected					*/
+	PAD_NC(GPP_A23, NONE),
+
+
+	/* B0:		Core Vendor ID 0				*/
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	/* B1:		Core Vendor ID 1				*/
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+	/* B2:		BC PROCHOT					*/
+	// PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	_PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)),
+	/* B3:		Not Connected					*/
+	PAD_NC(GPP_B3, NONE),
+	/* B4:		Not Connected					*/
+	PAD_NC(GPP_B4, NONE),
+	/* B5:		I2C 2 SDA		Touch Panel SDA		*/
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
+	/* B6:		I2C 2 SCL		Touch Panel Clock	*/
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
+	/* B7:		I2C 3 SDA		ALS SDA			*/
+	PAD_NC(GPP_B7, NONE),
+	/* B8:		I2C 3 SCL		ALS Clock		*/
+	PAD_NC(GPP_B8, NONE),
+	/* B9:		Not Connected					*/
+	PAD_NC(GPP_B9, NONE),
+	/* B10:		Not Connected					*/
+	PAD_NC(GPP_B10, NONE),
+	/* B11:		I2C PMC PD Interrupt	Test Point 28		*/
+	PAD_NC(GPP_B11, NONE),
+	/* B12:		PM SLP S0					*/
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* B13:		PLT RST						*/
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* B14:		Webcam Privacy LED				*/
+	PAD_NC(GPP_B14, NONE),
+	/* B15:		Not Connected					*/
+	PAD_NC(GPP_B15, NONE),
+	/* B16:		I2C 5 SDA		Webcam SDA		*/
+	PAD_NC(GPP_B16, NONE),
+	/* B17:		I2C 5 SDL		Webcam Clock		*/
+	PAD_NC(GPP_B17, NONE),
+	/* B18:		Reboot Support		Weak Internal PD 20K
+				High:	Disabled
+				Low:	Enabled				*/
+	PAD_NC(GPP_B18, NONE),
+	/* B19:		Not Connected					*/
+	PAD_NC(GPP_B19, NONE),
+	/* B20:		Not Connected					*/
+	PAD_NC(GPP_B20, NONE),
+	/* B21:		Not Connected					*/
+	PAD_NC(GPP_B21, NONE),
+	/* B22:		Not Connected					*/
+	PAD_NC(GPP_B22, NONE),
+	/* B23:		Front Camera LDO				*/
+	PAD_NC(GPP_B23, NONE),
+	/* B24:		Not Connected					*/
+	PAD_NC(GPP_B24, NONE),
+	/* B25:		Not Connected					*/
+	PAD_NC(GPP_B25, NONE),
+
+	/* C0:		SMB Clock					*/
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	/* C1:		SMB Data					*/
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+	/* C2:		TLS Confidentiality	Weak Internal PD 20K
+				Low:	Disabled
+				High:	Enabled				*/
+	PAD_CFG_GPO(GPP_C2, 0, DEEP),
+	/* C3:		SML 0 Clock					*/
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+	/* C4:		SML 0 Data					*/
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+	/* C5:		Boot Strap		Weak Internal PD 20K
+				Low:	ESPI
+				High:	Disabled			*/
+	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+	/* C6:		SML 1 Clock					*/
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
+	/* C7:		SML 1 Data					*/
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
+	/* C8:		Not Connected					*/
+	PAD_NC(GPP_C8, NONE),
+	/* C9:		Not Connected					*/
+	PAD_NC(GPP_C9, NONE),
+	/* C10:		Not Connected					*/
+	PAD_NC(GPP_C10, NONE),
+	/* C11:		Not Connected					*/
+	PAD_NC(GPP_C11, NONE),
+	/* C12:		Not Connected					*/
+	PAD_NC(GPP_C12, NONE),
+	/* C13:		Not Connected					*/
+	PAD_NC(GPP_C13, NONE),
+	/* C14:		Not Connected					*/
+	PAD_NC(GPP_C14, NONE),
+	/* C15:		Not Connected					*/
+	PAD_NC(GPP_C15, NONE),
+	/* C16:		Not Connected					*/
+	PAD_NC(GPP_C16, NONE),
+	/* C17:		Not Connected					*/
+	PAD_NC(GPP_C17, NONE),
+	/* C18:		Not Connected					*/
+	PAD_NC(GPP_C18, NONE),
+	/* C19:		Not Connected					*/
+	PAD_NC(GPP_C19, NONE),
+	/* C20:		Not Connected					*/
+	PAD_NC(GPP_C20, NONE),
+	/* C21:		Not Connected					*/
+	PAD_NC(GPP_C21, NONE),
+	/* C22:		Not Connected					*/
+	PAD_NC(GPP_C22, NONE),
+	/* C23:		Not Connected					*/
+	PAD_NC(GPP_C23, NONE),
+
+	/* D0:		Not used		Audio ID 0		*/
+	PAD_NC(GPP_D0, NONE),
+	/* D1:		Not used		Audio ID 1		*/
+	PAD_NC(GPP_D1, NONE),
+	/* D2:		Not used		Audio ID 2		*/
+	PAD_NC(GPP_D2, NONE),
+	/* D3:		Not Connected					*/
+	PAD_NC(GPP_D3, NONE),
+	/* D4:		Camera Image Clock Output			*/
+	PAD_NC(GPP_D4, NONE),
+	/* D5:		Clock Request 0		PCH M.2 SSD		*/
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	/* D6:		Clock Request 1		Wireless LAN		*/
+	PAD_NC(GPP_D6, NONE),
+	/* D7:		Clock Request 2					*/
+	PAD_NC(GPP_D7, NONE),
+	/* D8:		Clock Request 3					*/
+	PAD_NC(GPP_D8, NONE),
+	/* D9:		GSPI 2 FPS					*/
+	PAD_NC(GPP_D9, NONE),
+	/* D10:		GSPI 2 Clock					*/
+	PAD_NC(GPP_D10, NONE),
+	/* D11:		GSPI 2 MISO FPS					*/
+	PAD_NC(GPP_D11, NONE),
+	/* D12:		GSPI 2 MOSI FPS					*/
+	PAD_NC(GPP_D12, NONE),
+	/* D13:		Wireless LAN Wake				*/
+	PAD_CFG_GPO(GPP_D13, 1, PLTRST),
+	/* D14:		ALS Interrupt					*/
+	PAD_NC(GPP_D14, NONE),
+	/* D15:		Not Connected					*/
+	PAD_NC(GPP_D15, NONE),
+	/* D16:		PCH M.2 SSD Power Enable			*/
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST),
+	/* D17:		Not used		Fingerprint ID		*/
+	PAD_NC(GPP_D17, NONE),
+	/* D18:		Bluetooth Wake					*/
+	PAD_NC(GPP_D18, NONE),
+	/* D19:		Test Point 21					*/
+	PAD_NC(GPP_D19, NONE),
+
+	/* E0:		SATA x PCIe					*/
+	PAD_NC(GPP_E0, NONE),
+	/* E1:		Accelerometer Interrupt				*/
+	PAD_NC(GPP_E1, NONE),
+	/* E2:		Not Connected					*/
+	PAD_NC(GPP_E2, NONE),
+	/* E4:		P Offset					*/
+	PAD_NC(GPP_E4, NONE),
+	/* E5:		P Out						*/
+	PAD_NC(GPP_E5, NONE),
+	/* E6:		JTAG ODT		No internal PD
+				Low:	Disabled
+				High:	Enabled				*/
+	PAD_CFG_GPO(GPP_E6, 0, DEEP),
+	/* E7:		Embedded Controller SMI				*/
+	PAD_NC(GPP_E7, NONE),
+	/* E8:		DRAM Sleep					*/
+	PAD_NC(GPP_E8, NONE),
+	/* E9:		USB OverCurrent 0				*/
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	/* E10:		PWD Amplifier Input				*/
+	PAD_NC(GPP_E10, NONE),
+	/* E11:		TPM IRQ						*/
+	PAD_NC(GPP_E11, NONE),
+	/* E12:		Touchpad Interrupt				*/
+	PAD_NC(GPP_E12, NONE),
+	/* E13:		Not connected					*/
+	PAD_NC(GPP_E13, NONE),
+	/* E14:		EDP HPD						*/
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	/* E15:		Webcam Power Enable				*/
+	PAD_NC(GPP_E15, NONE),
+	/* E16:		Not Connected					*/
+	PAD_NC(GPP_E16, NONE),
+	/* E17:		Not Connected					*/
+	PAD_NC(GPP_E17, NONE),
+	/* E18:		Gyroscope Interrupt				*/
+	PAD_NC(GPP_E18, NONE),
+	/* E19:		Thunderbolt LSX RXD				*/
+	PAD_NC(GPP_E19, NONE),
+	/* E20:		Not Connected					*/
+	PAD_NC(GPP_E20, NONE),
+	/* E21:		Not Connected					*/
+	PAD_NC(GPP_E21, NONE),
+	/* E22:		Not Connected					*/
+	PAD_NC(GPP_E22, NONE),
+	/* E23:		Not Connected					*/
+	PAD_NC(GPP_E23, NONE),
+
+	/* F7:		TBT LSX VCCIO		Weak Internal PD 20K
+				Low:	1.8V
+				High:	3.3V				*/
+	PAD_CFG_GPO(GPP_F7, 0, DEEP),
+	/* F8:		Not Connected					*/
+	PAD_NC(GPP_F8, NONE),
+	/* F9:								*/
+	PAD_NC(GPP_F9, NONE),
+	/* F10:		Weak Internal PD 20K				*/
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+	/* F11:		TPM ID						*/
+	PAD_NC(GPP_F11, NONE),
+	/* F12:		Not Connected					*/
+	PAD_NC(GPP_F12, NONE),
+	/* F13:		Not Connected					*/
+	PAD_NC(GPP_F13, NONE),
+	/* F14:		Not Connected					*/
+	PAD_NC(GPP_F14, NONE),
+	/* F15:		Keyboard Detect					*/
+	PAD_NC(GPP_F15, NONE),
+	/* F16:		Not Connected					*/
+	PAD_NC(GPP_F16, NONE),
+	/* F17:		Touch Panel Reset				*/
+	PAD_CFG_GPO(GPP_F17, 1, PLTRST),
+	/* F18:		Touch Panel Interrupt				*/
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_F18, NONE, DEEP),
+	/* F19:		Not Connected					*/
+	PAD_NC(GPP_F19, NONE),
+	/* F20:		Not Connected					*/
+	PAD_NC(GPP_F20, NONE),
+	/* F21:		Not Connected					*/
+	PAD_NC(GPP_F21, NONE),
+	/* F22:		Not Connected					*/
+	PAD_NC(GPP_F22, NONE),
+	/* F23:		Not Connected					*/
+	PAD_NC(GPP_F23, NONE),
+
+	/* H0:		PCH M.2 SSD Reset				*/
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
+	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
+	PAD_CFG_GPO(GPP_H1, 0, DEEP),
+	/* H2:		Wireless LAN Reset				*/
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
+	/* H3:		Not Connected					*/
+	PAD_NC(GPP_H3, NONE),
+	/* H4:		I2C 0 SDA		G Sensor SDA		*/
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H5:		I2C 0 SCL		G Sensor Clock		*/
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H6:		I2C 1 SDC		Camera SDA		*/
+	PAD_NC(GPP_H6, NONE),
+	/* H7:		I2C 2 SCL		Camera Clock		*/
+	PAD_NC(GPP_H7, NONE),
+	/* H8:		Not Connected					*/
+	PAD_NC(GPP_H8, NONE),
+	/* H9:		Camera LDO Enable				*/
+	PAD_NC(GPP_H9, NONE),
+	/* H12:		Not Connected					*/
+	PAD_NC(GPP_H12, NONE),
+	/* H13:		PCH M.2 SSD Device Sleep			*/
+	PAD_NC(GPP_H13, NONE),
+	/* H14:		Not Connected					*/
+	PAD_NC(GPP_H14, NONE),
+	/* H15:		DDPB Control Clock				*/
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	/* H16:		Not Connected					*/
+	PAD_NC(GPP_H16, NONE),
+	/* H17:		DDPB Control Data				*/
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* H18:		CPI C10 Gate					*/
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+	/* H19:		Clock Request 4					*/
+	PAD_NC(GPP_H19, NONE),
+	/* H20:		Webcam Clock					*/
+	PAD_NC(GPP_H20, NONE),
+	/* H21:		Not Connected					*/
+	PAD_NC(GPP_H21, NONE),
+	/* H22:		Not Connected					*/
+	PAD_NC(GPP_H22, NONE),
+	/* H23:		MIPI Camera Power Enable			*/
+	PAD_NC(GPP_H23, NONE),
+
+	/* S0:		Not Connected					*/
+	PAD_NC(GPP_S0, NONE),
+	/* S1:		Not Connected					*/
+	PAD_NC(GPP_S1, NONE),
+	/* S2:		DMIC Clock					*/
+	PAD_NC(GPP_S2, NONE),
+	/* S3:		DMIC Data					*/
+	PAD_NC(GPP_S3, NONE),
+	/* S4:		Not Connected					*/
+	PAD_NC(GPP_S4, NONE),
+	/* S5:		Not Connected					*/
+	PAD_NC(GPP_S5, NONE),
+	/* S6:		Not Connected					*/
+	PAD_NC(GPP_S6, NONE),
+	/* S7:		Not Connected					*/
+	PAD_NC(GPP_S7, NONE),
+
+	/* T0:		 Not Connected					*/
+	PAD_NC(GPP_T0, NONE),
+	/* T1:		 Not Connected					*/
+	PAD_NC(GPP_T1, NONE),
+	/* T2:		 Not Connected					*/
+	PAD_NC(GPP_T2, NONE),
+	/* T3:		 Not Connected					*/
+	PAD_NC(GPP_T3, NONE),
+	/* T4:		 Not Connected					*/
+	PAD_NC(GPP_T4, NONE),
+	/* T5:		 Not Connected					*/
+	PAD_NC(GPP_T5, NONE),
+	/* T6:		 Not Connected					*/
+	PAD_NC(GPP_T6, NONE),
+	/* T7:		 Not Connected					*/
+	PAD_NC(GPP_T7, NONE),
+	/* T8:		 Not Connected					*/
+	PAD_NC(GPP_T8, NONE),
+	/* T9:		 Not Connected					*/
+	PAD_NC(GPP_T9, NONE),
+	/* T10:		 Not Connected					*/
+	PAD_NC(GPP_T10, NONE),
+	/* T11:		 Not Connected					*/
+	PAD_NC(GPP_T11, NONE),
+	/* T12:		 Not Connected					*/
+	PAD_NC(GPP_T12, NONE),
+	/* T13:		 Not Connected					*/
+	PAD_NC(GPP_T13, NONE),
+	/* T14:		 Not Connected					*/
+	PAD_NC(GPP_T14, NONE),
+	/* T15:		 Not Connected					*/
+	PAD_NC(GPP_T15, NONE),
+
+	/* R0:		HDA BCLK					*/
+	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),
+	/* R1:		HDA SYNC					*/
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
+	/* R2:		HDA SDO						*/
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
+	/* R3:		HDA SDI						*/
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
+	/* R4:		HDA Reset					*/
+	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),
+	/* R5:		Not Connected					*/
+	PAD_NC(GPP_R5, NONE),
+	/* R6:		Not Connected					*/
+	PAD_NC(GPP_R6, NONE),
+	/* R7:		Not Connected					*/
+	PAD_NC(GPP_R7, NONE),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}

src/mainboard/starlabs/starlite_adl/variants/mk_v/hda_verb.c

@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0269,	/* Codec Vendor / Device ID: Realtek ALC269 */
+	0x1e507038,	/* Subsystem ID */
+	18,		/* Number of jacks (NID entries) */
+
+	/* Reset Codec First */
+	AZALIA_RESET(0x1),
+
+	/* HDA Codec Subsystem ID */
+	AZALIA_SUBVENDOR(0, 0x1e507038),
+
+	/* Pin Widget Verb-table */
+	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x04214020),
+	AZALIA_PIN_CFG(0, 0x17, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a19040),
+	AZALIA_PIN_CFG(0, 0x19, 0x011111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40e38205),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+
+	/* ALC269 Default 1 */
+	0x02050018,
+	0x02040184,
+	0x0205001c,
+	0x02044800,
+	/* ALC269 Default 2 */
+	0x02050024,
+	0x02040000,
+	0x02050004,
+	0x02040080,
+	/* ALC269 Default 3 */
+	0x02050008,
+	0x02040000,
+	0x0205000c,
+	0x02043f00,
+	/* ALC269 Default 4 */
+	0x02050015,
+	0x02048002,
+	0x02050015,
+	0x02048002,
+	/* Widget 0x0c */
+	0x00c37080,
+	0x00270610,
+	0x00d37080,
+	0x00370610,
+
+	0x8086280d,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+
+	AZALIA_SUBVENDOR(2, 0x80860101),
+
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[] = {
+};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c

@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <option.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include <types.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg mem_config = {
+		.type = MEM_TYPE_LP5X,
+
+		.lpx_dq_map = {
+			.ddr0 = {
+				.dq0	= {	14,	13,	9,	8,	15,	10,	11,	12	},
+				.dq1	= {	1,	3,	7,	0,	6,	5,	2,	4	},
+			},
+			.ddr1 = {
+				.dq0	= {	1,	5,	0,	3,	6,	4,	2,	7	},
+				.dq1	= {	13,	12,	10,	8,	15,	9,	14,	11	},
+			},
+			.ddr2 = {
+				.dq0	= {	0,	1,	5,	3,	7,	2,	6,	4	},
+				.dq1	= {	8,	15,	12,	10,	14,	13,	9,	11	},
+			},
+			.ddr3 = {
+				.dq0	= {	2,	0,	4,	7,	3,	5,	1,	6	},
+				.dq1	= {	14,	8,	9,	11,	12,	15,	13,	10	},
+			},
+			.ddr4 = {
+				.dq0	= {	3,	2,	1,	0,	7,	4,	6,	5	},
+				.dq1	= {	8,	10,	11,	9,	14,	13,	12,	15	},
+			},
+			.ddr6 = {
+				.dq0	= {	8,	9,	10,	11,	12,	13,	14,	15	},
+				.dq1	= {	7,	6,	5,	4,	3,	2,	1,	0	},
+			},
+			.ddr6 =	{
+				.dq0	= {	13,	12,	15,	14,	9,	8,	11,	10	},
+				.dq1	= {	5,	4,	7,	6,	3,	1,	2,	0	},
+			},
+			.ddr7 = {
+				.dq0	= {	3,	1,	2,	0,	4,	6,	5,	7	},
+				.dq1	= {	15,	12,	9,	8,	11,	10,	13,	14	},
+			},
+		},
+
+		.lpx_dqs_map = {
+			.ddr0 =	{
+				.dqs0	= 1,
+				.dqs1	= 0,
+			},
+			.ddr1 =	{
+				.dqs0	= 0,
+				.dqs1	= 1,
+			},
+			.ddr2 =	{
+				.dqs0	= 0,
+				.dqs1	= 1,
+			},
+			.ddr3 =	{
+				.dqs0	= 0,
+				.dqs1	= 1,
+			},
+			.ddr4 =	{
+				.dqs0	= 1,
+				.dqs1	= 0,
+			},
+			.ddr5 =	{
+				.dqs0	= 0,
+				.dqs1	= 1,
+			},
+			.ddr6 =	{
+				.dqs0	= 0,
+				.dqs1	= 1,
+			},
+			.ddr7 =	{
+				.dqs0	= 1,
+				.dqs1	= 0,
+			}
+		},
+
+		.ect			= true,
+		.UserBd			= BOARD_TYPE_MOBILE,
+		.LpDdrDqDqsReTraining	= true,
+
+		.lp5x_config = {
+			.ccc_config	= 0x00,
+		}
+	};
+
+	const bool half_populated = true;
+
+	const struct mem_spd lpddr5_spd_info = {
+		.topo = MEM_TOPO_MEMORY_DOWN,
+		.cbfs_index = 0,
+	};
+
+	memcfg_init(mupd, &mem_config, &lpddr5_spd_info, half_populated);
+
+	const uint8_t vtd = get_uint_option("vtd", 1);
+	mupd->FspmConfig.VtdDisable = !vtd;
+};

src/mainboard/starlabs/starlite_adl/variants/mk_v/vboot.fmd

@@ -0,0 +1,24 @@
+FLASH	0x1000000 {
+	SI_ALL	0x600000 {
+		SI_DESC			0x1000
+		SI_ME			0x466000
+	}
+	SI_BIOS@0xa00000 {
+		EC@0x0	0x20000
+		RO_SECTION@0x20000	0x253000 {
+			FMAP@0x0			0x1000
+			COREBOOT(CBFS)@0x1000		0x210000
+			GBB@0x211000			0x40000
+			RO_FRID@0x251000		0x40
+			RO_VPD(PRESERVE)@0x252000	0x1000
+		}
+		MISC_RW@0x253000		0x10000 {
+			RW_MRC_CACHE@0x0		0x10000
+		}
+		SMMSTORE@0x263000		0x40000
+		CONSOLE@0x0x2a3000		0x20000
+		RW_NVRAM(PRESERVE)@0x2c3000	0x6000
+		RW_VPD(PRESERVE)@0x2c9000	0x2000
+		RW_LEGACY(CBFS)@0x32b000	0x60000
+	}
+}

src/mainboard/starlabs/starlite_adl/vboot.c

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootmode.h>
+
+int get_recovery_mode_switch(void)
+{
+	return 0;
+}