From c6df1ac62c4cfd3284e4a454ffa53989c8f7ff6e Mon Sep 17 00:00:00 2001 From: Weimin Wu Date: Tue, 20 Feb 2024 10:03:00 +0800 Subject: [PATCH] mb/google/nissa/var/anraggar: Change tdp_pl1_override from 6 W to 15 W Set tdp_pl1_override to 15 for performance required by the thermal team. Fix policies.critical index from 2 to 0. BUG=b:313833488 TEST=emerge-nissa coreboot Change-Id: I5341bd3d4842f9298a2f5d9e589918bb1b06ba69 Signed-off-by: Weimin Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/80620 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Eric Lai --- .../google/brya/variants/anraggar/overridetree.cb | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index 0fd63a72a3..77ae2b6782 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -134,6 +134,13 @@ chip soc/intel/alderlake }, }" + # Power limit config + register "power_limits_config[ADL_N_041_6W_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 25, + .tdp_pl4 = 78, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -155,8 +162,8 @@ chip soc/intel/alderlake ## Critical Policy register "policies.critical" = "{ - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), - [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN), + [0] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN), }" register "controls.power_limits" = "{