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fsp2_0: implement stage cache for silicon init

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Stage cache will save ~20ms on S3 resume for apollolake platforms.
Implementing the cache in ramstage to save silicon init and reload
it on resume. This patch adds passing S3 status to silicon init in
order to verify that the wake is from S3 and not for some other
reason. This patch also includes changes needed for quark and
skylake platforms that require fsp 2.0.

BUG=chrome-os-partner:56941
BRANCH=none
TEST=built for reef and tested boot and S3 resume path saving 20ms

Change-Id: I99dc93c1d7a7d5cf8d8de1aa253a326ec67f05f6
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/17460
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Brandon Breitenstein
2016-11-17 12:23:04 -08:00
committed by Martin Roth
parent 5c325491ca
commit c6ec8dd1cb
5 changed files with 34 additions and 5 deletions
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6
src/soc/intel/quark/chip.c
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@@ -17,6 +17,7 @@
#include <assert.h>
#include <console/console.h>
#include <device/device.h>
#include <romstage_handoff.h>
#include <soc/ramstage.h>
#include <soc/reg_access.h>
@@ -101,6 +102,8 @@ static const struct reg_script thermal_init_script[] = {
static void chip_init(void *chip_info)
{
struct romstage_handoff *handoff;
/* Validate the temperature settings */
ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255);
ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS
@@ -117,7 +120,8 @@ static void chip_init(void *chip_info)
| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE));
/* Perform silicon specific init. */
fsp_silicon_init();
handoff = romstage_handoff_find_or_add();
fsp_silicon_init(handoff->s3_resume);
}
static void pci_domain_set_resources(device_t dev)