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soc/intel/apollolake: Add tsc_freq.c to all the stages

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Change-Id: I3120a52e21cf4ad03bb1d16b5b2b8a5e68aabf3f
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14339
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Andrey Petrov 2016-04-12 17:00:52 -07:00 committed by Aaron Durbin
parent 399332d271
commit c6ee58c790
1 changed files with 2 additions and 0 deletions
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src/soc/intel/apollolake/Makefile.inc
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@ -25,6 +25,7 @@ romstage-y += gpio.c
romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
romstage-y += memmap.c romstage-y += memmap.c
romstage-y += mmap_boot.c romstage-y += mmap_boot.c
romstage-y += tsc_freq.c
smm-y += placeholders.c smm-y += placeholders.c
@ -40,6 +41,7 @@ ramstage-y += mmap_boot.c
ramstage-y += uart.c ramstage-y += uart.c
ramstage-y += northbridge.c ramstage-y += northbridge.c
ramstage-y += spi.c ramstage-y += spi.c
ramstage-y += tsc_freq.c
postcar-y += exit_car.S postcar-y += exit_car.S
postcar-y += memmap.c postcar-y += memmap.c