soc/intel/apollolake: Add tsc_freq.c to all the stages

Change-Id: I3120a52e21cf4ad03bb1d16b5b2b8a5e68aabf3f
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14339
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

src/soc/intel/apollolake/Makefile.inc

@@ -25,6 +25,7 @@ romstage-y += gpio.c
 romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 romstage-y += memmap.c
 romstage-y += mmap_boot.c
+romstage-y += tsc_freq.c
 
 smm-y += placeholders.c
 
@@ -40,6 +41,7 @@ ramstage-y += mmap_boot.c
 ramstage-y += uart.c
 ramstage-y += northbridge.c
 ramstage-y += spi.c
+ramstage-y += tsc_freq.c
 
 postcar-y += exit_car.S
 postcar-y += memmap.c