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device: Use pcidev_on_root()

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Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki
2018-05-22 02:18:00 +03:00
committed by Felix Held
parent 54efaae701
commit c70eed1e62
170 changed files with 348 additions and 347 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
View File

@@ -142,7 +142,8 @@ static void model_10xxx_init(struct device *dev)
uint32_t f5x80;
uint8_t enabled;
uint8_t compute_unit_count = 0;
f5x80 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 5)), 0x80);
f5x80 = pci_read_config32(pcidev_on_root(0x18 + id.nodeid, 5),
0x80);
enabled = f5x80 & 0xf;
if (enabled == 0x1)
compute_unit_count = 1;
@@ -161,11 +162,13 @@ static void model_10xxx_init(struct device *dev)
uint32_t f0x160;
uint8_t core_count = 0;
uint8_t node_count = 0;
f0x60 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x60);
f0x60 = pci_read_config32(pcidev_on_root(0x18 + id.nodeid, 0),
0x60);
core_count = (f0x60 >> 16) & 0x1f;
node_count = ((f0x60 >> 4) & 0x7) + 1;
if (is_gt_rev_d()) {
f0x160 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x160);
f0x160 = pci_read_config32(
pcidev_on_root(0x18 + id.nodeid, 0), 0x160);
core_count |= ((f0x160 >> 16) & 0x7) << 5;
}
core_count++;

3
src/cpu/amd/family_10h-family_15h/monotonic_timer.c
View File

@@ -51,7 +51,8 @@ static void init_timer(void)
/* Get boost capability */
if ((model == 0x8) || (model == 0x9)) { /* revision D */
boost_capable = (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 4)), 0x15c) & 0x4) >> 2;
boost_capable = (pci_read_config32(pcidev_on_root(0x18, 4),
0x15c) & 0x4) >> 2;
}
/* Set up TSC (BKDG v3.62 section 2.9.4)*/

17
src/cpu/amd/family_10h-family_15h/powernow_acpi.c
View File

@@ -233,16 +233,17 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
fam15h = !!(mctGetLogicalCPUID(0) & AMD_FAM15_ALL);
/* Get number of cores */
if (fam15h) {
cmp_cap = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 5)), 0x84) & 0xff;
cmp_cap = pci_read_config32(pcidev_on_root(0x18, 5), 0x84) &
0xff;
} else {
dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xe8);
dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xe8);
cmp_cap = (dtemp & 0x3000) >> 12;
if (mctGetLogicalCPUID(0) & (AMD_FAM10_REV_D | AMD_FAM15_ALL)) /* revision D or higher */
cmp_cap |= (dtemp & 0x8000) >> 13;
}
/* Get number of nodes */
dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x60);
dtemp = pci_read_config32(pcidev_on_root(0x18, 0), 0x60);
node_count = ((dtemp & 0x70) >> 4) + 1;
cores_per_node = cmp_cap + 1;
@@ -251,7 +252,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
/* Get number of boost states */
uint8_t boost_count = 0;
dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 4)), 0x15c);
dtemp = pci_read_config32(pcidev_on_root(0x18, 4), 0x15c);
if (fam10h_rev_e)
boost_count = (dtemp >> 2) & 0x1;
else if (mctGetLogicalCPUID(0) & AMD_FAM15_ALL)
@@ -289,7 +290,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
uint8_t single_link;
/* Determine if this is a PVI or SVI system */
dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0);
dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xA0);
if (dtemp & PVI_MODE)
pviModeFlag = 1;
@@ -361,10 +362,10 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
core_power = (core_voltage * cpuidd) / (expanded_cpuidv * 10);
/* Calculate transition latency */
dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xD4);
dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xD4);
power_step_up = (dtemp & 0xf000000) >> 24;
power_step_down = (dtemp & 0xf00000) >> 20;
dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0);
dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xA0);
pll_lock_time = (dtemp & 0x3800) >> 11;
if (all_enabled_cores_have_same_cpufid)
core_latency = ((12 * power_step_down) + power_step_up) / 1000;
@@ -396,7 +397,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
for (index = 0; index < total_core_count; index++) {
/* Determine if this is a single-link processor */
node_index = 0x18 + (index / cores_per_node);
dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(node_index, 0)), 0x80);
dtemp = pci_read_config32(pcidev_on_root(node_index, 0), 0x80);
single_link = !!(((dtemp & 0xff00) >> 8) == 0);
/* Enter processor core scope */

2
src/cpu/amd/family_10h-family_15h/processor_name.c
View File

@@ -235,7 +235,7 @@ int init_processor_name(void)
if (fam15h) {
/* Family 15h or later */
uint32_t dword;
struct device *cpu_fn5_dev = dev_find_slot(0, PCI_DEVFN(0x18, 5));
struct device *cpu_fn5_dev = pcidev_on_root(0x18, 5);
pci_write_config32(cpu_fn5_dev, 0x194, 0);
dword = pci_read_config32(cpu_fn5_dev, 0x198);
if (dword == 0) {

2
src/cpu/amd/family_10h-family_15h/ram_calc.c
View File

@@ -72,7 +72,7 @@ uint64_t get_cc6_memory_size()
if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18))
enable_cc6 = 1;
#else
struct device *dct_dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
struct device *dct_dev = pcidev_on_root(0x18, 2);
if (pci_read_config32(dct_dev, 0x118) & (0x1 << 18))
enable_cc6 = 1;
#endif