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device: Use pcidev_on_root()

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Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki
2018-05-22 02:18:00 +03:00
committed by Felix Held
parent 54efaae701
commit c70eed1e62
170 changed files with 348 additions and 347 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/intel/e7505/northbridge.c
View File

@@ -38,7 +38,7 @@ static void mch_domain_read_resources(struct device *dev)
pci_domain_read_resources(dev);
mc_dev = dev_find_slot(0, PCI_DEVFN(0x0, 0));
mc_dev = pcidev_on_root(0, 0);
if (!mc_dev)
die("Could not find MCH device\n");

4
src/northbridge/intel/fsp_rangeley/northbridge.c
View File

@@ -39,7 +39,7 @@ int bridge_silicon_revision(void)
if (bridge_revision_id < 0) {
uint8_t stepping = cpuid_eax(1) & 0xf;
uint8_t bridge_id = pci_read_config16(
dev_find_slot(0, PCI_DEVFN(0, 0)),
pcidev_on_root(0, 0),
PCI_DEVICE_ID) & 0xf0;
bridge_revision_id = bridge_id | stepping;
}
@@ -62,7 +62,7 @@ static int get_pcie_bar(u32 *base)
*base = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
dev = pcidev_on_root(0, 0);
if (!dev)
return 0;

8
src/northbridge/intel/gm45/acpi.c
View File

@@ -68,9 +68,11 @@ unsigned long acpi_fill_mcfg(unsigned long current)
static unsigned long acpi_fill_dmar(unsigned long current)
{
int me_active = (dev_find_slot(0, PCI_DEVFN(3, 0)) != NULL) &&
(pci_read_config8(dev_find_slot(0, PCI_DEVFN(3, 0)), PCI_CLASS_REVISION) != 0xff);
int stepping = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), PCI_CLASS_REVISION);
int me_active = (pcidev_on_root(3, 0) != NULL) &&
(pci_read_config8(pcidev_on_root(3, 0), PCI_CLASS_REVISION) !=
0xff);
int stepping = pci_read_config8(pcidev_on_root(0, 0),
PCI_CLASS_REVISION);
unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1);

2
src/northbridge/intel/gm45/gma.c
View File

@@ -815,7 +815,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor,
const struct i915_gpu_controller_info *
intel_gma_get_controller_info(void)
{
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
struct device *dev = pcidev_on_root(0x2, 0);
if (!dev) {
return NULL;
}

10
src/northbridge/intel/gm45/northbridge.c
View File

@@ -41,7 +41,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len)
*base = 0;
*len = 0;
struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *dev = pcidev_on_root(0, 0);
if (!dev)
return 0;
@@ -95,7 +95,7 @@ static void mch_domain_read_resources(struct device *dev)
pci_domain_read_resources(dev);
struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *mch = pcidev_on_root(0, 0);
/* Top of Upper Usable DRAM, including remap */
touud = pci_read_config16(mch, D0F0_TOUUD);
@@ -196,7 +196,7 @@ static void mch_domain_init(struct device *dev)
{
u32 reg32;
struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *mch = pcidev_on_root(0, 0);
/* Enable SERR */
reg32 = pci_read_config32(mch, PCI_COMMAND);
@@ -222,7 +222,7 @@ static const char *northbridge_acpi_name(const struct device *dev)
void northbridge_write_smram(u8 smram)
{
struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *dev = pcidev_on_root(0, 0);
if (dev == NULL)
die("could not find pci 00:00.0!\n");
@@ -309,7 +309,7 @@ static void gm45_init(void *const chip_info)
}
for (; fn >= 0; --fn) {
const struct device *const d =
dev_find_slot(0, PCI_DEVFN(dev, fn));
pcidev_on_root(dev, fn);
if (!d || d->enabled) continue;
const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN);
pci_write_config32(d0f0, D0F0_DEVEN,

4
src/northbridge/intel/haswell/acpi.c
View File

@@ -31,7 +31,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
int max_buses;
u32 mask;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
dev = pcidev_on_root(0, 0);
if (!dev)
return current;
@@ -72,7 +72,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
static unsigned long acpi_fill_dmar(unsigned long current)
{
struct device *const igfx_dev = dev_find_slot(0, PCI_DEVFN(2, 0));
struct device *const igfx_dev = pcidev_on_root(2, 0);
const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1;

2
src/northbridge/intel/haswell/gma.c
View File

@@ -512,7 +512,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor,
const struct i915_gpu_controller_info *
intel_gma_get_controller_info(void)
{
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
struct device *dev = pcidev_on_root(0x2, 0);
if (!dev) {
return NULL;
}

2
src/northbridge/intel/haswell/northbridge.c
View File

@@ -449,7 +449,7 @@ static void disable_devices(void)
{ PCI_DEVFN(7, 0), DEVEN_D7EN, "\"device 7\"" },
};
struct device *host_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *host_dev = pcidev_on_root(0x0, 0);
u32 deven;
size_t i;

2
src/northbridge/intel/i945/acpi.c
View File

@@ -29,7 +29,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
u32 pciexbar_reg;
int max_buses;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
dev = pcidev_on_root(0, 0);
if (!dev)
return current;

10
src/northbridge/intel/i945/gma.c
View File

@@ -73,7 +73,7 @@ static int gtt_setup(u8 *mmiobase)
/*
* The Video BIOS places the GTT right below top of memory.
*/
tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24;
tom = pci_read_config8(pcidev_on_root(0, 0), TOLUD) << 24;
PGETBL_save = tom - 256 * KiB;
PGETBL_save |= PGETBL_ENABLED;
PGETBL_save |= 2; /* set GTT to 256kb */
@@ -357,7 +357,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
/* Setup GTT. */
reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC);
uma_size = 0;
if (!(reg16 & 2)) {
uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
@@ -536,7 +536,7 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf,
/* Set up GTT. */
reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC);
uma_size = 0;
if (!(reg16 & 2)) {
uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
@@ -725,7 +725,7 @@ static void gma_func0_init(struct device *dev)
be re-enabled later. */
static void gma_func0_disable(struct device *dev)
{
struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0));
struct device *dev_host = pcidev_on_root(0x0, 0);
pci_write_config16(dev, GCFC, 0xa00);
pci_write_config16(dev_host, GGC, (1 << 1));
@@ -768,7 +768,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor,
const struct i915_gpu_controller_info *
intel_gma_get_controller_info(void)
{
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2, 0));
struct device *dev = pcidev_on_root(0x2, 0);
if (!dev)
return NULL;
struct northbridge_intel_i945_config *chip = dev->chip_info;

14
src/northbridge/intel/i945/northbridge.c
View File

@@ -34,7 +34,7 @@ static int get_pcie_bar(u32 *base)
*base = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
dev = pcidev_on_root(0, 0);
if (!dev)
return 0;
@@ -76,16 +76,16 @@ static void mch_domain_read_resources(struct device *dev)
printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm);
printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n",
pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), BSM));
pci_read_config32(pcidev_on_root(2, 0), BSM));
tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD);
tolud = pci_read_config8(pcidev_on_root(0, 0), TOLUD);
printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08x\n", tolud << 24);
tomk = tolud << 14;
tomk_stolen = tomk;
/* Note: subtract IGD device and TSEG */
reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC);
if (!(reg16 & 2)) {
printk(BIOS_DEBUG, "IGD decoded, subtracting ");
int uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
@@ -98,8 +98,8 @@ static void mch_domain_read_resources(struct device *dev)
uma_memory_size = uma_size * 1024ULL;
}
tseg_sizek = decode_tseg_size(pci_read_config8(dev_find_slot(0,
PCI_DEVFN(0, 0)), ESMRAMC)) >> 10;
tseg_sizek = decode_tseg_size(pci_read_config8(pcidev_on_root(0, 0),
ESMRAMC)) >> 10;
printk(BIOS_DEBUG, "TSEG decoded, subtracting %dM\n", tseg_sizek >> 10);
tomk_stolen -= tseg_sizek;
tseg_memory_base = tomk_stolen * 1024ULL;
@@ -157,7 +157,7 @@ static const char *northbridge_acpi_name(const struct device *dev)
void northbridge_write_smram(u8 smram)
{
struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *dev = pcidev_on_root(0, 0);
if (dev == NULL)
die("could not find pci 00:00.0!\n");

2
src/northbridge/intel/i945/raminit.c
View File

@@ -1219,7 +1219,7 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
tom = tolud >> 3;
/* Limit the value of TOLUD to leave some space for PCI memory. */
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
dev = pcidev_on_root(0, 0);
if (dev)
cfg = dev->chip_info;

2
src/northbridge/intel/nehalem/gma.c
View File

@@ -658,7 +658,7 @@ static void gma_read_resources(struct device *dev)
const struct i915_gpu_controller_info *
intel_gma_get_controller_info(void)
{
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
struct device *dev = pcidev_on_root(0x2, 0);
if (!dev) {
return NULL;
}

14
src/northbridge/intel/nehalem/northbridge.c
View File

@@ -39,7 +39,7 @@ int bridge_silicon_revision(void)
if (bridge_revision_id < 0) {
uint8_t stepping = cpuid_eax(1) & 0xf;
uint8_t bridge_id =
pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)),
pci_read_config16(pcidev_on_root(0, 0),
PCI_DEVICE_ID) & 0xf0;
bridge_revision_id = bridge_id | stepping;
}
@@ -129,8 +129,8 @@ static void mc_read_resources(struct device *dev)
mmconf_resource(dev, 0x50);
tseg_base = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG);
TOUUD = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)),
tseg_base = pci_read_config32(pcidev_on_root(0, 0), TSEG);
TOUUD = pci_read_config16(pcidev_on_root(0, 0),
D0F0_TOUUD);
printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base);
@@ -142,7 +142,7 @@ static void mc_read_resources(struct device *dev)
mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10);
reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GGC);
reg16 = pci_read_config16(pcidev_on_root(0, 0), D0F0_GGC);
const int uma_sizes_gtt[16] =
{ 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 };
/* Igd memory */
@@ -156,9 +156,9 @@ static void mc_read_resources(struct device *dev)
uma_size_gtt = uma_sizes_gtt[(reg16 >> 8) & 0xF];
igd_base =
pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_IGD_BASE);
pci_read_config32(pcidev_on_root(0, 0), D0F0_IGD_BASE);
gtt_base =
pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GTT_BASE);
pci_read_config32(pcidev_on_root(0, 0), D0F0_GTT_BASE);
mmio_resource(dev, 6, gtt_base >> 10, uma_size_gtt << 10);
mmio_resource(dev, 7, igd_base >> 10, uma_size_igd << 10);
@@ -174,7 +174,7 @@ static void mc_read_resources(struct device *dev)
u32 northbridge_get_tseg_base(void)
{
struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *dev = pcidev_on_root(0, 0);
return pci_read_config32(dev, TSEG) & ~1;
}

2
src/northbridge/intel/pineview/early_init.c
View File

@@ -41,7 +41,7 @@ static void early_graphics_setup(void)
u16 reg16;
u32 reg32;
const struct device *d0f0 = dev_find_slot(0, PCI_DEVFN(0,0));
const struct device *d0f0 = pcidev_on_root(0, 0);
const struct northbridge_intel_pineview_config *config = d0f0->chip_info;
pci_write_config8(D0F0, DEVEN, BOARD_DEVEN);

4
src/northbridge/intel/pineview/gma.c
View File

@@ -72,7 +72,7 @@ void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
static int gtt_setup(u8 *mmiobase)
{
u32 gttbase;
struct device *dev = dev_find_slot(0, PCI_DEVFN(0,0));
struct device *dev = pcidev_on_root(0, 0);
gttbase = pci_read_config32(dev, BGSM);
printk(BIOS_DEBUG, "gttbase = %08x\n", gttbase);
@@ -319,7 +319,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor,
const struct i915_gpu_controller_info *intel_gma_get_controller_info(void)
{
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
struct device *dev = pcidev_on_root(0x2, 0);
if (!dev) {
printk(BIOS_WARNING, "WARNING: Can't find IGD (0,2,0)\n");
return NULL;

4
src/northbridge/intel/pineview/northbridge.c
View File

@@ -60,7 +60,7 @@ static void mch_domain_read_resources(struct device *dev)
u16 index;
const u32 top32memk = 4 * (GiB / KiB);
struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *mch = pcidev_on_root(0, 0);
index = 3;
@@ -143,7 +143,7 @@ static void mch_domain_read_resources(struct device *dev)
void northbridge_write_smram(u8 smram)
{
struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *dev = pcidev_on_root(0, 0);
if (dev == NULL)
die("could not find pci 00:00.0!\n");

4
src/northbridge/intel/sandybridge/acpi.c
View File

@@ -29,7 +29,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
u32 pciexbar_reg;
int max_buses;
struct device *const dev = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *const dev = pcidev_on_root(0, 0);
if (!dev)
return current;
@@ -68,7 +68,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
static unsigned long acpi_fill_dmar(unsigned long current)
{
const struct device *const igfx = dev_find_slot(0, PCI_DEVFN(2, 0));
const struct device *const igfx = pcidev_on_root(2, 0);
if (igfx && igfx->enabled) {
const unsigned long tmp = current;

4
src/northbridge/intel/sandybridge/gma.c
View File

@@ -684,7 +684,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor,
const struct i915_gpu_controller_info *
intel_gma_get_controller_info(void)
{
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
struct device *dev = pcidev_on_root(0x2, 0);
if (!dev) {
return NULL;
}
@@ -737,7 +737,7 @@ static const char *gma_acpi_name(const struct device *dev)
static void gma_func0_disable(struct device *dev)
{
u16 reg16;
struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0,0));
struct device *dev_host = pcidev_on_root(0, 0);
reg16 = pci_read_config16(dev_host, GGC);
reg16 |= (1 << 1); /* disable VGA decode */

2
src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
View File

@@ -504,7 +504,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
write32(mmio + 0x0004f05c, 0x00000008);
/* Linux relies on VBT for panel info. */
generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)),
generate_fake_intel_oprom(info, pcidev_on_root(2, 0),
"$VBT SNB/IVB-MOBILE");
return 1;

2
src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
View File

@@ -469,7 +469,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
}
/* Linux relies on VBT for panel info. */
generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)),
generate_fake_intel_oprom(info, pcidev_on_root(2, 0),
"$VBT SNB/IVB-MOBILE");
return 1;

3
src/northbridge/intel/sandybridge/iommu.c
View File

@@ -37,8 +37,7 @@ void sandybridge_init_iommu(void)
/* lock policies */
write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000);
const struct device *const azalia =
dev_find_slot(0x00, PCI_DEVFN(0x1b, 0));
const struct device *const azalia = pcidev_on_root(0x1b, 0);
if (azalia && azalia->enabled) {
write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000);
write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000);

28
src/northbridge/intel/sandybridge/northbridge.c
View File

@@ -42,7 +42,7 @@ int bridge_silicon_revision(void)
if (bridge_revision_id < 0) {
uint8_t stepping = cpuid_eax(1) & 0xf;
uint8_t bridge_id = pci_read_config16(
dev_find_slot(0, PCI_DEVFN(0, 0)),
pcidev_on_root(0, 0),
PCI_DEVICE_ID) & 0xf0;
bridge_revision_id = bridge_id | stepping;
}
@@ -65,7 +65,7 @@ static int get_pcie_bar(u32 *base)
*base = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
dev = pcidev_on_root(0, 0);
if (!dev)
return 0;
@@ -151,7 +151,7 @@ static void pci_domain_set_resources(struct device *dev)
* 14fe00000 5368MB TOUUD
*/
struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *mch = pcidev_on_root(0, 0);
/* Top of Upper Usable DRAM, including remap */
touud = pci_read_config32(mch, TOUUD+4);
@@ -351,46 +351,46 @@ static void disable_peg(void)
struct device *dev;
u32 reg;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
dev = pcidev_on_root(0, 0);
reg = pci_read_config32(dev, DEVEN);
dev = dev_find_slot(0, PCI_DEVFN(1, 2));
dev = pcidev_on_root(1, 2);
if (!dev || !dev->enabled) {
printk(BIOS_DEBUG, "Disabling PEG12.\n");
reg &= ~DEVEN_PEG12;
}
dev = dev_find_slot(0, PCI_DEVFN(1, 1));
dev = pcidev_on_root(1, 1);
if (!dev || !dev->enabled) {
printk(BIOS_DEBUG, "Disabling PEG11.\n");
reg &= ~DEVEN_PEG11;
}
dev = dev_find_slot(0, PCI_DEVFN(1, 0));
dev = pcidev_on_root(1, 0);
if (!dev || !dev->enabled) {
printk(BIOS_DEBUG, "Disabling PEG10.\n");
reg &= ~DEVEN_PEG10;
}
dev = dev_find_slot(0, PCI_DEVFN(2, 0));
dev = pcidev_on_root(2, 0);
if (!dev || !dev->enabled) {
printk(BIOS_DEBUG, "Disabling IGD.\n");
reg &= ~DEVEN_IGD;
}
dev = dev_find_slot(0, PCI_DEVFN(4, 0));
dev = pcidev_on_root(4, 0);
if (!dev || !dev->enabled) {
printk(BIOS_DEBUG, "Disabling Device 4.\n");
reg &= ~DEVEN_D4EN;
}
dev = dev_find_slot(0, PCI_DEVFN(6, 0));
dev = pcidev_on_root(6, 0);
if (!dev || !dev->enabled) {
printk(BIOS_DEBUG, "Disabling PEG60.\n");
reg &= ~DEVEN_PEG60;
}
dev = dev_find_slot(0, PCI_DEVFN(7, 0));
dev = pcidev_on_root(7, 0);
if (!dev || !dev->enabled) {
printk(BIOS_DEBUG, "Disabling Device 7.\n");
reg &= ~DEVEN_D7EN;
}
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
dev = pcidev_on_root(0, 0);
pci_write_config32(dev, DEVEN, reg);
if (!(reg & (DEVEN_PEG60 | DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12))) {
/* Set the PEG clock gating bit.
@@ -469,7 +469,7 @@ static u32 northbridge_get_base_reg(struct device *dev, int reg)
u32 northbridge_get_tseg_base(void)
{
struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *dev = pcidev_on_root(0, 0);
return northbridge_get_base_reg(dev, TSEG);
}
@@ -481,7 +481,7 @@ u32 northbridge_get_tseg_size(void)
void northbridge_write_smram(u8 smram)
{
pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, smram);
pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram);
}
static struct pci_operations intel_pci_ops = {

2
src/northbridge/intel/x4x/acpi.c
View File

@@ -30,7 +30,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
u32 pciexbar = 0;
u32 length = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
dev = pcidev_on_root(0, 0);
if (!decode_pciebar(&pciexbar, &length))
return current;

8
src/northbridge/intel/x4x/gma.c
View File

@@ -69,10 +69,10 @@ static void gma_func0_init(struct device *dev)
pci_write_config32(dev, PCI_COMMAND, reg32);
/* configure GMBUSFREQ */
reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x2, 0)), 0xcc);
reg16 = pci_read_config16(pcidev_on_root(0x2, 0), 0xcc);
reg16 &= ~0x1ff;
reg16 |= 0xbc;
pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x2, 0)), 0xcc, reg16);
pci_write_config16(pcidev_on_root(0x2, 0), 0xcc, reg16);
int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1;
@@ -93,7 +93,7 @@ static void gma_func0_init(struct device *dev)
static void gma_func0_disable(struct device *dev)
{
struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *dev_host = pcidev_on_root(0, 0);
u16 ggc;
ggc = pci_read_config16(dev_host, D0F0_GGC);
@@ -117,7 +117,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor,
const struct i915_gpu_controller_info *
intel_gma_get_controller_info(void)
{
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2, 0));
struct device *dev = pcidev_on_root(0x2, 0);
if (!dev)
return NULL;
struct northbridge_intel_x4x_config *chip = dev->chip_info;

6
src/northbridge/intel/x4x/northbridge.c
View File

@@ -45,7 +45,7 @@ static void mch_domain_read_resources(struct device *dev)
pci_domain_read_resources(dev);
struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *mch = pcidev_on_root(0, 0);
/* Top of Upper Usable DRAM, including remap */
touud = pci_read_config16(mch, D0F0_TOUUD);
@@ -174,7 +174,7 @@ static const char *northbridge_acpi_name(const struct device *dev)
void northbridge_write_smram(u8 smram)
{
struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *dev = pcidev_on_root(0, 0);
if (dev == NULL)
die("could not find pci 00:00.0!\n");
@@ -266,7 +266,7 @@ static void x4x_init(void *const chip_info)
}
for (; fn >= 0; --fn) {
const struct device *const d =
dev_find_slot(0, PCI_DEVFN(dev, fn));
pcidev_on_root(dev, fn);
if (!d || d->enabled)
continue;
const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN);