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device: Use pcidev_on_root()

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Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki
2018-05-22 02:18:00 +03:00
committed by Felix Held
parent 54efaae701
commit c70eed1e62
170 changed files with 348 additions and 347 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/baytrail/pmutil.c
View File

@@ -43,7 +43,7 @@ static struct device *pcu_dev;
static struct device *get_pcu_dev(void)
{
if (pcu_dev == NULL)
pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0));
pcu_dev = pcidev_on_root(PCU_DEV, 0);
return pcu_dev;
}
#endif

2
src/soc/intel/baytrail/ramstage.c
View File

@@ -80,7 +80,7 @@ static void fill_in_pattrs(void)
struct pattrs *attrs = (struct pattrs *)pattrs_get();
attrs->cpuid = cpuid_eax(1);
dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
attrs->revid = pci_read_config8(dev, REVID);
/* The revision to stepping IDs have two values per metal stepping. */
if (attrs->revid >= RID_D_STEPPING_START) {

2
src/soc/intel/baytrail/romstage/pmc.c
View File

@@ -44,7 +44,7 @@ void punit_init(void)
const struct soc_intel_baytrail_config *cfg = NULL;
rid = pci_read_config8(IOSF_PCI_DEV, REVID);
dev = dev_find_slot(0, PCI_DEVFN(SOC_DEV, SOC_FUNC));
dev = pcidev_on_root(SOC_DEV, SOC_FUNC);
if (dev)
cfg = dev->chip_info;

2
src/soc/intel/baytrail/spi.c
View File

@@ -267,7 +267,7 @@ static ich9_spi_regs *spi_regs(void)
#ifdef __SMM__
pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
#else
struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
#endif
pci_read_config_dword(dev, SBASE, &sbase);
sbase &= ~0x1ff;

4
src/soc/intel/braswell/chip.c
View File

@@ -86,7 +86,7 @@ __weak void board_silicon_USB2_override(SILICON_INIT_UPD *params)
void soc_silicon_init_params(SILICON_INIT_UPD *params)
{
struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
struct soc_intel_braswell_config *config;
if (!dev) {
@@ -406,7 +406,7 @@ struct pci_operations soc_pci_ops = {
**/
int SocStepping(void)
{
struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
u8 revid = pci_read_config8(dev, 0x8);
switch (revid & B_PCH_LPC_RID_STEPPING_MASK) {

2
src/soc/intel/braswell/pmutil.c
View File

@@ -44,7 +44,7 @@ static struct device *pcu_dev;
static struct device *get_pcu_dev(void)
{
if (pcu_dev == NULL)
pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0));
pcu_dev = pcidev_on_root(PCU_DEV, 0);
return pcu_dev;
}
#endif /* ENV_SMM */

2
src/soc/intel/braswell/ramstage.c
View File

@@ -84,7 +84,7 @@ static void fill_in_pattrs(void)
struct pattrs *attrs = (struct pattrs *)pattrs_get();
attrs->cpuid = cpuid_eax(1);
dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
attrs->revid = pci_read_config8(dev, REVID);
/* The revision to stepping IDs have two values per metal stepping. */
if (attrs->revid >= RID_D_STEPPING_START) {

2
src/soc/intel/braswell/romstage/romstage.c
View File

@@ -216,7 +216,7 @@ void soc_memory_init_params(struct romstage_params *params,
const struct soc_intel_braswell_config *config;
/* Set the parameters for MemoryInit */
dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
if (!dev) {
printk(BIOS_ERR,

2
src/soc/intel/braswell/spi.c
View File

@@ -236,7 +236,7 @@ static ich9_spi_regs *spi_regs(void)
#if ENV_SMM
pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
#else
struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
#endif
if (!dev) {
printk(BIOS_ERR, "%s: PCI device not found", __func__);

4
src/soc/intel/common/block/lpc/lpc_lib.c
View File

@@ -265,7 +265,7 @@ static void pch_lpc_interrupt_init(void)
{
const struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
if (!dev || !dev->chip_info)
return;
@@ -278,7 +278,7 @@ void pch_enable_lpc(void)
const struct device *dev;
uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES];
dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
if (!dev || !dev->chip_info)
return;

6
src/soc/intel/fsp_baytrail/i2c.c
View File

@@ -114,7 +114,7 @@ int i2c_init(unsigned bus)
base_ptr = (char*)base_adr[bus];
/* Set the I2C-device the user wants to use */
dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1));
dev = pcidev_on_root(I2C1_DEV, bus + 1);
/* Ensure we have the right PCI device */
if ((pci_read_config16(dev, 0x0) != I2C_PCI_VENDOR_ID) ||
@@ -171,7 +171,7 @@ int i2c_read(unsigned bus, unsigned chip, unsigned addr,
int stat;
/* Get base address of desired I2C-controller */
dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1));
dev = pcidev_on_root(I2C1_DEV, bus + 1);
base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
if (base_ptr == NULL) {
printk(BIOS_INFO, "I2C: Invalid Base address\n");
@@ -230,7 +230,7 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr,
int stat;
/* Get base address of desired I2C-controller */
dev = dev_find_slot(0, PCI_DEVFN(I2C1_DEV, bus + 1));
dev = pcidev_on_root(I2C1_DEV, bus + 1);
base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
if (base_ptr == NULL) {
return I2C_ERR_INVALID_ADR;

2
src/soc/intel/fsp_baytrail/northcluster.c
View File

@@ -92,7 +92,7 @@ static int get_pcie_bar(u32 *base)
*base = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
dev = pcidev_on_root(0, 0);
if (!dev)
return 0;

2
src/soc/intel/fsp_baytrail/pmutil.c
View File

@@ -41,7 +41,7 @@ static struct device *pcu_dev;
static struct device *get_pcu_dev(void)
{
if (pcu_dev == NULL)
pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0));
pcu_dev = pcidev_on_root(PCU_DEV, 0);
return pcu_dev;
}
#endif

2
src/soc/intel/fsp_baytrail/ramstage.c
View File

@@ -78,7 +78,7 @@ static void fill_in_pattrs(void)
struct pattrs *attrs = (struct pattrs *)pattrs_get();
attrs->cpuid = cpuid_eax(1);
dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
attrs->revid = pci_read_config8(dev, REVID);
/* The revision to stepping IDs have two values per metal stepping. */
if (attrs->revid >= RID_D_STEPPING_START) {

6
src/soc/intel/fsp_baytrail/spi.c
View File

@@ -254,11 +254,9 @@ static ich9_spi_regs *spi_regs(void)
uint32_t sbase;
#ifdef __SMM__
pci_devfn_t dev;
dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
#else
struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
#endif
pci_read_config_dword(dev, SBASE, &sbase);
sbase &= ~0x1ff;

2
src/soc/intel/fsp_broadwell_de/acpi.c
View File

@@ -81,7 +81,7 @@ static int acpi_sci_irq(void)
{
uint8_t actl = 0;
static uint8_t sci_irq = 0;
struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
/* If this function was already called, just return the stored value. */
if (sci_irq)

2
src/soc/intel/fsp_broadwell_de/ramstage.c
View File

@@ -62,7 +62,7 @@ static void fill_in_pattrs(void)
attrs->cpuid = cpuid_eax(1);
attrs->stepping = (attrs->cpuid & 0x0F) - 1;
dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
attrs->revid = pci_read_config8(dev, REVID);
attrs->microcode_patch = intel_microcode_find();
attrs->address_bits = cpuid_eax(0x80000008) & 0xff;

5
src/soc/intel/quark/acpi.c
View File

@@ -31,9 +31,8 @@ unsigned long acpi_fill_mcfg(unsigned long current)
void acpi_fill_in_fadt(acpi_fadt_t *fadt)
{
struct device *dev = dev_find_slot(0,
PCI_DEVFN(PCI_DEVICE_NUMBER_QNC_LPC,
PCI_FUNCTION_NUMBER_QNC_LPC));
struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC,
PCI_FUNCTION_NUMBER_QNC_LPC);
uint32_t gpe0_base = pci_read_config32(dev, R_QNC_LPC_GPE0BLK)
& B_QNC_LPC_GPE0BLK_MASK;
uint32_t pmbase = pci_read_config32(dev, R_QNC_LPC_PM1BLK)