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device: Use pcidev_on_root()

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Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki
2018-05-22 02:18:00 +03:00
committed by Felix Held
parent 54efaae701
commit c70eed1e62
170 changed files with 348 additions and 347 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/southbridge/amd/cimx/sb800/spi.c
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@@ -50,7 +50,7 @@ void spi_init()
{
struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));
dev = pcidev_on_root(0x14, 3);
spibar = pci_read_config32(dev, 0xA0) & ~0x1F;
}

4
src/southbridge/amd/rs780/cmn.c
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@@ -192,8 +192,8 @@ void set_pcie_enable_bits(struct device *dev, u32 reg_pos, u32 mask, u32 val)
void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
{
/* K8 Function1 is address map */
struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
struct device *k8_f1 = pcidev_on_root(0x18, 1);
struct device *k8_f0 = pcidev_on_root(0x18, 0);
if (in_out) {
u32 dword, sblk;

14
src/southbridge/amd/rs780/gfx.c
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@@ -175,7 +175,7 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
CIM_STATUS Status = CIM_UNSUPPORTED;
u8 Bus, Dev, Reg, BusStart, BusEnd;
u32 Value;
struct device *dev0x14 = dev_find_slot(0, PCI_DEVFN(0x14, 4));
struct device *dev0x14 = pcidev_on_root(0x14, 4);
struct device *tempdev;
Value = pci_read_config32(dev0x14, 0x18);
BusStart = (Value >> 8) & 0xFF;
@@ -235,7 +235,7 @@ static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
int i, j, n = 7;
struct device *k8_f1;
k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
k8_f1 = pcidev_on_root(0x18, 1);
for (i = 0; i < 8; i++) {
int k = 0, MmioReg;
@@ -787,7 +787,7 @@ static void rs780_internal_gfx_enable(struct device *dev)
/* LPC DMA Deadlock workaround? */
/* GFX_InitCommon*/
struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
struct device *k8_f0 = pcidev_on_root(0x18, 0);
l_dword = pci_read_config32(k8_f0, 0x68);
l_dword &= ~(3 << 21);
l_dword |= (1 << 21);
@@ -802,9 +802,9 @@ static void rs780_internal_gfx_enable(struct device *dev)
#if IS_ENABLED(CONFIG_GFXUMA)
/* GFX_InitUMA. */
/* Copy CPU DDR Controller to NB MC. */
struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
struct device *k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
struct device *k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4));
struct device *k8_f1 = pcidev_on_root(0x18, 1);
struct device *k8_f2 = pcidev_on_root(0x18, 2);
struct device *k8_f4 = pcidev_on_root(0x18, 4);
for (i = 0; i < 12; i++) {
l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
nbmc_write_index(nb_dev, 0x30 + i, l_dword);
@@ -1145,7 +1145,7 @@ static void dynamic_link_width_control(struct device *nb_dev, struct device *dev
while (reg32 & 0x100);
/* step 5.9.1.6 */
sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
sb_dev = pcidev_on_root(8, 0);
do {
reg32 = pci_ext_read_config32(nb_dev, sb_dev,
PCIE_VC0_RESOURCE_STATUS);

2
src/southbridge/amd/rs780/ht.c
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@@ -26,7 +26,7 @@ void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev)
struct device *cpu_f0;
u8 reg;
cpu_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
cpu_f0 = pcidev_on_root(0x18, 0);
set_nbcfg_enable_bits(cpu_f0, 0x68, 3 << 21, 1 << 21);
reg = nbpcie_p_read_index(sb_dev, 0x10);

4
src/southbridge/amd/rs780/rs780.c
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@@ -271,14 +271,14 @@ void rs780_enable(struct device *dev)
printk(BIOS_INFO, "rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
nb_dev = pcidev_on_root(0, 0);
if (!nb_dev) {
die("rs780_enable: CAN NOT FIND RS780 DEVICE, HALT!\n");
/* NOT REACHED */
}
/* sb_dev (dev 8) is a bridge that links to southbridge. */
sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
sb_dev = pcidev_on_root(8, 0);
if (!sb_dev) {
die("rs780_enable: CAN NOT FIND SB bridge, HALT!\n");
/* NOT REACHED */

2
src/southbridge/amd/sb700/ide.c
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@@ -56,7 +56,7 @@ static void ide_init(struct device *dev)
/* set ide as primary, if you want to boot from IDE, you'd better set it
* in $vendor/$mainboard/devicetree.cb */
if (conf->boot_switch_sata_ide == 1) {
struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
struct device *sm_dev = pcidev_on_root(0x14, 0);
byte = pci_read_config8(sm_dev, 0xad);
byte |= 1 << 4;
pci_write_config8(sm_dev, 0xad, byte);

2
src/southbridge/amd/sb700/lpc.c
View File

@@ -40,7 +40,7 @@ static void lpc_init(struct device *dev)
printk(BIOS_SPEW, "%s\n", __func__);
/* Enable the LPC Controller */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
sm_dev = pcidev_on_root(0x14, 0);
dword = pci_read_config32(sm_dev, 0x64);
dword |= 1 << 20;
pci_write_config32(sm_dev, 0x64, dword);

4
src/southbridge/amd/sb700/sata.c
View File

@@ -134,7 +134,7 @@ static void sata_init(struct device *dev)
struct device *sm_dev;
/* SATA SMBus Disable */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
sm_dev = pcidev_on_root(0x14, 0);
/* WARNING
* Enabling the SATA link latency enhancement (SMBUS 0xAD bit 5)
@@ -171,7 +171,7 @@ static void sata_init(struct device *dev)
struct device *ide_dev;
/* IDE Device */
ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
ide_dev = pcidev_on_root(0x14, 1);
/* Disable legacy IDE mode (enable PATA_BAR0/2) */
byte = pci_read_config8(ide_dev, 0x09);

2
src/southbridge/amd/sb700/spi.c
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@@ -31,7 +31,7 @@ static uint32_t get_spi_bar(void)
{
struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));
dev = pcidev_on_root(0x14, 3);
return pci_read_config32(dev, 0xa0) & ~0x1f;
}

4
src/southbridge/amd/sb700/usb.c
View File

@@ -35,7 +35,7 @@ static void usb_init(struct device *dev)
/* 6.1 Enable OHCI0-4 and EHCI Controllers */
struct device *sm_dev;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
sm_dev = pcidev_on_root(0x14, 0);
byte = pci_read_config8(sm_dev, 0x68);
byte |= 0xFF;
pci_write_config8(sm_dev, 0x68, byte);
@@ -88,7 +88,7 @@ static void usb_init2(struct device *dev)
if (get_option(&nvram, "ehci_async_data_cache") == CB_SUCCESS)
ehci_async_data_cache = !!nvram;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
sm_dev = pcidev_on_root(0x14, 0);
rev = get_sb700_revision(sm_dev);
/* dword = pci_read_config32(dev, 0xf8); */

2
src/southbridge/amd/sb800/lpc.c
View File

@@ -35,7 +35,7 @@ static void lpc_init(struct device *dev)
struct device *sm_dev;
/* Enable the LPC Controller */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
sm_dev = pcidev_on_root(0x14, 0);
dword = pci_read_config32(sm_dev, 0x64);
dword |= 1 << 20;
pci_write_config32(sm_dev, 0x64, dword);

2
src/southbridge/amd/sb800/sata.c
View File

@@ -88,7 +88,7 @@ static void sata_init(struct device *dev)
struct device *sm_dev;
/* SATA SMBus Disable */
/* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
sm_dev = pcidev_on_root(0x14, 0);
/* get rev_id */
rev_id = pci_read_config8(sm_dev, 0x08) - 0x2F;

2
src/southbridge/amd/sb800/usb.c
View File

@@ -57,7 +57,7 @@ static void usb_init2(struct device *dev)
void *usb2_bar0;
struct device *sm_dev;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
sm_dev = pcidev_on_root(0x14, 0);
//rev = get_sb800_revision(sm_dev);
/* dword = pci_read_config32(dev, 0xf8); */

4
src/southbridge/amd/sr5650/ht.c
View File

@@ -187,8 +187,8 @@ static void sr5690_set_resources(struct device *dev)
printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);
/* Find requisite AMD CPU devices */
amd_ht_cfg_dev = dev_find_slot(0, PCI_DEVFN(0x18, 0));
amd_addr_map_dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
amd_ht_cfg_dev = pcidev_on_root(0x18, 0);
amd_addr_map_dev = pcidev_on_root(0x18, 1);
if (!amd_ht_cfg_dev || !amd_addr_map_dev) {
printk(BIOS_WARNING, "%s: %s Unable to locate CPU control devices\n", __func__, dev_path(dev));

2
src/southbridge/amd/sr5650/pcie.c
View File

@@ -843,7 +843,7 @@ static void lock_hwinitreg(struct device *nb_dev)
*/
void sr56x0_lock_hwinitreg(void)
{
struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *nb_dev = pcidev_on_root(0, 0);
/* Lock HWInit Register */
lock_hwinitreg(nb_dev);

14
src/southbridge/amd/sr5650/sr5650.c
View File

@@ -129,8 +129,8 @@ void l1cfg_ind_write_index(struct device *nb_dev, uint32_t index, uint32_t data)
void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
{
/* K8 Function1 is address map */
struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
struct device *k8_f1 = pcidev_on_root(0x18, 1);
struct device *k8_f0 = pcidev_on_root(0x18, 0);
if (in_out) {
u32 dword, sblk;
@@ -331,7 +331,7 @@ void detect_and_enable_iommu(struct device *iommu_dev) {
if (iommu) {
printk(BIOS_DEBUG, "Initializing IOMMU\n");
struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *nb_dev = pcidev_on_root(0, 0);
if (!nb_dev) {
printk(BIOS_WARNING, "Unable to find SR5690 device! IOMMU NOT initialized\n");
@@ -616,7 +616,7 @@ void sr5650_enable(struct device *dev)
struct southbridge_amd_sr5650_config *cfg;
printk(BIOS_INFO, "sr5650_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
nb_dev = pcidev_on_root(0, 0);
if (!nb_dev) {
die("sr5650_enable: CAN NOT FIND SR5650 DEVICE, HALT!\n");
/* NOT REACHED */
@@ -624,7 +624,7 @@ void sr5650_enable(struct device *dev)
cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
/* sb_dev (dev 8) is a bridge that links to southbridge. */
sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
sb_dev = pcidev_on_root(8, 0);
if (!sb_dev) {
die("sr5650_enable: CAN NOT FIND SB bridge, HALT!\n");
/* NOT REACHED */
@@ -823,14 +823,14 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
{
uint8_t *p;
struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
struct device *nb_dev = pcidev_on_root(0, 0);
if (!nb_dev) {
printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 "
"device! IVRS table not generated...\n");
return (unsigned long)ivrs;
}
struct device *iommu_dev = dev_find_slot(0, PCI_DEVFN(0, 2));
struct device *iommu_dev = pcidev_on_root(0, 2);
if (!iommu_dev) {
printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 "
"IOMMU device! IVRS table not generated...\n");