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The GPIOs used for UART2 RX and TX were reversed.

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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones
2007-06-19 22:07:16 +00:00
committed by Uwe Hermann
parent cbb8d8ad24
commit c72ff11281
1 changed files with 10 additions and 10 deletions
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20
src/southbridge/amd/cs5536/cs5536.c
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@@ -356,19 +356,19 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb)
msr.lo |= sb->com2_irq << 28; msr.lo |= sb->com2_irq << 28;
wrmsr(MDD_IRQM_YHIGH, msr); wrmsr(MDD_IRQM_YHIGH, msr);
/* GPIO3 - UART2_RX */ /* GPIO4 - UART2_RX */
/* Set: Output Enable (0x4) */ /* Set: Output Enable (0x4) */
outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
/* Set: OUTAUX1 Select (0x10) */ /* Set: OUTAUX1 Select (0x10) */
outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
/* GPIO4 - UART2_TX */ /* GPIO3 - UART2_TX */
/* Set: Input Enable (0x20) */ /* Set: Input Enable (0x20) */
outl(GPIOL_4_SET, gpio_addr + GPIOL_INPUT_ENABLE); outl(GPIOL_3_SET, gpio_addr + GPIOL_INPUT_ENABLE);
/* Set: INAUX1 Select (0x34) */ /* Set: INAUX1 Select (0x34) */
outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT); outl(GPIOL_3_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
/* Set: GPIO 3 + 3 Pull Up (0x18) */ /* Set: GPIO 3 and 4 Pull Up (0x18) */
outl(GPIOL_3_SET | GPIOL_4_SET, outl(GPIOL_3_SET | GPIOL_4_SET,
gpio_addr + GPIOL_PULLUP_ENABLE); gpio_addr + GPIOL_PULLUP_ENABLE);