mb/hp/snb_ivb_laptops: Add HP EliteBook 2170p as 2570p variant

Most of the code is taken from 2570p, adjusted with autoport, SuperIO
from 8470p and inteltool, GPIO config from inteltool via autoport.

The laptop works well under coreboot with SeaBIOS 1.16.1 payload,
running Debian GNU/Linux with kernel 6.1.15.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I854104516d5b6fbd78ee2989197000a7dbb85136
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73856
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Documentation/mainboard/hp/2170p.md

@@ -0,0 +1,91 @@
+# HP EliteBook 2170p
+
+This page is about the notebook [HP EliteBook 2170p].
+
+## Release status
+
+HP EliteBook 2170p was released in 2012 and is now end of life.
+It can be bought from a secondhand market like Taobao or eBay.
+
+## Required proprietary blobs
+
+The following blobs are required to operate the hardware:
+1. EC firmware
+2. Intel ME firmware
+
+EC firmware can be retrieved from the HP firmware update image, or the firmware
+backup of the laptop. EC Firmware is part of the coreboot build process.
+The guide on extracting EC firmware and using it to build coreboot is in
+document [HP Laptops with KBC1126 Embedded Controller](hp_kbc1126_laptops).
+
+Intel ME firmware is in the flash chip. It is not needed when building coreboot.
+
+## Programming
+
+The flash chip is located between the memory slots, WWAN card and CPU,
+covered by the base enclosure, which needs to be removed according to
+the [Maintenance and Service Guide] to access the flash chip. Unlike
+other variants, the flash chip on 2170p is socketed, so it can be taken
+off and operated with an external programmer.
+
+Pin 1 of the flash chip is at the side near the CPU.
+
+![Flash Chip in 2170p](2170p_flash.jpg)
+
+For more details have a look at the general [flashing tutorial].
+
+## Debugging
+
+The board can be debugged with serial port on the dock or EHCI debug.
+The EHCI debug port is the left USB3 port.
+
+## Test status
+
+### Known issues
+
+- GRUB payload freezes if at_keyboard module is in the GRUB image
+  ([bug #141])
+
+### Untested
+
+- Fingerprint Reader
+- Dock: Parallel port, PS/2 mouse, S-Video port
+
+### Working
+
+- Integrated graphics init with libgfxinit
+- SATA
+- Audio: speaker and microphone
+- Ethernet
+- WLAN
+- WWAN
+- Bluetooth
+- SD Card Reader
+- SmartCard Reader
+- USB
+- DisplayPort
+- Keyboard, touchpad and trackpoint
+- EC ACPI support and thermal control
+- Dock: all USB ports, DVI-D, Serial debug, PS/2 keyboard
+- TPM
+- Internal flashing when IFD is unlocked
+- Using `me_cleaner`
+
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU              | Intel Sandy/Ivy Bridge (FCPGA988)                |
++------------------+--------------------------------------------------+
+| PCH              | Intel Panther Point QM77                         |
++------------------+--------------------------------------------------+
+| EC               | SMSC KBC1126                                     |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+[HP EliteBook 2170p]: https://support.hp.com/us-en/product/hp-elitebook-2170p-notebook-pc/5245427
+[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c03387961.pdf
+[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md

Documentation/mainboard/index.md

@@ -78,6 +78,7 @@ The boards in this section are not real mainboards, but emulators.
 
 - [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md)
 - [HP Sure Start](hp/hp_sure_start.md)
+- [EliteBook 2170p](hp/2170p.md)
 - [EliteBook 2560p](hp/2560p.md)
 - [EliteBook 8760w](hp/8760w.md)
 - [EliteBook Folio 9480m](hp/folio_9480m.md)

src/mainboard/hp/snb_ivb_laptops/Kconfig

@@ -15,6 +15,16 @@ config BOARD_HP_SNB_IVB_LAPTOPS_COMMON
 	select SYSTEM_TYPE_LAPTOP
 	select USE_NATIVE_RAMINIT
 
+config BOARD_HP_2170P
+	select BOARD_HP_SNB_IVB_LAPTOPS_COMMON
+	select BOARD_ROMSIZE_KB_16384
+	select GFX_GMA_PANEL_1_ON_LVDS
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_INT15
+	select MAINBOARD_HAS_LIBGFXINIT
+	select SOUTHBRIDGE_INTEL_C216
+	select SUPERIO_SMSC_LPC47N217
+
 config BOARD_HP_2560P
 	select BOARD_HP_SNB_IVB_LAPTOPS_COMMON
 	select BOARD_ROMSIZE_KB_8192
@@ -101,6 +111,7 @@ config MAINBOARD_DIR
 	default "hp/snb_ivb_laptops"
 
 config VARIANT_DIR
+	default "2170p"          if BOARD_HP_2170P
 	default "2560p"          if BOARD_HP_2560P
 	default "2570p"          if BOARD_HP_2570P
 	default "2760p"          if BOARD_HP_2760P
@@ -112,6 +123,7 @@ config VARIANT_DIR
 	default "revolve_810_g1" if BOARD_HP_REVOLVE_810_G1
 
 config MAINBOARD_PART_NUMBER
+	default "EliteBook 2170p"          if BOARD_HP_2170P
 	default "EliteBook 2560p"          if BOARD_HP_2560P
 	default "EliteBook 2570p"          if BOARD_HP_2570P
 	default "EliteBook 2760p"          if BOARD_HP_2760P
@@ -132,7 +144,7 @@ config VGA_BIOS_ID
 
 config USBDEBUG_HCD_INDEX
 	int
-	default 0 if BOARD_HP_FOLIO_9470M
+	default 0 if BOARD_HP_2170P || BOARD_HP_FOLIO_9470M
 	default 1 if BOARD_HP_2560P || BOARD_HP_2760P || BOARD_HP_8460P
 	default 2 if BOARD_HP_2570P || BOARD_HP_8470P || BOARD_HP_8770W
 	default 1 if BOARD_HP_PROBOOK_6360B # FIXME: check this

src/mainboard/hp/snb_ivb_laptops/Kconfig.name

@@ -1,5 +1,8 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+config BOARD_HP_2170P
+	bool "EliteBook 2170p"
+
 config BOARD_HP_2560P
 	bool "EliteBook 2560p"
 

src/mainboard/hp/snb_ivb_laptops/variants/2170p/board_info.txt

@@ -0,0 +1,7 @@
+Category: laptop
+Board URL: https://support.hp.com/us-en/product/hp-elitebook-2170p-notebook-pc/5245427
+ROM protocol: SPI
+ROM package: SOIC-8
+ROM socketed: y
+Flashrom support: n
+Release year: 2012

src/mainboard/hp/snb_ivb_laptops/variants/2170p/early_init.c

@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/smsc/lpc47n217/lpc47n217.h>
+#include <ec/hp/kbc1126/ec.h>
+
+#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 1, 0 }, /* SSP1: dock */
+	{ 1, 1, 0 }, /* SSP2: left, EHCI Debug */
+	{ 0, 1, 1 }, /* SSP3 */
+	{ 1, 1, 1 }, /* SSP4: right */
+	{ 0, 0, 2 }, /* B0P5 */
+	{ 0, 0, 2 }, /* B0P6 */
+	{ 0, 0, 3 }, /* B0P7 */
+	{ 1, 0, 3 }, /* B0P8: smart card reader */
+	{ 1, 0, 4 }, /* B1P1: fingerprint reader */
+	{ 1, 0, 4 }, /* B1P2: (EHCI Debug) wlan usb */
+	{ 1, 1, 5 }, /* B1P3: Camera */
+	{ 1, 0, 5 }, /* B1P4 */
+	{ 1, 0, 6 }, /* B1P5: wwan USB */
+	{ 0, 0, 6 }, /* B1P6 */
+};
+
+void bootblock_mainboard_early_init(void)
+{
+	lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	kbc1126_enter_conf();
+	kbc1126_mailbox_init();
+	kbc1126_kbc_init();
+	kbc1126_ec_init();
+	kbc1126_pm1_init();
+	kbc1126_exit_conf();
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+}

src/mainboard/hp/snb_ivb_laptops/variants/2170p/gma-mainboard.ads

@@ -0,0 +1,22 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP1,
+      DP2,
+      DP3,
+      HDMI1,
+      HDMI2,
+      HDMI3,
+      Analog,
+      LVDS,
+      others => Disabled);
+
+end GMA.Mainboard;

src/mainboard/hp/snb_ivb_laptops/variants/2170p/gpio.c

@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_GPIO,
+	.gpio11 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_GPIO,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_GPIO,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_OUTPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_OUTPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio10 = GPIO_DIR_INPUT,
+	.gpio11 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_OUTPUT,
+	.gpio18 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_OUTPUT,
+	.gpio23 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_OUTPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio0 = GPIO_LEVEL_LOW,
+	.gpio2 = GPIO_LEVEL_HIGH,
+	.gpio8 = GPIO_LEVEL_LOW,
+	.gpio11 = GPIO_LEVEL_LOW,
+	.gpio17 = GPIO_LEVEL_HIGH,
+	.gpio22 = GPIO_LEVEL_HIGH,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio27 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio24 = GPIO_RESET_RSMRST,
+	.gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio1 = GPIO_INVERT,
+	.gpio3 = GPIO_INVERT,
+	.gpio6 = GPIO_INVERT,
+	.gpio7 = GPIO_INVERT,
+	.gpio10 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_GPIO,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_GPIO,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_GPIO,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_GPIO,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio36 = GPIO_DIR_OUTPUT,
+	.gpio37 = GPIO_DIR_OUTPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio44 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_OUTPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_OUTPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_OUTPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+	.gpio61 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio33 = GPIO_LEVEL_LOW,
+	.gpio35 = GPIO_LEVEL_LOW,
+	.gpio36 = GPIO_LEVEL_LOW,
+	.gpio37 = GPIO_LEVEL_LOW,
+	.gpio46 = GPIO_LEVEL_LOW,
+	.gpio49 = GPIO_LEVEL_LOW,
+	.gpio53 = GPIO_LEVEL_HIGH,
+	.gpio57 = GPIO_LEVEL_HIGH,
+	.gpio60 = GPIO_LEVEL_HIGH,
+	.gpio61 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_GPIO,
+	.gpio74 = GPIO_MODE_GPIO,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_OUTPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_OUTPUT,
+	.gpio71 = GPIO_DIR_OUTPUT,
+	.gpio72 = GPIO_DIR_OUTPUT,
+	.gpio73 = GPIO_DIR_OUTPUT,
+	.gpio74 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio68 = GPIO_LEVEL_HIGH,
+	.gpio70 = GPIO_LEVEL_HIGH,
+	.gpio71 = GPIO_LEVEL_HIGH,
+	.gpio72 = GPIO_LEVEL_LOW,
+	.gpio73 = GPIO_LEVEL_HIGH,
+	.gpio74 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};

src/mainboard/hp/snb_ivb_laptops/variants/2170p/hda_verb.c

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x111d7605,	/* Codec Vendor / Device ID: IDT */
+	0x103c1815,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x103c1815),
+	AZALIA_PIN_CFG(0, 0x0a, 0x21011030),
+	AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x0c, 0x03a11020),
+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0),
+	AZALIA_PIN_CFG(0, 0x0f, 0x2181102e),
+	AZALIA_PIN_CFG(0, 0x10, 0x40f000f0),
+	AZALIA_PIN_CFG(0, 0x11, 0xd5a30140),
+	AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0),
+	AZALIA_PIN_CFG(0, 0x20, 0x40f000f0),
+
+	0x80862806,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb

@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	register "gpu_cpu_backlight" = "0x0000040e"
+	register "gpu_panel_power_backlight_off_delay" = "2000"
+	register "gpu_pch_backlight" = "0x0d9c0d9c"
+	device domain 0 on
+		subsystemid 0x103c 0x1815 inherit
+
+		device pci 01.0 off end	# PCIe Bridge for discrete graphics
+		device pci 02.0 on  end	# Internal graphics
+
+		chip southbridge/intel/bd82x6x	# Intel Series 7 Panther Point PCH
+			# mailbox at 0x200/0x201 and PM1 at 0x220
+			register "gen1_dec" = "0x007c0201"
+			register "gen2_dec" = "0x000c0101"
+			register "gen3_dec" = "0x00fcfe01"
+			register "gen4_dec" = "0x000402e9"
+			register "gpi6_routing" = "2"
+			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
+			# HDD(0), ODD(1), mSATA(2), eSATA(4)
+			register "sata_port_map" = "0x3f"
+			register "superspeed_capable_ports" = "0x0000000f"
+			register "xhci_overcurrent_mapping" = "0x00000c03"
+			register "xhci_switchable_ports"    = "0x0000000f"
+
+			device pci 14.0 on  end	# USB 3.0 Controller
+			device pci 16.0 on  end	# Management Engine KT
+			device pci 1c.0 on  end	# PCIe Port #1
+			device pci 1c.1 off end	# PCIe Port #2
+			device pci 1c.2 on  end	# PCIe Port #3, SD/MMC
+			device pci 1c.3 on  end	# PCIe Port #4, WLAN
+			device pci 1c.4 off end	# PCIe Port #5
+			device pci 1c.5 off end	# PCIe Port #6
+			device pci 1c.6 off end	# PCIe Port #7
+			device pci 1c.7 off end	# PCIe Port #8
+			device pci 1f.0 on	# LPC bridge
+				chip ec/hp/kbc1126
+					register "ec_data_port" = "0x62"
+					register "ec_cmd_port"  = "0x66"
+					register "ec_ctrl_reg"  = "0x81"
+					register "ec_fan_ctrl_value" = "0x70"
+					device pnp ff.1 off end
+				end
+				chip superio/smsc/lpc47n217
+					device pnp 4e.3 on	# Parallel
+						io  0x60 = 0x378
+						irq 0x70 = 7
+					end
+					device pnp 4e.4 on	# COM1
+						io  0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 4e.5 off end	# COM2
+				end
+			end
+		end
+	end
+end