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src/soc/intel/common: Configure the gspi chip select state correctly

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This implementation updates the chip select control register
programming in gspi controller setup call to program the correct
bit fields for chip select state.

Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920a53
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/27889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aamir Bohra
2018-08-07 12:16:09 +05:30
committed by Subrata Banik
parent 94e2ec7253
commit c7b23e9dc8
1 changed files with 1 additions and 4 deletions
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5
src/soc/intel/common/block/gspi/gspi.c
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@@ -481,12 +481,9 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev)
cs_ctrl = CS_MODE_SW | CS_0;
pol = gspi_csctrl_polarity(cfg.cs_polarity);
cs_ctrl |= pol << CS_0_POL_SHIFT;
cs_ctrl |= gspi_csctrl_state(pol, CS_DEASSERT);
cs_ctrl |= gspi_csctrl_state(pol, CS_DEASSERT) << CS_STATE_SHIFT;
gspi_write_mmio_reg(p, SPI_CS_CONTROL, cs_ctrl);
/* De-assert chip select. */
__gspi_cs_change(p, CS_DEASSERT);
/* Disable SPI controller. */
gspi_write_mmio_reg(p, SSCR0, SSCR0_SSE_DISABLE);