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soc/intel/{alderlake,meteorlake}: Remove the dummy PS0 and PS3 methods

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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8515407eb10e1a74f37ea5a80fa31533c38badec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77455
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes
2023-08-25 13:53:10 +01:00
committed by Felix Held
parent 2e10a6d6f3
commit c7cd4a6334
1 changed files with 0 additions and 7 deletions
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7
src/soc/intel/tigerlake/acpi/tcss_dma.asl
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@@ -96,13 +96,6 @@ Method (D3CE, 0, Serialized)
* TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0. * TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0.
*/ */
Name (SD3C, 0) Name (SD3C, 0)
Method (_PS0, 0, Serialized)
{
}
Method (_PS3, 0, Serialized)
{
}
Method (_DSW, 3) Method (_DSW, 3)
{ {