soc/intel/common/opregion: Get rid of opregion.c

Get rid of custom opregion implementation and use drivers/intel/gma/opregion
implementation instead.

Test: boot Windows 10 on google/chell and google/edgar using Tianocore
payload with GOP init, observe Intel graphics driver loaded and functional.

Change-Id: I5f78e9030df12da5369d142dda5c59e576ebcef7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21703
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph
2017-09-26 19:34:35 +02:00
committed by Martin Roth
parent 0bcd86a14a
commit c7edf18f7c
13 changed files with 15 additions and 203 deletions

View File

@@ -94,7 +94,6 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SPI
select SOC_INTEL_COMMON_BLOCK_CSE
select SOC_INTEL_COMMON_GFX_OPREGION
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
@@ -106,6 +105,8 @@ config CPU_SPECIFIC_OPTIONS
select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
select HAVE_FSP_GOP
select NO_UART_ON_SUPERIO
select INTEL_GMA_ACPI
select INTEL_GMA_SWSMISCI
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC

View File

@@ -21,7 +21,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <intelblocks/graphics.h>
#include <soc/intel/common/opregion.h>
#include <drivers/intel/gma/opregion.h>
uintptr_t fsp_soc_get_igd_bar(void)
{
@@ -32,45 +32,15 @@ uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
uintptr_t current, struct acpi_rsdp *rsdp)
{
igd_opregion_t *opregion;
uint16_t reg16;
printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
opregion = (igd_opregion_t *)current;
if (init_igd_opregion(opregion) != CB_SUCCESS)
if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
return current;
/* FIXME: Add platform specific mailbox initialization */
current += sizeof(igd_opregion_t);
opregion->mailbox1.clid = 1;
/* TODO Initialize Mailbox 3 */
opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */
opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
/*
* TODO This needs to happen in S3 resume, too.
* Maybe it should move to the finalize handler.
*/
pci_write_config32(device, ASLS, (uintptr_t)opregion);
reg16 = pci_read_config16(device, SWSCI);
reg16 &= ~(1 << 0);
reg16 |= (1 << 15);
pci_write_config16(device, SWSCI, reg16);
return acpi_align_current(current);
}