mb/google/brya: Add PEG and initial Nvidia dGPU ASL support
Some brya variants will use a GN20 series Nvidia GPU, which requires quite a bit of ACPI support code to be written for it. This patch lands a decent bit of the initial code for it on the brya platform, including: 1) PEG RTD3 methods 2) DGPU power operations (RTD3 and GCOFF, NVJT _DSM and other Methods) 3) NVOP _DSM method There will be more support to come later, this is all written to specifications from the Nvidia Software Design Guide for GN20. BUG=b:214581763 TEST=build patch train Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ifce1610210e9636e87dda4b55c8287334adfcc42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Tim Wawrzynczak
297
src/mainboard/google/brya/acpi/power.asl
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297
src/mainboard/google/brya/acpi/power.asl
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* Voltage rail control signals */
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#define GPIO_1V8_PWR_EN GPP_E18
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#define GPIO_1V8_PG GPP_E20
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#define GPIO_NV33_PWR_EN GPP_A21
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#define GPIO_NV33_PG GPP_A22
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#define GPIO_NVVDD_PWR_EN GPP_E0
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#define GPIO_NVVDD_PG GPP_E16
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#define GPIO_PEXVDD_PWR_EN GPP_E10
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#define GPIO_PEXVDD_PG GPP_E17
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#define GPIO_FBVDD_PWR_EN GPP_A17
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#define GPIO_FBVDD_PG GPP_E4
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#define GPIO_GPU_PERST_L GPP_B3
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#define GPIO_GPU_ALLRAILS_PG GPP_E5
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#define GPIO_GPU_NVVDD_EN GPP_A19
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#define GC6_DEFER_TYPE_EXIT_GC6 3
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/* Optimus Power Control State */
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Name (OPCS, OPTIMUS_POWER_CONTROL_DISABLE)
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/* PCI configuration space Owner */
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Name (PCIO, PCI_OWNER_SBIOS)
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/* Saved PCI configuration space memory (VGA Buffer) */
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Name (VGAB, Buffer (0xfb) { 0x00 })
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/* Deferred GPU State */
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Name (OPS0, OPTIMUS_CONTROL_NO_RUN_PS0)
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/* GC6 Entry/Exit state */
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Name (GC6E, GC6_STATE_EXITED)
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/* Defer GC6 entry / exit until D3-cold request */
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Name (DFEN, 0)
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/* Deferred GC6 Enter control */
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Name (DFCI, 0)
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/* Deferred GC6 Exit control */
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Name (DFCO, 0)
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/* "GC6 In", i.e. GC6 Entry Sequence */
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Method (GC6I, 0, Serialized)
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{
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GC6E = GC6_STATE_TRANSITION
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/* Put PCIe link into L2/3 */
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\_SB.PCI0.PEG0.DL23 ()
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/* Assert GPU_PERST_L */
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\_SB.PCI0.STXS (GPIO_GPU_PERST_L)
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/* Deassert PG_GPU_ALLRAILS */
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\_SB.PCI0.CTXS (GPIO_GPU_ALLRAILS_PG)
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/* Deassert EN_PP0950_GPU_X */
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\_SB.PCI0.CTXS (GPIO_PEXVDD_PWR_EN)
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/* Wait for de-assertion of PG_PP0950_GPU */
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GPPL (GPIO_PEXVDD_PG, 0, 20)
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/* Deassert EN_PPVAR_GPU_NVVDD */
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\_SB.PCI0.CTXS (GPIO_NVVDD_PWR_EN)
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/* Wait for de-assertion of PG_PPVAR_GPU_NVVDD */
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GPPL (GPIO_NVVDD_PG, 0, 20)
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/* Deassert EN_PCH_PPVAR_GPU_FBVDDQ */
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\_SB.PCI0.CTXS (GPIO_FBVDD_PWR_EN)
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/* Deassert EN_PP3300_GPU */
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\_SB.PCI0.CTXS (GPIO_NV33_PWR_EN)
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/* Wait for de-assertion of PG_PP3300_GPU */
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GPPL (GPIO_NV33_PG, 0, 20)
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GC6E = GC6_STATE_ENTERED
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}
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/* "GC6 Out", i.e. GC6 Exit Sequence */
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Method (GC6O, 0, Serialized)
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{
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GC6E = GC6_STATE_TRANSITION
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/* Assert EN_PP3300_GPU */
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\_SB.PCI0.STXS (GPIO_NV33_PWR_EN)
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/* Wait for assertion of PG_PP3300_GPU */
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GPPL (GPIO_NV33_PG, 1, 20)
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/* Deassert GPU_PERST_L */
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\_SB.PCI0.CTXS (GPIO_GPU_PERST_L)
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/* Put PCIe link into L0 state */
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\_SB.PCI0.PEG0.LD23 ()
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/* Wait for GPU to assert GPU_NVVDD_EN */
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GPPL (GPIO_GPU_NVVDD_EN, 1, 20)
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/*
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* There is a 4ms window once the GPU asserts GPU_NVVDD_EN to
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* perform the following:
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* 1. Enable GPU_NVVDD
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* 2. Enable GPU_PEX
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* 3. Wait for all PG
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* 4. Assert FBVDD
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* At the end of the 4ms window, the GPU will deassert its
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* GPIO1_GC6_FB_EN signal that is used to keep the FBVDD
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* rail up during GC6.
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*/
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\_SB.PCI0.STXS (GPIO_NVVDD_PWR_EN)
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Stall (20)
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\_SB.PCI0.STXS (GPIO_PEXVDD_PWR_EN)
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GPPL (GPIO_NVVDD_PG, 1, 4)
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GPPL (GPIO_PEXVDD_PG, 1, 4)
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\_SB.PCI0.STXS (GPIO_FBVDD_PWR_EN)
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/* Assert PG_GPU_ALLRAILS */
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\_SB.PCI0.STXS (GPIO_GPU_ALLRAILS_PG)
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GC6E = GC6_STATE_EXITED
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}
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/* GCOFF exit sequence */
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Method (PGON, 0, Serialized)
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{
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/* Assert PERST# */
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\_SB.PCI0.CTXS (GPIO_GPU_PERST_L)
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/* Ramp up 1.8V rail */
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\_SB.PCI0.STXS (GPIO_1V8_PWR_EN)
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GPPL (GPIO_1V8_PG, 1, 20)
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/* Ramp up NV33 rail */
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\_SB.PCI0.STXS (GPIO_NV33_PWR_EN)
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GPPL (GPIO_NV33_PG, 1, 20)
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/* Ramp up NVVDD rail */
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\_SB.PCI0.STXS (GPIO_NVVDD_PWR_EN)
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GPPL (GPIO_NVVDD_PG, 1, 5)
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/* Ramp up PEXVDD rail */
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\_SB.PCI0.STXS (GPIO_PEXVDD_PWR_EN)
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GPPL (GPIO_PEXVDD_PG, 1, 5)
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/* Ramp up FBVDD rail */
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\_SB.PCI0.STXS (GPIO_FBVDD_PWR_EN)
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GPPL (GPIO_FBVDD_PG, 1, 5)
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/* All rails are good */
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\_SB.PCI0.STXS (GPIO_GPU_ALLRAILS_PG)
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Sleep (1)
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/* Deassert PERST# */
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\_SB.PCI0.STXS (GPIO_GPU_PERST_L)
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}
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/* GCOFF entry sequence */
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Method (PGOF, 0, Serialized)
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{
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/* Assert PERST# */
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\_SB.PCI0.CTXS (GPIO_GPU_PERST_L)
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Sleep (5)
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/* All rails are about to go down */
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\_SB.PCI0.CTXS (GPIO_GPU_ALLRAILS_PG)
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/* Ramp down FBVDD */
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\_SB.PCI0.CTXS (GPIO_FBVDD_PWR_EN)
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GPPL (GPIO_FBVDD_PG, 0, 20)
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/* Ramp down PEXVDD */
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\_SB.PCI0.CTXS (GPIO_PEXVDD_PWR_EN)
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GPPL (GPIO_PEXVDD_PG, 0, 20)
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/* Ramp down NVVDD */
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\_SB.PCI0.CTXS (GPIO_NVVDD_PWR_EN)
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GPPL (GPIO_NVVDD_PG, 0, 20)
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/* Ramp down NV33 */
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\_SB.PCI0.CTXS (GPIO_NV33_PWR_EN)
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GPPL (GPIO_NV33_PG, 0, 20)
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/* Ramp down 1.8V */
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\_SB.PCI0.CTXS (GPIO_1V8_PWR_EN)
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GPPL (GPIO_1V8_PG, 0, 20)
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}
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/* Handle deferred GC6 vs. poweron request */
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Method (NPON, 0, Serialized)
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{
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If (DFEN == GC6_DEFER_ENABLE) /* 1 */
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{
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If (DFCO == GC6_DEFER_TYPE_EXIT_GC6) /* 3 */
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{
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GC6O ()
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}
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DFEN = GC6_DEFER_DISABLE
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}
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Else
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{
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PGON ()
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}
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}
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/* Handle deferred GC6 vs. poweroff request */
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Method (NPOF, 0, Serialized)
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{
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If (DFEN == GC6_DEFER_ENABLE)
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{
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/* Deferred GC6 entry */
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If (DFCI == NVJT_GPC_EGNS || DFCI == NVJT_GPC_EGIS)
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{
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GC6I ()
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}
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DFEN = GC6_DEFER_DISABLE
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}
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Else
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{
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PGOF ()
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}
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}
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Method (_ON, 0, Serialized)
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{
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PGON ()
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}
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Method (_OFF, 0, Serialized)
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{
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PGOF ()
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}
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/* Put device into D0 */
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Method (_PS0, 0, NotSerialized)
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{
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If (OPS0 == OPTIMUS_CONTROL_RUN_PS0)
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{
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/* Restore PCI config space */
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If (PCIO == PCI_OWNER_SBIOS)
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{
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VGAR = VGAB
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}
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/* Poweron or deferred GC6 exit */
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NPON ()
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OPS0 = OPTIMUS_CONTROL_NO_RUN_PS0
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}
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}
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/* Put device into D3 */
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Method (_PS3, 0, NotSerialized)
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{
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If (OPCS == OPTIMUS_POWER_CONTROL_ENABLE)
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{
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/* Save PCI config space to ACPI buffer */
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If (PCIO == PCI_OWNER_SBIOS)
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{
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VGAB = VGAR
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}
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/* Poweroff or deferred GC6 entry */
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NPOF ()
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/* Because _PS3 ran _OFF, _PS0 must run _ON */
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OPS0 = OPTIMUS_CONTROL_RUN_PS0
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/* OPCS is one-shot, so reset it */
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OPCS = OPTIMUS_POWER_CONTROL_DISABLE
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}
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}
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/*
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* Normally, _ON and _OFF of the power resources listed in _PRx will be
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* evaluated before entering D0/D3. However, for Optimus, the package
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* should refer to the PCIe controller itself, not a dependent device.
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*/
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Name (_PR0, Package() { \_SB.PCI0.PEG0 })
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Name (_PR3, Package() { \_SB.PCI0.PEG0 })
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Method (_STA, 0, Serialized)
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{
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If (GC6E == GC6_STATE_EXITED &&
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\_SB.PCI0.GTXS(GPIO_GPU_ALLRAILS_PG) == 1)
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{
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Return (0xF)
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}
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Else
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{
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Return (0)
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}
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}
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