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mb/**/cmos.layout: Indent everything with tabs

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Time has shown that using spaces never converges into proper alignment.

Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This commit is contained in:
Angel Pons
2020-11-03 00:29:39 +01:00
parent 2c0aa00d6e
commit c85cce077c
114 changed files with 4733 additions and 4733 deletions
Download Patch File Download Diff File Expand all files Collapse all files

56
src/mainboard/intel/baskingridge/cmos.layout
View File

@@ -4,54 +4,54 @@
entries
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
395 4 e 6 debug_level
# coreboot config options: cpu
400 1 e 2 hyper_threading
400 1 e 2 hyper_threading
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
416 128 r 0 vbnv
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
# -----------------------------------------------------------------
checksums

72
src/mainboard/intel/d510mo/cmos.layout
View File

@@ -4,64 +4,64 @@
entries
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
395 4 e 6 debug_level
#400 8 r 0 reserved for century byte
#400 8 r 0 reserved for century byte
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
# coreboot config options: bootloader
416 512 s 0 boot_devices
416 512 s 0 boot_devices
# coreboot config options: cpu
# coreboot config options: northbridge
952 3 e 11 gfx_uma_size
952 3 e 11 gfx_uma_size
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
11 0 8M
11 1 16M
11 2 32M
11 3 48M
11 4 64M
11 5 128M
11 6 256M
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
11 0 8M
11 1 16M
11 2 32M
11 3 48M
11 4 64M
11 5 128M
11 6 256M
# -----------------------------------------------------------------
checksums

80
src/mainboard/intel/d945gclf/cmos.layout
View File

@@ -4,69 +4,69 @@
entries
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
395 4 e 6 debug_level
# coreboot config options: cpu
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
# coreboot config options: northbridge
411 3 e 11 gfx_uma_size
411 3 e 11 gfx_uma_size
# coreboot config options: bootloader
416 512 s 0 boot_devices
416 512 s 0 boot_devices
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
1048 4 r 0 C0DRT1
1052 4 r 0 C1DRT1
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
1048 4 r 0 C0DRT1
1052 4 r 0 C1DRT1
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
11 0 1M
11 1 4M
11 2 8M
11 3 16M
11 4 32M
11 5 48M
11 6 64M
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
11 0 1M
11 1 4M
11 2 8M
11 3 16M
11 4 32M
11 5 48M
11 6 64M
# -----------------------------------------------------------------
checksums

68
src/mainboard/intel/dg41wv/cmos.layout
View File

@@ -4,59 +4,59 @@
entries
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
395 4 e 6 debug_level
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
# coreboot config options: cpu
# coreboot config options: northbridge
432 4 e 11 gfx_uma_size
432 4 e 11 gfx_uma_size
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 1 Emergency
6 2 Alert
6 3 Critical
6 4 Error
6 5 Warning
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Disable
7 1 Enable
7 2 Keep
11 6 64M
11 7 128M
11 8 256M
11 9 96M
11 10 160M
11 11 224M
11 12 352M
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 1 Emergency
6 2 Alert
6 3 Critical
6 4 Error
6 5 Warning
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Disable
7 1 Enable
7 2 Keep
11 6 64M
11 7 128M
11 8 256M
11 9 96M
11 10 160M
11 11 224M
11 12 352M
# -----------------------------------------------------------------
checksums

84
src/mainboard/intel/dg43gt/cmos.layout
View File

@@ -4,67 +4,67 @@
entries
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
395 4 e 6 debug_level
# coreboot config options: southbridge
408 1 e 10 sata_mode
409 2 e 7 power_on_after_fail
411 1 e 1 nmi
408 1 e 10 sata_mode
409 2 e 7 power_on_after_fail
411 1 e 1 nmi
# coreboot config options: cpu
# coreboot config options: northbridge
432 4 e 11 gfx_uma_size
432 4 e 11 gfx_uma_size
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
10 0 AHCI
10 1 Compatible
11 1 4M
11 2 8M
11 3 16M
11 4 32M
11 5 48M
11 6 64M
11 7 128M
11 8 256M
11 9 96M
11 10 160M
11 11 224M
11 12 352M
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
10 0 AHCI
10 1 Compatible
11 1 4M
11 2 8M
11 3 16M
11 4 32M
11 5 48M
11 6 64M
11 7 128M
11 8 256M
11 9 96M
11 10 160M
11 11 224M
11 12 352M
# -----------------------------------------------------------------
checksums

82
src/mainboard/intel/emeraldlake2/cmos.layout
View File

@@ -4,71 +4,71 @@
entries
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
395 4 e 6 debug_level
# coreboot config options: cpu
400 1 e 2 hyper_threading
400 1 e 2 hyper_threading
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
411 1 e 8 sata_mode
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
411 1 e 8 sata_mode
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
416 128 r 0 vbnv
# coreboot config options: northbridge
544 3 e 11 gfx_uma_size
544 3 e 11 gfx_uma_size
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
8 0 AHCI
8 1 Compatible
11 0 32M
11 1 64M
11 2 96M
11 3 128M
11 4 160M
11 5 192M
11 6 224M
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
8 0 AHCI
8 1 Compatible
11 0 32M
11 1 64M
11 2 96M
11 3 128M
11 4 160M
11 5 192M
11 6 224M
# -----------------------------------------------------------------
checksums

62
src/mainboard/intel/kblrvp/cmos.layout
View File

@@ -3,61 +3,61 @@
# -----------------------------------------------------------------
entries
#start-bit length config config-ID name
#start-bit length config config-ID name
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
395 4 e 6 debug_level
# coreboot config options: cpu
400 1 e 2 hyper_threading
400 1 e 2 hyper_threading
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
416 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
# -----------------------------------------------------------------
checksums

62
src/mainboard/intel/kunimitsu/cmos.layout
View File

@@ -3,61 +3,61 @@
# -----------------------------------------------------------------
entries
#start-bit length config config-ID name
#start-bit length config config-ID name
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
395 4 e 6 debug_level
# coreboot config options: cpu
400 1 e 2 hyper_threading
400 1 e 2 hyper_threading
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
416 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
# -----------------------------------------------------------------
checksums

54
src/mainboard/intel/saddlebrook/cmos.layout
View File

@@ -3,54 +3,54 @@
# -----------------------------------------------------------------
entries
#start-bit length config config-ID name
#start-bit length config config-ID name
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
392 3 r 0 unused
395 4 e 6 debug_level
392 3 r 0 unused
395 4 e 6 debug_level
# coreboot config options: cpu
# coreboot config options: southbridge
409 2 e 7 power_on_after_fail
409 2 e 7 power_on_after_fail
# coreboot config options: bootloader
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
# -----------------------------------------------------------------
checksums

62
src/mainboard/intel/strago/cmos.layout
View File

@@ -3,61 +3,61 @@
# -----------------------------------------------------------------
entries
#start-bit length config config-ID name
#start-bit length config config-ID name
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
395 4 e 6 debug_level
# coreboot config options: cpu
400 1 e 2 hyper_threading
400 1 e 2 hyper_threading
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
416 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
# -----------------------------------------------------------------
checksums

60
src/mainboard/intel/wtm2/cmos.layout
View File

@@ -4,58 +4,58 @@
entries
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
395 4 e 6 debug_level
# coreboot config options: cpu
400 1 e 2 hyper_threading
400 1 e 2 hyper_threading
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
416 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
# -----------------------------------------------------------------
checksums