mb/**/cmos.layout: Indent everything with tabs
Time has shown that using spaces never converges into proper alignment. Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This commit is contained in:
Angel Pons
@@ -4,67 +4,67 @@
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entries
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entries
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# -----------------------------------------------------------------
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# -----------------------------------------------------------------
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||||||
0 120 r 0 reserved_memory
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0 120 r 0 reserved_memory
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||||||
|
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||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
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||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
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||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
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||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
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# coreboot config options: console
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||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
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||||||
|
|
||||||
# coreboot config options: southbridge
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# coreboot config options: southbridge
|
||||||
408 1 e 10 sata_mode
|
408 1 e 10 sata_mode
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||||||
409 2 e 7 power_on_after_fail
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409 2 e 7 power_on_after_fail
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||||||
411 1 e 1 nmi
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411 1 e 1 nmi
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||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
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||||||
# coreboot config options: northbridge
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# coreboot config options: northbridge
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||||||
432 4 e 11 gfx_uma_size
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432 4 e 11 gfx_uma_size
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||||||
|
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||||||
# coreboot config options: check sums
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# coreboot config options: check sums
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||||||
984 16 h 0 check_sum
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984 16 h 0 check_sum
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||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
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||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
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6 7 Debug
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||||||
6 8 Spew
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6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
10 0 AHCI
|
10 0 AHCI
|
||||||
10 1 Compatible
|
10 1 Compatible
|
||||||
11 1 4M
|
11 1 4M
|
||||||
11 2 8M
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11 2 8M
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||||||
11 3 16M
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11 3 16M
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||||||
11 4 32M
|
11 4 32M
|
||||||
11 5 48M
|
11 5 48M
|
||||||
11 6 64M
|
11 6 64M
|
||||||
11 7 128M
|
11 7 128M
|
||||||
11 8 256M
|
11 8 256M
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||||||
11 9 96M
|
11 9 96M
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||||||
11 10 160M
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11 10 160M
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||||||
11 11 224M
|
11 11 224M
|
||||||
11 12 352M
|
11 12 352M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
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||||||
|
|||||||
@@ -5,49 +5,49 @@
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entries
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entries
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||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -5,49 +5,49 @@
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|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
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||||||
|
|||||||
@@ -5,49 +5,49 @@
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|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -5,49 +5,49 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -5,49 +5,49 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -5,49 +5,49 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -5,49 +5,49 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,76 +4,76 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
#409 2 e 7 power_on_after_fail
|
#409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
411 3 e 11 gfx_uma_size
|
411 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
416 512 s 0 boot_devices
|
416 512 s 0 boot_devices
|
||||||
928 8 h 0 boot_default
|
928 8 h 0 boot_default
|
||||||
936 1 e 8 cmos_defaults_loaded
|
936 1 e 8 cmos_defaults_loaded
|
||||||
937 1 e 1 lpt
|
937 1 e 1 lpt
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# RAM initialization internal data
|
# RAM initialization internal data
|
||||||
1024 8 r 0 C0WL0REOST
|
1024 8 r 0 C0WL0REOST
|
||||||
1032 8 r 0 C1WL0REOST
|
1032 8 r 0 C1WL0REOST
|
||||||
1040 8 r 0 RCVENMT
|
1040 8 r 0 RCVENMT
|
||||||
1048 4 r 0 C0DRT1
|
1048 4 r 0 C0DRT1
|
||||||
1052 4 r 0 C1DRT1
|
1052 4 r 0 C1DRT1
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 No
|
8 0 No
|
||||||
8 1 Yes
|
8 1 Yes
|
||||||
9 0 Secondary
|
9 0 Secondary
|
||||||
9 1 Primary
|
9 1 Primary
|
||||||
11 0 1M
|
11 0 1M
|
||||||
11 1 4M
|
11 1 4M
|
||||||
11 2 8M
|
11 2 8M
|
||||||
11 3 16M
|
11 3 16M
|
||||||
11 4 32M
|
11 4 32M
|
||||||
11 5 48M
|
11 5 48M
|
||||||
11 6 64M
|
11 6 64M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -3,49 +3,49 @@
|
|||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
entries
|
entries
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
#432 5 e 11 gfx_uma_size
|
#432 5 e 11 gfx_uma_size
|
||||||
#440 8 h 0 volume
|
#440 8 h 0 volume
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
enumerations
|
enumerations
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
checksum 392 447 984
|
checksum 392 447 984
|
||||||
|
|||||||
@@ -5,52 +5,52 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 2 e 3 power_on_after_fail
|
400 2 e 3 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
3 0 Off
|
3 0 Off
|
||||||
3 1 On
|
3 1 On
|
||||||
3 2 Last
|
3 2 Last
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,59 +4,59 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 4 e 11 gfx_uma_size
|
432 4 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
11 6 64M
|
11 6 64M
|
||||||
11 7 128M
|
11 7 128M
|
||||||
11 8 256M
|
11 8 256M
|
||||||
11 9 96M
|
11 9 96M
|
||||||
11 10 160M
|
11 10 160M
|
||||||
11 11 224M
|
11 11 224M
|
||||||
11 12 352M
|
11 12 352M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -3,61 +3,61 @@
|
|||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
entries
|
entries
|
||||||
|
|
||||||
#start-bit length config config-ID name
|
#start-bit length config config-ID name
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,53 +4,53 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 3 boot_option
|
384 1 e 3 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 4 debug_level
|
395 4 e 4 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 5 power_on_after_fail
|
409 2 e 5 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
|
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
|
|
||||||
3 0 Fallback
|
3 0 Fallback
|
||||||
3 1 Normal
|
3 1 Normal
|
||||||
|
|
||||||
4 0 Emergency
|
4 0 Emergency
|
||||||
4 1 Alert
|
4 1 Alert
|
||||||
4 2 Critical
|
4 2 Critical
|
||||||
4 3 Error
|
4 3 Error
|
||||||
4 4 Warning
|
4 4 Warning
|
||||||
4 5 Notice
|
4 5 Notice
|
||||||
4 6 Info
|
4 6 Info
|
||||||
4 7 Debug
|
4 7 Debug
|
||||||
4 8 Spew
|
4 8 Spew
|
||||||
|
|
||||||
5 0 Disable
|
5 0 Disable
|
||||||
5 1 Enable
|
5 1 Enable
|
||||||
5 2 Keep
|
5 2 Keep
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -5,49 +5,49 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -2,54 +2,54 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
#456 1 e 1 ECC_memory
|
#456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -5,45 +5,45 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
#start-bit length config config-ID name
|
#start-bit length config config-ID name
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 r 0 reboot_counter
|
388 4 r 0 reboot_counter
|
||||||
#400 1 e 1 power_on_after_fail
|
#400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
416 4 e 7 boot_first
|
416 4 e 7 boot_first
|
||||||
420 4 e 7 boot_second
|
420 4 e 7 boot_second
|
||||||
424 4 e 7 boot_third
|
424 4 e 7 boot_third
|
||||||
428 4 r 0 boot_index
|
428 4 r 0 boot_index
|
||||||
432 8 r 0 boot_countdown
|
432 8 r 0 boot_countdown
|
||||||
440 8 e 10 sata_mode
|
440 8 e 10 sata_mode
|
||||||
448 8 e 11 sata_speed
|
448 8 e 11 sata_speed
|
||||||
#728 256 h 0 user_data
|
#728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
#1 0 Disable
|
#1 0 Disable
|
||||||
#1 1 Enable
|
#1 1 Enable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Network
|
7 0 Network
|
||||||
7 1 HDD
|
7 1 HDD
|
||||||
7 2 Floppy
|
7 2 Floppy
|
||||||
7 8 Fallback_Network
|
7 8 Fallback_Network
|
||||||
7 9 Fallback_HDD
|
7 9 Fallback_HDD
|
||||||
7 10 Fallback_Floppy
|
7 10 Fallback_Floppy
|
||||||
10 0 IDE
|
10 0 IDE
|
||||||
10 2 AHCI
|
10 2 AHCI
|
||||||
11 1 3Gbps
|
11 1 3Gbps
|
||||||
11 0 6Gbps
|
11 0 6Gbps
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -5,49 +5,49 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,61 +4,61 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 IDE
|
9 1 IDE
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,73 +4,73 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 3 boot_option
|
384 1 e 3 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 4 debug_level
|
395 4 e 4 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 5 power_on_after_fail
|
409 2 e 5 power_on_after_fail
|
||||||
411 1 e 6 sata_mode
|
411 1 e 6 sata_mode
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
412 3 e 7 gfx_uma_size
|
412 3 e 7 gfx_uma_size
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
|
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
|
|
||||||
3 0 Fallback
|
3 0 Fallback
|
||||||
3 1 Normal
|
3 1 Normal
|
||||||
|
|
||||||
4 0 Emergency
|
4 0 Emergency
|
||||||
4 1 Alert
|
4 1 Alert
|
||||||
4 2 Critical
|
4 2 Critical
|
||||||
4 3 Error
|
4 3 Error
|
||||||
4 4 Warning
|
4 4 Warning
|
||||||
4 5 Notice
|
4 5 Notice
|
||||||
4 6 Info
|
4 6 Info
|
||||||
4 7 Debug
|
4 7 Debug
|
||||||
4 8 Spew
|
4 8 Spew
|
||||||
|
|
||||||
5 0 Disable
|
5 0 Disable
|
||||||
5 1 Enable
|
5 1 Enable
|
||||||
5 2 Keep
|
5 2 Keep
|
||||||
|
|
||||||
6 0 AHCI
|
6 0 AHCI
|
||||||
6 1 Compatible
|
6 1 Compatible
|
||||||
|
|
||||||
7 0 32M
|
7 0 32M
|
||||||
7 1 64M
|
7 1 64M
|
||||||
7 2 96M
|
7 2 96M
|
||||||
7 3 128M
|
7 3 128M
|
||||||
7 4 160M
|
7 4 160M
|
||||||
7 5 192M
|
7 5 192M
|
||||||
7 6 224M
|
7 6 224M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -2,65 +2,65 @@
|
|||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
entries
|
entries
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
411 3 e 11 gfx_uma_size
|
411 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
416 512 s 0 boot_devices
|
416 512 s 0 boot_devices
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# RAM initialization internal data
|
# RAM initialization internal data
|
||||||
1024 8 r 0 C0WL0REOST
|
1024 8 r 0 C0WL0REOST
|
||||||
1032 8 r 0 C1WL0REOST
|
1032 8 r 0 C1WL0REOST
|
||||||
1040 8 r 0 RCVENMT
|
1040 8 r 0 RCVENMT
|
||||||
1048 4 r 0 C0DRT1
|
1048 4 r 0 C0DRT1
|
||||||
1052 4 r 0 C1DRT1
|
1052 4 r 0 C1DRT1
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
11 0 1M
|
11 0 1M
|
||||||
11 1 4M
|
11 1 4M
|
||||||
11 2 8M
|
11 2 8M
|
||||||
11 3 16M
|
11 3 16M
|
||||||
11 4 32M
|
11 4 32M
|
||||||
11 5 48M
|
11 5 48M
|
||||||
11 6 64M
|
11 6 64M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,54 +4,54 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 10 sata_mode
|
408 1 e 10 sata_mode
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
411 1 e 1 nmi
|
411 1 e 1 nmi
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
10 0 AHCI
|
10 0 AHCI
|
||||||
10 1 Compatible
|
10 1 Compatible
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,59 +4,59 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
411 1 e 1 nmi
|
411 1 e 1 nmi
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 4 e 11 gfx_uma_size
|
432 4 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
11 6 64M
|
11 6 64M
|
||||||
11 7 128M
|
11 7 128M
|
||||||
11 8 256M
|
11 8 256M
|
||||||
11 9 96M
|
11 9 96M
|
||||||
11 10 160M
|
11 10 160M
|
||||||
11 11 224M
|
11 11 224M
|
||||||
11 12 352M
|
11 12 352M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,59 +4,59 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 4 e 11 gfx_uma_size
|
432 4 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 1 Emergency
|
6 1 Emergency
|
||||||
6 2 Alert
|
6 2 Alert
|
||||||
6 3 Critical
|
6 3 Critical
|
||||||
6 4 Error
|
6 4 Error
|
||||||
6 5 Warning
|
6 5 Warning
|
||||||
6 6 Notice
|
6 6 Notice
|
||||||
6 7 Info
|
6 7 Info
|
||||||
6 8 Debug
|
6 8 Debug
|
||||||
6 9 Spew
|
6 9 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
11 6 64M
|
11 6 64M
|
||||||
11 7 128M
|
11 7 128M
|
||||||
11 8 256M
|
11 8 256M
|
||||||
11 9 96M
|
11 9 96M
|
||||||
11 10 160M
|
11 10 160M
|
||||||
11 11 224M
|
11 11 224M
|
||||||
11 12 352M
|
11 12 352M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,68 +4,68 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 3 boot_option
|
384 1 e 3 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 4 debug_level
|
395 4 e 4 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 5 power_on_after_fail
|
409 2 e 5 power_on_after_fail
|
||||||
411 1 e 6 sata_mode
|
411 1 e 6 sata_mode
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
412 3 e 7 gfx_uma_size
|
412 3 e 7 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
|
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
|
|
||||||
3 0 Fallback
|
3 0 Fallback
|
||||||
3 1 Normal
|
3 1 Normal
|
||||||
|
|
||||||
4 0 Emergency
|
4 0 Emergency
|
||||||
4 1 Alert
|
4 1 Alert
|
||||||
4 2 Critical
|
4 2 Critical
|
||||||
4 3 Error
|
4 3 Error
|
||||||
4 4 Warning
|
4 4 Warning
|
||||||
4 5 Notice
|
4 5 Notice
|
||||||
4 6 Info
|
4 6 Info
|
||||||
4 7 Debug
|
4 7 Debug
|
||||||
4 8 Spew
|
4 8 Spew
|
||||||
|
|
||||||
5 0 Disable
|
5 0 Disable
|
||||||
5 1 Enable
|
5 1 Enable
|
||||||
5 2 Keep
|
5 2 Keep
|
||||||
|
|
||||||
6 0 AHCI
|
6 0 AHCI
|
||||||
6 1 Compatible
|
6 1 Compatible
|
||||||
|
|
||||||
7 0 32M
|
7 0 32M
|
||||||
7 1 64M
|
7 1 64M
|
||||||
7 2 96M
|
7 2 96M
|
||||||
7 3 128M
|
7 3 128M
|
||||||
7 4 160M
|
7 4 160M
|
||||||
7 5 192M
|
7 5 192M
|
||||||
7 6 224M
|
7 6 224M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,61 +4,61 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 IDE
|
9 1 IDE
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,27 +4,27 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 3 boot_option
|
384 1 e 3 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 4 debug_level
|
395 4 e 4 debug_level
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
|
|
||||||
# Non Maskable Interrupt(NMI) support, which is an interrupt that may
|
# Non Maskable Interrupt(NMI) support, which is an interrupt that may
|
||||||
# occur on a RAM or unrecoverable error.
|
# occur on a RAM or unrecoverable error.
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
|
|
||||||
409 2 e 5 power_on_after_fail
|
409 2 e 5 power_on_after_fail
|
||||||
411 1 e 6 sata_mode
|
411 1 e 6 sata_mode
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
@@ -32,119 +32,119 @@ entries
|
|||||||
# gfx_uma_size
|
# gfx_uma_size
|
||||||
# Quantity of shared video memory the IGP can use
|
# Quantity of shared video memory the IGP can use
|
||||||
#
|
#
|
||||||
416 5 e 7 gfx_uma_size
|
416 5 e 7 gfx_uma_size
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: usb3
|
# coreboot config options: usb3
|
||||||
|
|
||||||
# usb3_mode
|
# usb3_mode
|
||||||
# Controls how the motherboard's USB3 ports act at boot time
|
# Controls how the motherboard's USB3 ports act at boot time
|
||||||
421 2 e 8 usb3_mode
|
421 2 e 8 usb3_mode
|
||||||
|
|
||||||
# usb3_drv
|
# usb3_drv
|
||||||
# Load (or not) pre-OS xHCI USB3 BIOS driver
|
# Load (or not) pre-OS xHCI USB3 BIOS driver
|
||||||
#
|
#
|
||||||
423 1 e 1 usb3_drv
|
423 1 e 1 usb3_drv
|
||||||
|
|
||||||
# usb3_streams
|
# usb3_streams
|
||||||
# Streams can provide more speed (as they can use 64Kb packets),
|
# Streams can provide more speed (as they can use 64Kb packets),
|
||||||
# but they might cause incompatibilities with some devices.
|
# but they might cause incompatibilities with some devices.
|
||||||
#
|
#
|
||||||
424 1 e 1 usb3_streams
|
424 1 e 1 usb3_streams
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# Sandy/Ivy Bridge MRC Scrambler Seed values
|
# Sandy/Ivy Bridge MRC Scrambler Seed values
|
||||||
# note: MUST NOT be covered by checksum!
|
# note: MUST NOT be covered by checksum!
|
||||||
464 32 r 0 mrc_scrambler_seed
|
464 32 r 0 mrc_scrambler_seed
|
||||||
496 32 r 0 mrc_scrambler_seed_s3
|
496 32 r 0 mrc_scrambler_seed_s3
|
||||||
528 16 r 0 mrc_scrambler_seed_chk
|
528 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
544 16 h 0 check_sum
|
544 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
#ID value text
|
#ID value text
|
||||||
|
|
||||||
# Generic on/off enum
|
# Generic on/off enum
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
|
|
||||||
# boot_option
|
# boot_option
|
||||||
3 0 Fallback
|
3 0 Fallback
|
||||||
3 1 Normal
|
3 1 Normal
|
||||||
|
|
||||||
# debug_level
|
# debug_level
|
||||||
4 0 Emergency
|
4 0 Emergency
|
||||||
4 1 Alert
|
4 1 Alert
|
||||||
4 2 Critical
|
4 2 Critical
|
||||||
4 3 Error
|
4 3 Error
|
||||||
4 4 Warning
|
4 4 Warning
|
||||||
4 5 Notice
|
4 5 Notice
|
||||||
4 6 Info
|
4 6 Info
|
||||||
4 7 Debug
|
4 7 Debug
|
||||||
4 8 Spew
|
4 8 Spew
|
||||||
|
|
||||||
# power_on_after_fail
|
# power_on_after_fail
|
||||||
5 0 Disable
|
5 0 Disable
|
||||||
5 1 Enable
|
5 1 Enable
|
||||||
5 2 Keep
|
5 2 Keep
|
||||||
|
|
||||||
# sata_mode
|
# sata_mode
|
||||||
6 0 AHCI
|
6 0 AHCI
|
||||||
6 1 Compatible
|
6 1 Compatible
|
||||||
|
|
||||||
# gfx_uma_size (Intel IGP Video RAM size)
|
# gfx_uma_size (Intel IGP Video RAM size)
|
||||||
7 0 32M
|
7 0 32M
|
||||||
7 1 64M
|
7 1 64M
|
||||||
7 2 96M
|
7 2 96M
|
||||||
7 3 128M
|
7 3 128M
|
||||||
7 4 160M
|
7 4 160M
|
||||||
7 5 192M
|
7 5 192M
|
||||||
7 6 224M
|
7 6 224M
|
||||||
7 7 256M
|
7 7 256M
|
||||||
7 8 288M
|
7 8 288M
|
||||||
7 9 320M
|
7 9 320M
|
||||||
7 10 352M
|
7 10 352M
|
||||||
7 11 384M
|
7 11 384M
|
||||||
7 12 416M
|
7 12 416M
|
||||||
7 13 448M
|
7 13 448M
|
||||||
7 14 480M
|
7 14 480M
|
||||||
7 15 512M
|
7 15 512M
|
||||||
7 16 544M
|
7 16 544M
|
||||||
7 17 576M
|
7 17 576M
|
||||||
7 18 608M
|
7 18 608M
|
||||||
7 19 640M
|
7 19 640M
|
||||||
7 20 672M
|
7 20 672M
|
||||||
7 21 704M
|
7 21 704M
|
||||||
7 22 736M
|
7 22 736M
|
||||||
7 23 768M
|
7 23 768M
|
||||||
7 24 800M
|
7 24 800M
|
||||||
7 25 832M
|
7 25 832M
|
||||||
7 26 864M
|
7 26 864M
|
||||||
7 27 896M
|
7 27 896M
|
||||||
7 28 928M
|
7 28 928M
|
||||||
7 29 960M
|
7 29 960M
|
||||||
7 30 992M
|
7 30 992M
|
||||||
|
|
||||||
# usb3_mode
|
# usb3_mode
|
||||||
# Disable = Use the port always as USB 2.0 for compatibility
|
# Disable = Use the port always as USB 2.0 for compatibility
|
||||||
# Enable = Use the port always as USB 3.0 for speed
|
# Enable = Use the port always as USB 3.0 for speed
|
||||||
# Auto = Initialize the port as USB 2.0, until the OS loads
|
# Auto = Initialize the port as USB 2.0, until the OS loads
|
||||||
# xHCI USB 3.0 driver
|
# xHCI USB 3.0 driver
|
||||||
# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver
|
# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver
|
||||||
# and the computer is reset, keep the USB 3.0 mode.
|
# and the computer is reset, keep the USB 3.0 mode.
|
||||||
#
|
#
|
||||||
8 0 Disable
|
8 0 Disable
|
||||||
8 1 Enable
|
8 1 Enable
|
||||||
8 2 Auto
|
8 2 Auto
|
||||||
8 3 SmartAuto
|
8 3 SmartAuto
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# <startBit[must be byte-aligned]> <endBit[must be byte aligned]>
|
# <startBit[must be byte-aligned]> <endBit[must be byte aligned]>
|
||||||
# <bit where to start storing checksum[must be 16bits-aligned]>
|
# <bit where to start storing checksum[must be 16bits-aligned]>
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
checksum 392 431 544
|
checksum 392 431 544
|
||||||
|
|||||||
@@ -5,49 +5,49 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -5,49 +5,49 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -5,84 +5,84 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
#start-bit length config config-ID name
|
#start-bit length config config-ID name
|
||||||
#0 8 r 0 seconds
|
#0 8 r 0 seconds
|
||||||
#8 8 r 0 alarm_seconds
|
#8 8 r 0 alarm_seconds
|
||||||
#16 8 r 0 minutes
|
#16 8 r 0 minutes
|
||||||
#24 8 r 0 alarm_minutes
|
#24 8 r 0 alarm_minutes
|
||||||
#32 8 r 0 hours
|
#32 8 r 0 hours
|
||||||
#40 8 r 0 alarm_hours
|
#40 8 r 0 alarm_hours
|
||||||
#48 8 r 0 day_of_week
|
#48 8 r 0 day_of_week
|
||||||
#56 8 r 0 day_of_month
|
#56 8 r 0 day_of_month
|
||||||
#64 8 r 0 month
|
#64 8 r 0 month
|
||||||
#72 8 r 0 year
|
#72 8 r 0 year
|
||||||
#80 4 r 0 rate_select
|
#80 4 r 0 rate_select
|
||||||
#84 3 r 0 REF_Clock
|
#84 3 r 0 REF_Clock
|
||||||
#87 1 r 0 UIP
|
#87 1 r 0 UIP
|
||||||
#88 1 r 0 auto_switch_DST
|
#88 1 r 0 auto_switch_DST
|
||||||
#89 1 r 0 24_hour_mode
|
#89 1 r 0 24_hour_mode
|
||||||
#90 1 r 0 binary_values_enable
|
#90 1 r 0 binary_values_enable
|
||||||
#91 1 r 0 square-wave_out_enable
|
#91 1 r 0 square-wave_out_enable
|
||||||
#92 1 r 0 update_finished_enable
|
#92 1 r 0 update_finished_enable
|
||||||
#93 1 r 0 alarm_interrupt_enable
|
#93 1 r 0 alarm_interrupt_enable
|
||||||
#94 1 r 0 periodic_interrupt_enable
|
#94 1 r 0 periodic_interrupt_enable
|
||||||
#95 1 r 0 disable_clock_updates
|
#95 1 r 0 disable_clock_updates
|
||||||
#96 288 r 0 temporary_filler
|
#96 288 r 0 temporary_filler
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
386 1 e 1 ECC_memory
|
386 1 e 1 ECC_memory
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
416 4 e 7 boot_first
|
416 4 e 7 boot_first
|
||||||
420 4 e 7 boot_second
|
420 4 e 7 boot_second
|
||||||
424 4 e 7 boot_third
|
424 4 e 7 boot_third
|
||||||
428 4 h 0 boot_index
|
428 4 h 0 boot_index
|
||||||
432 8 h 0 boot_countdown
|
432 8 h 0 boot_countdown
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Network
|
7 0 Network
|
||||||
7 1 HDD
|
7 1 HDD
|
||||||
7 2 Floppy
|
7 2 Floppy
|
||||||
7 8 Fallback_Network
|
7 8 Fallback_Network
|
||||||
7 9 Fallback_HDD
|
7 9 Fallback_HDD
|
||||||
7 10 Fallback_Floppy
|
7 10 Fallback_Floppy
|
||||||
#7 3 ROM
|
#7 3 ROM
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -5,60 +5,60 @@ entries
|
|||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 IDE
|
9 1 IDE
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -3,45 +3,45 @@
|
|||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
entries
|
entries
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,70 +4,70 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
411 1 e 8 sata_mode
|
411 1 e 8 sata_mode
|
||||||
|
|
||||||
# coreboot config options: EC
|
# coreboot config options: EC
|
||||||
412 1 e 1 fan_full_speed
|
412 1 e 1 fan_full_speed
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 9 gfx_uma_size
|
432 3 e 9 gfx_uma_size
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 AHCI
|
8 0 AHCI
|
||||||
8 1 Compatible
|
8 1 Compatible
|
||||||
9 0 32M
|
9 0 32M
|
||||||
9 1 64M
|
9 1 64M
|
||||||
9 2 96M
|
9 2 96M
|
||||||
9 3 128M
|
9 3 128M
|
||||||
9 4 160M
|
9 4 160M
|
||||||
9 5 192M
|
9 5 192M
|
||||||
9 6 224M
|
9 6 224M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -5,49 +5,49 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 r 0 reboot_bits
|
388 4 r 0 reboot_bits
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -1,35 +1,35 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
|
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
400 8 r 0 reserved_century
|
400 8 r 0 reserved_century
|
||||||
440 8 r 0 reserved_ibm_ps2_century
|
440 8 r 0 reserved_ibm_ps2_century
|
||||||
|
|
||||||
448 1 e 1 power_on_after_fail
|
448 1 e 1 power_on_after_fail
|
||||||
452 4 e 6 debug_level
|
452 4 e 6 debug_level
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
|
|
||||||
# VBOOT
|
# VBOOT
|
||||||
464 128 r 0 vbnv
|
464 128 r 0 vbnv
|
||||||
|
|
||||||
1008 16 h 0 check_sum
|
1008 16 h 0 check_sum
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -1,35 +1,35 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
|
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
400 8 r 0 reserved_century
|
400 8 r 0 reserved_century
|
||||||
440 8 r 0 reserved_ibm_ps2_century
|
440 8 r 0 reserved_ibm_ps2_century
|
||||||
|
|
||||||
448 1 e 1 power_on_after_fail
|
448 1 e 1 power_on_after_fail
|
||||||
452 4 e 6 debug_level
|
452 4 e 6 debug_level
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
|
|
||||||
# VBOOT
|
# VBOOT
|
||||||
464 128 r 0 vbnv
|
464 128 r 0 vbnv
|
||||||
|
|
||||||
1008 16 h 0 check_sum
|
1008 16 h 0 check_sum
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -3,55 +3,55 @@
|
|||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
entries
|
entries
|
||||||
|
|
||||||
#start-bit length config config-ID name
|
#start-bit length config config-ID name
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
# reboot_counter reserved for core, not used by platform.
|
# reboot_counter reserved for core, not used by platform.
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -3,55 +3,55 @@
|
|||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
entries
|
entries
|
||||||
|
|
||||||
#start-bit length config config-ID name
|
#start-bit length config config-ID name
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
# reboot_counter reserved for core, not used by platform.
|
# reboot_counter reserved for core, not used by platform.
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,64 +4,64 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
416 512 s 0 boot_devices
|
416 512 s 0 boot_devices
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
952 3 e 11 gfx_uma_size
|
952 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
11 0 8M
|
11 0 8M
|
||||||
11 1 16M
|
11 1 16M
|
||||||
11 2 32M
|
11 2 32M
|
||||||
11 3 48M
|
11 3 48M
|
||||||
11 4 64M
|
11 4 64M
|
||||||
11 5 128M
|
11 5 128M
|
||||||
11 6 256M
|
11 6 256M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,59 +4,59 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 4 e 11 gfx_uma_size
|
432 4 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
11 6 64M
|
11 6 64M
|
||||||
11 7 128M
|
11 7 128M
|
||||||
11 8 256M
|
11 8 256M
|
||||||
11 9 96M
|
11 9 96M
|
||||||
11 10 160M
|
11 10 160M
|
||||||
11 11 224M
|
11 11 224M
|
||||||
11 12 352M
|
11 12 352M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,74 +4,74 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
#409 2 e 7 power_on_after_fail
|
#409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
411 3 e 11 gfx_uma_size
|
411 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
416 512 s 0 boot_devices
|
416 512 s 0 boot_devices
|
||||||
928 8 h 0 boot_default
|
928 8 h 0 boot_default
|
||||||
936 1 e 8 cmos_defaults_loaded
|
936 1 e 8 cmos_defaults_loaded
|
||||||
937 1 e 1 lpt
|
937 1 e 1 lpt
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# RAM initialization internal data
|
# RAM initialization internal data
|
||||||
1024 8 r 0 C0WL0REOST
|
1024 8 r 0 C0WL0REOST
|
||||||
1032 8 r 0 C1WL0REOST
|
1032 8 r 0 C1WL0REOST
|
||||||
1040 8 r 0 RCVENMT
|
1040 8 r 0 RCVENMT
|
||||||
1048 4 r 0 C0DRT1
|
1048 4 r 0 C0DRT1
|
||||||
1052 4 r 0 C1DRT1
|
1052 4 r 0 C1DRT1
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 No
|
8 0 No
|
||||||
8 1 Yes
|
8 1 Yes
|
||||||
11 0 1M
|
11 0 1M
|
||||||
11 1 4M
|
11 1 4M
|
||||||
11 2 8M
|
11 2 8M
|
||||||
11 3 16M
|
11 3 16M
|
||||||
11 4 32M
|
11 4 32M
|
||||||
11 5 48M
|
11 5 48M
|
||||||
11 6 64M
|
11 6 64M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,69 +4,69 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
411 3 e 11 gfx_uma_size
|
411 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
416 512 s 0 boot_devices
|
416 512 s 0 boot_devices
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# RAM initialization internal data
|
# RAM initialization internal data
|
||||||
1024 8 r 0 C0WL0REOST
|
1024 8 r 0 C0WL0REOST
|
||||||
1032 8 r 0 C1WL0REOST
|
1032 8 r 0 C1WL0REOST
|
||||||
1040 8 r 0 RCVENMT
|
1040 8 r 0 RCVENMT
|
||||||
1048 4 r 0 C0DRT1
|
1048 4 r 0 C0DRT1
|
||||||
1052 4 r 0 C1DRT1
|
1052 4 r 0 C1DRT1
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
11 0 1M
|
11 0 1M
|
||||||
11 1 4M
|
11 1 4M
|
||||||
11 2 8M
|
11 2 8M
|
||||||
11 3 16M
|
11 3 16M
|
||||||
11 4 32M
|
11 4 32M
|
||||||
11 5 48M
|
11 5 48M
|
||||||
11 6 64M
|
11 6 64M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,61 +4,61 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 IDE
|
9 1 IDE
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,64 +4,64 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 4 e 11 gfx_uma_size
|
432 4 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
11 1 4M
|
11 1 4M
|
||||||
11 2 8M
|
11 2 8M
|
||||||
11 3 16M
|
11 3 16M
|
||||||
11 4 32M
|
11 4 32M
|
||||||
11 5 48M
|
11 5 48M
|
||||||
11 6 64M
|
11 6 64M
|
||||||
11 7 128M
|
11 7 128M
|
||||||
11 8 256M
|
11 8 256M
|
||||||
11 9 96M
|
11 9 96M
|
||||||
11 10 160M
|
11 10 160M
|
||||||
11 11 224M
|
11 11 224M
|
||||||
11 12 352M
|
11 12 352M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,61 +4,61 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 IDE
|
9 1 IDE
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -5,49 +5,49 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -5,49 +5,49 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,58 +4,58 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,58 +4,58 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,74 +4,74 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
# No serial port on this motherboard
|
# No serial port on this motherboard
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
# hyper_threading not supported by the Celeron 847 on this board
|
# hyper_threading not supported by the Celeron 847 on this board
|
||||||
#400 1 e 2 hyper_threading
|
#400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
411 1 e 8 sata_mode
|
411 1 e 8 sata_mode
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
544 3 e 11 gfx_uma_size
|
544 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 AHCI
|
8 0 AHCI
|
||||||
8 1 Compatible
|
8 1 Compatible
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -3,61 +3,61 @@
|
|||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
entries
|
entries
|
||||||
|
|
||||||
#start-bit length config config-ID name
|
#start-bit length config config-ID name
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -3,61 +3,61 @@
|
|||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
entries
|
entries
|
||||||
|
|
||||||
#start-bit length config config-ID name
|
#start-bit length config config-ID name
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -3,61 +3,61 @@
|
|||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
entries
|
entries
|
||||||
|
|
||||||
#start-bit length config config-ID name
|
#start-bit length config config-ID name
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,71 +4,71 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
411 1 e 8 sata_mode
|
411 1 e 8 sata_mode
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
544 3 e 11 gfx_uma_size
|
544 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 AHCI
|
8 0 AHCI
|
||||||
8 1 Compatible
|
8 1 Compatible
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,71 +4,71 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
411 1 e 8 sata_mode
|
411 1 e 8 sata_mode
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
544 3 e 11 gfx_uma_size
|
544 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 AHCI
|
8 0 AHCI
|
||||||
8 1 Compatible
|
8 1 Compatible
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,58 +4,58 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,58 +4,58 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,71 +4,71 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
411 1 e 8 sata_mode
|
411 1 e 8 sata_mode
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
544 3 e 11 gfx_uma_size
|
544 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 AHCI
|
8 0 AHCI
|
||||||
8 1 Compatible
|
8 1 Compatible
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -5,49 +5,49 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,67 +4,67 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
400 3 h 0 psu_fan_lvl
|
400 3 h 0 psu_fan_lvl
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 IDE
|
9 1 IDE
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -1,42 +1,42 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
#start-bit length config config-ID name
|
#start-bit length config config-ID name
|
||||||
|
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# southbridge/amd/agesa/hudson should use this but it doesn't
|
# southbridge/amd/agesa/hudson should use this but it doesn't
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
|
|
||||||
# The only option that is actually used
|
# The only option that is actually used
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
|
|
||||||
# southbridge/amd/agesa/hudson should use this but it doesn't
|
# southbridge/amd/agesa/hudson should use this but it doesn't
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
|
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,72 +4,72 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
440 8 h 0 volume
|
440 8 h 0 volume
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 Compatible
|
9 1 Compatible
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,69 +4,69 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
400 3 h 0 psu_fan_lvl
|
400 3 h 0 psu_fan_lvl
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
448 128 r 0 vbnv
|
448 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 IDE
|
9 1 IDE
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,120 +4,120 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
411 3 e 11 gfx_uma_size
|
411 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
416 512 s 0 boot_devices
|
416 512 s 0 boot_devices
|
||||||
|
|
||||||
# coreboot config options: mainboard specific options
|
# coreboot config options: mainboard specific options
|
||||||
948 2 e 8 cpufan_cruise_control
|
948 2 e 8 cpufan_cruise_control
|
||||||
950 2 e 8 sysfan_cruise_control
|
950 2 e 8 sysfan_cruise_control
|
||||||
952 4 e 9 cpufan_speed
|
952 4 e 9 cpufan_speed
|
||||||
#956 4 e 10 cpufan_temperature
|
#956 4 e 10 cpufan_temperature
|
||||||
960 4 e 9 sysfan_speed
|
960 4 e 9 sysfan_speed
|
||||||
#964 4 e 10 sysfan_temperature
|
#964 4 e 10 sysfan_temperature
|
||||||
|
|
||||||
968 1 e 2 ethernet1
|
968 1 e 2 ethernet1
|
||||||
969 1 e 2 ethernet2
|
969 1 e 2 ethernet2
|
||||||
970 1 e 2 ethernet3
|
970 1 e 2 ethernet3
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# RAM initialization internal data
|
# RAM initialization internal data
|
||||||
1024 8 r 0 C0WL0REOST
|
1024 8 r 0 C0WL0REOST
|
||||||
1032 8 r 0 C1WL0REOST
|
1032 8 r 0 C1WL0REOST
|
||||||
1040 8 r 0 RCVENMT
|
1040 8 r 0 RCVENMT
|
||||||
1048 4 r 0 C0DRT1
|
1048 4 r 0 C0DRT1
|
||||||
1052 4 r 0 C1DRT1
|
1052 4 r 0 C1DRT1
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# Fan Cruise Control
|
# Fan Cruise Control
|
||||||
8 0 Disabled
|
8 0 Disabled
|
||||||
8 1 Speed
|
8 1 Speed
|
||||||
#8 2 Thermal
|
#8 2 Thermal
|
||||||
# Fan Speed (Rotations per Minute)
|
# Fan Speed (Rotations per Minute)
|
||||||
9 0 5625
|
9 0 5625
|
||||||
9 1 5192
|
9 1 5192
|
||||||
9 2 4753
|
9 2 4753
|
||||||
9 3 4326
|
9 3 4326
|
||||||
9 4 3924
|
9 4 3924
|
||||||
9 5 3552
|
9 5 3552
|
||||||
9 6 3214
|
9 6 3214
|
||||||
9 7 2909
|
9 7 2909
|
||||||
9 8 2636
|
9 8 2636
|
||||||
9 9 2393
|
9 9 2393
|
||||||
9 10 2177
|
9 10 2177
|
||||||
9 11 1985
|
9 11 1985
|
||||||
9 12 1814
|
9 12 1814
|
||||||
9 13 1662
|
9 13 1662
|
||||||
9 14 1527
|
9 14 1527
|
||||||
9 15 1406
|
9 15 1406
|
||||||
#
|
#
|
||||||
# Temperature (°C/°F)
|
# Temperature (°C/°F)
|
||||||
#10 0 30/86
|
#10 0 30/86
|
||||||
#10 1 33/91
|
#10 1 33/91
|
||||||
#10 2 36/96
|
#10 2 36/96
|
||||||
#10 3 39/102
|
#10 3 39/102
|
||||||
#10 4 42/107
|
#10 4 42/107
|
||||||
#10 5 45/113
|
#10 5 45/113
|
||||||
#10 6 48/118
|
#10 6 48/118
|
||||||
#10 7 51/123
|
#10 7 51/123
|
||||||
#10 8 54/129
|
#10 8 54/129
|
||||||
#10 9 57/134
|
#10 9 57/134
|
||||||
#10 10 60/140
|
#10 10 60/140
|
||||||
#10 11 63/145
|
#10 11 63/145
|
||||||
#10 12 66/150
|
#10 12 66/150
|
||||||
#10 13 69/156
|
#10 13 69/156
|
||||||
#10 14 72/161
|
#10 14 72/161
|
||||||
#10 15 75/167
|
#10 15 75/167
|
||||||
11 0 1M
|
11 0 1M
|
||||||
11 1 4M
|
11 1 4M
|
||||||
11 2 8M
|
11 2 8M
|
||||||
11 3 16M
|
11 3 16M
|
||||||
11 4 32M
|
11 4 32M
|
||||||
11 5 48M
|
11 5 48M
|
||||||
11 6 64M
|
11 6 64M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,54 +4,54 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,64 +4,64 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
416 512 s 0 boot_devices
|
416 512 s 0 boot_devices
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
952 3 e 11 gfx_uma_size
|
952 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
11 0 8M
|
11 0 8M
|
||||||
11 1 16M
|
11 1 16M
|
||||||
11 2 32M
|
11 2 32M
|
||||||
11 3 48M
|
11 3 48M
|
||||||
11 4 64M
|
11 4 64M
|
||||||
11 5 128M
|
11 5 128M
|
||||||
11 6 256M
|
11 6 256M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,69 +4,69 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
411 3 e 11 gfx_uma_size
|
411 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
416 512 s 0 boot_devices
|
416 512 s 0 boot_devices
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# RAM initialization internal data
|
# RAM initialization internal data
|
||||||
1024 8 r 0 C0WL0REOST
|
1024 8 r 0 C0WL0REOST
|
||||||
1032 8 r 0 C1WL0REOST
|
1032 8 r 0 C1WL0REOST
|
||||||
1040 8 r 0 RCVENMT
|
1040 8 r 0 RCVENMT
|
||||||
1048 4 r 0 C0DRT1
|
1048 4 r 0 C0DRT1
|
||||||
1052 4 r 0 C1DRT1
|
1052 4 r 0 C1DRT1
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
11 0 1M
|
11 0 1M
|
||||||
11 1 4M
|
11 1 4M
|
||||||
11 2 8M
|
11 2 8M
|
||||||
11 3 16M
|
11 3 16M
|
||||||
11 4 32M
|
11 4 32M
|
||||||
11 5 48M
|
11 5 48M
|
||||||
11 6 64M
|
11 6 64M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,59 +4,59 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 4 e 11 gfx_uma_size
|
432 4 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 1 Emergency
|
6 1 Emergency
|
||||||
6 2 Alert
|
6 2 Alert
|
||||||
6 3 Critical
|
6 3 Critical
|
||||||
6 4 Error
|
6 4 Error
|
||||||
6 5 Warning
|
6 5 Warning
|
||||||
6 6 Notice
|
6 6 Notice
|
||||||
6 7 Info
|
6 7 Info
|
||||||
6 8 Debug
|
6 8 Debug
|
||||||
6 9 Spew
|
6 9 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
11 6 64M
|
11 6 64M
|
||||||
11 7 128M
|
11 7 128M
|
||||||
11 8 256M
|
11 8 256M
|
||||||
11 9 96M
|
11 9 96M
|
||||||
11 10 160M
|
11 10 160M
|
||||||
11 11 224M
|
11 11 224M
|
||||||
11 12 352M
|
11 12 352M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,67 +4,67 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 10 sata_mode
|
408 1 e 10 sata_mode
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
411 1 e 1 nmi
|
411 1 e 1 nmi
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 4 e 11 gfx_uma_size
|
432 4 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
10 0 AHCI
|
10 0 AHCI
|
||||||
10 1 Compatible
|
10 1 Compatible
|
||||||
11 1 4M
|
11 1 4M
|
||||||
11 2 8M
|
11 2 8M
|
||||||
11 3 16M
|
11 3 16M
|
||||||
11 4 32M
|
11 4 32M
|
||||||
11 5 48M
|
11 5 48M
|
||||||
11 6 64M
|
11 6 64M
|
||||||
11 7 128M
|
11 7 128M
|
||||||
11 8 256M
|
11 8 256M
|
||||||
11 9 96M
|
11 9 96M
|
||||||
11 10 160M
|
11 10 160M
|
||||||
11 11 224M
|
11 11 224M
|
||||||
11 12 352M
|
11 12 352M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,71 +4,71 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
411 1 e 8 sata_mode
|
411 1 e 8 sata_mode
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
544 3 e 11 gfx_uma_size
|
544 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 AHCI
|
8 0 AHCI
|
||||||
8 1 Compatible
|
8 1 Compatible
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -3,61 +3,61 @@
|
|||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
entries
|
entries
|
||||||
|
|
||||||
#start-bit length config config-ID name
|
#start-bit length config config-ID name
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -3,61 +3,61 @@
|
|||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
entries
|
entries
|
||||||
|
|
||||||
#start-bit length config config-ID name
|
#start-bit length config config-ID name
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -3,54 +3,54 @@
|
|||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
entries
|
entries
|
||||||
|
|
||||||
#start-bit length config config-ID name
|
#start-bit length config config-ID name
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
392 3 r 0 unused
|
392 3 r 0 unused
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -3,61 +3,61 @@
|
|||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
entries
|
entries
|
||||||
|
|
||||||
#start-bit length config config-ID name
|
#start-bit length config config-ID name
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,58 +4,58 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
#Used by ChromeOS:
|
#Used by ChromeOS:
|
||||||
416 128 r 0 vbnv
|
416 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -5,49 +5,49 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,125 +4,125 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
411 3 e 12 gfx_uma_size
|
411 3 e 12 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
416 512 s 0 boot_devices
|
416 512 s 0 boot_devices
|
||||||
928 8 h 0 boot_default
|
928 8 h 0 boot_default
|
||||||
936 1 e 11 cmos_defaults_loaded
|
936 1 e 11 cmos_defaults_loaded
|
||||||
|
|
||||||
# coreboot config options: mainboard specific options
|
# coreboot config options: mainboard specific options
|
||||||
948 2 e 8 cpufan_cruise_control
|
948 2 e 8 cpufan_cruise_control
|
||||||
950 2 e 8 sysfan_cruise_control
|
950 2 e 8 sysfan_cruise_control
|
||||||
952 4 e 9 cpufan_speed
|
952 4 e 9 cpufan_speed
|
||||||
#956 4 e 10 cpufan_temperature
|
#956 4 e 10 cpufan_temperature
|
||||||
960 4 e 9 sysfan_speed
|
960 4 e 9 sysfan_speed
|
||||||
#964 4 e 10 sysfan_temperature
|
#964 4 e 10 sysfan_temperature
|
||||||
|
|
||||||
968 1 e 2 ethernet1
|
968 1 e 2 ethernet1
|
||||||
969 1 e 2 ethernet2
|
969 1 e 2 ethernet2
|
||||||
970 1 e 2 ethernet3
|
970 1 e 2 ethernet3
|
||||||
971 1 e 1 lpt
|
971 1 e 1 lpt
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# RAM initialization internal data
|
# RAM initialization internal data
|
||||||
1024 8 r 0 C0WL0REOST
|
1024 8 r 0 C0WL0REOST
|
||||||
1032 8 r 0 C1WL0REOST
|
1032 8 r 0 C1WL0REOST
|
||||||
1040 8 r 0 RCVENMT
|
1040 8 r 0 RCVENMT
|
||||||
1048 4 r 0 C0DRT1
|
1048 4 r 0 C0DRT1
|
||||||
1052 4 r 0 C1DRT1
|
1052 4 r 0 C1DRT1
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
# Fan Cruise Control
|
# Fan Cruise Control
|
||||||
8 0 Disabled
|
8 0 Disabled
|
||||||
8 1 Speed
|
8 1 Speed
|
||||||
#8 2 Thermal
|
#8 2 Thermal
|
||||||
# Fan Speed (Rotations per Minute)
|
# Fan Speed (Rotations per Minute)
|
||||||
9 0 5625
|
9 0 5625
|
||||||
9 1 5192
|
9 1 5192
|
||||||
9 2 4753
|
9 2 4753
|
||||||
9 3 4326
|
9 3 4326
|
||||||
9 4 3924
|
9 4 3924
|
||||||
9 5 3552
|
9 5 3552
|
||||||
9 6 3214
|
9 6 3214
|
||||||
9 7 2909
|
9 7 2909
|
||||||
9 8 2636
|
9 8 2636
|
||||||
9 9 2393
|
9 9 2393
|
||||||
9 10 2177
|
9 10 2177
|
||||||
9 11 1985
|
9 11 1985
|
||||||
9 12 1814
|
9 12 1814
|
||||||
9 13 1662
|
9 13 1662
|
||||||
9 14 1527
|
9 14 1527
|
||||||
9 15 1406
|
9 15 1406
|
||||||
#
|
#
|
||||||
# Temperature (°C/°F)
|
# Temperature (°C/°F)
|
||||||
#10 0 30/86
|
#10 0 30/86
|
||||||
#10 1 33/91
|
#10 1 33/91
|
||||||
#10 2 36/96
|
#10 2 36/96
|
||||||
#10 3 39/102
|
#10 3 39/102
|
||||||
#10 4 42/107
|
#10 4 42/107
|
||||||
#10 5 45/113
|
#10 5 45/113
|
||||||
#10 6 48/118
|
#10 6 48/118
|
||||||
#10 7 51/123
|
#10 7 51/123
|
||||||
#10 8 54/129
|
#10 8 54/129
|
||||||
#10 9 57/134
|
#10 9 57/134
|
||||||
#10 10 60/140
|
#10 10 60/140
|
||||||
#10 11 63/145
|
#10 11 63/145
|
||||||
#10 12 66/150
|
#10 12 66/150
|
||||||
#10 13 69/156
|
#10 13 69/156
|
||||||
#10 14 72/161
|
#10 14 72/161
|
||||||
#10 15 75/167
|
#10 15 75/167
|
||||||
11 0 No
|
11 0 No
|
||||||
11 1 Yes
|
11 1 Yes
|
||||||
12 0 1M
|
12 0 1M
|
||||||
12 1 4M
|
12 1 4M
|
||||||
12 2 8M
|
12 2 8M
|
||||||
12 3 16M
|
12 3 16M
|
||||||
12 4 32M
|
12 4 32M
|
||||||
12 5 48M
|
12 5 48M
|
||||||
12 6 64M
|
12 6 64M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -3,55 +3,55 @@
|
|||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 3 debug_level
|
395 4 e 3 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
|
|
||||||
# coreboot config options: pch
|
# coreboot config options: pch
|
||||||
408 2 e 4 power_on_after_fail
|
408 2 e 4 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: mainboard
|
# coreboot config options: mainboard
|
||||||
440 1 e 2 ethernet1
|
440 1 e 2 ethernet1
|
||||||
441 1 e 2 ethernet2
|
441 1 e 2 ethernet2
|
||||||
442 1 e 2 ethernet3
|
442 1 e 2 ethernet3
|
||||||
|
|
||||||
# payload config options
|
# payload config options
|
||||||
512 256 s 0 boot_devices
|
512 256 s 0 boot_devices
|
||||||
768 8 h 0 boot_default
|
768 8 h 0 boot_default
|
||||||
776 1 e 1 cmos_defaults_loaded
|
776 1 e 1 cmos_defaults_loaded
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 No
|
1 0 No
|
||||||
1 1 Yes
|
1 1 Yes
|
||||||
2 0 Disable
|
2 0 Disable
|
||||||
2 1 Enable
|
2 1 Enable
|
||||||
3 1 Emergency
|
3 1 Emergency
|
||||||
3 2 Alert
|
3 2 Alert
|
||||||
3 3 Critical
|
3 3 Critical
|
||||||
3 4 Error
|
3 4 Error
|
||||||
3 5 Warning
|
3 5 Warning
|
||||||
3 6 Notice
|
3 6 Notice
|
||||||
3 7 Info
|
3 7 Info
|
||||||
3 8 Debug
|
3 8 Debug
|
||||||
3 9 Spew
|
3 9 Spew
|
||||||
4 0 Disable
|
4 0 Disable
|
||||||
4 1 Enable
|
4 1 Enable
|
||||||
4 2 Keep
|
4 2 Keep
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,101 +4,101 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
400 1 e 2 hyper_threading
|
400 1 e 2 hyper_threading
|
||||||
401 3 e 12 gfx_uma_size
|
401 3 e 12 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
407 1 e 1 nmi
|
407 1 e 1 nmi
|
||||||
408 2 e 7 power_on_after_fail
|
408 2 e 7 power_on_after_fail
|
||||||
410 2 e 11 sata_mode
|
410 2 e 11 sata_mode
|
||||||
|
|
||||||
# coreboot config options: additional mainboard options
|
# coreboot config options: additional mainboard options
|
||||||
412 4 e 10 systemp_type
|
412 4 e 10 systemp_type
|
||||||
416 7 h 0 fan1_min
|
416 7 h 0 fan1_min
|
||||||
424 7 h 0 fan1_max
|
424 7 h 0 fan1_max
|
||||||
432 7 h 0 fan2_min
|
432 7 h 0 fan2_min
|
||||||
440 7 h 0 fan2_max
|
440 7 h 0 fan2_max
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
448 64 r 0 write_protected_by_bios
|
448 64 r 0 write_protected_by_bios
|
||||||
512 328 s 0 boot_devices
|
512 328 s 0 boot_devices
|
||||||
840 8 h 0 boot_default
|
840 8 h 0 boot_default
|
||||||
848 1 e 9 cmos_defaults_loaded
|
848 1 e 9 cmos_defaults_loaded
|
||||||
849 1 e 2 ethernet1
|
849 1 e 2 ethernet1
|
||||||
850 1 e 2 ethernet2
|
850 1 e 2 ethernet2
|
||||||
|
|
||||||
# coreboot config options: mainboard specific options
|
# coreboot config options: mainboard specific options
|
||||||
856 2 e 8 fan1_mode
|
856 2 e 8 fan1_mode
|
||||||
858 2 r 0 fan1_reserved
|
858 2 r 0 fan1_reserved
|
||||||
860 2 e 8 fan2_mode
|
860 2 e 8 fan2_mode
|
||||||
862 2 r 0 fan2_reserved
|
862 2 r 0 fan2_reserved
|
||||||
864 16 h 0 fan1_target
|
864 16 h 0 fan1_target
|
||||||
880 16 h 0 fan2_target
|
880 16 h 0 fan2_target
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 Auto
|
8 0 Auto
|
||||||
8 1 PWM
|
8 1 PWM
|
||||||
8 2 Speed
|
8 2 Speed
|
||||||
8 3 Thermal
|
8 3 Thermal
|
||||||
9 0 No
|
9 0 No
|
||||||
9 1 Yes
|
9 1 Yes
|
||||||
10 0 None
|
10 0 None
|
||||||
10 1 AMD
|
10 1 AMD
|
||||||
10 2 LM75@90
|
10 2 LM75@90
|
||||||
10 3 GPIO16
|
10 3 GPIO16
|
||||||
10 4 LM75@9e
|
10 4 LM75@9e
|
||||||
11 0 AHCI
|
11 0 AHCI
|
||||||
11 1 Compatible
|
11 1 Compatible
|
||||||
11 2 Legacy
|
11 2 Legacy
|
||||||
12 0 32M
|
12 0 32M
|
||||||
12 1 64M
|
12 1 64M
|
||||||
12 2 96M
|
12 2 96M
|
||||||
12 3 128M
|
12 3 128M
|
||||||
12 4 160M
|
12 4 160M
|
||||||
12 5 192M
|
12 5 192M
|
||||||
12 6 224M
|
12 6 224M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -5,50 +5,50 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
#400 8 r 8 reserved for century byte
|
#400 8 r 8 reserved for century byte
|
||||||
408 1 e 1 power_on_after_fail
|
408 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
@@ -4,91 +4,91 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: EC
|
# coreboot config options: EC
|
||||||
411 1 e 8 first_battery
|
411 1 e 8 first_battery
|
||||||
412 1 e 1 bluetooth
|
412 1 e 1 bluetooth
|
||||||
413 1 e 1 wwan
|
413 1 e 1 wwan
|
||||||
414 1 e 1 touchpad
|
414 1 e 1 touchpad
|
||||||
415 1 e 1 wlan
|
415 1 e 1 wlan
|
||||||
416 1 e 1 trackpoint
|
416 1 e 1 trackpoint
|
||||||
417 1 e 1 fn_ctrl_swap
|
417 1 e 1 fn_ctrl_swap
|
||||||
418 1 e 1 sticky_fn
|
418 1 e 1 sticky_fn
|
||||||
419 2 e 12 usb_always_on
|
419 2 e 12 usb_always_on
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
422 2 e 10 backlight
|
422 2 e 10 backlight
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
440 8 h 0 volume
|
440 8 h 0 volume
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 Secondary
|
8 0 Secondary
|
||||||
8 1 Primary
|
8 1 Primary
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 Compatible
|
9 1 Compatible
|
||||||
10 0 Both
|
10 0 Both
|
||||||
10 1 Keyboard only
|
10 1 Keyboard only
|
||||||
10 2 Thinklight only
|
10 2 Thinklight only
|
||||||
10 3 None
|
10 3 None
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
12 0 Disable
|
12 0 Disable
|
||||||
12 1 AC and battery
|
12 1 AC and battery
|
||||||
12 2 AC only
|
12 2 AC only
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,94 +4,94 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 10 sata_mode
|
408 1 e 10 sata_mode
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: EC
|
# coreboot config options: EC
|
||||||
411 1 e 9 first_battery
|
411 1 e 9 first_battery
|
||||||
412 1 e 1 bluetooth
|
412 1 e 1 bluetooth
|
||||||
413 1 e 1 wwan
|
413 1 e 1 wwan
|
||||||
414 1 e 1 wlan
|
414 1 e 1 wlan
|
||||||
415 1 e 1 trackpoint
|
415 1 e 1 trackpoint
|
||||||
416 8 h 0 volume
|
416 8 h 0 volume
|
||||||
424 1 e 1 fn_ctrl_swap
|
424 1 e 1 fn_ctrl_swap
|
||||||
425 1 e 1 sticky_fn
|
425 1 e 1 sticky_fn
|
||||||
426 1 e 1 power_management_beeps
|
426 1 e 1 power_management_beeps
|
||||||
427 1 e 1 low_battery_beep
|
427 1 e 1 low_battery_beep
|
||||||
428 1 e 1 uwb
|
428 1 e 1 uwb
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
432 512 s 0 boot_devices
|
432 512 s 0 boot_devices
|
||||||
944 8 h 0 boot_default
|
944 8 h 0 boot_default
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
952 2 e 12 hybrid_graphics_mode
|
952 2 e 12 hybrid_graphics_mode
|
||||||
954 4 e 11 gfx_uma_size
|
954 4 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# RAM initialization internal data
|
# RAM initialization internal data
|
||||||
1024 128 r 0 read_training_results
|
1024 128 r 0 read_training_results
|
||||||
|
|
||||||
# VBOOT
|
# VBOOT
|
||||||
1152 128 r 0 vbnv
|
1152 128 r 0 vbnv
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 No
|
8 0 No
|
||||||
8 1 Yes
|
8 1 Yes
|
||||||
9 0 Secondary
|
9 0 Secondary
|
||||||
9 1 Primary
|
9 1 Primary
|
||||||
10 0 AHCI
|
10 0 AHCI
|
||||||
10 1 Compatible
|
10 1 Compatible
|
||||||
11 4 32M
|
11 4 32M
|
||||||
11 5 48M
|
11 5 48M
|
||||||
11 6 64M
|
11 6 64M
|
||||||
11 7 128M
|
11 7 128M
|
||||||
11 8 256M
|
11 8 256M
|
||||||
11 9 96M
|
11 9 96M
|
||||||
11 10 160M
|
11 10 160M
|
||||||
11 11 224M
|
11 11 224M
|
||||||
11 12 352M
|
11 12 352M
|
||||||
12 0 Integrated Only
|
12 0 Integrated Only
|
||||||
12 1 Discrete Only
|
12 1 Discrete Only
|
||||||
12 2 Dual Graphics
|
12 2 Dual Graphics
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,85 +4,85 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: EC
|
# coreboot config options: EC
|
||||||
411 1 e 8 first_battery
|
411 1 e 8 first_battery
|
||||||
412 1 e 1 bluetooth
|
412 1 e 1 bluetooth
|
||||||
413 1 e 1 wwan
|
413 1 e 1 wwan
|
||||||
414 1 e 1 touchpad
|
414 1 e 1 touchpad
|
||||||
415 1 e 1 wlan
|
415 1 e 1 wlan
|
||||||
416 1 e 1 trackpoint
|
416 1 e 1 trackpoint
|
||||||
417 1 e 1 fn_ctrl_swap
|
417 1 e 1 fn_ctrl_swap
|
||||||
418 1 e 1 sticky_fn
|
418 1 e 1 sticky_fn
|
||||||
419 1 e 1 power_management_beeps
|
419 1 e 1 power_management_beeps
|
||||||
420 1 e 1 low_battery_beep
|
420 1 e 1 low_battery_beep
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
422 2 e 11 usb_always_on
|
422 2 e 11 usb_always_on
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
424 3 e 10 gfx_uma_size
|
424 3 e 10 gfx_uma_size
|
||||||
432 2 e 12 hybrid_graphics_mode
|
432 2 e 12 hybrid_graphics_mode
|
||||||
|
|
||||||
# VBOOT
|
# VBOOT
|
||||||
448 128 r 0 vbnv
|
448 128 r 0 vbnv
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 Secondary
|
8 0 Secondary
|
||||||
8 1 Primary
|
8 1 Primary
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 Compatible
|
9 1 Compatible
|
||||||
10 0 32M
|
10 0 32M
|
||||||
10 1 48M
|
10 1 48M
|
||||||
10 2 64M
|
10 2 64M
|
||||||
10 3 128M
|
10 3 128M
|
||||||
10 5 96M
|
10 5 96M
|
||||||
10 6 160M
|
10 6 160M
|
||||||
11 0 Disable
|
11 0 Disable
|
||||||
11 1 AC and battery
|
11 1 AC and battery
|
||||||
11 2 AC only
|
11 2 AC only
|
||||||
12 0 Integrated Only
|
12 0 Integrated Only
|
||||||
12 1 Discrete Only
|
12 1 Discrete Only
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,99 +4,99 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: EC
|
# coreboot config options: EC
|
||||||
411 1 e 8 first_battery
|
411 1 e 8 first_battery
|
||||||
412 1 e 1 bluetooth
|
412 1 e 1 bluetooth
|
||||||
413 1 e 1 wwan
|
413 1 e 1 wwan
|
||||||
414 1 e 1 touchpad
|
414 1 e 1 touchpad
|
||||||
415 1 e 1 wlan
|
415 1 e 1 wlan
|
||||||
416 1 e 1 trackpoint
|
416 1 e 1 trackpoint
|
||||||
417 1 e 1 fn_ctrl_swap
|
417 1 e 1 fn_ctrl_swap
|
||||||
418 1 e 1 sticky_fn
|
418 1 e 1 sticky_fn
|
||||||
419 1 e 1 power_management_beeps
|
419 1 e 1 power_management_beeps
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
422 2 e 13 usb_always_on
|
422 2 e 13 usb_always_on
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
435 2 e 12 hybrid_graphics_mode
|
435 2 e 12 hybrid_graphics_mode
|
||||||
|
|
||||||
440 8 h 0 volume
|
440 8 h 0 volume
|
||||||
|
|
||||||
# VBOOT
|
# VBOOT
|
||||||
448 128 r 0 vbnv
|
448 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 Secondary
|
8 0 Secondary
|
||||||
8 1 Primary
|
8 1 Primary
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 Compatible
|
9 1 Compatible
|
||||||
10 0 Both
|
10 0 Both
|
||||||
10 1 Keyboard only
|
10 1 Keyboard only
|
||||||
10 2 Thinklight only
|
10 2 Thinklight only
|
||||||
10 3 None
|
10 3 None
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
12 0 Integrated Only
|
12 0 Integrated Only
|
||||||
12 1 Discrete Only
|
12 1 Discrete Only
|
||||||
12 2 Dual Graphics
|
12 2 Dual Graphics
|
||||||
13 0 Disable
|
13 0 Disable
|
||||||
13 1 AC and battery
|
13 1 AC and battery
|
||||||
13 2 AC only
|
13 2 AC only
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,99 +4,99 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: EC
|
# coreboot config options: EC
|
||||||
411 1 e 8 first_battery
|
411 1 e 8 first_battery
|
||||||
412 1 e 1 bluetooth
|
412 1 e 1 bluetooth
|
||||||
413 1 e 1 wwan
|
413 1 e 1 wwan
|
||||||
414 1 e 1 touchpad
|
414 1 e 1 touchpad
|
||||||
415 1 e 1 wlan
|
415 1 e 1 wlan
|
||||||
416 1 e 1 trackpoint
|
416 1 e 1 trackpoint
|
||||||
417 1 e 1 fn_ctrl_swap
|
417 1 e 1 fn_ctrl_swap
|
||||||
418 1 e 1 sticky_fn
|
418 1 e 1 sticky_fn
|
||||||
419 1 e 1 power_management_beeps
|
419 1 e 1 power_management_beeps
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
422 2 e 13 usb_always_on
|
422 2 e 13 usb_always_on
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
435 2 e 12 hybrid_graphics_mode
|
435 2 e 12 hybrid_graphics_mode
|
||||||
|
|
||||||
440 8 h 0 volume
|
440 8 h 0 volume
|
||||||
|
|
||||||
# VBOOT
|
# VBOOT
|
||||||
448 128 r 0 vbnv
|
448 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 Secondary
|
8 0 Secondary
|
||||||
8 1 Primary
|
8 1 Primary
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 Compatible
|
9 1 Compatible
|
||||||
10 0 Both
|
10 0 Both
|
||||||
10 1 Keyboard only
|
10 1 Keyboard only
|
||||||
10 2 Thinklight only
|
10 2 Thinklight only
|
||||||
10 3 None
|
10 3 None
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
12 0 Integrated Only
|
12 0 Integrated Only
|
||||||
12 1 Discrete Only
|
12 1 Discrete Only
|
||||||
12 2 Dual Graphics
|
12 2 Dual Graphics
|
||||||
13 0 Disable
|
13 0 Disable
|
||||||
13 1 AC and battery
|
13 1 AC and battery
|
||||||
13 2 AC only
|
13 2 AC only
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,98 +4,98 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: EC
|
# coreboot config options: EC
|
||||||
411 1 e 8 first_battery
|
411 1 e 8 first_battery
|
||||||
412 1 e 1 bluetooth
|
412 1 e 1 bluetooth
|
||||||
413 1 e 1 wwan
|
413 1 e 1 wwan
|
||||||
414 1 e 1 touchpad
|
414 1 e 1 touchpad
|
||||||
415 1 e 1 wlan
|
415 1 e 1 wlan
|
||||||
416 1 e 1 trackpoint
|
416 1 e 1 trackpoint
|
||||||
417 1 e 1 fn_ctrl_swap
|
417 1 e 1 fn_ctrl_swap
|
||||||
418 1 e 1 sticky_fn
|
418 1 e 1 sticky_fn
|
||||||
419 2 e 13 usb_always_on
|
419 2 e 13 usb_always_on
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
422 2 e 10 backlight
|
422 2 e 10 backlight
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
435 2 e 12 hybrid_graphics_mode
|
435 2 e 12 hybrid_graphics_mode
|
||||||
440 8 h 0 volume
|
440 8 h 0 volume
|
||||||
|
|
||||||
# VBOOT
|
# VBOOT
|
||||||
448 128 r 0 vbnv
|
448 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 Secondary
|
8 0 Secondary
|
||||||
8 1 Primary
|
8 1 Primary
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 Compatible
|
9 1 Compatible
|
||||||
10 0 Both
|
10 0 Both
|
||||||
10 1 Keyboard only
|
10 1 Keyboard only
|
||||||
10 2 Thinklight only
|
10 2 Thinklight only
|
||||||
10 3 None
|
10 3 None
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
12 0 Integrated Only
|
12 0 Integrated Only
|
||||||
12 1 Discrete Only
|
12 1 Discrete Only
|
||||||
12 2 Dual Graphics
|
12 2 Dual Graphics
|
||||||
13 0 Disable
|
13 0 Disable
|
||||||
13 1 AC and battery
|
13 1 AC and battery
|
||||||
13 2 AC only
|
13 2 AC only
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,96 +4,96 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: EC
|
# coreboot config options: EC
|
||||||
411 1 e 8 first_battery
|
411 1 e 8 first_battery
|
||||||
412 1 e 1 bluetooth
|
412 1 e 1 bluetooth
|
||||||
413 1 e 1 wwan
|
413 1 e 1 wwan
|
||||||
414 1 e 1 touchpad
|
414 1 e 1 touchpad
|
||||||
415 1 e 1 wlan
|
415 1 e 1 wlan
|
||||||
416 1 e 1 trackpoint
|
416 1 e 1 trackpoint
|
||||||
417 1 e 1 fn_ctrl_swap
|
417 1 e 1 fn_ctrl_swap
|
||||||
418 1 e 1 sticky_fn
|
418 1 e 1 sticky_fn
|
||||||
419 2 e 12 usb_always_on
|
419 2 e 12 usb_always_on
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
422 2 e 10 backlight
|
422 2 e 10 backlight
|
||||||
424 1 e 1 f1_to_f12_as_primary
|
424 1 e 1 f1_to_f12_as_primary
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
435 1 e 1 enable_dual_graphics
|
435 1 e 1 enable_dual_graphics
|
||||||
440 8 h 0 volume
|
440 8 h 0 volume
|
||||||
|
|
||||||
# VBOOT
|
# VBOOT
|
||||||
448 128 r 0 vbnv
|
448 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 Secondary
|
8 0 Secondary
|
||||||
8 1 Primary
|
8 1 Primary
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 Compatible
|
9 1 Compatible
|
||||||
10 0 Both
|
10 0 Both
|
||||||
10 1 Keyboard only
|
10 1 Keyboard only
|
||||||
10 2 Thinklight only
|
10 2 Thinklight only
|
||||||
10 3 None
|
10 3 None
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
12 0 Disable
|
12 0 Disable
|
||||||
12 1 AC and battery
|
12 1 AC and battery
|
||||||
12 2 AC only
|
12 2 AC only
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,78 +4,78 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: EC
|
# coreboot config options: EC
|
||||||
411 1 e 8 first_battery
|
411 1 e 8 first_battery
|
||||||
415 1 e 1 wlan
|
415 1 e 1 wlan
|
||||||
416 1 e 1 trackpoint
|
416 1 e 1 trackpoint
|
||||||
417 1 e 1 fn_ctrl_swap
|
417 1 e 1 fn_ctrl_swap
|
||||||
418 1 e 1 sticky_fn
|
418 1 e 1 sticky_fn
|
||||||
419 2 e 13 usb_always_on
|
419 2 e 13 usb_always_on
|
||||||
422 2 e 10 backlight
|
422 2 e 10 backlight
|
||||||
424 1 e 1 f1_to_f12_as_primary
|
424 1 e 1 f1_to_f12_as_primary
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
435 1 e 1 enable_dual_graphics
|
435 1 e 1 enable_dual_graphics
|
||||||
440 8 h 0 volume
|
440 8 h 0 volume
|
||||||
|
|
||||||
# VBOOT
|
# VBOOT
|
||||||
448 128 r 0 vbnv
|
448 128 r 0 vbnv
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 Secondary
|
8 0 Secondary
|
||||||
8 1 Primary
|
8 1 Primary
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 Compatible
|
9 1 Compatible
|
||||||
# Haswell ThinkPads have no Thinklight
|
# Haswell ThinkPads have no Thinklight
|
||||||
#10 0 Both
|
#10 0 Both
|
||||||
10 1 Keyboard
|
10 1 Keyboard
|
||||||
#10 2 Thinklight only
|
#10 2 Thinklight only
|
||||||
10 3 None
|
10 3 None
|
||||||
13 0 Disable
|
13 0 Disable
|
||||||
13 1 AC and battery
|
13 1 AC and battery
|
||||||
13 2 AC only
|
13 2 AC only
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,98 +4,98 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: EC
|
# coreboot config options: EC
|
||||||
411 1 e 8 first_battery
|
411 1 e 8 first_battery
|
||||||
412 1 e 1 bluetooth
|
412 1 e 1 bluetooth
|
||||||
413 1 e 1 wwan
|
413 1 e 1 wwan
|
||||||
414 1 e 1 touchpad
|
414 1 e 1 touchpad
|
||||||
415 1 e 1 wlan
|
415 1 e 1 wlan
|
||||||
416 1 e 1 trackpoint
|
416 1 e 1 trackpoint
|
||||||
417 1 e 1 fn_ctrl_swap
|
417 1 e 1 fn_ctrl_swap
|
||||||
418 1 e 1 sticky_fn
|
418 1 e 1 sticky_fn
|
||||||
419 2 e 13 usb_always_on
|
419 2 e 13 usb_always_on
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
422 2 e 10 backlight
|
422 2 e 10 backlight
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
435 2 e 12 hybrid_graphics_mode
|
435 2 e 12 hybrid_graphics_mode
|
||||||
440 8 h 0 volume
|
440 8 h 0 volume
|
||||||
|
|
||||||
# VBOOT
|
# VBOOT
|
||||||
448 128 r 0 vbnv
|
448 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 Secondary
|
8 0 Secondary
|
||||||
8 1 Primary
|
8 1 Primary
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 Compatible
|
9 1 Compatible
|
||||||
10 0 Both
|
10 0 Both
|
||||||
10 1 Keyboard only
|
10 1 Keyboard only
|
||||||
10 2 Thinklight only
|
10 2 Thinklight only
|
||||||
10 3 None
|
10 3 None
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
12 0 Integrated Only
|
12 0 Integrated Only
|
||||||
12 1 Discrete Only
|
12 1 Discrete Only
|
||||||
12 2 Dual Graphics
|
12 2 Dual Graphics
|
||||||
13 0 Disable
|
13 0 Disable
|
||||||
13 1 AC and battery
|
13 1 AC and battery
|
||||||
13 2 AC only
|
13 2 AC only
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,99 +4,99 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: EC
|
# coreboot config options: EC
|
||||||
411 1 e 8 first_battery
|
411 1 e 8 first_battery
|
||||||
412 1 e 1 bluetooth
|
412 1 e 1 bluetooth
|
||||||
413 1 e 1 wwan
|
413 1 e 1 wwan
|
||||||
414 1 e 1 touchpad
|
414 1 e 1 touchpad
|
||||||
415 1 e 1 wlan
|
415 1 e 1 wlan
|
||||||
416 1 e 1 trackpoint
|
416 1 e 1 trackpoint
|
||||||
417 1 e 1 fn_ctrl_swap
|
417 1 e 1 fn_ctrl_swap
|
||||||
418 1 e 1 sticky_fn
|
418 1 e 1 sticky_fn
|
||||||
419 2 e 13 usb_always_on
|
419 2 e 13 usb_always_on
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
422 2 e 10 backlight
|
422 2 e 10 backlight
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
435 2 e 12 hybrid_graphics_mode
|
435 2 e 12 hybrid_graphics_mode
|
||||||
|
|
||||||
440 8 h 0 volume
|
440 8 h 0 volume
|
||||||
|
|
||||||
# VBOOT
|
# VBOOT
|
||||||
448 128 r 0 vbnv
|
448 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 Secondary
|
8 0 Secondary
|
||||||
8 1 Primary
|
8 1 Primary
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 Compatible
|
9 1 Compatible
|
||||||
10 0 Both
|
10 0 Both
|
||||||
10 1 Keyboard only
|
10 1 Keyboard only
|
||||||
10 2 Thinklight only
|
10 2 Thinklight only
|
||||||
10 3 None
|
10 3 None
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
12 0 Integrated Only
|
12 0 Integrated Only
|
||||||
12 1 Discrete Only
|
12 1 Discrete Only
|
||||||
12 2 Dual Graphics
|
12 2 Dual Graphics
|
||||||
13 0 Disable
|
13 0 Disable
|
||||||
13 1 AC and battery
|
13 1 AC and battery
|
||||||
13 2 AC only
|
13 2 AC only
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,90 +4,90 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
#409 2 e 7 power_on_after_fail
|
#409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
411 3 e 11 gfx_uma_size
|
411 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
416 512 s 0 boot_devices
|
416 512 s 0 boot_devices
|
||||||
928 8 h 0 boot_default
|
928 8 h 0 boot_default
|
||||||
936 1 e 8 cmos_defaults_loaded
|
936 1 e 8 cmos_defaults_loaded
|
||||||
937 1 e 1 lpt
|
937 1 e 1 lpt
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: ec
|
# coreboot config options: ec
|
||||||
948 1 e 1 touchpad
|
948 1 e 1 touchpad
|
||||||
949 1 e 1 bluetooth
|
949 1 e 1 bluetooth
|
||||||
950 1 e 1 wwan
|
950 1 e 1 wwan
|
||||||
951 1 e 1 wlan
|
951 1 e 1 wlan
|
||||||
952 8 h 0 volume
|
952 8 h 0 volume
|
||||||
960 1 e 9 first_battery
|
960 1 e 9 first_battery
|
||||||
961 1 e 1 trackpoint
|
961 1 e 1 trackpoint
|
||||||
963 1 e 1 sticky_fn
|
963 1 e 1 sticky_fn
|
||||||
964 1 e 1 power_management_beeps
|
964 1 e 1 power_management_beeps
|
||||||
965 1 e 1 low_battery_beep
|
965 1 e 1 low_battery_beep
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# RAM initialization internal data
|
# RAM initialization internal data
|
||||||
1024 8 r 0 C0WL0REOST
|
1024 8 r 0 C0WL0REOST
|
||||||
1032 8 r 0 C1WL0REOST
|
1032 8 r 0 C1WL0REOST
|
||||||
1040 8 r 0 RCVENMT
|
1040 8 r 0 RCVENMT
|
||||||
1048 4 r 0 C0DRT1
|
1048 4 r 0 C0DRT1
|
||||||
1052 4 r 0 C1DRT1
|
1052 4 r 0 C1DRT1
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 No
|
8 0 No
|
||||||
8 1 Yes
|
8 1 Yes
|
||||||
9 0 Secondary
|
9 0 Secondary
|
||||||
9 1 Primary
|
9 1 Primary
|
||||||
11 0 1M
|
11 0 1M
|
||||||
11 1 4M
|
11 1 4M
|
||||||
11 2 8M
|
11 2 8M
|
||||||
11 3 16M
|
11 3 16M
|
||||||
11 4 32M
|
11 4 32M
|
||||||
11 5 48M
|
11 5 48M
|
||||||
11 6 64M
|
11 6 64M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,59 +4,59 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 4 e 11 gfx_uma_size
|
432 4 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 1 Emergency
|
6 1 Emergency
|
||||||
6 2 Alert
|
6 2 Alert
|
||||||
6 3 Critical
|
6 3 Critical
|
||||||
6 4 Error
|
6 4 Error
|
||||||
6 5 Warning
|
6 5 Warning
|
||||||
6 6 Notice
|
6 6 Notice
|
||||||
6 7 Info
|
6 7 Info
|
||||||
6 8 Debug
|
6 8 Debug
|
||||||
6 9 Spew
|
6 9 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
11 6 64M
|
11 6 64M
|
||||||
11 7 128M
|
11 7 128M
|
||||||
11 8 256M
|
11 8 256M
|
||||||
11 9 96M
|
11 9 96M
|
||||||
11 10 160M
|
11 10 160M
|
||||||
11 11 224M
|
11 11 224M
|
||||||
11 12 352M
|
11 12 352M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,87 +4,87 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
411 1 e 8 sata_mode
|
411 1 e 8 sata_mode
|
||||||
|
|
||||||
# coreboot config options: EC
|
# coreboot config options: EC
|
||||||
412 1 e 1 bluetooth
|
412 1 e 1 bluetooth
|
||||||
413 1 e 1 wwan
|
413 1 e 1 wwan
|
||||||
414 1 e 1 touchpad
|
414 1 e 1 touchpad
|
||||||
415 1 e 1 wlan
|
415 1 e 1 wlan
|
||||||
416 1 e 1 trackpoint
|
416 1 e 1 trackpoint
|
||||||
417 1 e 1 fn_ctrl_swap
|
417 1 e 1 fn_ctrl_swap
|
||||||
418 1 e 1 sticky_fn
|
418 1 e 1 sticky_fn
|
||||||
419 2 e 12 usb_always_on
|
419 2 e 12 usb_always_on
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
440 8 h 0 volume
|
440 8 h 0 volume
|
||||||
|
|
||||||
# VBOOT
|
# VBOOT
|
||||||
448 128 r 0 vbnv
|
448 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 AHCI
|
8 0 AHCI
|
||||||
8 1 Compatible
|
8 1 Compatible
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
12 0 Disable
|
12 0 Disable
|
||||||
12 1 AC and battery
|
12 1 AC and battery
|
||||||
12 2 AC only
|
12 2 AC only
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,95 +4,95 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: EC
|
# coreboot config options: EC
|
||||||
411 1 e 8 first_battery
|
411 1 e 8 first_battery
|
||||||
412 1 e 1 bluetooth
|
412 1 e 1 bluetooth
|
||||||
413 1 e 1 wwan
|
413 1 e 1 wwan
|
||||||
414 1 e 1 touchpad
|
414 1 e 1 touchpad
|
||||||
415 1 e 1 wlan
|
415 1 e 1 wlan
|
||||||
416 1 e 1 trackpoint
|
416 1 e 1 trackpoint
|
||||||
417 1 e 1 fn_ctrl_swap
|
417 1 e 1 fn_ctrl_swap
|
||||||
418 1 e 1 sticky_fn
|
418 1 e 1 sticky_fn
|
||||||
419 2 e 12 usb_always_on
|
419 2 e 12 usb_always_on
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
422 2 e 10 backlight
|
422 2 e 10 backlight
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
440 8 h 0 volume
|
440 8 h 0 volume
|
||||||
|
|
||||||
# VBOOT
|
# VBOOT
|
||||||
448 128 r 0 vbnv
|
448 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 Secondary
|
8 0 Secondary
|
||||||
8 1 Primary
|
8 1 Primary
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 Compatible
|
9 1 Compatible
|
||||||
10 0 Both
|
10 0 Both
|
||||||
10 1 Keyboard only
|
10 1 Keyboard only
|
||||||
10 2 Thinklight only
|
10 2 Thinklight only
|
||||||
10 3 None
|
10 3 None
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
12 0 Disable
|
12 0 Disable
|
||||||
12 1 AC and battery
|
12 1 AC and battery
|
||||||
12 2 AC only
|
12 2 AC only
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,90 +4,90 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 10 sata_mode
|
408 1 e 10 sata_mode
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: EC
|
# coreboot config options: EC
|
||||||
411 1 e 9 first_battery
|
411 1 e 9 first_battery
|
||||||
412 1 e 1 bluetooth
|
412 1 e 1 bluetooth
|
||||||
413 1 e 1 wwan
|
413 1 e 1 wwan
|
||||||
414 1 e 1 wlan
|
414 1 e 1 wlan
|
||||||
415 1 e 1 trackpoint
|
415 1 e 1 trackpoint
|
||||||
416 8 h 0 volume
|
416 8 h 0 volume
|
||||||
424 1 e 1 fn_ctrl_swap
|
424 1 e 1 fn_ctrl_swap
|
||||||
425 1 e 1 sticky_fn
|
425 1 e 1 sticky_fn
|
||||||
426 1 e 1 power_management_beeps
|
426 1 e 1 power_management_beeps
|
||||||
427 1 e 1 low_battery_beep
|
427 1 e 1 low_battery_beep
|
||||||
428 1 e 1 uwb
|
428 1 e 1 uwb
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
432 512 s 0 boot_devices
|
432 512 s 0 boot_devices
|
||||||
944 8 h 0 boot_default
|
944 8 h 0 boot_default
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
952 4 e 11 gfx_uma_size
|
952 4 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# RAM initialization internal data
|
# RAM initialization internal data
|
||||||
1024 128 r 0 read_training_results
|
1024 128 r 0 read_training_results
|
||||||
|
|
||||||
# VBOOT
|
# VBOOT
|
||||||
1152 128 r 0 vbnv
|
1152 128 r 0 vbnv
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 No
|
8 0 No
|
||||||
8 1 Yes
|
8 1 Yes
|
||||||
9 0 Secondary
|
9 0 Secondary
|
||||||
9 1 Primary
|
9 1 Primary
|
||||||
10 0 AHCI
|
10 0 AHCI
|
||||||
10 1 Compatible
|
10 1 Compatible
|
||||||
11 4 32M
|
11 4 32M
|
||||||
11 5 48M
|
11 5 48M
|
||||||
11 6 64M
|
11 6 64M
|
||||||
11 7 128M
|
11 7 128M
|
||||||
11 8 256M
|
11 8 256M
|
||||||
11 9 96M
|
11 9 96M
|
||||||
11 10 160M
|
11 10 160M
|
||||||
11 11 224M
|
11 11 224M
|
||||||
11 12 352M
|
11 12 352M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,83 +4,83 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: EC
|
# coreboot config options: EC
|
||||||
411 1 e 8 first_battery
|
411 1 e 8 first_battery
|
||||||
412 1 e 1 bluetooth
|
412 1 e 1 bluetooth
|
||||||
413 1 e 1 wwan
|
413 1 e 1 wwan
|
||||||
414 1 e 1 touchpad
|
414 1 e 1 touchpad
|
||||||
415 1 e 1 wlan
|
415 1 e 1 wlan
|
||||||
416 1 e 1 trackpoint
|
416 1 e 1 trackpoint
|
||||||
417 1 e 1 fn_ctrl_swap
|
417 1 e 1 fn_ctrl_swap
|
||||||
418 1 e 1 sticky_fn
|
418 1 e 1 sticky_fn
|
||||||
419 1 e 1 power_management_beeps
|
419 1 e 1 power_management_beeps
|
||||||
420 1 e 1 low_battery_beep
|
420 1 e 1 low_battery_beep
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
422 2 e 11 usb_always_on
|
422 2 e 11 usb_always_on
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
424 3 e 10 gfx_uma_size
|
424 3 e 10 gfx_uma_size
|
||||||
432 8 h 0 volume
|
432 8 h 0 volume
|
||||||
|
|
||||||
# VBOOT
|
# VBOOT
|
||||||
448 128 r 0 vbnv
|
448 128 r 0 vbnv
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 Secondary
|
8 0 Secondary
|
||||||
8 1 Primary
|
8 1 Primary
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 Compatible
|
9 1 Compatible
|
||||||
10 0 32M
|
10 0 32M
|
||||||
10 1 48M
|
10 1 48M
|
||||||
10 2 64M
|
10 2 64M
|
||||||
10 3 128M
|
10 3 128M
|
||||||
10 5 96M
|
10 5 96M
|
||||||
10 6 160M
|
10 6 160M
|
||||||
11 0 Disable
|
11 0 Disable
|
||||||
11 1 AC and battery
|
11 1 AC and battery
|
||||||
11 2 AC only
|
11 2 AC only
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,94 +4,94 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: EC
|
# coreboot config options: EC
|
||||||
411 1 e 8 first_battery
|
411 1 e 8 first_battery
|
||||||
412 1 e 1 bluetooth
|
412 1 e 1 bluetooth
|
||||||
413 1 e 1 wwan
|
413 1 e 1 wwan
|
||||||
414 1 e 1 touchpad
|
414 1 e 1 touchpad
|
||||||
415 1 e 1 wlan
|
415 1 e 1 wlan
|
||||||
416 1 e 1 trackpoint
|
416 1 e 1 trackpoint
|
||||||
417 1 e 1 fn_ctrl_swap
|
417 1 e 1 fn_ctrl_swap
|
||||||
418 1 e 1 sticky_fn
|
418 1 e 1 sticky_fn
|
||||||
419 1 e 1 power_management_beeps
|
419 1 e 1 power_management_beeps
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
422 2 e 12 usb_always_on
|
422 2 e 12 usb_always_on
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
440 8 h 0 volume
|
440 8 h 0 volume
|
||||||
|
|
||||||
# VBOOT
|
# VBOOT
|
||||||
448 128 r 0 vbnv
|
448 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 Secondary
|
8 0 Secondary
|
||||||
8 1 Primary
|
8 1 Primary
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 Compatible
|
9 1 Compatible
|
||||||
10 0 Both
|
10 0 Both
|
||||||
10 1 Keyboard only
|
10 1 Keyboard only
|
||||||
10 2 Thinklight only
|
10 2 Thinklight only
|
||||||
10 3 None
|
10 3 None
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
12 0 Disable
|
12 0 Disable
|
||||||
12 1 AC and battery
|
12 1 AC and battery
|
||||||
12 2 AC only
|
12 2 AC only
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,96 +4,96 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
409 2 e 7 power_on_after_fail
|
409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: EC
|
# coreboot config options: EC
|
||||||
411 1 e 8 first_battery
|
411 1 e 8 first_battery
|
||||||
412 1 e 1 bluetooth
|
412 1 e 1 bluetooth
|
||||||
413 1 e 1 wwan
|
413 1 e 1 wwan
|
||||||
414 1 e 1 touchpad
|
414 1 e 1 touchpad
|
||||||
415 1 e 1 wlan
|
415 1 e 1 wlan
|
||||||
416 1 e 1 trackpoint
|
416 1 e 1 trackpoint
|
||||||
417 1 e 1 fn_ctrl_swap
|
417 1 e 1 fn_ctrl_swap
|
||||||
418 1 e 1 sticky_fn
|
418 1 e 1 sticky_fn
|
||||||
419 2 e 12 usb_always_on
|
419 2 e 12 usb_always_on
|
||||||
421 1 e 9 sata_mode
|
421 1 e 9 sata_mode
|
||||||
422 2 e 10 backlight
|
422 2 e 10 backlight
|
||||||
424 1 e 1 f1_to_f12_as_primary
|
424 1 e 1 f1_to_f12_as_primary
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
432 3 e 11 gfx_uma_size
|
432 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
440 8 h 0 volume
|
440 8 h 0 volume
|
||||||
|
|
||||||
# VBOOT
|
# VBOOT
|
||||||
448 128 r 0 vbnv
|
448 128 r 0 vbnv
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
# SandyBridge MRC Scrambler Seed values
|
||||||
896 32 r 0 mrc_scrambler_seed
|
896 32 r 0 mrc_scrambler_seed
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
928 32 r 0 mrc_scrambler_seed_s3
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
960 16 r 0 mrc_scrambler_seed_chk
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 Secondary
|
8 0 Secondary
|
||||||
8 1 Primary
|
8 1 Primary
|
||||||
9 0 AHCI
|
9 0 AHCI
|
||||||
9 1 Compatible
|
9 1 Compatible
|
||||||
10 0 Both
|
10 0 Both
|
||||||
10 1 Keyboard only
|
10 1 Keyboard only
|
||||||
10 2 Thinklight only
|
10 2 Thinklight only
|
||||||
10 3 None
|
10 3 None
|
||||||
11 0 32M
|
11 0 32M
|
||||||
11 1 64M
|
11 1 64M
|
||||||
11 2 96M
|
11 2 96M
|
||||||
11 3 128M
|
11 3 128M
|
||||||
11 4 160M
|
11 4 160M
|
||||||
11 5 192M
|
11 5 192M
|
||||||
11 6 224M
|
11 6 224M
|
||||||
12 0 Disable
|
12 0 Disable
|
||||||
12 1 AC and battery
|
12 1 AC and battery
|
||||||
12 2 AC only
|
12 2 AC only
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -4,91 +4,91 @@
|
|||||||
entries
|
entries
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
0 120 r 0 reserved_memory
|
0 120 r 0 reserved_memory
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
# coreboot config options: console
|
# coreboot config options: console
|
||||||
395 4 e 6 debug_level
|
395 4 e 6 debug_level
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
#400 8 r 0 reserved for century byte
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
# coreboot config options: southbridge
|
||||||
408 1 e 1 nmi
|
408 1 e 1 nmi
|
||||||
#409 2 e 7 power_on_after_fail
|
#409 2 e 7 power_on_after_fail
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
# coreboot config options: northbridge
|
||||||
411 3 e 11 gfx_uma_size
|
411 3 e 11 gfx_uma_size
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
# coreboot config options: bootloader
|
||||||
416 512 s 0 boot_devices
|
416 512 s 0 boot_devices
|
||||||
928 8 h 0 boot_default
|
928 8 h 0 boot_default
|
||||||
936 1 e 8 cmos_defaults_loaded
|
936 1 e 8 cmos_defaults_loaded
|
||||||
937 1 e 1 lpt
|
937 1 e 1 lpt
|
||||||
|
|
||||||
# coreboot config options: cpu
|
# coreboot config options: cpu
|
||||||
|
|
||||||
# coreboot config options: ec
|
# coreboot config options: ec
|
||||||
949 1 e 9 first_battery
|
949 1 e 9 first_battery
|
||||||
950 1 e 1 bluetooth
|
950 1 e 1 bluetooth
|
||||||
951 1 e 1 wwan
|
951 1 e 1 wwan
|
||||||
952 1 e 1 wlan
|
952 1 e 1 wlan
|
||||||
953 1 e 1 trackpoint
|
953 1 e 1 trackpoint
|
||||||
955 1 e 1 sticky_fn
|
955 1 e 1 sticky_fn
|
||||||
956 1 e 1 power_management_beeps
|
956 1 e 1 power_management_beeps
|
||||||
959 1 e 1 low_battery_beep
|
959 1 e 1 low_battery_beep
|
||||||
960 8 h 0 volume
|
960 8 h 0 volume
|
||||||
968 8 h 0 tft_brightness
|
968 8 h 0 tft_brightness
|
||||||
|
|
||||||
# coreboot config options: check sums
|
# coreboot config options: check sums
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
|
|
||||||
# RAM initialization internal data
|
# RAM initialization internal data
|
||||||
1024 8 r 0 C0WL0REOST
|
1024 8 r 0 C0WL0REOST
|
||||||
1032 8 r 0 C1WL0REOST
|
1032 8 r 0 C1WL0REOST
|
||||||
1040 8 r 0 RCVENMT
|
1040 8 r 0 RCVENMT
|
||||||
1048 4 r 0 C0DRT1
|
1048 4 r 0 C0DRT1
|
||||||
1052 4 r 0 C1DRT1
|
1052 4 r 0 C1DRT1
|
||||||
|
|
||||||
1056 128 r 0 vbnv
|
1056 128 r 0 vbnv
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 0 Emergency
|
6 0 Emergency
|
||||||
6 1 Alert
|
6 1 Alert
|
||||||
6 2 Critical
|
6 2 Critical
|
||||||
6 3 Error
|
6 3 Error
|
||||||
6 4 Warning
|
6 4 Warning
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
7 0 Disable
|
7 0 Disable
|
||||||
7 1 Enable
|
7 1 Enable
|
||||||
7 2 Keep
|
7 2 Keep
|
||||||
8 0 No
|
8 0 No
|
||||||
8 1 Yes
|
8 1 Yes
|
||||||
9 0 Secondary
|
9 0 Secondary
|
||||||
9 1 Primary
|
9 1 Primary
|
||||||
11 0 1M
|
11 0 1M
|
||||||
11 1 4M
|
11 1 4M
|
||||||
11 2 8M
|
11 2 8M
|
||||||
11 3 16M
|
11 3 16M
|
||||||
11 4 32M
|
11 4 32M
|
||||||
11 5 48M
|
11 5 48M
|
||||||
11 6 64M
|
11 6 64M
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
||||||
checksums
|
checksums
|
||||||
|
|||||||
@@ -5,49 +5,49 @@
|
|||||||
|
|
||||||
entries
|
entries
|
||||||
|
|
||||||
0 384 r 0 reserved_memory
|
0 384 r 0 reserved_memory
|
||||||
384 1 e 4 boot_option
|
384 1 e 4 boot_option
|
||||||
388 4 h 0 reboot_counter
|
388 4 h 0 reboot_counter
|
||||||
395 1 e 1 hw_scrubber
|
395 1 e 1 hw_scrubber
|
||||||
396 1 e 1 interleave_chip_selects
|
396 1 e 1 interleave_chip_selects
|
||||||
397 2 e 8 max_mem_clock
|
397 2 e 8 max_mem_clock
|
||||||
399 1 e 2 multi_core
|
399 1 e 2 multi_core
|
||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
440 4 e 9 slow_cpu
|
440 4 e 9 slow_cpu
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
445 1 e 1 iommu
|
||||||
456 1 e 1 ECC_memory
|
456 1 e 1 ECC_memory
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
1000 24 r 0 amd_reserved
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
enumerations
|
enumerations
|
||||||
|
|
||||||
#ID value text
|
#ID value text
|
||||||
1 0 Disable
|
1 0 Disable
|
||||||
1 1 Enable
|
1 1 Enable
|
||||||
2 0 Enable
|
2 0 Enable
|
||||||
2 1 Disable
|
2 1 Disable
|
||||||
4 0 Fallback
|
4 0 Fallback
|
||||||
4 1 Normal
|
4 1 Normal
|
||||||
6 5 Notice
|
6 5 Notice
|
||||||
6 6 Info
|
6 6 Info
|
||||||
6 7 Debug
|
6 7 Debug
|
||||||
6 8 Spew
|
6 8 Spew
|
||||||
8 0 400Mhz
|
8 0 400Mhz
|
||||||
8 1 333Mhz
|
8 1 333Mhz
|
||||||
8 2 266Mhz
|
8 2 266Mhz
|
||||||
8 3 200Mhz
|
8 3 200Mhz
|
||||||
9 0 off
|
9 0 off
|
||||||
9 1 87.5%
|
9 1 87.5%
|
||||||
9 2 75.0%
|
9 2 75.0%
|
||||||
9 3 62.5%
|
9 3 62.5%
|
||||||
9 4 50.0%
|
9 4 50.0%
|
||||||
9 5 37.5%
|
9 5 37.5%
|
||||||
9 6 25.0%
|
9 6 25.0%
|
||||||
9 7 12.5%
|
9 7 12.5%
|
||||||
|
|
||||||
checksums
|
checksums
|
||||||
|
|
||||||
|
|||||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user