diff --git a/.gitignore b/.gitignore index 6ce8cb7c0f..b90a93fa1d 100644 --- a/.gitignore +++ b/.gitignore @@ -56,6 +56,7 @@ site-local *.\# *.bin *.debug +!Kconfig.debug *.elf *.o *.out diff --git a/.gitmodules b/.gitmodules index 77c74777f6..130778b7ea 100644 --- a/.gitmodules +++ b/.gitmodules @@ -37,3 +37,8 @@ [submodule "3rdparty/ffs"] path = 3rdparty/ffs url = https://github.com/coreboot/ffs.git +[submodule "3rdparty/amd_blobs"] + path = 3rdparty/amd_blobs + url = https://review.coreboot.org/amd_blobs.git + update = none + ignore = dirty diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs new file mode 160000 index 0000000000..cf227316b0 --- /dev/null +++ b/3rdparty/amd_blobs @@ -0,0 +1 @@ +Subproject commit cf227316b0fbd3995854ce21e81a63270b29bfb5 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index a815704c84..fe7985f2a0 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit a815704c84b4823f5b723404a37efed9d6c85d66 +Subproject commit fe7985f2a0692bc773d470a92ec54d22d3c12e4b diff --git a/AUTHORS b/AUTHORS index 72521a1043..6fbee9d19c 100644 --- a/AUTHORS +++ b/AUTHORS @@ -13,12 +13,17 @@ Advanced Micro Devices, Inc. Alex Züpke Alexander Couzens Alexandru Gagniuc +Analog Devices Inc. Andy Fleming ARM Limited and Contributors Arthur Heymans +ASPEED Technology Inc. +Atheros Corporation +Atmel Corporation Carl-Daniel Hailfinger coresystems GmbH Damien Zammit +David Brownell David Hendricks David Mosberger-Tang Denis Dowling @@ -26,6 +31,7 @@ DENX Software Engineering DMP Electronics Inc. Drew Eckhardt Egbert Eich +Eltan B.V Eric Biederman Eswar Nallusamy Facebook, Inc. @@ -37,12 +43,16 @@ Gary Jennejohn Gerd Hoffmann Google LLC Greg Watson +Idwer Vollering Imagination Technologies +Infineon Technologies Intel Corporation Jason Zhao +Jonathan Neuschäfer Jordan Crouse Joseph Smith Keith Hui +Keith Packard Kshitij Kyösti Mälkki Lei Wen @@ -50,43 +60,58 @@ Li-Ta Lo Libra Li Linus Torvalds Linux Networx, Inc. +Luc Verhaegen Marc Jones Marek Vasut Marius Gröger Martin Mares +Marvell International Ltd. Marvell Semiconductor Inc. MediaTek Inc. MontaVista Software, Inc. Myles Watson +Network Appliance Inc. Nicholas Sielicki Nick Barker Nico Huber +Ollie Lo +Orion Technologies, LLC Patrick Georgi Patrick Rudolph PC Engines GmbH Per Odlund Peter Stuge Raptor Engineering, LLC +Red Hat Inc +Reinhard Meyer Richard Woodruff Ronald G. Minnich Rudolf Marek Russell King Sage Electronic Engineering, LLC +Samsung Electronics SciTech Software, Inc. +Sebastian Grzywna secunet Security Networks AG Siemens AG Silicon Integrated System Corporation Stefan Reinauer Steve Magnani +ST Microelectronics SUSE LINUX AG Sven Schnelle Syed Mohammed Khasim Texas Instruments The Linux Foundation +Thomas Winischhofer Timothy Pearson +Tungsten Graphics, Inc. Tyan Computer Corp. +ucRobotics Inc. Uwe Hermann VIA Technologies, Inc +Vipin Kumar +Ward Vandewege Wolfgang Denk Yinghai Lu @@ -99,3 +124,4 @@ src/commonlib src/console src/cpu src/device +src/drivers diff --git a/Documentation/RFC/config.tex b/Documentation/RFC/config.tex deleted file mode 100644 index c11e62219d..0000000000 --- a/Documentation/RFC/config.tex +++ /dev/null @@ -1,290 +0,0 @@ - New config language for LinuxBIOS - -\begin{abstract} -We describe the new configuration language for LinuxBIOS. -\end{abstract} - -\section{Scope} -This document defines the new configuration language for LinuxBIOS. - -\section{Goals} -The goals of the new language are these: -\begin{itemize} -\item Simplified Makefiles so people can see what is set -\item Move from the regular-expression-based language to something -a bit more comprehensible and flexible -\item make the specification easier for people to use and understand -\item allow unique register-set-specifiers for each chip -\item allow generic register-set-specifiers for each chip -\item generate static initialization code, as needed, for the -specifiers. -\end{itemize} - -\section{Language} -Here is the new language. It is very similar to the old one, differing -in only a few respects. It borrows heavily from Greg Watson's suggestions. - -I am presenting it in a pseudo-BNF in the hopes it will be easier. Things -in '' are keywords; things in ``'' are strings in the actual text. -\begin{verbatim} -#exprs are composed of factor or factor + factor etc. -expr ::= factor ( ``+'' factor | ``-'' factor | )* -#factors are term or term * term or term / term or ... -factor ::= term ( ``*'' term | ``/'' term | ... )* -# -unary-op ::= ``!'' ID -# term is a number, hexnumber, ID, unary-op, or a full-blown expression -term ::= NUM | XNUM | ID | unary-op | ``(`` expr ``)'' - -# Option command. Can be an expression or quote-string. -# Options are used in the config tool itself (in expressions and 'if') -# and are also passed to the C compiler when building linuxbios. -# It is an error to have two option commands in a file. -# It is an error to have an option command after the ID has been used -# in an expression (i.e. 'set after used' is an error) -option ::= 'option' ID '=' (``value'' | term) - -# Default command. The ID is set to this value if no option command -# is scanned. -# Multiple defaults for an ID will produce warning, but not errors. -# It is OK to scan a default command after use of an ID. -# Options always over-ride defaults. -default ::= 'default' ID '=' (``value'' | term) - -# the mainboard, southbridge, northbridge commands -# cause sourcing of Config.lb files as in the old config tool -# as parts are sourced, a device tree is built. The structure -# of the tree is determined by the structure of the components -# as they are specified. To attach a superio to a southbridge, for -# example, one would do this: -# southbridge acer/5432 -# superio nsc/123 -# end -# end -# the tool generates static initializers for this hierarchy. - -# add C code to the current component (motherboard, etc. ) -# to initialise the component-INDEPENDENT structure members -init ::= 'init' ``CODE'' - -# add C code to the current component (motherboard, etc. ) -# to initialise the component-DEPENDENT structure members -register ::= 'register' ``CODE'' - - -# mainboard command -# statements in this block will set variables controlling the mainboard, -# and will also place components (northbridge etc.) in the device tree -# under this mainboard -mainboard ::= 'mainboard' PATH (statements)* 'end' - -# standard linuxbios commands -southbridge ::= 'southbridge' PATH (statemnts)* 'end' -northbridge ::= 'northbridge' PATH (statemnts)* 'end' -superio ::= 'superio PATH (statemnts)* 'end' -cpu ::= 'cpu' PATH (statemnts)* 'end' -arch ::= 'arch' PATH (statemnts)* 'end' - -# files for building linuxbios -# include a file in crt0.S -mainboardinit ::= 'mainboardinit' PATH - -# object file -object ::= 'object' PATH -# driver objects are just built into the image in a different way -driver ::= 'driver' PATH - -# Use the Config.lb file in the PATH -dir ::= 'dir' PATH - -# add a file to the set of ldscript files -ldscript ::= 'ldscript' PATH - -# dependencies or actions for the makerule command -dep ::= 'dep' ``dependency-string'' -act ::= 'act' ``actions'' -depsacts ::= (dep | act)* -# set up a makerule -# -makerule ::= 'makerule' PATH depsacts - -#defines for use in makefiles only -# note usable in the config tool, not passed to cc -makedefine ::= 'makedefine' ``RAWTEXT'' - -# add an action to an existing make rule -addaction ::= 'addaction' PATH ``ACTION'' - -# statements -statement ::= - option - | default - | cpu - | arch - | northbridge - | southbridge - | superio - | object - | driver - | mainboardinit - | makerule - | makedefine - | addaction - | init - | register - | iif - | dir - | ldscript - -statements ::= (statement)* - -# target directory specification -target ::= 'target' PATH - -# and the whole thing -board ::= target (option)* mainboard - -\end{verbatim} - -\subsubsection{Command definitions} -\subsubsubsection{option} -\subsubsubsection{default} -\subsubsubsection{cpu} -\subsubsubsection{arch} -\subsubsubsection{northbridge} -\subsubsubsection{southbridge} -\subsubsubsection{superio} -\subsubsubsection{object} -\subsubsubsection{driver} -\subsubsubsection{mainboardinit} -\subsubsubsection{makerule} -\subsubsubsection{makedefine} -\subsubsubsection{addaction} -\subsubsubsection{init} -\subsubsubsection{register} -\subsubsubsection{iif} -\subsubsubsection{dir} -\subsubsubsection{ldscript} - - -A sample file: - -\begin{verbatim} -target x - -# over-ride the default ROM size in the mainboard file -option CONFIG_ROM_SIZE=1024*1024 -mainboard amd/solo -end - -\end{verbatim} - -Sample mainboard file -\begin{verbatim} -# -### -### Set all of the defaults for an x86 architecture -### -arch i386 end -cpu k8 end -# -option CONFIG_DEBUG=1 -default CONFIG_USE_FALLBACK_IMAGE=1 -option A=(1+2) -option B=0xa -# -### -### Build our 16 bit and 32 bit linuxBIOS entry code -### -mainboardinit cpu/i386/entry16.inc -mainboardinit cpu/i386/entry32.inc -ldscript cpu/i386/entry16.lds -ldscript cpu/i386/entry32.lds -# -### -### Build our reset vector (This is where linuxBIOS is entered) -### -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/i386/reset16.inc - ldscript cpu/i386/reset16.lds -else - mainboardinit cpu/i386/reset32.inc - ldscript cpu/i386/reset32.lds -end -. -. -. -if CONFIG_USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end -# -### -### Romcc output -### -#makerule ./failover.E dep "$(CONFIG_MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c > ./failever.E" -#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc" -#mainboardinit ./failover.inc -makerule ./auto.E dep "$(CONFIG_MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c > ./auto.E" -makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc" -mainboardinit ./auto.inc -# -### -### Include the secondary Configuration files -### -northbridge amd/amdk8 -end -southbridge amd/amd8111 -end -#mainboardinit arch/i386/smp/secondary.inc -superio nsc/pc87360 - register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1" -end -dir /pc80 -##dir /src/superio/winbond/w83627hf -cpu p5 end -cpu p6 end -cpu k7 end -cpu k8 end -# -### -### Build the objects we have code for in this directory. -### -##object mainboard.o -driver mainboard.o -object static_devices.o -if CONFIG_HAVE_MP_TABLE object mptable.o end -if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end -### Location of the DIMM EEPROMS on the SMBUS -### This is fixed into a narrow range by the DIMM package standard. -### -option SMBUS_MEM_DEVICE_START=(0xa << 3) -option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +1) -option SMBUS_MEM_DEVICE_INC=1 -# -### The linuxBIOS bootloader. -### -option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE) -option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) -# - -\end{verbatim} - -I've found the output of the new tool to be easier to -handle. Makefile.settings looks like this, for example: -\begin{verbatim} -TOP:=/home/rminnich/src/yapps2/freebios2 -TARGET_DIR:=x -export CONFIG_MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo -export CONFIG_ARCH:=i386 -export CONFIG_RAMBASE:=0x4000 -export CONFIG_ROM_IMAGE_SIZE:=65535 -export CONFIG_PAYLOAD_SIZE:=131073 -export CONFIG_MAX_CPUS:=1 -export CONFIG_HEAP_SIZE:=8192 -export CONFIG_STACK_SIZE:=8192 -export CONFIG_MEMORY_HOLE:=0 -export COREBOOT_VERSION:=1.1.0 -export CC:=$(CONFIG_CROSS_COMPILE)gcc - -\end{verbatim} - -In other words, instead of expressions, we see the values. It's easier to -deal with. diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 73c982385a..462e7e6c6e 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -16,24 +16,36 @@ In order to add support for x86_64 the following assumptions are made: * The reference implementation is qemu * The CPU supports 1GiB hugepages -## Assuptions for ARCH_ROMSTAGE_X86_64 reference implementation -* 0-4GiB are identity mapped using 1GiB huge-pages +## Assuptions for all stages using the reference implementation +* 0-4GiB are identity mapped using 2MiB-pages as WB * Memory above 4GiB isn't accessible -* pagetables reside in _pagetables -* Romstage must install new pagetables in CBMEM after RAMINIT +* page tables reside in memory mapped ROM +* A stage can install new page tables in RAM -## Assuptions for ARCH_RAMSTAGE_X86_64 reference implementation -* Romstage installed pagetables according to memory layout -* Memory above 4GiB is accessible +## Page tables +Page tables are generated by a tool in `util/pgtblgen/pgtblgen`. It writes +the page tables to a file which is then included into the CBFS as file called +`pagetables`. + +To generate the static page tables it must know the physical address where to +place the file. + +The page tables contains the following structure: +* PML4E pointing to PDPE +* PDPE with *$n* entries each pointing to PDE +* *$n* PDEs with 512 entries each + +At the moment *$n* is 4, which results in identity mapping the lower 4 GiB. ## Steps to add basic support for x86_64 * Add x86_64 toolchain support - *DONE* * Fix compilation errors - *DONE* * Fix linker errors - *TODO* -* Add x86_64 rmodule support - *ONGERRIT* +* Add x86_64 rmodule support - *DONE* * Add x86_64 exception handlers - *TODO* -* Setup page tables for long mode - *TODO* -* Add assembly code for long mode - *TODO* +* Setup page tables for long mode - *DONE* +* Add assembly code for long mode - *DONE* +* Add assembly code for postcar stage - *TODO* * Add assembly code to return to protected mode - *TODO* * Implement reference code for mainboard `emulation/qemu-q35` - *TODO* diff --git a/Documentation/community/services.md b/Documentation/community/services.md new file mode 100644 index 0000000000..07c6f2c688 --- /dev/null +++ b/Documentation/community/services.md @@ -0,0 +1,45 @@ +# Accounts on coreboot.org + +There are a number of places where you can benefit from creaating an account +in our community. Since there is no single sign-on system in place (at this +time), they come with their own setup routines. + +## Gerrit code review +We exchange and review patches to the code using our [Gerrit code review +system](https://review.coreboot.org). + +It allows logging in with a Google or GitHub account using OAuth2 as well +as with any OpenID provider that you may already use. + +On the [settings screen](https://review.coreboot.org/settings) you can register +all your email addresses you intend to use in the context of coreboot +development so that commits with your email address in them are associated with +you properly. + +### https push access +When using the https URLs to git repositories, you can push with the "HTTP +Credentials" you can have Gerrit generate for you on that page. By default, +git uses `$HOME/.netrc` for http authentication data, so add a line there +stating: + + machine review.coreboot.org login $your-user-name password $your-password + +### Gerrit user avatar +To setup an avatar to show in Gerrit, clone the avatars repository at +https://review.coreboot.org/gerrit-avatars.git and add a file named +$your-user-ID.jpg (the user ID is a number shown on the [settings screen](https://review.coreboot.org/settings)). +The image must be provided in JPEG format, must be square and have at most 50000 +bytes. + +After you push for review, the system will automatically verify your change +and, if adhering to these constraints, approve it. You can then immediately +submit it. + +## Issue tracker +We have an [issue tracker](https://ticket.coreboot.org) that is used for +coreboot and related code, such as libpayload, as well as for the project's +infrastructure. + +It can be helpful to refer to issues we track there in commit messages: + + Fixes: https://ticket.coreboot.org/issues/$id diff --git a/Documentation/getting_started/architecture.md b/Documentation/getting_started/architecture.md index 6ef63594cf..d037f752d9 100644 --- a/Documentation/getting_started/architecture.md +++ b/Documentation/getting_started/architecture.md @@ -1,6 +1,6 @@ # coreboot architecture -## Overwiew +## Overview ![][architecture] [architecture]: comparision_coreboot_uefi.svg diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md index fb942a426e..dc3cd34413 100644 --- a/Documentation/getting_started/writing_documentation.md +++ b/Documentation/getting_started/writing_documentation.md @@ -14,18 +14,40 @@ coreboot uses [Sphinx] documentation tool. We prefer the markdown format over reStructuredText so only embedded ReST is supported. Checkout the [Markdown Guide] for more information. -### Install Sphinx +### option 1: Use the docker image + +The easiest way to build the documentation is using a docker image. +To build the image run the following in the base directory: + + make -C util/docker/ doc.coreboot.org + +Before building the documentation make sure the output directory is given +the correct permissions before running docker. + + mkdir -p Documentation/_build + +To build the documentation: + + make -C util/docker docker-build-docs + +To have the documentation build and served over a web server live run: + + make -C util/docker docker-livehtml-docs + +On the host machine, open a browser to the address . + +### option 2: Install Sphinx Please follow this official [guide] to install sphinx. You will also need python-recommonmark for sphinx to be able to handle -markdown documenation. +markdown documentation. The recommended version is sphinx 1.7.7, sphinx_rtd_theme 0.4.1 and recommonmark 0.4.0. ### Optional -Install [shpinx-autobuild] for rebuilding markdown/rst sources on the fly! +Install [sphinx-autobuild] for rebuilding markdown/rst sources on the fly! ## Basic and simple rules @@ -116,7 +138,7 @@ TOC tree. [coreboot]: https://coreboot.org [Documentation]: https://review.coreboot.org/cgit/coreboot.git/tree/Documentation -[shpinx-autobuild]: https://github.com/GaretJax/sphinx-autobuild +[sphinx-autobuild]: https://github.com/GaretJax/sphinx-autobuild [guide]: http://www.sphinx-doc.org/en/stable/install.html [Sphinx]: http://www.sphinx-doc.org/en/master/ [Markdown Guide]: https://www.markdownguide.org/ diff --git a/Documentation/gfx/libgfxinit.md b/Documentation/gfx/libgfxinit.md index c000f27d60..0608363906 100644 --- a/Documentation/gfx/libgfxinit.md +++ b/Documentation/gfx/libgfxinit.md @@ -7,13 +7,14 @@ Introduction and Current State in coreboot *libgfxinit* is a library of full-featured graphics initialization (aka. modesetting) drivers. It's implemented in SPARK (a subset of Ada with formal verification features). While not restricted to in -any way, it currently only supports Intel's integrated gfx control- -lers (GMA). +any way, it currently only supports Intel's integrated graphics +controllers (GMA). -Currently, it supports the Intel Core i3/i5/i7 processor line and -will support HDMI and DP on the Atom successor Apollo Lake. At the -time of writing, Sandy Bridge, Ivy Bridge, and Haswell are veri- -fied to work within *coreboot*. +Currently, it supports the Intel Core i3/i5/i7 processor line, HDMI +and DP on the Apollo Lake processors and everything but SDVO on G45 +and GM45 chipsets. At the time of writing, G45, GM45, everything +from Arrandale to Coffee Lake, and Apollo Lake are verified to work +within *coreboot*. GMA: Framebuffer Configuration ------------------------------ diff --git a/Documentation/ifdtool/index.md b/Documentation/ifdtool/index.md index e6e6057a74..4348009f10 100644 --- a/Documentation/ifdtool/index.md +++ b/Documentation/ifdtool/index.md @@ -1,3 +1,4 @@ +# ifdtool Contents: diff --git a/Documentation/index.md b/Documentation/index.md index 39c8d11f9a..8a996b917d 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -166,10 +166,11 @@ Contents: * [Project Ideas](contributing/project_ideas.md) * [Code of Conduct](community/code_of_conduct.md) * [Community forums](community/forums.md) +* [Project services](community/services.md) * [coreboot at conferences](community/conferences.md) * [Payloads](payloads.md) * [Distributions](distributions.md) -* [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md) +* [Technotes](technotes/index.md) * [GPIO toggling in ACPI AML](acpi/gpio.md) * [Adding devices to a device tree](acpi/devicetree.md) * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md) diff --git a/Documentation/lib/flashmap.md b/Documentation/lib/flashmap.md index 5da0e998c9..d3d8bbf6ea 100644 --- a/Documentation/lib/flashmap.md +++ b/Documentation/lib/flashmap.md @@ -17,7 +17,7 @@ something else) should have its own Flashmap section, and everything else should normally go into CBFS. The Flashmap itself starts with a header `struct fmap` and followed by a list of -section descriptions in `strcut fmap_area`. +section descriptions in `struct fmap_area`. ### Header The header `struct fmap` has following fields: diff --git a/Documentation/mainboard/amd/index.md b/Documentation/mainboard/amd/index.md deleted file mode 100644 index 7a33de8f78..0000000000 --- a/Documentation/mainboard/amd/index.md +++ /dev/null @@ -1,7 +0,0 @@ -# AMD platforms documentation - -This section contains documentation about specific AMD mainboards. - -## Mainboard - -- [padmelon](padmelon/padmelon.md) diff --git a/Documentation/mainboard/amd/padmelon/padmelon.md b/Documentation/mainboard/amd/padmelon/padmelon.md index f606f47ad3..20b1b13052 100644 --- a/Documentation/mainboard/amd/padmelon/padmelon.md +++ b/Documentation/mainboard/amd/padmelon/padmelon.md @@ -75,6 +75,6 @@ Three items are marked in this picture [Merlin Falcon BKDG][merlinfalcon] -[merlinfalcon]: ../../soc/amd/family15h.md +[merlinfalcon]: ../../../soc/amd/family15h.md [padmelon]: padmelon.jpg [padmelon_io]: padmelon_io.jpg diff --git a/Documentation/mainboard/asrock/h81m-hds.md b/Documentation/mainboard/asrock/h81m-hds.md index df00abd2b4..6a0da5b315 100644 --- a/Documentation/mainboard/asrock/h81m-hds.md +++ b/Documentation/mainboard/asrock/h81m-hds.md @@ -70,7 +70,7 @@ facing towards the bottom of the board. - The VGA port doesn't work until the OS reinitialises the display. - There is no automatic, OS-independent fan control. This is because - the super I/O hardware monitor can only obtain valid CPU temperature + the Super I/O hardware monitor can only obtain valid CPU temperature readings from the PECI agent, but the required driver doesn't exist in coreboot. The `coretemp` driver can still be used for accurate CPU temperature readings from an OS. diff --git a/Documentation/mainboard/asus/p8h61-m_lx.md b/Documentation/mainboard/asus/p8h61-m_lx.md index 5eb7193f34..212ed9709c 100644 --- a/Documentation/mainboard/asus/p8h61-m_lx.md +++ b/Documentation/mainboard/asus/p8h61-m_lx.md @@ -49,7 +49,7 @@ region is not readable even by the host. suspend. - There is no automatic, OS-independent fan control. This is because - the super I/O hardware monitor can only obtain valid CPU temperature + the Super I/O hardware monitor can only obtain valid CPU temperature readings from the PECI agent, whose complete initialisation is not publicly documented. The `coretemp` driver can still be used for accurate CPU temperature readings. diff --git a/Documentation/mainboard/asus/p8h61-m_pro.md b/Documentation/mainboard/asus/p8h61-m_pro.md index 169678efcd..713c794b0a 100644 --- a/Documentation/mainboard/asus/p8h61-m_pro.md +++ b/Documentation/mainboard/asus/p8h61-m_pro.md @@ -46,7 +46,7 @@ region is not readable even by the host. ## Known issues - There is no automatic, OS-independent fan control. This is because - the super I/O hardware monitor can only obtain valid CPU temperature + the Super I/O hardware monitor can only obtain valid CPU temperature readings from the PECI agent, whose complete initialisation is not publicly documented. The `coretemp` driver can still be used for accurate CPU temperature readings. diff --git a/Documentation/mainboard/facebook/fbg1701.md b/Documentation/mainboard/facebook/fbg1701.md old mode 100644 new mode 100755 index 89e8a6abbc..e59627721a --- a/Documentation/mainboard/facebook/fbg1701.md +++ b/Documentation/mainboard/facebook/fbg1701.md @@ -5,16 +5,17 @@ This page describes how to run coreboot on the Facebook FBG1701. FBG1701 are assembled with different onboard memory modules: Rev 1.0 Onboard Samsung K4B8G1646D-MYKO memory Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory + Rev 1.3 Onboard Kingston B5116ECMDXGGB memory -Use make menuconfig to configure `onboard memory manufacturer` in Mainboard -menu. +Use make menuconfig to configure `onboard memory manufacturer Samsung` in +Mainboard menu. ## Required blobs This board currently requires: fsp blob 3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd Microcode Intel Braswell cpuid 1046C4 version 410 - (Used pre-build binary retrieved from Intel site) + (Used pre-built binary retrieved from Intel site) ## Flashing coreboot @@ -25,7 +26,7 @@ The main SPI flash can be accessed using [flashrom]. ### External programming The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip. -This chip is located to the top middle side of the board. It's located +This chip is located on the top middle side of the board. It's located between SoC and Q7 connector. Use clip (or solder wires) to program the chip. Specifically, it's a Winbond W25Q64FW (1.8V), whose datasheet can be found diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index ea476eb59f..8e88443ac3 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -2,6 +2,9 @@ This section contains documentation about coreboot on specific mainboards. +## AMD +- [padmelon](amd/padmelon/padmelon.md) + ## ASRock - [H81M-HDS](asrock/h81m-hds.md) @@ -62,9 +65,18 @@ The boards in this section are not real mainboards, but emulators. - [Mainboard codenames](lenovo/codenames.md) - [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md) +- [R60](lenovo/r60.md) - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) +### Nehalem series + +- [T410](lenovo/t410.md) + +### GM45 series + +- [X301](lenovo/x301.md) + ### Sandy Bridge series - [T420](lenovo/t420.md) @@ -79,6 +91,14 @@ The boards in this section are not real mainboards, but emulators. - [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md) - [T431s](lenovo/t431s.md) +### Haswell series + +- [T440p](lenovo/t440p.md) + +## Portwell + +- [PQ7-M107](portwell/pq7-m107.md) + ## MSI - [MS-7707](msi/ms7707/ms7707.md) @@ -108,7 +128,7 @@ The boards in this section are not real mainboards, but emulators. ## Supermicro - [X10SLM+-F](supermicro/x10slm-f.md) -- [X11 LGA1151 series](supermicro/x11-lga1151-series/index.md) +- [X11 LGA1151 series](supermicro/x11-lga1151-series/x11-lga1151-series.md) ## UP diff --git a/Documentation/mainboard/lenovo/r60.md b/Documentation/mainboard/lenovo/r60.md new file mode 100644 index 0000000000..91854fbfb6 --- /dev/null +++ b/Documentation/mainboard/lenovo/r60.md @@ -0,0 +1,44 @@ +# Lenovo Thinkpad R60 + +Untested on boards with external Radeon graphics adapter. If you have such +board, proceed at your own risk and document if it does work. + +## Flashing instructions + +### External flashing + +The flash IC is located at the bottom center of the mainboard. Access to +the flash chip is blocked by the magnesium frame, so you need to disassemble +the entire laptop and remove the mainboard. The flash chip is referenced as U49 in +the schematics and in the boardview. + +![](r60_chip.jpg) + +To disassemble the laptop, follow the [Hardware Maintenance Manual](https://thinkpads.com/support/hmm/hmm_pdf/42x3749_02.pdf). + +### Internal flashing on Vendor BIOS + +This [method](https://gist.github.com/ArthurHeymans/c5ef494ada01af372735f237f6c6adbe) describes a way to install coreboot with vendor firmware still +installed on the Lenovo Thinkpad X60. It is reported to also work in Thinkpad +R60, with the only difference being the board target you build coreboot for. + +### Flashing on coreboot + +Default configuration of coreboot doesn't feature any flash restrictions +like the vendor firmware, therefore flashrom is able to flash any rom without problems. + +## Things tested and working in Linux 5.3: + +- Intel WiFi card +- Suspend and resume +- Native graphics initialization. Both legacy VGA and linear framebuffer work +- GRUB2 2.04 and SeaBIOS 1.12.1 payloads +- Reflashing with flashrom (use flashrom-git as of 17.09.2019) +- 2G+1G memory configuration working +- 2504 dock USB ports if not hotplugged + +## Things tested and not working: + +- 2504 dock hotplugging +- Black bar at the left side of the screen. Doesn't appear in Linux. See picture at top +- Sometimes it takes several second to run coreboot. Just wait for it diff --git a/Documentation/mainboard/lenovo/r60_chip.jpg b/Documentation/mainboard/lenovo/r60_chip.jpg new file mode 100644 index 0000000000..94d26a1001 Binary files /dev/null and b/Documentation/mainboard/lenovo/r60_chip.jpg differ diff --git a/Documentation/mainboard/lenovo/t410.md b/Documentation/mainboard/lenovo/t410.md new file mode 100644 index 0000000000..980c9590a9 --- /dev/null +++ b/Documentation/mainboard/lenovo/t410.md @@ -0,0 +1,44 @@ +# Lenovo T410 + +## Known issues +* Dock has wrong ACPI ID (causes "AC adapter state cannot be read" in Linux) +* TPM not working with VBOOT and C_ENV bootblock (works without C_ENV BB) + +## Flashing instructions +```eval_rst ++---------------------+--------------------------------+ +| Type | Value | ++=====================+================================+ +| Socketed flash | no | ++---------------------+--------------------------------+ +| Size | 8 MiB | ++---------------------+--------------------------------+ +| In circuit flashing | Only in S3/WoL | ++---------------------+--------------------------------+ +| Package | SOIC-8 | ++---------------------+--------------------------------+ +| Write protection | No | ++---------------------+--------------------------------+ +| Dual BIOS feature | No | ++---------------------+--------------------------------+ +| Internal flashing | Yes | ++---------------------+--------------------------------+ +``` + +The flash IC is located at the bottom center of the mainboard. Sadly, +access to the IC is blocked by the magnesum frame, so you need to disassemble +the entire laptop and remove the mainboard. + +Below is a picture of IC on the mainboard, with the pinouts labeled. + +![t410_chip_location](t410_chip_location.jpg) + +The chip will either be a Macronix MX25L6405D or a Winbond W25Q64CVSIG. +Do not rely on dots painted in the corner of the chip (such as the blue dot +pictured) to orient the pins! + +[Flashing tutorial](../../flash_tutorial/no_ext_power.md) + +Steps to access the flash IC are described here [T4xx series]. + +[T4xx series]: t4xx_series.md diff --git a/Documentation/mainboard/lenovo/t410_chip_location.jpg b/Documentation/mainboard/lenovo/t410_chip_location.jpg new file mode 100644 index 0000000000..96bbbcbbe9 Binary files /dev/null and b/Documentation/mainboard/lenovo/t410_chip_location.jpg differ diff --git a/Documentation/mainboard/lenovo/t440p.md b/Documentation/mainboard/lenovo/t440p.md new file mode 100644 index 0000000000..98c1da54ac --- /dev/null +++ b/Documentation/mainboard/lenovo/t440p.md @@ -0,0 +1,66 @@ +# Lenovo ThinkPad T440p + +This page describes how to run coreboot on [Lenovo ThinkPad T440p]. + +## Required proprietary blobs + +Please see [mrc.bin](../../northbridge/intel/haswell/mrc.bin). + +## Flashing instructions + +T440p has two flash chips, an 8MB W25Q64FV and a 4MB W25Q32FV. To flash +coreboot, you just need to remove the big door according to the T440 +[Hardware Maintenance Manual] and flash the 4MB chip. + +![T440p flash chip](t440p_flash_chip.jpg) + +To access the 8MB chip, you need to remove the base cover. + +![T440p 8MB flash chip](t440p_all_flash_chips.jpg) + +The flash layout of the OEM firmware is as follows: + + 00000000:00000fff fd + 00001000:00002fff gbe + 00003000:004fffff me + 00500000:00bfffff bios + +After flashing coreboot, you may need to re-plug the AC adapter to make +the laptop able to power on. + +## Known Issues + +- No audio output when using a headphone +- The touchpad is misconfigured, the 3 keys on top are all identified + as left button +- Cannot get the mainboard serial number from the mainboard: the OEM + UEFI firmware gets the serial number from an "emulated EEPROM" via + I/O port 0x1630/0x1634, but it's still unknown how to make it work + +## Untested + +- the dGPU model + +## Working + +- boot Arch Linux with Linux 4.19.77 from SeaBIOS payload +- integrated graphics init with libgfxinit +- EHCI debug: the port is the non-charging USB2 port on the right +- video output: internal (eDP), miniDP, dock DP, dock HDMI +- ACPI support +- keyboard and trackpoint +- SATA +- M.2 SATA SSD +- USB +- Ethernet +- WLAN +- WWAN +- bluetooth +- virtualization: VT-x and VT-d +- dock +- CMOS options: wlan, trackpoint, fn_ctrl_swap +- internal flashing when IFD is unlocked +- using `me_cleaner` + +[Lenovo ThinkPad T440p]: https://pcsupport.lenovo.com/us/zh/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t440p +[Hardware Maintenance Manual]: https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/t440p_hmm_en_sp40a25467_04.pdf diff --git a/Documentation/mainboard/lenovo/t440p_all_flash_chips.jpg b/Documentation/mainboard/lenovo/t440p_all_flash_chips.jpg new file mode 100644 index 0000000000..cab80f21c5 Binary files /dev/null and b/Documentation/mainboard/lenovo/t440p_all_flash_chips.jpg differ diff --git a/Documentation/mainboard/lenovo/t440p_flash_chip.jpg b/Documentation/mainboard/lenovo/t440p_flash_chip.jpg new file mode 100644 index 0000000000..3e041e8d15 Binary files /dev/null and b/Documentation/mainboard/lenovo/t440p_flash_chip.jpg differ diff --git a/Documentation/mainboard/lenovo/x301.md b/Documentation/mainboard/lenovo/x301.md new file mode 100644 index 0000000000..28b512d24d --- /dev/null +++ b/Documentation/mainboard/lenovo/x301.md @@ -0,0 +1,44 @@ +# Lenovo X301 + +## Disassembly Instructions + +You must remove the following parts to access the SPI flash: + +![X301 with WSON8 chip replaced with SOIC8 chip](x301_kb_removed.jpg) + +* Battery pack +* Keyboard + +Its [Hardware Maintenance Manual](https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/43y9441.pdf) can be used as a guidance of disassembly. + +The WSON-8 flash chip (surrounded with red circle in the photo above, +already replaced with a SOIC-8 one) sits under a piece of insulating +tape. If solders between the chip and soldering pads fortunately +overflows beside the chip as tiny tin balls attached to soldering pads, +it will be possible to use a pomona 5250 clip to hold the chip, with +its metal tips just attached to tin balls, thus connecting the chip to +the programmer. Otherwise, it may be recommended to replace it with a +SOIC-8 one (you might need to add the chip to the IFD VSCC list), as +what is done in the photo. + +The vendor IFD VSCC list contains: + -MACRONIX_MX25L6405 (0xc2, 0x2017) + -WINBOND_NEX_W25X64 (0xef, 0x3017) + -ATMEL_AT25DF641 (0x1f, 0x4800) + +```eval_rst +:doc:`../../flash_tutorial/ext_power` +``` +Tested: + - CPU Core 2 Duo U9400 + - Slotted DIMM 4GiB*2 from samsung + - Camera + - pci-e slots + - sata and usb2 + - libgfxinit-based graphic init + - NVRAM options for North and South bridges + - Sound + - Thinkpad EC + - S3 + - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from + Linux payload (Heads) and Seabios. diff --git a/Documentation/mainboard/lenovo/x301_kb_removed.jpg b/Documentation/mainboard/lenovo/x301_kb_removed.jpg new file mode 100644 index 0000000000..1225dd7339 Binary files /dev/null and b/Documentation/mainboard/lenovo/x301_kb_removed.jpg differ diff --git a/Documentation/mainboard/portwell/pq7-m107.md b/Documentation/mainboard/portwell/pq7-m107.md index e4da415bf4..71bd26a100 100644 --- a/Documentation/mainboard/portwell/pq7-m107.md +++ b/Documentation/mainboard/portwell/pq7-m107.md @@ -4,9 +4,10 @@ This page describes how to run coreboot on the [Portwell PQ7-M107]. PQ7-M107 are assembled with different onboard memory modules: Rev 1.0 Onboard Samsung K4B8G1646D-MYKO memory - Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory + Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory + Rev 1.3 Onboard Kingston B5116ECMDXGGB memory -Use 'make menuconfig' to configure `onboard memory manufacture` in Mainboard +Use 'make menuconfig' to configure `onboard memory manufacturer` in Mainboard menu. ## Required blobs @@ -53,7 +54,7 @@ serial/video/pcie ports might be available. - eMMC - SATA - serial port -- SMbus +- SMBus - HDA (codec on carrier) - initialization with FSP MR2 - SeaBIOS payload (version rel-1.11.0-44-g7961917) diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md index 7fae61fc5f..acb2c84fa2 100644 --- a/Documentation/mainboard/supermicro/x10slm-f.md +++ b/Documentation/mainboard/supermicro/x10slm-f.md @@ -168,7 +168,7 @@ Please also see :doc:`../../northbridge/intel/haswell/known-issues`. - VGA graphics - disabling VGA graphics using the jumper - hiding the AST2400 using the CMOS setting -- super I/O hardware monitor (see [Known issues](#known-issues)) +- Super I/O hardware monitor (see [Known issues](#known-issues)) - initialisation with Haswell MRC version 1.6.1 build 2 - flashrom under coreboot - Wake-on-LAN diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/index.md b/Documentation/mainboard/supermicro/x11-lga1151-series/index.md deleted file mode 100644 index 79d2571009..0000000000 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/index.md +++ /dev/null @@ -1,7 +0,0 @@ -# X11 LGA1151 series - -The supermicros X11 series with socket LGA1151 are mostly the same boards with some minor -differences in internal and external interfaces like available PCIe slots, 1 GbE, 10 GbE, -IPMI etc. This is why those boards are grouped as "X11 LGA1151 series". - -- [X11SSH-TF](x11ssh-tf/x11ssh-tf.md) diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md new file mode 100644 index 0000000000..adee88acb2 --- /dev/null +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md @@ -0,0 +1,62 @@ +# X11 LGA1151 series + +The [Supermicro X11 LGA1151 series] are mostly the same boards with some minor differences in +internal and external interfaces like available PCIe slots, NICs (1 GbE, 10 GbE), IPMI, RAID +Controller etc. + +## Supported boards + +- [X11SSH-TF](x11ssh-tf/x11ssh-tf.md) +- [X11SSM-F](x11ssm-f/x11ssm-f.md) + +## Required proprietary blobs + +- [Intel FSP2.0] +- Intel ME + +## De-blobbing + +- [Intel FSP2.0] can not be removed as long as there is no free replacement +- Intel ME can be cleaned using me_cleaner (~4.5 MB more free space) +- Intel Ethernet Controller Firmware can be removed when it's extended functionality is not + needed. For more details refer to the respective datasheet (e.g 333016-008 for I210). +- Boards with [AST2400] BMC/IPMI: Firmware can be replaced by [OpenBMC] + +## Flashing coreboot + +Look at the [flashing tutorial] and the board-specific section. + +## Known issues + +These issues apply to all boards. Have a look at the board-specific issues, too. + +- TianoCore doesn't work with Aspeed NGI, as it's text mode only (Fix is WIP CB:35726) +- MRC caching does not work with cold boot + +## ToDo + +- Fix issues above +- Fix issues in board specific sections +- Fix TODOs mentioned in code +- Add more boards! :-) + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Kaby Lake | ++------------------+--------------------------------------------------+ +| PCH | Intel C232/C236 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel SPS (server version of the ME) | ++------------------+--------------------------------------------------+ +``` + +## Extra links + +[Supermicro X11 LGA1151 series]: https://www.supermicro.com/products/motherboard/Xeon3000/#1151 +[OpenBMC]: https://www.openbmc.org/ +[flashrom]: https://flashrom.org/Flashrom +[flashing tutorial]: ../../../../flash_tutorial/ext_power.md +[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md +[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md index 79e7f3e5eb..1caa34b3f7 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md @@ -2,46 +2,40 @@ This section details how to run coreboot on the [Supermicro X11SSH-TF]. -## Required proprietary blobs - -* [Intel FSP2.0] -* Intel ME - ## Flashing coreboot -The board can be flashed externally using *some* programmers. -The CH341 was found working, while Dediprog won't detect the chip. - -For more details have a look at the [flashing tutorial]. +The board can be flashed externally using *some* programmers. The CH341 was found working, while +Dediprog didn't detect the chip. The flash IC can be found between the two PCIe slots near the southbridge: ![](x11ssh-tf_flash.jpg) ## BMC (IPMI) -This board has an ASPEED [AST2400], which has BMC functionality. The -BMC firmware resides in a 32 MiB SOIC-16 chip in the corner of the -mainboard near the [AST2400]. This chip is an [MX25L25635F]. - -## Known issues - -- Intel SGX causes secondary APs to crash (disabled for now). -- Tianocore doesn't work with Aspeed NGI, as it's text mode only. -- SMBus / I2C does not work (interrupt timeout) +This board has an ASPEED [AST2400], which has BMC/[IPMI] functionality. The BMC firmware resides +in a 32 MiB SOIC-16 chip in the corner of the mainboard near the [AST2400]. This chip is an +[MX25L25635F]. ## Tested and working - USB ports -- M.2 2280 NVMe slot -- 2x 10GB Ethernet -- SATA -- RS232 -- VGA on Aspeed -- Super I/O initialisation +- Ethernet +- SATA ports +- RS232 external - ECC DRAM detection - PCIe slots -- TPM on TPM expansion header +- M.2 2280 NVMe slot - BMC (IPMI) +- VGA on Aspeed +- TPM on TPM expansion header + +## Known issues + +See general issue section. + +## ToDo + +- Fix TODOs mentioned in code ## Technology @@ -51,23 +45,46 @@ mainboard near the [AST2400]. This chip is an [MX25L25635F]. +------------------+--------------------------------------------------+ | PCH | Intel C236 | +------------------+--------------------------------------------------+ -| Super I/O | ASPEED AST2400 | -+------------------+--------------------------------------------------+ | Coprocessor | Intel SPS (server version of the ME) | +------------------+--------------------------------------------------+ -| Coprocessor | ASPEED AST2400 | +| Super I/O | ASPEED AST2400 | ++------------------+--------------------------------------------------+ +| Ethernet | 2x Intel® X550 10GBase-T Ethernet | +| | 1x dedicated BMC | ++------------------+--------------------------------------------------+ +| PCIe slots | 1x 3.0 x8 | +| | 1x 3.0 x2 (in x4) | +| | 1x 3.0 M.2 2260 x4 (Key M, with S-ATA) | ++------------------+--------------------------------------------------+ +| USB slots | 2x USB 2.0 (ext) | +| | 2x USB 3.0 (ext) | +| | 1x USB 3.0 (int) | +| | 1x dual USB 3.0 header | +| | 2x dual USB 2.0 header | ++------------------+--------------------------------------------------+ +| SATA slots | 8x SATA III | ++------------------+--------------------------------------------------+ +| Other slots | 1x RS232 (ext) | +| | 1x RS232 header | +| | 1x TPM header | +| | 1x Power SMB header | +| | 6x PWM Fan connector | +| | 2x I-SGPIO | +| | 2x S-ATA DOM Power connector | +| | 1x XDP Port | +| | 1x External BMC I2C Header (for IPMI card) | +| | 1x Chassis Intrusion Header | +------------------+--------------------------------------------------+ ``` ## Extra links +- [Supermicro X11SSH-TF] - [Board manual] -[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 +[Supermicro X11SSH-TF]: https://www.supermicro.com/en/products/motherboard/X11SSH-TF [Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1783.pdf -[flashrom]: https://flashrom.org/Flashrom +[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 +[IPMI]: ../../../../drivers/ipmi_kcs.md [MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf [N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_128mb_3v_65nm.pdf -[flashing tutorial]: ../../../../flash_tutorial/ext_power.md -[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md -[Supermicro X11SSH-TF]: https://www.supermicro.com/en/products/motherboard/X11SSH-TF diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md new file mode 100644 index 0000000000..5213bce6de --- /dev/null +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md @@ -0,0 +1,93 @@ +# Supermicro X11SSM-F + +This section details how to run coreboot on the [Supermicro X11SSM-F]. + +## Flashing coreboot + +The board can be flashed externally. FTDI FT2232H and FT232H based programmers worked. + +The flash IC [MX25L12873F] can be found near PCH PCIe Slot 4. It is socketed on retail boards. + +For doing ISP (In-System-Programming) one needs to add a diode between VCC and the flash chip. + +## BMC (IPMI) + +This board has an ASPEED [AST2400], which has BMC/[IPMI] functionality. The BMC firmware resides in a +32 MiB SOIC-16 chip in the corner of the mainboard near the PCH PCIe Slot 4. This chip is a +[MX25L25635F]. + +## Tested and working + +- GRUB2 payload with Debian testing and kernel 5.2 +- ECC ram (Linux' ie31200 driver works) +- USB ports +- Ethernet +- SATA ports +- RS232 external +- PCIe slots +- BMC (IPMI) +- VGA on Aspeed +- TPM on TPM expansion header + +## Known issues + +- See general issue section +- "only partially covers this bridge" info from Linux kernel (what does that mean?) +- LNXTHERM missing +- S3 resume not working + +## ToDo + +- Fix TODOs mentioned in code + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Kaby Lake | ++------------------+--------------------------------------------------+ +| PCH | Intel C236 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel SPS (server version of the ME) | ++------------------+--------------------------------------------------+ +| Super I/O | ASPEED AST2400 | ++------------------+--------------------------------------------------+ +| Ethernet | 2x Intel I210-AT 1 GbE | +| | 1x dedicated BMC | ++------------------+--------------------------------------------------+ +| PCIe slots | 1x 3.0 x8 | +| | 1x 3.0 x8 (in x16) | +| | 2x 3.0 x4 (in x8) | ++------------------+--------------------------------------------------+ +| USB slots | 2x USB 2.0 (ext) | +| | 2x USB 3.0 (ext) | +| | 1x USB 3.0 (int) | +| | 1x dual USB 3.0 header | +| | 2x dual USB 2.0 header | ++------------------+--------------------------------------------------+ +| SATA slots | 8x S-ATA III | ++------------------+--------------------------------------------------+ +| Other slots | 1x RS232 (ext) | +| | 1x RS232 header | +| | 1x TPM header | +| | 1x Power SMB header | +| | 5x PWM Fan connector | +| | 2x I-SGPIO | +| | 2x S-ATA DOM Power connector | +| | 1x XDP Port | +| | 1x External BMC I2C Header (for IPMI card) | +| | 1x Chassis Intrusion Header | ++------------------+--------------------------------------------------+ +``` + +## Extra links + +- [Supermicro X11SSM-F] +- [Board manual] + +[Supermicro X11SSM-F]: https://www.supermicro.com/en/products/motherboard/X11SSM-F +[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1785.pdf +[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 +[IPMI]: ../../../../drivers/ipmi_kcs.md +[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf +[MX25L12873F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L12873F.pdf diff --git a/Documentation/releases/coreboot-4.11-relnotes.md b/Documentation/releases/coreboot-4.11-relnotes.md index 995a8e7eea..7dd99a3522 100644 --- a/Documentation/releases/coreboot-4.11-relnotes.md +++ b/Documentation/releases/coreboot-4.11-relnotes.md @@ -11,7 +11,32 @@ notes. * The chip and board additions and removals will be updated right before the release, so those do not need to be added. +Clean Up +-------- +Because there was only a single developer board (AMD Torpedo) +using AGESA family 12h, and because there were multiple, +unique Coverity issues with it, the associated vendorcode will +be removed shortly after this release. + Significant changes ------------------- ### Add significant changes here + +### `__PRE_RAM__` is deprecated + +Preprocessor use of `defined(__PRE_RAM_)` have been mostly replaced with +`if (ENV_ROMSTAGE_OR_BEFORE)` or the inverse `if (ENV_RAMSTAGE)`. + +The remaining cases and `-D__PRE_RAM__` are to be removed soon after release. + +### `CAR_GLOBAL` is removed where possible + +For all platform code with `NO_CAR_GLOBAL_MIGRATION=y`, any `CAR_GLOBAL` +attributes have been removed. Remaining cases from common code are to be +removed soon after release. + +### `TSEG` and `cbmem_top()` mapping + +Significant refactoring has bee done to achieve some consistency across platforms +and to reduce code duplication. diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md index ccbd6fe130..c49a61a29d 100644 --- a/Documentation/releases/index.md +++ b/Documentation/releases/index.md @@ -10,6 +10,7 @@ Release notes for previous releases * [4.7 - January 2018](coreboot-4.7-relnotes.md) * [4.8 - May 2018](coreboot-4.8.1-relnotes.md) * [4.9 - December 2018](coreboot-4.9-relnotes.md) +* [4.10 - July 2019](coreboot-4.10-relnotes.md) The checklist contains instructions to ensure that a release covers all important things and provides a reliable format for tarballs, branch @@ -21,4 +22,4 @@ Upcoming release ---------------- Please add to the release notes as changes are added: -* [4.10 - April 2019](coreboot-4.10-relnotes.md) +* [4.11 - October 2019](coreboot-4.11-relnotes.md) diff --git a/Documentation/soc/amd/amdblobs_license.md b/Documentation/soc/amd/amdblobs_license.md new file mode 100755 index 0000000000..bf91c0281e --- /dev/null +++ b/Documentation/soc/amd/amdblobs_license.md @@ -0,0 +1,68 @@ +# License Agreement for amd_blobs Repository + +## Abstract + +AMD has generated a simpler and more flexible license agreement for using +proprietary precompiled binary images. The new agreement is intended to cover +all blobs in the directory structure below where the license resides and +eliminates any unique agreements previously provided for individual products. + +A [3rdparty/amd_blobs](https://review.coreboot.org/admin/repos/amd_blobs) repo +now exists for distributing new blobs to coreboot developers and consumers. +Images for older products will be moved to amd_blobs as time permits. + +By cloning the amd_blobs repo, you will be agreeing to the license agreement +contained there. + +## Text of License Agreement + +The language of the agreement is duplicated below for your reference. The +official license agreement may be found inside the Git repository. + +> Copyright (c) 2019 ADVANCED MICRO DEVICES, INC. +> +> READ CAREFULLY: DO NOT DOWNLOAD, COPY OR USE THE ASSOCIATED AMD SOFTWARE +> ("LICENSED SOFTWARE") UNTIL YOU HAVE CAREFULLY READ THE FOLLOWING. BY USING +> THE LICENSED SOFTWARE, YOU ARE AGREEING TO BE BOUND BY THE FOLLOWING TERMS: +> +> Redistribution and use in binary form, without modification, is permitted +> subject to the following conditions: +> +> a. Reverse engineering, disassembly, or de-compilation of the Licensed +> Software is not permitted; +> +> b. All the content of this document, including the above copyright notice and +> below disclaimer, must be included in the documentation or other materials +> provided with any distribution, and you may not alter or remove any copyright, +> trademark or patent notice(s) in the Licensed Software; and, +> +> c. The name “AMD” or “Advanced Micro Devices” may not be used to promote +> products derived from the Licensed Software. +> +> Except for the limited license expressly granted above, you have no other +> rights in the Licensed Software, whether express, implied, arising by estoppel +> or otherwise. The Licensed Software including all Intellectual Property Rights +> therein is and remains the sole and exclusive property of AMD or its +> licensors, and You shall have no right, title or interest therein except as +> expressly set forth above. +> +> Disclaimer of Warranty. THE LICENSED SOFTWARE IS PROVIDED "AS IS" WITHOUT +> WARRANTY OF ANY KIND. AMD DISCLAIMS ALL WARRANTIES, EXPRESS, IMPLIED, OR +> STATUTORY, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF +> MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NON- +> INFRINGEMENT, THAT THE LICENSED SOFTWARE WILL RUN UNINTERRUPTED OR ERROR-FREE +> OR WARRANTIES ARISING FROM CUSTOM OF TRADE OR COURSE OF USAGE. THE ENTIRE RISK +> ASSOCIATED WITH THE USE OF THE LICENSED SOFTWARE IS ASSUMED BY YOU INCLUDING, +> WITHOUT LIMITATION, PERFORMANCE AND INTEROPERABILITY ISSUES THAT MAY ADVERSELY +> AFFECT YOUR EXPERIENCE AND THE STABILITY OF YOUR COMPUTING SYSTEM; AND +> (C) OTHER EXPERIENCES RESULTING IN ADVERSE EFFECTS, INCLUDING, BUT NOT +> LIMITED, TO DATA CORRUPTION OR LOSS. AMD WILL NOT, UNDER ANY CIRCUMSTANCES BE +> LIABLE TO YOU FOR ANY PUNITIVE, DIRECT, INCIDENTAL, INDIRECT, SPECIAL OR +> CONSEQUENTIAL DAMAGES INCLUDING LOSS OF USE, PROFITS, OR DATA ARISING FROM USE +> OF THE LICENSED SOFTWARE EVEN IF AMD AND ITS LICENSORS HAVE BEEN ADVISED OF +> THE POSSIBILITY OF SUCH DAMAGES. +> +> The Licensed Software including all Intellectual Property Rights therein is +> and remains the sole and exclusive property of AMD or its licensors, and You +> shall have no right, title or interest therein except as expressly set forth +> above or as required by law. diff --git a/Documentation/soc/amd/index.md b/Documentation/soc/amd/index.md index d6f31c88ca..80413b0937 100644 --- a/Documentation/soc/amd/index.md +++ b/Documentation/soc/amd/index.md @@ -7,3 +7,6 @@ This section contains documentation about coreboot on specific AMD SOCs. - [Family 15h](family15h.md) - [Family 17h](family17h.md) +## amd_blobs Repository License + +- [amd_blobs](amdblobs_license.md) diff --git a/Documentation/soc/index.md b/Documentation/soc/index.md index fccddbd025..1415c721bb 100644 --- a/Documentation/soc/index.md +++ b/Documentation/soc/index.md @@ -7,3 +7,4 @@ This section contains documentation about coreboot on specific SOCs. - [AMD](amd/index.md) - [Cavium](cavium/index.md) - [Intel](intel/index.md) +- [Qualcomm](qualcomm/index.md) diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index cd7fe0b302..aac7b35a50 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -21,6 +21,12 @@ those are fixed. If possible a workaround is described here as well. * Workaround: Don't disable this PCI device * Issue on public tracker: [Issue 13] +* FSP Notify(EnumInitPhaseAfterPciEnumeration) hangs if 00:02.03/00:02.03 are hidden + * Release MR2 + * Seems to get stuck on some SKUs only if hidden after MemoryInit + * Workaround: Hide before MemoryInit + * Issue on public tracker: [Issue 35] + ### KabylakeFsp * MfgId and ModulePartNum in the DIMM_INFO struct are empty * Release 3.7.1 @@ -59,4 +65,5 @@ those are fixed. If possible a workaround is described here as well. [Issue 13]: https://github.com/IntelFsp/FSP/issues/13 [Issue 15]: https://github.com/IntelFsp/FSP/issues/15 [Issue 22]: https://github.com/IntelFsp/FSP/issues/22 +[Issue 35]: https://github.com/IntelFsp/FSP/issues/35 diff --git a/Documentation/soc/qualcomm/index.md b/Documentation/soc/qualcomm/index.md new file mode 100644 index 0000000000..5cd79819bd --- /dev/null +++ b/Documentation/soc/qualcomm/index.md @@ -0,0 +1,7 @@ +# Qualcomm SOC-specific documentation + +This section contains documentation about coreboot on specific Qualcomm SOCs. + +## Platforms + +- [SC7180 series](sc7180/index.md) diff --git a/Documentation/soc/qualcomm/sc7180/index.md b/Documentation/soc/qualcomm/sc7180/index.md new file mode 100644 index 0000000000..8f5d33d8c4 --- /dev/null +++ b/Documentation/soc/qualcomm/sc7180/index.md @@ -0,0 +1,19 @@ +# Qualcomm SC7180 documentation + +## SOC code + +The SOC folder contains functions for: +* MMU +* CLOCK +* GPIO +* QUPv3 FW (provides a bridge to serial interfaces) +* UART +* SPI-NOR +* AOP FW +* USB + +## Notes about the hardware + +The timer is used from the ARMv8 architecture specific code. + + diff --git a/Documentation/superio/common/ssdt.md b/Documentation/superio/common/ssdt.md index 4353cde3aa..f2bb3346a0 100644 --- a/Documentation/superio/common/ssdt.md +++ b/Documentation/superio/common/ssdt.md @@ -19,7 +19,7 @@ I/O range and ISA IRQ number. This example is based on AST2400. -```code +``` # Add a "container" for proper ACPI code generation chip superio/common device pnp 2e.0 on # just for the base device, not for the LDNs diff --git a/Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md b/Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md new file mode 100644 index 0000000000..9accbfe65d --- /dev/null +++ b/Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md @@ -0,0 +1,268 @@ +Rebuilding coreboot image generation +==================================== + +Current situation +----------------- +Chrome OS (CrOS) probably has the most complex image bundling process in the +coreboot ecosystem. To make CrOS features more accessible to the wider +coreboot community, we want to move these capabilities into upstream +coreboot’s build system. + +Right now, the CrOS build system creates coreboot images, and various +instances of the payload (with different configuration options), plus some +more files (eg. EC firmware), then passes them to a CrOS-specific utility +(`bundle_firmware.py`) to build the final image from that. + +`bundle_firmware` adds a flashmap (fmap) to the final image and creates +additional CBFS filesystems in fmap regions. It then extracts some files from +the original CBFS region (that was put in place carefully to later match to +the default fmap region) and copies some of them into the others, as well as +putting more data (eg. the bitmap data, keys) as raw data into other fmap +regions. + +With the recent addition of more files to CBFS, both on the coreboot side +(dsdt, FSP, and so on) and with Chrome OS specifics (eg. more files describing +boot screens) we either need to expand the scope of bundle\_firmware or move +the capability to build complex images to upstream coreboot’s build system. +This document proposes to do the latter and outlines how this could be +achieved. + +Problems with the current build system parts +-------------------------------------------- +One common sentiment is that it should be possible to reuse some of the +existing mechanisms that are supposed to be supplanted by this. +The main concern during this design that precluded their use was that none of +them provides a comprehensive solution to building complex coreboot based +images: +* fmap.dts and fmd provide a flash layout, but no assignment of files of regions +* cbfs-files-y ends up as an internal make variable using + `weird|formatting|to|deal|with|make’s|limitations` +* make isn’t powerful enough to deal with ordering these entries in said + variable to guarantee success if there’s enough room for the files. While that + could be added, that becomes more make macro work indistinguishable from magic + that people fail to understand, break and with good reason complain about + to work around such issues, Chrome OS firmware uses a custom tool with even + more special cases to finally build the image it needs. If coreboot upstream + is to support vboot, it should also be powerful enough not to need magic tools + that only live within downstream projects. + +Requirements +------------ +A complete Chrome OS coreboot image consists of (depending on the device) +* platform specific data in raw fmap regions (eg IFD, ME firmware), +* the bootblock (coming from the bootblock), +* three copies of coreboot, consisting of the stages (verstage, romstage, + ramstage) plus data, +* depthcharge plus data (with each of the coreboot copies), +* EC firmware files (with each of the coreboot copies), +* signatures over several parts of the image and +* some final checksumming over parts of the image to satisfy boot ROM + tests on ARM + +A complete upstream coreboot image (with fallback/normal switch configuration, +using a yet to be implemented switching scheme based on fmaps) consists of +* platform specific data in raw fmap regions (eg IFD, ME firmware), +* two copies of coreboot, consisting of + * the bootblock and + * the stages (romstage, ramstage) plus data, +* payload plus data (with each of the coreboot copies), + +Since a single platform is potentially built with different payload +configurations (eg. modding a Chromebook to not use the verified Chrome OS +boot scheme), some concerns need to be kept separate: +* Platform requirements that have nothing to do with the payload or boot schemes + * IFD, ME, … need to copied to the right place + * boot ROM requirements such as checksums must be honored +* Payload/boot scheme requirements + * Having one to three regions with certain files copied into them + +Proposal +-------- +The proposal is based on manifest files that describe certain aspects of the +final image. +The number of manifest files may change over time, but this seems to be a +reasonable approach for now. As long as coreboot uses fmap and cbfs, there +should be few need to change the language, since composition is done through +files. + +The final image is generated by a utility that is handed a number of manifests +and the size of the flash (derived from `CONFIG_ROM_SIZE`). These manifest files +deal with different concerns, with the following an example that should match +current use cases: + +Chipset manifest +---------------- +The chipset details if there are any non-coreboot regions, and assigns them +names, locations, sizes and file contents and prepares a region for what is +“platform visible” (eg. IFD’s BIOS region) that may be of flexible size +(depending on the flash chip’s size). For the purpose of this document, that +region is called “BIOS”. +It can also specify if there’s a post processing requirement on the final +image. + +coreboot manifest +----------------- +coreboot provides lists of the files it generates for each category it’s +building (eg. bootblock, verstage, romstage, ramstage). They not only contain +the stages themselves, but also additional files (eg. dsdt belongs to ramstage +since that’s where it is used) + +Boot method manifest +-------------------- +The boot method manifest can subdivide the BIOS region, eg. using it directly +(for coreboot’s “simple” bootblock), splitting it in two (for coreboot’s +fallback/normal) or in many parts (for Chrome OS, which requires two CBFS +regions, one for GBB, several for VPD, …). +It also specifies which of the file lists specified earlier belong in which +region (eg. with verstage verifying romstage, verstage needs to be only in +Chrome OS’ RO region, while romstage belongs in RO and both RW regions). +It can also specify a post processing step that is executed before the +chipset’s. + +Payload and additional manifests +-------------------------------- +External components should also provide manifests to add files to categories. +This way the payload and other components (eg. EC firmware) can be developed +without needing to touch the central boot method manifest (that likely resides +in the coreboot tree, given that coreboot needs to deal with choosing fmap +regions already). + +coreboot build system +--------------------- +The coreboot build system will be split more distinctly in two phases: The +first is about building the files (with results like romstage.elf), while the +second phase covers the assembly of the final image. + +By having a global picture of the final image’s requirements, we can also +avoid issues where files added earlier may prevent later additions that have +stricter constraints - without resorting to hacks like +https://chromium-review.googlesource.com/289491 that reorder the file addition +manually. + +Example +------- +As an example, we’ll define an Intel-based board with a postprocessing tool +(something that doesn’t exist, but isn’t hard to imagine): + +It specifies an IFD region, an ME, and the BIOS region. After the image is +built, the entire image needs to be processed (although the tool likely works +only on a small part of it) + +It’s built in a Chrome OS-like configuration (simplified at places to avoid +distracting from the important parts), so it has three CBFS regions, and +several data regions for its own purpose (similar to GBB, FWID, VPD, …). After +the regions are filled, one data region must be post-processed to contain +signatures to enable verifying other regions. + +``` +Chipset manifest +================ +# A region called IFD, starting at 0, ending at 4K +region IFD: 0 4K +# Add the specified file “raw” into the region. +# If the file is smaller than the region, put it at the bottom and fill up +# with 0xff +raw IFD: build/ifd.bin align=bottom empty=0xff +# Call the postprocessor on the data that ends up in IFD (in this example it +# might lock the IFD) +postprocess IFD: util/ifdprocess -l + +# a region called ME, starting at 4K, ending at 2M +region ME: 4K 2M +raw ME: 3rdparty/blobs/soc/intel/xanadu/me.bin align=bottom empty=0x00 + +# a region called BIOS, starting at 2M, filling up the free space +# filling up fails (build error) if two regions are requested to fill up +# against each other +region BIOS: 2M * + +# This would define a region that covers the last 4K of flash. +# The BIOS region specified above will end right before it instead of +# expanding to end of flash +# region AUX: -4K -0 + +# specify the tool that post-processes the entire image. +postprocess image: util/intelchksum/intelchksum.sh + +coreboot manifest +================= +# declare that build/verstage.elf belongs into the group ‘verstage’ +# these groups are later referred to by the “cbfs” command. +group verstage: build/verstage.elf stage xip name=fallback/verstage +group romstage: build/romstage.elf stage xip name=fallback/romstage +group ramstage: build/ramstage.elf stage name=fallback/ramstage +compression=lzma +group ramstage: build/dsdt.aml compression=lzma + +boot method manifest +==================== +# Define RO as region inside BIOS, covering the upper half of the image. +# It’s a build error if the result crosses outside BIOS. +# math expressions are wrapped with ( ), +# and mentions of regions therein always refer to their size +subregion BIOS RO: ( image / 2 ) -0 + +# Define RW to cover the rest of BIOS. +# The order of RW and RO doesn’t matter except to keep comments clearer. +# Dynamic items like RW (“*”) will be sized to fill unused space after +# everything else is placed. +subregion BIOS RW: 0 * + +# It may be necessary to separate the RO/RW definition into another manifest +# file +# that defines the RO configuration of the flash + +# Some more subregions, with dynamically calculated sizes +subregion RW RW_A: 0 ( RW / 2 ) +subregion RW RW_B: * -0 +subregion RW_A FW_MAIN_A: RW_A * -0 +subregion RW_A VBLOCK_A: 0 64K +# foo +bar specifies start + size, not (start, end) +# also, start is given as “the end of VBLOCK_A” +# (while using a region in the “end” field means “start of region”) +subregion RW_A FWID_A: VBLOCK_A +64 + +# To make the example not too verbose, RO only has the CBFS region +subregion RO BOOTSTUB: 0 * + +# Postprocess the data that ends up in VBLOCK_A, +# passing the listed regions as additional arguments. +# Circular dependencies are build errors. +postprocess VBLOCK_A(FW_MAIN_A): signtool + +# binding files to regions indirectly through groups +cbfs BOOTSTUB: verstage, romstage, ramstage, payload +cbfs FW_MAIN_A: romstage, ramstage, payload + +# defining defaults: unless overridden, in all regions that use CBFS (“*”), +# we want all files to come with SHA256 hashes. +# Wildcard defaults have lower priority than specific defaults. +# Other conflicts lead to a build error. +cbfsdefaults *: hash=sha3 + +payload manifest +================ +group payload: payload.elf payload +group payload: bootscreen.jpg name=splashscreen.jpg type=splashscreen + +EC firmware manifest +==================== +# overrides the cbfsdefault above +group payload: ecrw.bin name=ecrw hash=sha256 +group payload: pdrw.bin name=pdrw hash=sha256 +``` + +manifest parsing +---------------- +The exact BNF is work in progress. + +Some parser rules are +* one line per statement +* '#' introduces a command until the end of line + +Some processing rules +* When there’s a conflict (eg. two statements on what to do to a region, + overlap, anything that can’t be determined), that is a build error. +* the order of statements doesn’t matter, enabling simple addition of more + manifests where the need arises. + diff --git a/Documentation/technotes/index.md b/Documentation/technotes/index.md new file mode 100644 index 0000000000..7c231fc672 --- /dev/null +++ b/Documentation/technotes/index.md @@ -0,0 +1,4 @@ +# Technotes + +* [Dealing with Untrusted Input in SMM](2017-02-dealing-with-untrusted-input-in-smm.md) +* [Rebuilding coreboot image generation](2015-11-rebuilding-coreboot-image-generation.md) diff --git a/Documentation/util.md b/Documentation/util.md index 3a09b00101..021af791c7 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -1,4 +1,7 @@ # Utilities + +## List of utils + _Scripts and programs found in the `./util` directory_ * __abuild__ - coreboot autobuild script builds coreboot images for all available targets. `bash` @@ -131,3 +134,8 @@ CPUs. `C` * __x86__ - Generates 32-bit PAE page tables based on a CSV input file. `Go` * __xcompile__ - Cross compile setup `Bash` + + +## In depth documentation + +* [ifdtool](ifdtool/index.md) diff --git a/LICENSES/Apache-2.0.txt b/LICENSES/Apache-2.0.txt new file mode 100644 index 0000000000..4ed90b9522 --- /dev/null +++ b/LICENSES/Apache-2.0.txt @@ -0,0 +1,208 @@ +Apache License + +Version 2.0, January 2004 + +http://www.apache.org/licenses/ TERMS AND CONDITIONS FOR USE, REPRODUCTION, +AND DISTRIBUTION + + 1. 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For the avoidance of doubt, +this trademark restriction does not form part of the License. + +Creative Commons may be contacted at http://creativecommons.org/. diff --git a/LICENSES/GPL-2.0-only.txt b/LICENSES/GPL-2.0-only.txt new file mode 100644 index 0000000000..0f3d6411da --- /dev/null +++ b/LICENSES/GPL-2.0-only.txt @@ -0,0 +1,319 @@ +GNU GENERAL PUBLIC LICENSE + +Version 2, June 1991 + +Copyright (C) 1989, 1991 Free Software Foundation, Inc. + +51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + +Everyone is permitted to copy and distribute verbatim copies of this license +document, but changing it is not allowed. + +Preamble + +The licenses for most software are designed to take away your freedom to share +and change it. By contrast, the GNU General Public License is intended to +guarantee your freedom to share and change free software--to make sure the +software is free for all its users. This General Public License applies to +most of the Free Software Foundation's software and to any other program whose +authors commit to using it. (Some other Free Software Foundation software +is covered by the GNU Lesser General Public License instead.) You can apply +it to your programs, too. + +When we speak of free software, we are referring to freedom, not price. Our +General Public Licenses are designed to make sure that you have the freedom +to distribute copies of free software (and charge for this service if you +wish), that you receive source code or can get it if you want it, that you +can change the software or use pieces of it in new free programs; and that +you know you can do these things. + +To protect your rights, we need to make restrictions that forbid anyone to +deny you these rights or to ask you to surrender the rights. These restrictions +translate to certain responsibilities for you if you distribute copies of +the software, or if you modify it. + +For example, if you distribute copies of such a program, whether gratis or +for a fee, you must give the recipients all the rights that you have. You +must make sure that they, too, receive or can get the source code. And you +must show them these terms so they know their rights. + +We protect your rights with two steps: (1) copyright the software, and (2) +offer you this license which gives you legal permission to copy, distribute +and/or modify the software. + +Also, for each author's protection and ours, we want to make certain that +everyone understands that there is no warranty for this free software. If +the software is modified by someone else and passed on, we want its recipients +to know that what they have is not the original, so that any problems introduced +by others will not reflect on the original authors' reputations. + +Finally, any free program is threatened constantly by software patents. We +wish to avoid the danger that redistributors of a free program will individually +obtain patent licenses, in effect making the program proprietary. To prevent +this, we have made it clear that any patent must be licensed for everyone's +free use or not licensed at all. + +The precise terms and conditions for copying, distribution and modification +follow. + +TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + +0. This License applies to any program or other work which contains a notice +placed by the copyright holder saying it may be distributed under the terms +of this General Public License. The "Program", below, refers to any such program +or work, and a "work based on the Program" means either the Program or any +derivative work under copyright law: that is to say, a work containing the +Program or a portion of it, either verbatim or with modifications and/or translated +into another language. (Hereinafter, translation is included without limitation +in the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not covered +by this License; they are outside its scope. The act of running the Program +is not restricted, and the output from the Program is covered only if its +contents constitute a work based on the Program (independent of having been +made by running the Program). Whether that is true depends on what the Program +does. + +1. You may copy and distribute verbatim copies of the Program's source code +as you receive it, in any medium, provided that you conspicuously and appropriately +publish on each copy an appropriate copyright notice and disclaimer of warranty; +keep intact all the notices that refer to this License and to the absence +of any warranty; and give any other recipients of the Program a copy of this +License along with the Program. + +You may charge a fee for the physical act of transferring a copy, and you +may at your option offer warranty protection in exchange for a fee. + +2. You may modify your copy or copies of the Program or any portion of it, +thus forming a work based on the Program, and copy and distribute such modifications +or work under the terms of Section 1 above, provided that you also meet all +of these conditions: + +a) You must cause the modified files to carry prominent notices stating that +you changed the files and the date of any change. + +b) You must cause any work that you distribute or publish, that in whole or +in part contains or is derived from the Program or any part thereof, to be +licensed as a whole at no charge to all third parties under the terms of this +License. + +c) If the modified program normally reads commands interactively when run, +you must cause it, when started running for such interactive use in the most +ordinary way, to print or display an announcement including an appropriate +copyright notice and a notice that there is no warranty (or else, saying that +you provide a warranty) and that users may redistribute the program under +these conditions, and telling the user how to view a copy of this License. +(Exception: if the Program itself is interactive but does not normally print +such an announcement, your work based on the Program is not required to print +an announcement.) + +These requirements apply to the modified work as a whole. If identifiable +sections of that work are not derived from the Program, and can be reasonably +considered independent and separate works in themselves, then this License, +and its terms, do not apply to those sections when you distribute them as +separate works. But when you distribute the same sections as part of a whole +which is a work based on the Program, the distribution of the whole must be +on the terms of this License, whose permissions for other licensees extend +to the entire whole, and thus to each and every part regardless of who wrote +it. + +Thus, it is not the intent of this section to claim rights or contest your +rights to work written entirely by you; rather, the intent is to exercise +the right to control the distribution of derivative or collective works based +on the Program. + +In addition, mere aggregation of another work not based on the Program with +the Program (or with a work based on the Program) on a volume of a storage +or distribution medium does not bring the other work under the scope of this +License. + +3. You may copy and distribute the Program (or a work based on it, under Section +2) in object code or executable form under the terms of Sections 1 and 2 above +provided that you also do one of the following: + +a) Accompany it with the complete corresponding machine-readable source code, +which must be distributed under the terms of Sections 1 and 2 above on a medium +customarily used for software interchange; or, + +b) Accompany it with a written offer, valid for at least three years, to give +any third party, for a charge no more than your cost of physically performing +source distribution, a complete machine-readable copy of the corresponding +source code, to be distributed under the terms of Sections 1 and 2 above on +a medium customarily used for software interchange; or, + +c) Accompany it with the information you received as to the offer to distribute +corresponding source code. (This alternative is allowed only for noncommercial +distribution and only if you received the program in object code or executable +form with such an offer, in accord with Subsection b above.) + +The source code for a work means the preferred form of the work for making +modifications to it. For an executable work, complete source code means all +the source code for all modules it contains, plus any associated interface +definition files, plus the scripts used to control compilation and installation +of the executable. However, as a special exception, the source code distributed +need not include anything that is normally distributed (in either source or +binary form) with the major components (compiler, kernel, and so on) of the +operating system on which the executable runs, unless that component itself +accompanies the executable. + +If distribution of executable or object code is made by offering access to +copy from a designated place, then offering equivalent access to copy the +source code from the same place counts as distribution of the source code, +even though third parties are not compelled to copy the source along with +the object code. + +4. You may not copy, modify, sublicense, or distribute the Program except +as expressly provided under this License. Any attempt otherwise to copy, modify, +sublicense or distribute the Program is void, and will automatically terminate +your rights under this License. However, parties who have received copies, +or rights, from you under this License will not have their licenses terminated +so long as such parties remain in full compliance. + +5. You are not required to accept this License, since you have not signed +it. However, nothing else grants you permission to modify or distribute the +Program or its derivative works. These actions are prohibited by law if you +do not accept this License. Therefore, by modifying or distributing the Program +(or any work based on the Program), you indicate your acceptance of this License +to do so, and all its terms and conditions for copying, distributing or modifying +the Program or works based on it. + +6. Each time you redistribute the Program (or any work based on the Program), +the recipient automatically receives a license from the original licensor +to copy, distribute or modify the Program subject to these terms and conditions. +You may not impose any further restrictions on the recipients' exercise of +the rights granted herein. You are not responsible for enforcing compliance +by third parties to this License. + +7. If, as a consequence of a court judgment or allegation of patent infringement +or for any other reason (not limited to patent issues), conditions are imposed +on you (whether by court order, agreement or otherwise) that contradict the +conditions of this License, they do not excuse you from the conditions of +this License. If you cannot distribute so as to satisfy simultaneously your +obligations under this License and any other pertinent obligations, then as +a consequence you may not distribute the Program at all. For example, if a +patent license would not permit royalty-free redistribution of the Program +by all those who receive copies directly or indirectly through you, then the +only way you could satisfy both it and this License would be to refrain entirely +from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under any +particular circumstance, the balance of the section is intended to apply and +the section as a whole is intended to apply in other circumstances. + +It is not the purpose of this section to induce you to infringe any patents +or other property right claims or to contest validity of any such claims; +this section has the sole purpose of protecting the integrity of the free +software distribution system, which is implemented by public license practices. +Many people have made generous contributions to the wide range of software +distributed through that system in reliance on consistent application of that +system; it is up to the author/donor to decide if he or she is willing to +distribute software through any other system and a licensee cannot impose +that choice. + +This section is intended to make thoroughly clear what is believed to be a +consequence of the rest of this License. + +8. If the distribution and/or use of the Program is restricted in certain +countries either by patents or by copyrighted interfaces, the original copyright +holder who places the Program under this License may add an explicit geographical +distribution limitation excluding those countries, so that distribution is +permitted only in or among countries not thus excluded. In such case, this +License incorporates the limitation as if written in the body of this License. + +9. The Free Software Foundation may publish revised and/or new versions of +the General Public License from time to time. Such new versions will be similar +in spirit to the present version, but may differ in detail to address new +problems or concerns. + +Each version is given a distinguishing version number. If the Program specifies +a version number of this License which applies to it and "any later version", +you have the option of following the terms and conditions either of that version +or of any later version published by the Free Software Foundation. If the +Program does not specify a version number of this License, you may choose +any version ever published by the Free Software Foundation. + +10. If you wish to incorporate parts of the Program into other free programs +whose distribution conditions are different, write to the author to ask for +permission. For software which is copyrighted by the Free Software Foundation, +write to the Free Software Foundation; we sometimes make exceptions for this. +Our decision will be guided by the two goals of preserving the free status +of all derivatives of our free software and of promoting the sharing and reuse +of software generally. + + NO WARRANTY + +11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR +THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE +STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM +"AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, +BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE +OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME +THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + +12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE +THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY +GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE +OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA +OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES +OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH +HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +END OF TERMS AND CONDITIONS + +How to Apply These Terms to Your New Programs + +If you develop a new program, and you want it to be of the greatest possible +use to the public, the best way to achieve this is to make it free software +which everyone can redistribute and change under these terms. + +To do so, attach the following notices to the program. It is safest to attach +them to the start of each source file to most effectively convey the exclusion +of warranty; and each file should have at least the "copyright" line and a +pointer to where the full notice is found. + + + +Copyright (C)< yyyy> + +This program is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free Software +Foundation; either version 2 of the License, or (at your option) any later +version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along with +this program; if not, write to the Free Software Foundation, Inc., 51 Franklin +Street, Fifth Floor, Boston, MA 02110-1301, USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this when +it starts in an interactive mode: + +Gnomovision version 69, Copyright (C) year name of author Gnomovision comes +with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, +and you are welcome to redistribute it under certain conditions; type `show +c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may be +called something other than `show w' and `show c'; they could even be mouse-clicks +or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your school, +if any, to sign a "copyright disclaimer" for the program, if necessary. Here +is a sample; alter the names: + +Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' +(which makes passes at compilers) written by James Hacker. + +, 1 April 1989 Ty Coon, President of Vice This General +Public License does not permit incorporating your program into proprietary +programs. If your program is a subroutine library, you may consider it more +useful to permit linking proprietary applications with the library. If this +is what you want to do, use the GNU Lesser General Public License instead +of this License. diff --git a/LICENSES/GPL-2.0-or-later.txt b/LICENSES/GPL-2.0-or-later.txt new file mode 100644 index 0000000000..1d80ac3653 --- /dev/null +++ b/LICENSES/GPL-2.0-or-later.txt @@ -0,0 +1,319 @@ +GNU GENERAL PUBLIC LICENSE + +Version 2, June 1991 + +Copyright (C) 1989, 1991 Free Software Foundation, Inc. + +51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + +Everyone is permitted to copy and distribute verbatim copies of this license +document, but changing it is not allowed. + +Preamble + +The licenses for most software are designed to take away your freedom to share +and change it. By contrast, the GNU General Public License is intended to +guarantee your freedom to share and change free software--to make sure the +software is free for all its users. This General Public License applies to +most of the Free Software Foundation's software and to any other program whose +authors commit to using it. (Some other Free Software Foundation software +is covered by the GNU Lesser General Public License instead.) You can apply +it to your programs, too. + +When we speak of free software, we are referring to freedom, not price. Our +General Public Licenses are designed to make sure that you have the freedom +to distribute copies of free software (and charge for this service if you +wish), that you receive source code or can get it if you want it, that you +can change the software or use pieces of it in new free programs; and that +you know you can do these things. + +To protect your rights, we need to make restrictions that forbid anyone to +deny you these rights or to ask you to surrender the rights. These restrictions +translate to certain responsibilities for you if you distribute copies of +the software, or if you modify it. + +For example, if you distribute copies of such a program, whether gratis or +for a fee, you must give the recipients all the rights that you have. You +must make sure that they, too, receive or can get the source code. And you +must show them these terms so they know their rights. + +We protect your rights with two steps: (1) copyright the software, and (2) +offer you this license which gives you legal permission to copy, distribute +and/or modify the software. + +Also, for each author's protection and ours, we want to make certain that +everyone understands that there is no warranty for this free software. If +the software is modified by someone else and passed on, we want its recipients +to know that what they have is not the original, so that any problems introduced +by others will not reflect on the original authors' reputations. + +Finally, any free program is threatened constantly by software patents. We +wish to avoid the danger that redistributors of a free program will individually +obtain patent licenses, in effect making the program proprietary. To prevent +this, we have made it clear that any patent must be licensed for everyone's +free use or not licensed at all. + +The precise terms and conditions for copying, distribution and modification +follow. + +TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + +0. This License applies to any program or other work which contains a notice +placed by the copyright holder saying it may be distributed under the terms +of this General Public License. The "Program", below, refers to any such program +or work, and a "work based on the Program" means either the Program or any +derivative work under copyright law: that is to say, a work containing the +Program or a portion of it, either verbatim or with modifications and/or translated +into another language. (Hereinafter, translation is included without limitation +in the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not covered +by this License; they are outside its scope. The act of running the Program +is not restricted, and the output from the Program is covered only if its +contents constitute a work based on the Program (independent of having been +made by running the Program). Whether that is true depends on what the Program +does. + +1. You may copy and distribute verbatim copies of the Program's source code +as you receive it, in any medium, provided that you conspicuously and appropriately +publish on each copy an appropriate copyright notice and disclaimer of warranty; +keep intact all the notices that refer to this License and to the absence +of any warranty; and give any other recipients of the Program a copy of this +License along with the Program. + +You may charge a fee for the physical act of transferring a copy, and you +may at your option offer warranty protection in exchange for a fee. + +2. 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You may copy and distribute the Program (or a work based on it, under Section +2) in object code or executable form under the terms of Sections 1 and 2 above +provided that you also do one of the following: + +a) Accompany it with the complete corresponding machine-readable source code, +which must be distributed under the terms of Sections 1 and 2 above on a medium +customarily used for software interchange; or, + +b) Accompany it with a written offer, valid for at least three years, to give +any third party, for a charge no more than your cost of physically performing +source distribution, a complete machine-readable copy of the corresponding +source code, to be distributed under the terms of Sections 1 and 2 above on +a medium customarily used for software interchange; or, + +c) Accompany it with the information you received as to the offer to distribute +corresponding source code. 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Each time you redistribute the Program (or any work based on the Program), +the recipient automatically receives a license from the original licensor +to copy, distribute or modify the Program subject to these terms and conditions. +You may not impose any further restrictions on the recipients' exercise of +the rights granted herein. You are not responsible for enforcing compliance +by third parties to this License. + +7. If, as a consequence of a court judgment or allegation of patent infringement +or for any other reason (not limited to patent issues), conditions are imposed +on you (whether by court order, agreement or otherwise) that contradict the +conditions of this License, they do not excuse you from the conditions of +this License. If you cannot distribute so as to satisfy simultaneously your +obligations under this License and any other pertinent obligations, then as +a consequence you may not distribute the Program at all. For example, if a +patent license would not permit royalty-free redistribution of the Program +by all those who receive copies directly or indirectly through you, then the +only way you could satisfy both it and this License would be to refrain entirely +from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under any +particular circumstance, the balance of the section is intended to apply and +the section as a whole is intended to apply in other circumstances. + +It is not the purpose of this section to induce you to infringe any patents +or other property right claims or to contest validity of any such claims; +this section has the sole purpose of protecting the integrity of the free +software distribution system, which is implemented by public license practices. +Many people have made generous contributions to the wide range of software +distributed through that system in reliance on consistent application of that +system; it is up to the author/donor to decide if he or she is willing to +distribute software through any other system and a licensee cannot impose +that choice. + +This section is intended to make thoroughly clear what is believed to be a +consequence of the rest of this License. + +8. If the distribution and/or use of the Program is restricted in certain +countries either by patents or by copyrighted interfaces, the original copyright +holder who places the Program under this License may add an explicit geographical +distribution limitation excluding those countries, so that distribution is +permitted only in or among countries not thus excluded. In such case, this +License incorporates the limitation as if written in the body of this License. + +9. The Free Software Foundation may publish revised and/or new versions of +the General Public License from time to time. Such new versions will be similar +in spirit to the present version, but may differ in detail to address new +problems or concerns. + +Each version is given a distinguishing version number. If the Program specifies +a version number of this License which applies to it and "any later version", +you have the option of following the terms and conditions either of that version +or of any later version published by the Free Software Foundation. If the +Program does not specify a version number of this License, you may choose +any version ever published by the Free Software Foundation. + +10. If you wish to incorporate parts of the Program into other free programs +whose distribution conditions are different, write to the author to ask for +permission. For software which is copyrighted by the Free Software Foundation, +write to the Free Software Foundation; we sometimes make exceptions for this. +Our decision will be guided by the two goals of preserving the free status +of all derivatives of our free software and of promoting the sharing and reuse +of software generally. + + NO WARRANTY + +11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR +THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE +STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM +"AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, +BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE +OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME +THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + +12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE +THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY +GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE +OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA +OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES +OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH +HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +END OF TERMS AND CONDITIONS + +How to Apply These Terms to Your New Programs + +If you develop a new program, and you want it to be of the greatest possible +use to the public, the best way to achieve this is to make it free software +which everyone can redistribute and change under these terms. + +To do so, attach the following notices to the program. It is safest to attach +them to the start of each source file to most effectively convey the exclusion +of warranty; and each file should have at least the "copyright" line and a +pointer to where the full notice is found. + + + +Copyright (C) + +This program is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free Software +Foundation; either version 2 of the License, or (at your option) any later +version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along with +this program; if not, write to the Free Software Foundation, Inc., 51 Franklin +Street, Fifth Floor, Boston, MA 02110-1301, USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this when +it starts in an interactive mode: + +Gnomovision version 69, Copyright (C) year name of author Gnomovision comes +with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, +and you are welcome to redistribute it under certain conditions; type `show +c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may be +called something other than `show w' and `show c'; they could even be mouse-clicks +or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your school, +if any, to sign a "copyright disclaimer" for the program, if necessary. Here +is a sample; alter the names: + +Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' +(which makes passes at compilers) written by James Hacker. + +, 1 April 1989 Ty Coon, President of Vice This General +Public License does not permit incorporating your program into proprietary +programs. If your program is a subroutine library, you may consider it more +useful to permit linking proprietary applications with the library. If this +is what you want to do, use the GNU Lesser General Public License instead +of this License. diff --git a/LICENSES/GPL-3.0-only.txt b/LICENSES/GPL-3.0-only.txt new file mode 100644 index 0000000000..e142a525bd --- /dev/null +++ b/LICENSES/GPL-3.0-only.txt @@ -0,0 +1,625 @@ +GNU GENERAL PUBLIC LICENSE + +Version 3, 29 June 2007 + +Copyright © 2007 Free Software Foundation, Inc. + +Everyone is permitted to copy and distribute verbatim copies of this license +document, but changing it is not allowed. + +Preamble + +The GNU General Public License is a free, copyleft license for software and +other kinds of works. + +The licenses for most software and other practical works are designed to take +away your freedom to share and change the works. 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It is safest to attach +them to the start of each source file to most effectively state the exclusion +of warranty; and each file should have at least the "copyright" line and a +pointer to where the full notice is found. + + + +Copyright (C) + +This program is free software: you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free Software +Foundation, either version 3 of the License, or (at your option) any later +version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along with +this program. If not, see . + +Also add information on how to contact you by electronic and paper mail. + +If the program does terminal interaction, make it output a short notice like +this when it starts in an interactive mode: + + Copyright (C) + +This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + +This is free software, and you are welcome to redistribute it under certain +conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands might +be different; for a GUI interface, you would use an "about box". + +You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. For +more information on this, and how to apply and follow the GNU GPL, see . + +The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General Public +License instead of this License. But first, please read . diff --git a/LICENSES/ISC.txt b/LICENSES/ISC.txt new file mode 100644 index 0000000000..412d4e203d --- /dev/null +++ b/LICENSES/ISC.txt @@ -0,0 +1,14 @@ +ISC License Copyright (c) 2004-2010 by Internet Systems Consortium, Inc. ("ISC") + +Copyright (c) 1995-2003 by Internet Software Consortium + +Permission to use, copy, modify, and /or distribute this software for any +purpose with or without fee is hereby granted, provided that the above copyright +notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND ISC DISCLAIMS ALL WARRANTIES WITH REGARD +TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. +IN NO EVENT SHALL ISC BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL +DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING +OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. diff --git a/LICENSES/MIT.txt b/LICENSES/MIT.txt new file mode 100644 index 0000000000..204b93da48 --- /dev/null +++ b/LICENSES/MIT.txt @@ -0,0 +1,19 @@ +MIT License Copyright (c) + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is furnished +to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS +OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. diff --git a/LICENSES/X11.txt b/LICENSES/X11.txt new file mode 100644 index 0000000000..da478eb05a --- /dev/null +++ b/LICENSES/X11.txt @@ -0,0 +1,24 @@ +X11 License Copyright (C) 1996 X Consortium + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is furnished +to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM +BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH +THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of the X Consortium shall not +be used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from the X Consortium. + +X Window System is a trademark of X Consortium, Inc. diff --git a/MAINTAINERS b/MAINTAINERS index 030ed7a593..9abbdb1527 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -391,6 +391,11 @@ M: Tristan Corrick S: Maintained F: src/mainboard/supermicro/x10slm-f/ +SUPERMICRO X11-LGA1151-SERIES +M: Michael Niewöhner +S: Maintained +F: src/mainboard/supermicro/x11-lga1151-series + FACEBOOK FBG1701 MAINBOARD M: Frans Hendriks M: Wim Vervoorn diff --git a/Makefile b/Makefile index 35a4b32c2a..f3f9592649 100644 --- a/Makefile +++ b/Makefile @@ -144,12 +144,11 @@ endif \mv -f $@.tmp $@ 2> /dev/null rm -f $@.tmp --include $(TOPLEVEL)/site-local/Makefile.inc - ifeq ($(NOCOMPILE),1) include $(TOPLEVEL)/Makefile.inc include $(TOPLEVEL)/payloads/Makefile.inc include $(TOPLEVEL)/util/testing/Makefile.inc +-include $(TOPLEVEL)/site-local/Makefile.inc real-all: @echo "Error: Expected config file ($(DOTCONFIG)) not present." >&2 @echo "Please specify a config file or run 'make menuconfig' to" >&2 @@ -195,7 +194,7 @@ $(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG) $(objutil)/kconfig/conf $(KCONFIG_AUTOCONFIG): $(KCONFIG_AUTOHEADER) true -$(KCONFIG_AUTOADS): $(KCONFIG_AUTOCONFIG) $(objutil)/kconfig/toada +$(KCONFIG_AUTOADS): $(KCONFIG_CONFIG) $(KCONFIG_AUTOHEADER) $(objutil)/kconfig/toada $(objutil)/kconfig/toada CB.Config <$< >$@ $(obj)/%/$(notdir $(KCONFIG_AUTOADS)): $(KCONFIG_AUTOADS) @@ -253,13 +252,13 @@ includemakefiles= \ $(foreach class,classes subdirs $(classes) $(special-classes), $(eval $(class)-y:=)) \ $(eval -include $(1)) \ $(foreach class,$(classes-y), $(call add-class,$(class))) \ + $(foreach special,$(special-classes), \ + $(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \ $(foreach class,$(classes), \ $(eval $(class)-srcs+= \ $$(subst $(absobj)/,$(obj)/, \ $$(subst $(top)/,, \ $$(abspath $$(subst $(dir $(1))/,/,$$(addprefix $(dir $(1)),$$($(class)-y)))))))) \ - $(foreach special,$(special-classes), \ - $(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \ $(eval subdirs+=$$(subst $(CURDIR)/,,$$(wildcard $$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y)))))) # For each path in $(subdirs) call includemakefiles diff --git a/Makefile.inc b/Makefile.inc index 86764045a6..8ecc0ef3b2 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -93,7 +93,7 @@ subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) subdirs-y += src/superio subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) subdirs-y += src/cpu src/vendorcode -subdirs-y += util/cbfstool util/sconfig util/nvramtool +subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen subdirs-y += util/futility util/marvell util/bincfg subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) @@ -107,6 +107,10 @@ subdirs-y += util/checklist util/testing # Add source classes and their build options classes-y := ramstage romstage bootblock decompressor postcar smm smmstub cpu_microcode verstage +# Add a special 'all' class to add sources to all stages +$(call add-special-class,all) +all-handler = $(foreach class,bootblock verstage romstage postcar ramstage,$(eval $(class)-y += $(2))) + # Add dynamic classes for rmodules $(foreach supported_arch,$(ARCH_SUPPORTED), \ $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch)))) @@ -193,15 +197,16 @@ ifneq ($(UPDATED_SUBMODULES),1) # try to fetch non-optional submodules if the source is under git forgetthis:=$(if $(GIT),$(shell git submodule update --init)) ifeq ($(CONFIG_USE_BLOBS),y) -# this is necessary because 3rdparty/{blobs,intel-microcode} is update=none, and so is ignored -# unless explicitly requested and enabled through --checkout +# These items are necessary because each has update=none in .gitmodules. They are ignored +# until expressly requested and enabled with --checkout forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs)) forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode)) ifeq ($(CONFIG_PLATFORM_USES_FSP1_0)$(CONFIG_PLATFORM_USES_FSP1_1)$(CONFIG_PLATFORM_USES_FSP2_0),y) -# this is necessary because 3rdparty/fsp is update=none, and so is ignored -# unless explicitly requested and enabled through --checkout forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp)) endif +ifeq ($(CONFIG_USE_AMD_BLOBS),y) +forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs)) +endif endif UPDATED_SUBMODULES:=1 COREBOOT_EXPORTS += UPDATED_SUBMODULES @@ -591,11 +596,12 @@ OVERRIDE_DEVICETREE_FILE := $(src)/mainboard/$(MAINBOARDDIR)/$(CONFIG_OVERRIDE_D endif DEVICETREE_STATIC_C := $(obj)/mainboard/$(MAINBOARDDIR)/static.c +DEVICETREE_STATIC_H := $(obj)/static.h $(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(objutil)/sconfig/sconfig @printf " SCONFIG $(subst $(src)/,,$(<))\n" mkdir -p $(dir $(DEVICETREE_STATIC_C)) - $(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C) $(OVERRIDE_DEVICETREE_FILE) + $(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C) $(DEVICETREE_STATIC_H) $(OVERRIDE_DEVICETREE_FILE) ramstage-y+=$(DEVICETREE_STATIC_C) romstage-y+=$(DEVICETREE_STATIC_C) @@ -677,6 +683,18 @@ find-class = $(if $(filter $(1),$(basename $(1))),$(if $(CC_$(1)), $(1), $(call # the linker marked it NOBITS automatically because there are only zeroes in it. preserve-bss-flags := --set-section-flags .bss=load,alloc,data --set-section-flags .data=load,alloc,data +# For Intel TXT files in the CBFS needs to be marked as 'Initial Boot Block'. +# As CBFS attributes aren't cheap, only mark them if TXT is enabled. +ifeq ($(CONFIG_INTEL_TXT),y) + +TXTIBB := --ibb + +else + +TXTIBB := + +endif + ifeq ($(CONFIG_COMPRESS_BOOTBLOCK),y) $(objcbfs)/bootblock.lz4: $(objcbfs)/bootblock.elf $(objutil)/cbfstool/cbfs-compression-tool @@ -1030,6 +1048,7 @@ ifeq ($(CONFIG_ARCH_X86),y) -f $(objcbfs)/bootblock.bin \ -n bootblock \ -t bootblock \ + $(TXTIBB) \ -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \ $(TS_OPTIONS) else # ifeq ($(CONFIG_ARCH_X86),y) @@ -1167,6 +1186,9 @@ endif # CONFIG_NO_FIXED_XIP_ROM_SIZE endif # CONFIG_NO_XIP_EARLY_STAGES endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 +ifeq ($(CONFIG_VBOOT_STARTS_IN_ROMSTAGE),y) +$(CONFIG_CBFS_PREFIX)/romstage-options += $(TXTIBB) +endif cbfs-files-$(CONFIG_HAVE_RAMSTAGE) += $(CONFIG_CBFS_PREFIX)/ramstage $(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE) diff --git a/configs/config.lenovo_t400_all_debug_and_option_table b/configs/config.lenovo_t400_vboot_and_debug similarity index 84% rename from configs/config.lenovo_t400_all_debug_and_option_table rename to configs/config.lenovo_t400_vboot_and_debug index dc407478c7..5a1add6788 100644 --- a/configs/config.lenovo_t400_all_debug_and_option_table +++ b/configs/config.lenovo_t400_vboot_and_debug @@ -11,3 +11,5 @@ CONFIG_DEBUG_MALLOC=y CONFIG_DEBUG_ACPI=y CONFIG_DEBUG_BOOT_STATE=y CONFIG_DEBUG_ADA_CODE=y +CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y +CONFIG_VBOOT=y diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile index b433bc09b3..20afdc36c4 100644 --- a/payloads/external/GRUB2/Makefile +++ b/payloads/external/GRUB2/Makefile @@ -1,4 +1,4 @@ -TAG-$(CONFIG_GRUB2_MASTER)= +TAG-$(CONFIG_GRUB2_MASTER)=origin/HEAD TAG-$(CONFIG_GRUB2_REVISION)=$(CONFIG_GRUB2_REVISION_ID) TAG-$(CONFIG_GRUB2_STABLE)=grub-2.04 NAME-$(CONFIG_GRUB2_MASTER)=HEAD @@ -15,14 +15,14 @@ all: grub2 checkout: echo " GIT GRUB2 $(NAME-y)" - test -d grub2 || \ - git clone $(project_git_repo) $(project_dir) - cd grub2 && \ - git checkout master && \ - git pull; \ - test -n "$(TAG-y)" && \ - git branch -f $(NAME-y) $(TAG-y) && \ - git checkout $(NAME-y) || true + test -d $(project_dir) || git clone $(project_git_repo) $(project_dir) + git -C $(project_dir) fetch +ifeq ("$(shell git -C $(project_dir) status --ignored=no --untracked-files=no --porcelain)",) + git -C $(project_dir) checkout -f $(TAG-y) +else + echo "WARNING: index/tree not clean, skipping update / force checkout." + echo " Checkout manually with `git -C $(project_dir) checkout -f`." +endif grub2/build/config.h: $(CONFIG_DEP) | checkout echo " CONFIG GRUB2 $(NAME-y)" diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index 1a0acf1781..b1ab302794 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -221,12 +221,12 @@ includemakefiles= \ $(foreach class,classes subdirs $(classes) $(special-classes), $(eval $(class)-y:=)) \ $(eval -include $(1)) \ $(foreach class,$(classes-y), $(call add-class,$(class))) \ + $(foreach special,$(special-classes), \ + $(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \ $(foreach class,$(classes), \ $(eval $(class)-srcs+= \ $$(subst $(top)/,, \ $$(abspath $$(addprefix $(dir $(1)),$$($(class)-y)))))) \ - $(foreach special,$(special-classes), \ - $(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \ $(eval subdirs+=$$(subst $(CURDIR)/,,$$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y))))) # For each path in $(subdirs) call includemakefiles diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h index a707154648..ad1e9e2638 100644 --- a/payloads/libpayload/include/cbfs_core.h +++ b/payloads/libpayload/include/cbfs_core.h @@ -144,6 +144,7 @@ struct cbfs_file { #define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff #define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c #define CBFS_FILE_ATTR_TAG_HASH 0x68736148 +#define CBFS_FILE_ATTR_TAG_IBB 0x32494242 /* Initial BootBlock */ /* The common fields of extended cbfs file attributes. Attributes are expected to start with tag/len, then append their diff --git a/src/Kconfig b/src/Kconfig index 8fcb3ae8a3..793927a484 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -37,9 +37,26 @@ config CONFIGURABLE_CBFS_PREFIX help Select this to prompt to use to configure the prefix for cbfs files. +choice + prompt "CBFS prefix to use" + depends on CONFIGURABLE_CBFS_PREFIX + default CBFS_PREFIX_FALLBACK + +config CBFS_PREFIX_FALLBACK + bool "fallback" + +config CBFS_PREFIX_NORMAL + bool "normal" + +config CBFS_PREFIX_DIY + bool "Define your own cbfs prefix" + +endchoice + config CBFS_PREFIX - string "CBFS prefix to use" if CONFIGURABLE_CBFS_PREFIX - default "fallback" + string "CBFS prefix to use" if CBFS_PREFIX_DIY + default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK + default "normal" if CBFS_PREFIX_NORMAL help Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative. @@ -218,6 +235,20 @@ config USE_BLOBS might be required for some chipsets or boards. This flag ensures that a "Free" option remains available for users. +config USE_AMD_BLOBS + bool "Allow AMD blobs repository (with license agreement)" + depends on USE_BLOBS + help + This draws in the amd_blobs repository, which contains binary files + distributed by AMD, including VBIOS, PSP bootloaders, SMU firmwares, + etc. Selecting this item to download or clone the repo implies your + agreement to the AMD license agreement. A copy of the license text + may be reviewed by reading Documentation/soc/amd/amdblobs_license.md, + and your copy of the license is present in the repo once downloaded. + + Note that for some products, omitting PSP, SMU images, or other items + may result in a nonbooting coreboot.rom. + config COVERAGE bool "Code coverage support" depends on COMPILER_GCC @@ -1212,11 +1243,6 @@ config HAVE_ROMSTAGE bool default y -config HAVE_POSTCAR - bool - depends on POSTCAR_STAGE - default y - config HAVE_RAMSTAGE bool default n if RAMPAYLOAD diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index 47c333bf6a..9e10378510 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -17,6 +17,7 @@ config ARCH_ROMSTAGE_ARM config ARCH_RAMSTAGE_ARM bool select ARCH_ARM + select RAMSTAGE_CBMEM_TOP_ARG source src/arch/arm/armv4/Kconfig source src/arch/arm/armv7/Kconfig diff --git a/src/arch/arm/include/arch/stages.h b/src/arch/arm/include/arch/stages.h index 3841265341..795a3a3e7a 100644 --- a/src/arch/arm/include/arch/stages.h +++ b/src/arch/arm/include/arch/stages.h @@ -14,8 +14,9 @@ #ifndef __ARCH_STAGES_H #define __ARCH_STAGES_H +#include #include -void stage_entry(void); +void stage_entry(uintptr_t stage_arg); #endif diff --git a/src/arch/arm/libgcc/udivmoddi4.c b/src/arch/arm/libgcc/udivmoddi4.c index a97f4ad34c..6073848fb2 100644 --- a/src/arch/arm/libgcc/udivmoddi4.c +++ b/src/arch/arm/libgcc/udivmoddi4.c @@ -17,7 +17,7 @@ uint64_t __udivmoddi4(uint64_t num, uint64_t den, uint64_t *rem_p) { uint64_t quot = 0, qbit = 1; if (den == 0) { - return 1 / ((unsigned)den); /* Intentional divide by zero, without + return 1 / ((unsigned int)den); /* Intentional divide by zero, without triggering a compiler warning which would abort the build */ } diff --git a/src/arch/arm/stages.c b/src/arch/arm/stages.c index c9f5744f75..fc2ebdb2fc 100644 --- a/src/arch/arm/stages.c +++ b/src/arch/arm/stages.c @@ -22,13 +22,16 @@ * .text.stage_entry section created by -ffunction-sections). */ +#include #include #include /** * generic stage entry point. override this if board specific code is needed. */ -__weak void stage_entry(void) +__weak void stage_entry(uintptr_t stage_arg) { + if (!ENV_ROMSTAGE_OR_BEFORE) + _cbmem_top_ptr = stage_arg; main(); } diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index 3d1d1843e0..c7eafe649a 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -17,6 +17,7 @@ config ARCH_ROMSTAGE_ARM64 config ARCH_RAMSTAGE_ARM64 bool select ARCH_ARM64 + select RAMSTAGE_CBMEM_TOP_ARG source src/arch/arm64/armv8/Kconfig diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index c6df0ee02e..479a910cae 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -48,7 +49,10 @@ void arch_prog_run(struct prog *prog) } /* Generic stage entry point. Can be overridden by board/SoC if needed. */ -__weak void stage_entry(void) +__weak void stage_entry(uintptr_t stage_arg) { + if (!ENV_ROMSTAGE_OR_BEFORE) + _cbmem_top_ptr = stage_arg; + main(); } diff --git a/src/arch/arm64/include/arch/stages.h b/src/arch/arm64/include/arch/stages.h index d86172b2d0..c8a3bdd20e 100644 --- a/src/arch/arm64/include/arch/stages.h +++ b/src/arch/arm64/include/arch/stages.h @@ -17,7 +17,7 @@ #include #include -void stage_entry(void); +void stage_entry(uintptr_t stage_arg); /* This function is the romstage platform entry point, and should contain all chipset and mainboard setup until DRAM is initialized and accessible. */ diff --git a/src/arch/mips/Kconfig b/src/arch/mips/Kconfig index 9df514b21b..321bfc91fd 100644 --- a/src/arch/mips/Kconfig +++ b/src/arch/mips/Kconfig @@ -22,6 +22,7 @@ config ARCH_BOOTBLOCK_MIPS default n select BOOTBLOCK_CUSTOM select C_ENVIRONMENT_BOOTBLOCK + select RAMSTAGE_CBMEM_TOP_ARG config ARCH_VERSTAGE_MIPS bool diff --git a/src/arch/mips/include/arch/stages.h b/src/arch/mips/include/arch/stages.h index 63306bd783..3da02da1ca 100644 --- a/src/arch/mips/include/arch/stages.h +++ b/src/arch/mips/include/arch/stages.h @@ -14,8 +14,9 @@ #ifndef __MIPS_ARCH_STAGES_H #define __MIPS_ARCH_STAGES_H +#include #include -void stage_entry(void); +void stage_entry(uintptr_t stage_arg); #endif /* __MIPS_ARCH_STAGES_H */ diff --git a/src/arch/mips/stages.c b/src/arch/mips/stages.c index 0971e98905..bf31153d98 100644 --- a/src/arch/mips/stages.c +++ b/src/arch/mips/stages.c @@ -11,10 +11,13 @@ * GNU General Public License for more details. */ +#include #include #include -void stage_entry(void) +void stage_entry(uintptr_t stage_arg) { + if (!ENV_ROMSTAGE_OR_BEFORE) + _cbmem_top_ptr = stage_arg; main(); } diff --git a/src/arch/ppc64/Kconfig b/src/arch/ppc64/Kconfig index 0699e910ce..da9c155917 100644 --- a/src/arch/ppc64/Kconfig +++ b/src/arch/ppc64/Kconfig @@ -1,5 +1,6 @@ config ARCH_PPC64 bool + select RAMSTAGE_CBMEM_TOP_ARG config ARCH_BOOTBLOCK_PPC64 bool diff --git a/src/arch/ppc64/include/arch/stages.h b/src/arch/ppc64/include/arch/stages.h index a4939b1758..37e9f85c8c 100644 --- a/src/arch/ppc64/include/arch/stages.h +++ b/src/arch/ppc64/include/arch/stages.h @@ -16,6 +16,6 @@ #include -void stage_entry(void) __attribute__((section(".text.stage_entry"))); +void stage_entry(uintptr_t stage_arg) __attribute__((section(".text.stage_entry"))); #endif diff --git a/src/arch/ppc64/stages.c b/src/arch/ppc64/stages.c index 3cc9371ffe..aacf45f88f 100644 --- a/src/arch/ppc64/stages.c +++ b/src/arch/ppc64/stages.c @@ -22,9 +22,12 @@ * linker script. */ +#include #include -void stage_entry(void) +void stage_entry(uintptr_t stage_arg) { + if (!ENV_ROMSTAGE_OR_BEFORE) + _cbmem_top_ptr = stage_arg; main(); } diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c index 60a4bc0557..78e95fdd83 100644 --- a/src/arch/riscv/fit_payload.c +++ b/src/arch/riscv/fit_payload.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 502e7747f4..37b7d2daaa 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -16,6 +16,7 @@ config ARCH_X86 default n select PCI select RELOCATABLE_MODULES + select RAMSTAGE_CBMEM_TOP_ARG # stage selectors for x86 @@ -65,6 +66,14 @@ config ARCH_RAMSTAGE_X86_64 bool default n +config ARCH_X86_64_PGTBL_LOC + hex "x86_64 page table location in CBFS" + depends on ARCH_BOOTBLOCK_X86_64 + default 0xfffea000 + help + The position where to place pagetables. Needs to be known at + compile time. Must not overlap other files in CBFS. + config USE_MARCH_586 def_bool n help @@ -169,15 +178,6 @@ config BOOTBLOCK_NORTHBRIDGE_INIT config BOOTBLOCK_RESETS string -config BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP - bool - default n - help - Select this value to provide a routine to save the BIST and timestamp - values. The default code places the BIST value in MM0 and the - timestamp value in MM2:MM1. Another file is necessary when the CPU - does not support the MMx register set. - config HAVE_CMOS_DEFAULT def_bool n depends on HAVE_OPTION_TABLE diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 612424d5c8..447fd57a11 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -47,12 +47,6 @@ cbfs-files-$(CONFIG_VGA_BIOS_DGPU) += pci$(stripped_vgabios_dgpu_id).rom pci$(stripped_vgabios_dgpu_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_DGPU_FILE)) pci$(stripped_vgabios_dgpu_id).rom-type := optionrom -verstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c -bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c -romstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c -ramstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c -postcar-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c - ############################################################################### # common support for early assembly includes ############################################################################### @@ -94,18 +88,28 @@ $$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs) fi endef +############################################################################### +# all (bootblock,verstage,romstage,postcar,ramstage) +############################################################################### + +ifeq ($(CONFIG_ARCH_X86),y) + +all-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c +all-y += boot.c +all-y += memcpy.c +all-y += memset.c +all-y += cpu_common.c + +endif + ############################################################################### # bootblock ############################################################################### ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y) -bootblock-y += boot.c -bootblock-y += cpu_common.c bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S -bootblock-y += memcpy.c -bootblock-y += memset.c bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c @@ -183,14 +187,10 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) -verstage-y += boot.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += gdt_init.S verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S -verstage-y += cpu_common.c -verstage-y += memset.c -verstage-y += memcpy.c verstage-y += memmove.c verstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c # If verstage is a separate stage it means there's no need @@ -219,19 +219,15 @@ endif # CONFIG_ARCH_VERSTAGE_X86_32 / CONFIG_ARCH_VERSTAGE_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c -romstage-y += boot.c # gdt_init.S is included by entry32.inc when romstage is the first C # environment. romstage-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += gdt_init.S romstage-y += cbmem.c romstage-y += cbfs_and_run.c -romstage-y += cpu_common.c romstage-$(CONFIG_EARLY_EBDA_INIT) += ebda.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S -romstage-y += memcpy.c romstage-y += memmove.c -romstage-y += memset.c romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c romstage-y += postcar_loader.c romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c @@ -261,18 +257,13 @@ $(eval $(call create_class_compiler,postcar,x86_32)) postcar-generic-ccopts += -D__POSTCAR__ postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c -postcar-y += boot.c postcar-y += gdt_init.S postcar-y += cbfs_and_run.c -postcar-y += cbmem.c -postcar-y += cpu_common.c postcar-$(CONFIG_EARLY_EBDA_INIT) += ebda.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S postcar-y += exit_car.S -postcar-y += memcpy.c postcar-y += memmove.c -postcar-y += memset.c postcar-y += memlayout.ld postcar-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c postcar-y += postcar.c @@ -306,20 +297,15 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_device.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_pld.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c -ramstage-y += boot.c ramstage-y += c_start.S -ramstage-y += cbmem.c ramstage-y += cpu.c -ramstage-y += cpu_common.c ramstage-y += ebda.c ramstage-y += exception.c ramstage-y += idt.S ramstage-y += gdt.c ramstage-$(CONFIG_IOAPIC) += ioapic.c -ramstage-y += memcpy.c ramstage-y += memlayout.ld ramstage-y += memmove.c -ramstage-y += memset.c ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index b48640901c..2f793b4cb2 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -37,6 +37,8 @@ #include #include +static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp); + u8 acpi_checksum(u8 *table, u32 length) { u8 ret = 0; @@ -125,7 +127,7 @@ int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic) { - lapic->type = 0; /* Local APIC structure */ + lapic->type = LOCAL_APIC; /* Local APIC structure */ lapic->length = sizeof(acpi_madt_lapic_t); lapic->flags = (1 << 0); /* Processor/LAPIC enabled */ lapic->processor_id = cpu; @@ -163,7 +165,7 @@ unsigned long acpi_create_madt_lapics(unsigned long current) int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, u32 gsi_base) { - ioapic->type = 1; /* I/O APIC structure */ + ioapic->type = IO_APIC; /* I/O APIC structure */ ioapic->length = sizeof(acpi_madt_ioapic_t); ioapic->reserved = 0x00; ioapic->gsi_base = gsi_base; @@ -176,7 +178,7 @@ int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, u8 bus, u8 source, u32 gsirq, u16 flags) { - irqoverride->type = 2; /* Interrupt source override */ + irqoverride->type = IRQ_SOURCE_OVERRIDE; /* Interrupt source override */ irqoverride->length = sizeof(acpi_madt_irqoverride_t); irqoverride->bus = bus; irqoverride->source = source; @@ -189,7 +191,7 @@ int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, u16 flags, u8 lint) { - lapic_nmi->type = 4; /* Local APIC NMI structure */ + lapic_nmi->type = LOCAL_APIC_NMI; /* Local APIC NMI structure */ lapic_nmi->length = sizeof(acpi_madt_lapic_nmi_t); lapic_nmi->flags = flags; lapic_nmi->processor_id = cpu; @@ -735,14 +737,14 @@ void acpi_create_hpet(acpi_hpet_t *hpet) } void acpi_create_vfct(struct device *device, - struct acpi_vfct *vfct, + acpi_vfct_t *vfct, unsigned long (*acpi_fill_vfct)(struct device *device, - struct acpi_vfct *vfct_struct, unsigned long current)) + acpi_vfct_t *vfct_struct, unsigned long current)) { acpi_header_t *header = &(vfct->header); - unsigned long current = (unsigned long)vfct + sizeof(struct acpi_vfct); + unsigned long current = (unsigned long)vfct + sizeof(acpi_vfct_t); - memset((void *)vfct, 0, sizeof(struct acpi_vfct)); + memset((void *)vfct, 0, sizeof(acpi_vfct_t)); if (!header) return; @@ -1260,9 +1262,51 @@ unsigned long write_acpi_tables(unsigned long start) /* Align ACPI tables to 16byte */ current = acpi_align_current(current); + /* Special case for qemu */ fw = fw_cfg_acpi_tables(current); - if (fw) + if (fw) { + rsdp = NULL; + /* Find RSDP. */ + for (void *p = (void *)current; p < (void *)fw; p += 16) { + if (valid_rsdp((acpi_rsdp_t *)p)) { + rsdp = p; + break; + } + } + if (!rsdp) + return fw; + + /* Add BOOT0000 for Linux google firmware driver */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)fw; + current = (unsigned long)ssdt + sizeof(acpi_header_t); + + memset((void *)ssdt, 0, sizeof(acpi_header_t)); + + memcpy(&ssdt->signature, "SSDT", 4); + ssdt->revision = get_acpi_table_revision(SSDT); + memcpy(&ssdt->oem_id, OEM_ID, 6); + memcpy(&ssdt->oem_table_id, oem_table_id, 8); + ssdt->oem_revision = 42; + memcpy(&ssdt->asl_compiler_id, ASLC, 4); + ssdt->asl_compiler_revision = asl_revision; + ssdt->length = sizeof(acpi_header_t); + + acpigen_set_current((char *) current); + + /* Write object to declare coreboot tables */ + acpi_ssdt_write_cbtable(); + + /* (Re)calculate length and checksum. */ + ssdt->length = current - (unsigned long)ssdt; + ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + + acpi_add_table(rsdp, ssdt); + return fw; + } dsdt_file = cbfs_boot_map_with_leak( CONFIG_CBFS_PREFIX "/dsdt.aml", diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c index 5f60f1394a..ada49d0368 100644 --- a/src/arch/x86/boot.c +++ b/src/arch/x86/boot.c @@ -30,13 +30,12 @@ int payload_arch_usable_ram_quirk(uint64_t start, uint64_t size) void arch_prog_run(struct prog *prog) { - __asm__ volatile ( #ifdef __x86_64__ - "jmp *%%rdi\n" + void (*doit)(void *arg); #else - "jmp *%%edi\n" + /* Ensure the argument is pushed on the stack. */ + asmlinkage void (*doit)(void *arg); #endif - - :: "D"(prog_entry(prog)) - ); + doit = prog_entry(prog); + doit(prog_entry_arg(prog)); } diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 3cb57e058c..9fcb5c4e4a 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -31,6 +31,12 @@ #include #include + /* BIST result in eax */ + mov %eax, %ebx + /* entry64.inc preserves ebx. */ +#include + mov %ebx, %eax + #if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP) /* Wait for a JTAG debugger to break in and set EBX non-zero */ diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c index fc041c8018..d161435424 100644 --- a/src/arch/x86/bootblock_simple.c +++ b/src/arch/x86/bootblock_simple.c @@ -27,12 +27,7 @@ static void main(unsigned long bist) #endif } -#if CONFIG(VBOOT_SEPARATE_VERSTAGE) - const char *target1 = "fallback/verstage"; -#else const char *target1 = "fallback/romstage"; -#endif - unsigned long entry; entry = findstage(target1); if (entry) diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 32b848df9b..bd99c21c91 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -12,6 +12,7 @@ */ #include +#include /* Place the stack in the bss section. It's not necessary to define it in the * the linker script. */ @@ -42,16 +43,16 @@ _start: cli lgdt %cs:gdtaddr #ifndef __x86_64__ - ljmp $0x10, $1f + ljmp $RAM_CODE_SEG, $1f #endif -1: movl $0x18, %eax +1: movl $RAM_DATA_SEG, %eax movl %eax, %ds movl %eax, %es movl %eax, %ss movl %eax, %fs movl %eax, %gs #ifdef __x86_64__ - mov $0x48, %ecx + mov $RAM_CODE_SEG64, %ecx call SetCodeSelector #endif @@ -59,6 +60,14 @@ _start: cld +#ifdef __x86_64__ + mov %rdi, _cbmem_top_ptr +#else + /* The return argument is at 0(%esp), the calling argument at 4(%esp) */ + movl 4(%esp), %eax + movl %eax, _cbmem_top_ptr +#endif + /** poison the stack. Code should not count on the * stack being full of zeros. This stack poisoning * recently uncovered a bug in the broadcast SIPI diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 16c35b5dea..fc85bc617f 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -16,21 +16,10 @@ #if CONFIG(CBMEM_TOP_BACKUP) -void *cbmem_top(void) +void *cbmem_top_chipset(void) { - static void *cbmem_top_backup; - void *top_backup; - - if (ENV_RAMSTAGE && cbmem_top_backup != NULL) - return cbmem_top_backup; - /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ - top_backup = (void *)restore_top_of_low_cacheable(); - - if (ENV_RAMSTAGE) - cbmem_top_backup = top_backup; - - return top_backup; + return (void *)restore_top_of_low_cacheable(); } #endif /* CBMEM_TOP_BACKUP */ diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index cfab21956b..30d2cca87a 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -315,7 +315,7 @@ void lb_arch_add_records(struct lb_header *header) struct lb_tsc_info *tsc_info; /* Don't advertise a TSC rate unless it's constant. */ - if (!CONFIG(TSC_CONSTANT_RATE)) + if (!tsc_constant_rate()) return; freq_khz = tsc_freq_mhz() * 1000; diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 679e335eb3..8c2878481b 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -31,6 +31,14 @@ _start: /* Migrate GDT to this text segment */ call gdt_init +#ifdef __x86_64__ + mov %rdi, _cbmem_top_ptr +#else + /* The return argument is at 0(%esp), the calling argument at 4(%esp) */ + movl 4(%esp), %eax + movl %eax, _cbmem_top_ptr +#endif + /* chipset_teardown_car() is expected to disable cache-as-ram. */ call chipset_teardown_car diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 6cd4e9fae8..479067ffaa 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -147,21 +147,21 @@ typedef struct acpi_table_header { /* RSDT (Root System Description Table) */ typedef struct acpi_rsdt { - struct acpi_table_header header; + acpi_header_t header; u32 entry[MAX_ACPI_TABLES]; } __packed acpi_rsdt_t; /* XSDT (Extended System Description Table) */ typedef struct acpi_xsdt { - struct acpi_table_header header; + acpi_header_t header; u64 entry[MAX_ACPI_TABLES]; } __packed acpi_xsdt_t; /* HPET timers */ typedef struct acpi_hpet { - struct acpi_table_header header; + acpi_header_t header; u32 id; - struct acpi_gen_regaddr addr; + acpi_addr_t addr; u8 number; u16 min_tick; u8 attributes; @@ -169,19 +169,19 @@ typedef struct acpi_hpet { /* MCFG (PCI Express MMIO config space BAR description table) */ typedef struct acpi_mcfg { - struct acpi_table_header header; + acpi_header_t header; u8 reserved[8]; } __packed acpi_mcfg_t; typedef struct acpi_tcpa { - struct acpi_table_header header; + acpi_header_t header; u16 platform_class; u32 laml; u64 lasa; } __packed acpi_tcpa_t; typedef struct acpi_tpm2 { - struct acpi_table_header header; + acpi_header_t header; u16 platform_class; u8 reserved[2]; u64 control_area; @@ -202,7 +202,7 @@ typedef struct acpi_mcfg_mmconfig { /* SRAT (System Resource Affinity Table) */ typedef struct acpi_srat { - struct acpi_table_header header; + acpi_header_t header; u32 resv; u64 resv1; /* Followed by static resource allocation structure[n] */ @@ -239,19 +239,19 @@ typedef struct acpi_srat_mem { /* SLIT (System Locality Distance Information Table) */ typedef struct acpi_slit { - struct acpi_table_header header; + acpi_header_t header; /* Followed by static resource allocation 8+byte[num*num] */ } __packed acpi_slit_t; /* MADT (Multiple APIC Description Table) */ typedef struct acpi_madt { - struct acpi_table_header header; + acpi_header_t header; u32 lapic_addr; /* Local APIC address */ u32 flags; /* Multiple APIC flags */ } __packed acpi_madt_t; /* VFCT image header */ -struct acpi_vfct_image_hdr { +typedef struct acpi_vfct_image_hdr { u32 PCIBus; u32 PCIDevice; u32 PCIFunction; @@ -262,17 +262,17 @@ struct acpi_vfct_image_hdr { u32 Revision; u32 ImageLength; u8 VbiosContent; // dummy - copy VBIOS here -} __packed; +} __packed acpi_vfct_image_hdr_t; /* VFCT (VBIOS Fetch Table) */ -struct acpi_vfct { - struct acpi_table_header header; +typedef struct acpi_vfct { + acpi_header_t header; u8 TableUUID[16]; u32 VBIOSImageOffset; u32 Lib1ImageOffset; u32 Reserved[4]; - struct acpi_vfct_image_hdr image_hdr; -} __packed; + acpi_vfct_image_hdr_t image_hdr; +} __packed acpi_vfct_t; typedef struct acpi_ivrs_info { } __packed acpi_ivrs_info_t; @@ -294,7 +294,7 @@ typedef struct acpi_ivrs_ivhd { /* IVRS (I/O Virtualization Reporting Structure) Type 10h */ typedef struct acpi_ivrs { - struct acpi_table_header header; + acpi_header_t header; uint32_t iv_info; uint32_t reserved[2]; struct acpi_ivrs_ivhd ivhd; @@ -382,7 +382,7 @@ typedef struct dmar_andd_entry { /* DMAR (DMA Remapping Reporting Structure) */ typedef struct acpi_dmar { - struct acpi_table_header header; + acpi_header_t header; u8 host_address_width; u8 flags; u8 reserved[10]; @@ -390,24 +390,23 @@ typedef struct acpi_dmar { } __packed acpi_dmar_t; /* MADT: APIC Structure Types */ -/* TODO: Convert to ALLCAPS. */ enum acpi_apic_types { - LocalApic = 0, /* Processor local APIC */ - IOApic = 1, /* I/O APIC */ - IRQSourceOverride = 2, /* Interrupt source override */ - NMIType = 3, /* NMI source */ - LocalApicNMI = 4, /* Local APIC NMI */ - LApicAddressOverride = 5, /* Local APIC address override */ - IOSApic = 6, /* I/O SAPIC */ - LocalSApic = 7, /* Local SAPIC */ - PlatformIRQSources = 8, /* Platform interrupt sources */ - Localx2Apic = 9, /* Processor local x2APIC */ - Localx2ApicNMI = 10, /* Local x2APIC NMI */ - GICC = 11, /* GIC CPU Interface */ - GICD = 12, /* GIC Distributor */ - GIC_MSI_FRAME = 13, /* GIC MSI Frame */ - GICR = 14, /* GIC Redistributor */ - GIC_ITS = 15, /* Interrupt Translation Service */ + LOCAL_APIC, /* Processor local APIC */ + IO_APIC, /* I/O APIC */ + IRQ_SOURCE_OVERRIDE, /* Interrupt source override */ + NMI_TYPE, /* NMI source */ + LOCAL_APIC_NMI, /* Local APIC NMI */ + LAPIC_ADDRESS_OVERRIDE, /* Local APIC address override */ + IO_SAPIC, /* I/O SAPIC */ + LOCAL_SAPIC, /* Local SAPIC */ + PLATFORM_IRQ_SOURCES, /* Platform interrupt sources */ + LOCAL_X2APIC, /* Processor local x2APIC */ + LOCAL_X2APIC_NMI, /* Local x2APIC NMI */ + GICC, /* GIC CPU Interface */ + GICD, /* GIC Distributor */ + GIC_MSI_FRAME, /* GIC MSI Frame */ + GICR, /* GIC Redistributor */ + GIC_ITS, /* Interrupt Translation Service */ /* 0x10-0x7f: Reserved */ /* 0x80-0xff: Reserved for OEM use */ }; @@ -466,7 +465,7 @@ typedef struct acpi_madt_irqoverride { /* DBG2: Microsoft Debug Port Table 2 header */ typedef struct acpi_dbg2_header { - struct acpi_table_header header; + acpi_header_t header; uint32_t devices_offset; uint32_t devices_count; } __attribute__((packed)) acpi_dbg2_header_t; @@ -489,7 +488,7 @@ typedef struct acpi_dbg2_device { /* FADT (Fixed ACPI Description Table) */ typedef struct acpi_fadt { - struct acpi_table_header header; + acpi_header_t header; u32 firmware_ctrl; u32 dsdt; u8 reserved; /* Should be 0 */ @@ -528,7 +527,7 @@ typedef struct acpi_fadt { u16 iapc_boot_arch; u8 res2; u32 flags; - struct acpi_gen_regaddr reset_reg; + acpi_addr_t reset_reg; u8 reset_value; u16 ARM_boot_arch; u8 FADT_MinorVersion; @@ -536,14 +535,14 @@ typedef struct acpi_fadt { u32 x_firmware_ctl_h; u32 x_dsdt_l; u32 x_dsdt_h; - struct acpi_gen_regaddr x_pm1a_evt_blk; - struct acpi_gen_regaddr x_pm1b_evt_blk; - struct acpi_gen_regaddr x_pm1a_cnt_blk; - struct acpi_gen_regaddr x_pm1b_cnt_blk; - struct acpi_gen_regaddr x_pm2_cnt_blk; - struct acpi_gen_regaddr x_pm_tmr_blk; - struct acpi_gen_regaddr x_gpe0_blk; - struct acpi_gen_regaddr x_gpe1_blk; + acpi_addr_t x_pm1a_evt_blk; + acpi_addr_t x_pm1b_evt_blk; + acpi_addr_t x_pm1a_cnt_blk; + acpi_addr_t x_pm1b_cnt_blk; + acpi_addr_t x_pm2_cnt_blk; + acpi_addr_t x_pm_tmr_blk; + acpi_addr_t x_gpe0_blk; + acpi_addr_t x_gpe1_blk; } __packed acpi_fadt_t; /* FADT TABLE Revision values */ @@ -634,9 +633,9 @@ typedef struct acpi_facs { /* ECDT (Embedded Controller Boot Resources Table) */ typedef struct acpi_ecdt { - struct acpi_table_header header; - struct acpi_gen_regaddr ec_control; /* EC control register */ - struct acpi_gen_regaddr ec_data; /* EC data register */ + acpi_header_t header; + acpi_addr_t ec_control; /* EC control register */ + acpi_addr_t ec_data; /* EC data register */ u32 uid; /* UID */ u8 gpe_bit; /* GPE bit */ u8 ec_id[]; /* EC ID */ @@ -644,7 +643,7 @@ typedef struct acpi_ecdt { /* HEST (Hardware Error Source Table) */ typedef struct acpi_hest { - struct acpi_table_header header; + acpi_header_t header; u32 error_source_count; /* error_source_struct(s) */ } __packed acpi_hest_t; @@ -677,7 +676,7 @@ typedef struct acpi_hest_hen { /* BERT (Boot Error Record Table) */ typedef struct acpi_bert { - struct acpi_table_header header; + acpi_header_t header; u32 region_length; u64 error_region; } __packed acpi_bert_t; @@ -794,7 +793,7 @@ enum acpi_ipmi_interface_type { /* ACPI IPMI 2.0 */ struct acpi_spmi { - struct acpi_table_header header; + acpi_header_t header; u8 interface_type; u8 reserved; u16 specification_revision; @@ -864,9 +863,9 @@ void acpi_create_slit(acpi_slit_t *slit, unsigned long (*acpi_fill_slit)(unsigned long current)); void acpi_create_vfct(struct device *device, - struct acpi_vfct *vfct, + acpi_vfct_t *vfct, unsigned long (*acpi_fill_vfct)(struct device *device, - struct acpi_vfct *vfct_struct, + acpi_vfct_t *vfct_struct, unsigned long current)); void acpi_create_ipmi(struct device *device, diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index b82473621d..9133f53065 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -141,6 +141,11 @@ static inline unsigned int cpuid_edx(unsigned int op) return edx; } +static inline unsigned int cpuid_get_max_func(void) +{ + return cpuid_eax(0); +} + #define X86_VENDOR_INVALID 0 #define X86_VENDOR_INTEL 1 #define X86_VENDOR_CYRIX 2 diff --git a/src/arch/x86/include/arch/ram_segs.h b/src/arch/x86/include/arch/ram_segs.h new file mode 100644 index 0000000000..39d0c64896 --- /dev/null +++ b/src/arch/x86/include/arch/ram_segs.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef RAM_SEGS_H +#define RAM_SEGS_H + +#define RAM_CODE_SEG 0x10 +#define RAM_DATA_SEG 0x18 +#define RAM_CODE16_SEG 0x28 +#define RAM_DATA16_SEG 0x30 +#define RAM_CODE_ACPI_SEG 0x38 +#define RAM_DATA_ACPI_SEG 0x40 +#define RAM_CODE_SEG64 0x48 + +#endif /* RAM_SEGS_H */ diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index c6149ab26a..0a5d50cc1a 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -225,5 +225,7 @@ void run_postcar_phase(struct postcar_frame *pcf) /* As postcar exist, it's end of romstage here */ timestamp_add_now(TS_END_ROMSTAGE); + prog_set_arg(&prog, cbmem_top()); + prog_run(&prog); } diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 4eb8726137..261888fc7f 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -492,7 +492,7 @@ smbios_board_type __weak smbios_mainboard_board_type(void) return SMBIOS_BOARD_TYPE_UNKNOWN; } -u8 __weak smbios_mainboard_enclosure_type(void) +smbios_enclosure_type __weak smbios_mainboard_enclosure_type(void) { return CONFIG_SMBIOS_ENCLOSURE_TYPE; } @@ -522,6 +522,16 @@ void __weak smbios_system_set_uuid(u8 *uuid) /* leave all zero */ } +unsigned int __weak smbios_cpu_get_max_speed_mhz(void) +{ + return 0; /* Unknown */ +} + +unsigned int __weak smbios_cpu_get_current_speed_mhz(void) +{ + return 0; /* Unknown */ +} + const char *__weak smbios_system_sku(void) { return ""; @@ -648,11 +658,20 @@ static int smbios_write_type4(unsigned long *current, int handle) t->processor_family = (res.eax > 0) ? 0x0c : 0x6; t->processor_type = 3; /* System Processor */ t->core_count = (res.ebx >> 16) & 0xff; + /* Assume we enable all the cores always, capped only by MAX_CPUS */ + t->core_enabled = MAX(t->core_count, CONFIG_MAX_CPUS); t->l1_cache_handle = 0xffff; t->l2_cache_handle = 0xffff; t->l3_cache_handle = 0xffff; t->processor_upgrade = get_socket_type(); len = t->length + smbios_string_table_len(t->eos); + if (cpu_have_cpuid() && cpuid_get_max_func() >= 0x16) { + t->max_speed = cpuid_ebx(0x16); + t->current_speed = cpuid_eax(0x16); /* base frequency */ + } else { + t->max_speed = smbios_cpu_get_max_speed_mhz(); + t->current_speed = smbios_cpu_get_current_speed_mhz(); + } *current += len; return len; } diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c index 92d9590af4..8cf0f96e31 100644 --- a/src/arch/x86/timestamp.c +++ b/src/arch/x86/timestamp.c @@ -22,7 +22,7 @@ uint64_t timestamp_get(void) int timestamp_tick_freq_mhz(void) { /* Chipsets that have a constant TSC provide this value correctly. */ - if (CONFIG(TSC_CONSTANT_RATE)) + if (tsc_constant_rate()) return tsc_freq_mhz(); /* Filling tick_freq_mhz = 0 in timestamps-table will trigger diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h index 6e254f6bbe..a4708e8124 100644 --- a/src/commonlib/include/commonlib/cbfs_serialized.h +++ b/src/commonlib/include/commonlib/cbfs_serialized.h @@ -157,6 +157,7 @@ struct cbfs_file_attribute { #define CBFS_FILE_ATTR_TAG_HASH 0x68736148 #define CBFS_FILE_ATTR_TAG_POSITION 0x42435350 /* PSCB */ #define CBFS_FILE_ATTR_TAG_ALIGNMENT 0x42434c41 /* ALCB */ +#define CBFS_FILE_ATTR_TAG_IBB 0x32494242 /* Initial BootBlock */ struct cbfs_file_attr_compression { uint32_t tag; diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 30bf88ada8..54a0dee55a 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -56,6 +56,8 @@ #define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4 #define CBMEM_ID_ROOT 0xff4007ff #define CBMEM_ID_SMBIOS 0x534d4254 +#define CBMEM_ID_BERT_RAW_DATA 0x42455254 +#define CBMEM_ID_SMM_TSEG_SPACE 0x54534547 #define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee #define CBMEM_ID_STAGEx_META 0x57a9e000 #define CBMEM_ID_STAGEx_CACHE 0x57a9e100 @@ -119,6 +121,8 @@ { CBMEM_ID_ROMSTAGE_RAM_STACK, "ROMSTG STCK" }, \ { CBMEM_ID_ROOT, "CBMEM ROOT " }, \ { CBMEM_ID_SMBIOS, "SMBIOS " }, \ + { CBMEM_ID_BERT_RAW_DATA, "BERT DATA " }, \ + { CBMEM_ID_SMM_TSEG_SPACE, "TSEG " }, \ { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \ { CBMEM_ID_STORAGE_DATA, "SD/MMC/eMMC" }, \ { CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \ diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index 4429ea41c3..f3b71d7016 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -137,4 +137,8 @@ #define __unused __attribute__((unused)) #endif +#ifndef alloca +#define alloca(x) __builtin_alloca(x) +#endif + #endif /* COMMONLIB_HELPERS_H */ diff --git a/src/console/Kconfig b/src/console/Kconfig index 5d505d2d21..e767edd4fd 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -176,13 +176,6 @@ config CONSOLE_USB # TODO: Deps? # TODO: Improve description. -config ONBOARD_VGA_IS_PRIMARY - bool "Use onboard VGA as primary video device" - default n - depends on PCI - help - If not selected, the last adapter found will be used. - config CONSOLE_NE2K bool "Network console over NE2000 compatible Ethernet adapter" default n diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 3311849941..2154eb9254 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -23,7 +23,8 @@ romstage-y += init.c console.c romstage-y += post.c romstage-y += die.c -postcar-$(CONFIG_POSTCAR_CONSOLE) += vtxprintf.c printk.c vsprintf.c +postcar-y += vtxprintf.c vsprintf.c +postcar-$(CONFIG_POSTCAR_CONSOLE) += printk.c postcar-$(CONFIG_POSTCAR_CONSOLE) += init.c console.c postcar-y += post.c postcar-y += die.c diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index f21bf5467f..b1fde2dcf7 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -28,20 +28,10 @@ config CPU_AMD_AGESA select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG + select NO_FIXED_XIP_ROM_SIZE if CPU_AMD_AGESA -config XIP_ROM_SIZE - hex - default 0x100000 - help - Overwride the default write through caching size as 1M Bytes. - On some AMD platforms, one socket supports 2 or more kinds of - processor family, compiling several CPU families agesa code - will increase the romstage size. - In order to execute romstage in place on the flash ROM, - more space is required to be set as write through caching. - config UDELAY_LAPIC_FIXED_FSB int default 200 diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig index 4fc2ba076c..0324d129a3 100644 --- a/src/cpu/amd/agesa/family12/Kconfig +++ b/src/cpu/amd/agesa/family12/Kconfig @@ -21,8 +21,4 @@ config CPU_ADDR_BITS int default 48 -config XIP_ROM_SIZE - hex - default 0x80000 - endif diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index adbe7fdb76..518235b12c 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -21,8 +21,4 @@ config CPU_ADDR_BITS int default 36 -config XIP_ROM_SIZE - hex - default 0x80000 - endif diff --git a/src/cpu/amd/agesa/family14/acpi/cpu.asl b/src/cpu/amd/agesa/family14/acpi/cpu.asl index 81b5a3550a..98b0193c77 100644 --- a/src/cpu/amd/agesa/family14/acpi/cpu.asl +++ b/src/cpu/amd/agesa/family14/acpi/cpu.asl @@ -16,19 +16,14 @@ * */ Scope (\_PR) { /* define processor scope */ - Processor( - C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ - 0, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + + Device (C000) { + Name (_HID, "ACPI0007") + Name (_UID, 0) } - Processor( - C001, /* name space name */ - 1, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (C001) { + Name (_HID, "ACPI0007") + Name (_UID, 1) } } /* End _PR scope */ diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index fde1adf118..93e9ab26ae 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -21,8 +21,4 @@ config CPU_ADDR_BITS int default 48 -config XIP_ROM_SIZE - hex - default 0x100000 - endif diff --git a/src/cpu/amd/agesa/family15tn/acpi/cpu.asl b/src/cpu/amd/agesa/family15tn/acpi/cpu.asl index 82168508c4..68e6e97bf3 100644 --- a/src/cpu/amd/agesa/family15tn/acpi/cpu.asl +++ b/src/cpu/amd/agesa/family15tn/acpi/cpu.asl @@ -11,66 +11,49 @@ * GNU General Public License for more details. */ - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Processor( - P000, /* name space name */ - 0, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } +/* + * Processor Object + * + */ +Scope (\_PR) { /* define processor scope */ - Processor( - P001, /* name space name */ - 1, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P002, /* name space name */ - 2, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P003, /* name space name */ - 3, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P004, /* name space name */ - 4, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P005, /* name space name */ - 5, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P006, /* name space name */ - 6, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P007, /* name space name */ - 7, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - } /* End _PR scope */ + Device (P000) { + Name(_HID, "ACPI0007") + Name(_UID, 0) + } + + Device (P001) { + Name(_HID, "ACPI0007") + Name(_UID, 1) + } + + Device (P002) { + Name(_HID, "ACPI0007") + Name(_UID, 2) + } + + Device (P003) { + Name(_HID, "ACPI0007") + Name(_UID, 3) + } + + Device (P004) { + Name(_HID, "ACPI0007") + Name(_UID, 4) + } + + Device (P005) { + Name(_HID, "ACPI0007") + Name(_UID, 5) + } + + Device (P006) { + Name(_HID, "ACPI0007") + Name(_UID, 6) + } + + Device (P007) { + Name(_HID, "ACPI0007") + Name(_UID, 7) + } +} /* End _PR scope */ diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index 9fef94d327..e87a2d4e42 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -21,10 +21,6 @@ config CPU_ADDR_BITS int default 40 -config XIP_ROM_SIZE - hex - default 0x100000 - config FORCE_AM1_SOCKET_SUPPORT bool default n diff --git a/src/cpu/amd/agesa/family16kb/acpi/cpu.asl b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl index bc52b681e5..37eb58abc0 100644 --- a/src/cpu/amd/agesa/family16kb/acpi/cpu.asl +++ b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl @@ -15,62 +15,44 @@ * Processor Object * */ -Scope (\_PR) { /* define processor scope */ - Processor( - P000, /* name space name */ - 0, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { +Scope (\_PR) {/* define processor scope */ + Device (P000) { + Name(_HID, "ACPI0007") + Name(_UID, 0) } - Processor( - P001, /* name space name */ - 1, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (P001) { + Name(_HID, "ACPI0007") + Name(_UID, 1) } - Processor( - P002, /* name space name */ - 2, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + + Device (P002) { + Name(_HID, "ACPI0007") + Name(_UID, 2) } - Processor( - P003, /* name space name */ - 3, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + + Device (P003) { + Name(_HID, "ACPI0007") + Name(_UID, 3) } - Processor( - P004, /* name space name */ - 4, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + + Device (P004) { + Name(_HID, "ACPI0007") + Name(_UID, 4) } - Processor( - P005, /* name space name */ - 5, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + + Device (P005) { + Name(_HID, "ACPI0007") + Name(_UID, 5) } - Processor( - P006, /* name space name */ - 6, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + + Device (P006) { + Name(_HID, "ACPI0007") + Name(_UID, 6) } - Processor( - P007, /* name space name */ - 7, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + + Device (P007) { + Name(_HID, "ACPI0007") + Name(_UID, 7) } } /* End _PR scope */ diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 1c2b214dce..57207a431a 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -91,6 +91,7 @@ b.- prep_fid_change(...) #include #include #include +#include static inline void print_debug_fv(const char *str, u32 val) { @@ -1042,7 +1043,7 @@ struct ap_apicid_st { u8 apicid[NODE_NUMS * 4]; }; -static void store_ap_apicid(unsigned ap_apicid, void *gp) +static void store_ap_apicid(unsigned int ap_apicid, void *gp) { struct ap_apicid_st *p = gp; diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h index 07d7dbf8a9..4be6ee806f 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.h +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.h @@ -26,7 +26,7 @@ #define NODE_MC(x) NODE_PCI(x,3) #define NODE_LC(x) NODE_PCI(x,4) -unsigned int get_sbdn(unsigned bus); +unsigned int get_sbdn(unsigned int bus); void cpuSetAMDMSR(uint8_t node_id); typedef void (*process_ap_t) (u32 apicid, void *gp); diff --git a/src/cpu/amd/family_10h-family_15h/processor_name.c b/src/cpu/amd/family_10h-family_15h/processor_name.c index fbd2bb5a33..c5e31fd59d 100644 --- a/src/cpu/amd/family_10h-family_15h/processor_name.c +++ b/src/cpu/amd/family_10h-family_15h/processor_name.c @@ -27,6 +27,8 @@ #include #include #include +#include +#include /* The maximum length of CPU names is 48 bytes, including the final NULL byte. * If you change these names your BIOS will _NOT_ pass the AMD validation and diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c index 3946b67b2d..a1dc1f4ba6 100644 --- a/src/cpu/amd/family_10h-family_15h/ram_calc.c +++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c @@ -86,7 +86,7 @@ uint64_t get_cc6_memory_size() return cc6_size; } -void *cbmem_top(void) +void *cbmem_top_chipset(void) { uint32_t topmem = rdmsr(TOP_MEM).lo; diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index e5e27b55b4..37025ab4bf 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -21,8 +21,4 @@ config CPU_ADDR_BITS int default 48 -config XIP_ROM_SIZE - hex - default 0x100000 - endif diff --git a/src/cpu/amd/pi/00630F01/acpi/cpu.asl b/src/cpu/amd/pi/00630F01/acpi/cpu.asl index ef71a0fd5b..68e6e97bf3 100644 --- a/src/cpu/amd/pi/00630F01/acpi/cpu.asl +++ b/src/cpu/amd/pi/00630F01/acpi/cpu.asl @@ -11,94 +11,49 @@ * GNU General Public License for more details. */ - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Processor( - P000, /* name space name */ - 0, /* Unique core number for this processor within a socket */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } +/* + * Processor Object + * + */ +Scope (\_PR) { /* define processor scope */ - Processor( - P001, /* name space name */ - 1, /* Unique core number for this processor within a socket */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P002, /* name space name */ - 2, /* Unique core number for this processor within a socket */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P003, /* name space name */ - 3, /* Unique core number for this processor within a socket */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P004, /* name space name */ - 4, /* Unique core number for this processor within a socket */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P005, /* name space name */ - 5, /* Unique core number for this processor within a socket */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P006, /* name space name */ - 6, /* Unique core number for this processor within a socket */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P007, /* name space name */ - 7, /* Unique core number for this processor within a socket */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P008, /* name space name */ - 8, /* Unique core number for this processor within a socket */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P009, /* name space name */ - 9, /* Unique core number for this processor within a socket */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P010, /* name space name */ - 10, /* Unique core number for this processor within a socket */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P011, /* name space name */ - 11, /* Unique core number for this processor within a socket */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - } /* End _PR scope */ + Device (P000) { + Name(_HID, "ACPI0007") + Name(_UID, 0) + } + + Device (P001) { + Name(_HID, "ACPI0007") + Name(_UID, 1) + } + + Device (P002) { + Name(_HID, "ACPI0007") + Name(_UID, 2) + } + + Device (P003) { + Name(_HID, "ACPI0007") + Name(_UID, 3) + } + + Device (P004) { + Name(_HID, "ACPI0007") + Name(_UID, 4) + } + + Device (P005) { + Name(_HID, "ACPI0007") + Name(_UID, 5) + } + + Device (P006) { + Name(_HID, "ACPI0007") + Name(_UID, 6) + } + + Device (P007) { + Name(_HID, "ACPI0007") + Name(_UID, 7) + } +} /* End _PR scope */ diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index 647044843a..374672da03 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -21,8 +21,4 @@ config CPU_ADDR_BITS int default 48 -config XIP_ROM_SIZE - hex - default 0x100000 - endif diff --git a/src/cpu/amd/pi/00660F01/acpi/cpu.asl b/src/cpu/amd/pi/00660F01/acpi/cpu.asl index bc52b681e5..68e6e97bf3 100644 --- a/src/cpu/amd/pi/00660F01/acpi/cpu.asl +++ b/src/cpu/amd/pi/00660F01/acpi/cpu.asl @@ -15,62 +15,45 @@ * Processor Object * */ -Scope (\_PR) { /* define processor scope */ - Processor( - P000, /* name space name */ - 0, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { +Scope (\_PR) { /* define processor scope */ + + Device (P000) { + Name(_HID, "ACPI0007") + Name(_UID, 0) } - Processor( - P001, /* name space name */ - 1, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (P001) { + Name(_HID, "ACPI0007") + Name(_UID, 1) } - Processor( - P002, /* name space name */ - 2, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + + Device (P002) { + Name(_HID, "ACPI0007") + Name(_UID, 2) } - Processor( - P003, /* name space name */ - 3, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + + Device (P003) { + Name(_HID, "ACPI0007") + Name(_UID, 3) } - Processor( - P004, /* name space name */ - 4, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + + Device (P004) { + Name(_HID, "ACPI0007") + Name(_UID, 4) } - Processor( - P005, /* name space name */ - 5, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + + Device (P005) { + Name(_HID, "ACPI0007") + Name(_UID, 5) } - Processor( - P006, /* name space name */ - 6, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + + Device (P006) { + Name(_HID, "ACPI0007") + Name(_UID, 6) } - Processor( - P007, /* name space name */ - 7, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + + Device (P007) { + Name(_HID, "ACPI0007") + Name(_UID, 7) } } /* End _PR scope */ diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index 43abc80aba..7ba49439eb 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -23,8 +23,4 @@ config CPU_ADDR_BITS int default 40 -config XIP_ROM_SIZE - hex - default 0x100000 - endif diff --git a/src/cpu/amd/pi/00730F01/acpi/cpu.asl b/src/cpu/amd/pi/00730F01/acpi/cpu.asl index 82168508c4..68e6e97bf3 100644 --- a/src/cpu/amd/pi/00730F01/acpi/cpu.asl +++ b/src/cpu/amd/pi/00730F01/acpi/cpu.asl @@ -11,66 +11,49 @@ * GNU General Public License for more details. */ - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Processor( - P000, /* name space name */ - 0, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } +/* + * Processor Object + * + */ +Scope (\_PR) { /* define processor scope */ - Processor( - P001, /* name space name */ - 1, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P002, /* name space name */ - 2, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P003, /* name space name */ - 3, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P004, /* name space name */ - 4, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P005, /* name space name */ - 5, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P006, /* name space name */ - 6, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P007, /* name space name */ - 7, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - } /* End _PR scope */ + Device (P000) { + Name(_HID, "ACPI0007") + Name(_UID, 0) + } + + Device (P001) { + Name(_HID, "ACPI0007") + Name(_UID, 1) + } + + Device (P002) { + Name(_HID, "ACPI0007") + Name(_UID, 2) + } + + Device (P003) { + Name(_HID, "ACPI0007") + Name(_UID, 3) + } + + Device (P004) { + Name(_HID, "ACPI0007") + Name(_UID, 4) + } + + Device (P005) { + Name(_HID, "ACPI0007") + Name(_UID, 5) + } + + Device (P006) { + Name(_HID, "ACPI0007") + Name(_UID, 6) + } + + Device (P007) { + Name(_HID, "ACPI0007") + Name(_UID, 7) + } +} /* End _PR scope */ diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 973a086e9f..b33302ecef 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -28,23 +28,13 @@ config CPU_AMD_PI select SPI_FLASH if HAVE_ACPI_RESUME select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER select SMM_ASEG + select NO_FIXED_XIP_ROM_SIZE if CPU_AMD_PI config BINARYPI_LEGACY_WRAPPER def_bool n -config XIP_ROM_SIZE - hex - default 0x100000 - help - Overwride the default write through caching size as 1M Bytes. - On some AMD platforms, one socket supports 2 or more kinds of - processor family, compiling several CPU families agesa code - will increase the romstage size. - In order to execute romstage in place on the flash ROM, - more space is required to be set as write through caching. - config UDELAY_LAPIC_FIXED_FSB int default 200 diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index f8fa806125..a1bec12ede 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -18,6 +18,15 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) +#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" +#endif +#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE +#else +#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE +#endif + .global bootblock_pre_c_entry .code32 @@ -148,13 +157,13 @@ addrsize_set_high: * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html */ movl $_program, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + andl $(~(XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr post_code(0x28) diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 9a7dc5f256..33f0bfd2a3 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -18,6 +18,15 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) +#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" +#endif +#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE +#else +#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE +#endif + .global bootblock_pre_c_entry .code32 @@ -136,13 +145,13 @@ addrsize_set_high: * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html */ movl $_program, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + andl $(~(XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr post_code(0x2e) diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index b7eb37b6a6..58e411dcc3 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -26,6 +26,15 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) +#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" +#endif +#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE +#else +#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE +#endif + .global bootblock_pre_c_entry .code32 @@ -168,12 +177,6 @@ cores_counted: hyper_threading_cpu: - /* delay 10 ms */ - movl $10000, %ecx -1: inb $0x80, %al - dec %ecx - jnz 1b - post_code(0x25) /* Send Start IPI to all excluding ourself. */ @@ -189,12 +192,6 @@ hyper_threading_cpu: andl $LAPIC_ICR_BUSY, %ecx jnz 1b - /* delay 250 us */ - movl $250, %ecx -1: inb $0x80, %al - dec %ecx - jnz 1b - post_code(0x26) /* Wait for sibling CPU to start. */ @@ -354,13 +351,13 @@ cache_rom: * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html */ movl $_program, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + andl $(~(XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr fill_cache: diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 2fff90c690..9819ee7d87 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -56,8 +56,13 @@ void set_feature_ctrl_vmx(void) if (enable) { msr.lo |= (1 << 2); - if (feature_flag & CPUID_SMX) + if (feature_flag & CPUID_SMX) { msr.lo |= (1 << 1); + if (CONFIG(INTEL_TXT)) { + /* Enable GetSec and all GetSec leaves */ + msr.lo |= (0xff << 8); + } + } } wrmsr(IA32_FEATURE_CONTROL, msr); diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index c32bc235c2..14dbd60e24 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -12,7 +12,6 @@ */ #include -#include #include #include #include diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 77ba0bdb98..3e71469947 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -32,7 +32,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select TSC_MONOTONIC_TIMER - select TSC_CONSTANT_RATE select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select NO_SMM diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index db119a05cc..d8d8b97004 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -14,7 +14,6 @@ config CPU_SPECIFIC_OPTIONS select MMX select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index b75d145ffd..b838f3476d 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -22,25 +22,6 @@ * Document Number 504790 * Revision 1.6.0, June 2012 */ -#if 0 -static void msr_set_bit(unsigned int reg, unsigned int bit) -{ - msr_t msr = rdmsr(reg); - - if (bit < 32) { - if (msr.lo & (1 << bit)) - return; - msr.lo |= 1 << bit; - } else { - if (msr.hi & (1 << (bit - 32))) - return; - msr.hi |= 1 << (bit - 32); - } - - wrmsr(reg, msr); -} -#endif - void intel_cpu_haswell_finalize_smm(void) { #if 0 diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 037234ab37..564a428bbc 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -7,9 +7,9 @@ config CPU_INTEL_MODEL_1067X select SMP select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 43c4048786..1ba8894940 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -7,7 +7,6 @@ config CPU_INTEL_MODEL_106CX select SMP select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 897a3b4804..a76a95dc6d 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -12,7 +12,6 @@ config CPU_SPECIFIC_OPTIONS select SMP select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT @@ -23,10 +22,6 @@ config CPU_SPECIFIC_OPTIONS select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP -config BOOTBLOCK_CPU_INIT - string - default "cpu/intel/model_2065x/bootblock.c" - config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index dde4234521..142842174e 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -15,7 +15,10 @@ smm-y += finalize.c cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*) -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../car/non-evict/cache_as_ram.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../../x86/early_reset.S + postcar-y += ../car/non-evict/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c deleted file mode 100644 index 273c193f3a..0000000000 --- a/src/cpu/intel/model_2065x/bootblock.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include - -#if CONFIG(SOUTHBRIDGE_INTEL_IBEXPEAK) -#include -#include "model_2065x.h" -#else -#error "CPU must be paired with Intel Ibex Peak southbridge" -#endif - -static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, - unsigned int type) - -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - /* FIXME: It only support 4G less range */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} - -static void set_flex_ratio_to_tdp_nominal(void) -{ - msr_t flex_ratio, msr; - u32 soft_reset; - u8 nominal_ratio; - - /* Minimum CPU revision for configurable TDP support */ - if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) - return; - - /* Check for Flex Ratio support */ - flex_ratio = rdmsr(MSR_FLEX_RATIO); - if (!(flex_ratio.lo & FLEX_RATIO_EN)) - return; - - /* Check for >0 configurable TDPs */ - msr = rdmsr(MSR_PLATFORM_INFO); - if (((msr.hi >> 1) & 3) == 0) - return; - - /* Use nominal TDP ratio for flex ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - nominal_ratio = msr.lo & 0xff; - - /* See if flex ratio is already set to nominal TDP ratio */ - if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) - return; - - /* Set flex ratio to nominal TDP ratio */ - flex_ratio.lo &= ~0xff00; - flex_ratio.lo |= nominal_ratio << 8; - flex_ratio.lo |= FLEX_RATIO_LOCK; - wrmsr(MSR_FLEX_RATIO, flex_ratio); - - /* Set flex ratio in soft reset data register bits 11:6. - * RCBA region is enabled in southbridge bootblock */ - soft_reset = RCBA32(SOFT_RESET_DATA); - soft_reset &= ~(0x3f << 6); - soft_reset |= (nominal_ratio & 0x3f) << 6; - RCBA32(SOFT_RESET_DATA) = soft_reset; - - /* Set soft reset control to use register value */ - RCBA32_OR(SOFT_RESET_CTRL, 1); - - /* Issue warm reset, will be "CPU only" due to soft reset data */ - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); -} - -static void bootblock_cpu_init(void) -{ - /* Set flex ratio and reset if needed */ - set_flex_ratio_to_tdp_nominal(); - enable_rom_caching(); - intel_update_microcode_from_cbfs(); -} diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index 3c1c2db1c4..a0a3fe227b 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -23,23 +23,6 @@ * Document Number 504790 * Revision 1.6.0, June 2012 */ -static void msr_set_bit(unsigned int reg, unsigned int bit) -{ - msr_t msr = rdmsr(reg); - - if (bit < 32) { - if (msr.lo & (1 << bit)) - return; - msr.lo |= 1 << bit; - } else { - if (msr.hi & (1 << (bit - 32))) - return; - msr.hi |= 1 << (bit - 32); - } - - wrmsr(reg, msr); -} - void intel_model_2065x_finalize_smm(void) { /* Lock C-State MSR */ diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 97d8d3d0d6..8dae6ecc30 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS select MMX select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index c9d53769b3..d51fb21847 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -23,23 +23,6 @@ * Document Number 504790 * Revision 1.6.0, June 2012 */ -static void msr_set_bit(unsigned int reg, unsigned int bit) -{ - msr_t msr = rdmsr(reg); - - if (bit < 32) { - if (msr.lo & (1 << bit)) - return; - msr.lo |= 1 << bit; - } else { - if (msr.hi & (1 << (bit - 32))) - return; - msr.hi |= 1 << (bit - 32); - } - - wrmsr(reg, msr); -} - void intel_model_206ax_finalize_smm(void) { /* Lock C-State MSR */ diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index ff16724651..3af52722f3 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -7,7 +7,6 @@ config CPU_INTEL_MODEL_6EX select SMP select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 32f6e8c42a..cfd3e7c6e0 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -7,10 +7,10 @@ config CPU_INTEL_MODEL_6FX select SMP select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index d9324944da..3d0522a09d 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -25,6 +25,7 @@ config SLOT_SPECIFIC_OPTIONS # dummy select CPU_INTEL_MODEL_6XX select NO_SMM select NO_MONOTONIC_TIMER + select UNKNOWN_TSC_RATE config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 3eb869ae1f..5350d1c930 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -168,6 +168,9 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, if (smm_reloc_params.ied_size) setup_ied_area(&smm_reloc_params); + /* This may not be be correct for older CPU's supported by this code, + but given that em64t101_smm_state_save_area_t is larger than the + save_state of these CPU's it works. */ *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); } @@ -191,6 +194,8 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, { msr_t mtrr_cap; struct smm_relocation_params *relo_params = &smm_reloc_params; + /* The em64t101 save state is sufficiently compatible with older + save states with regards of smbase, smm_revision. */ em64t101_smm_state_save_area_t *save_state; u32 smbase = staggered_smbase; u32 iedbase = relo_params->ied_base; @@ -208,7 +213,10 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state)); save_state->smbase = smbase; - save_state->iedbase = iedbase; + + printk(BIOS_SPEW, "SMM revision: 0x%08x\n", save_state->smm_revision); + if (save_state->smm_revision == 0x00030101) + save_state->iedbase = iedbase; /* Write EMRR and SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index 6c5e414029..eef81d570a 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -14,4 +14,8 @@ config DCACHE_RAM_SIZE hex default 0x8000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + endif diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index 05514a1548..7656416aad 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -8,7 +8,8 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S +bootblock-y += ../car/core2/cache_as_ram.S +bootblock-y += ../car/bootblock.c postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 4ec46e0ac8..a2ebeb2325 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -9,7 +9,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select MMX select SSE select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select C_ENVIRONMENT_BOOTBLOCK diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig index 0ec9ced5d0..6ba74eea90 100644 --- a/src/cpu/intel/socket_p/Kconfig +++ b/src/cpu/intel/socket_p/Kconfig @@ -15,4 +15,8 @@ config DCACHE_RAM_SIZE hex default 0x8000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + endif diff --git a/src/cpu/intel/socket_p/Makefile.inc b/src/cpu/intel/socket_p/Makefile.inc index 78d7c0ee58..76c4127d4d 100644 --- a/src/cpu/intel/socket_p/Makefile.inc +++ b/src/cpu/intel/socket_p/Makefile.inc @@ -9,7 +9,8 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S +bootblock-y += ../car/core2/cache_as_ram.S +bootblock-y += ../car/bootblock.c postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index a6c9b74360..7504233bda 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -20,5 +20,6 @@ config CPU_QEMU_X86 select SMP select UDELAY_TSC select TSC_MONOTONIC_TIMER + select UNKNOWN_TSC_RATE select C_ENVIRONMENT_BOOTBLOCK select SMM_ASEG diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 6ec2e4dc2c..f5678a1807 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -38,9 +38,17 @@ cache_as_ram: /* Align the stack and keep aligned for call to bootblock_c_entry() */ and $0xfffffff0, %esp - sub $4, %esp /* Restore the BIST result and timestamps. */ +#if defined(__x86_64__) + movd %mm1, %rdi + shld %rdi, 32 + movd %mm1, %rsi + or %rsi, %rdi + movd %mm2, %rsi +#else + sub $4, %esp + movd %mm0, %ebx movd %mm1, %eax movd %mm2, %edx @@ -48,6 +56,7 @@ cache_as_ram: pushl %ebx pushl %edx pushl %eax +#endif before_c_entry: post_code(0x29) diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index 24a79dd378..d3ef9701e8 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -10,7 +10,6 @@ romstage-y += cbmem.c ramstage-y += dmtimer.c ramstage-y += monotonic_timer.c ramstage-y += nand.c -ramstage-y += cbmem.c bootblock-y += uart.c romstage-y += uart.c diff --git a/src/cpu/ti/am335x/cbmem.c b/src/cpu/ti/am335x/cbmem.c index a626ec6adf..2ecca65551 100644 --- a/src/cpu/ti/am335x/cbmem.c +++ b/src/cpu/ti/am335x/cbmem.c @@ -15,7 +15,7 @@ #include #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return _dram + (CONFIG_DRAM_SIZE_MB << 20); } diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig index 4b96c7ce82..14acfd5662 100644 --- a/src/cpu/via/nano/Kconfig +++ b/src/cpu/via/nano/Kconfig @@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select UDELAY_TSC select TSC_MONOTONIC_TIMER + select UNKNOWN_TSC_RATE select MMX select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/via/nano/microcode_blob.c b/src/cpu/via/nano/microcode_blob.c index 97a773d22b..49866428d5 100644 --- a/src/cpu/via/nano/microcode_blob.c +++ b/src/cpu/via/nano/microcode_blob.c @@ -1,4 +1,4 @@ -unsigned array[3588] = +unsigned int array[3588] = { #include "../../../../3rdparty/blobs/cpu/via/nano/microcode.h" }; diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h index 31f5925cf0..7cf3f2871c 100644 --- a/src/cpu/via/nano/update_ucode.h +++ b/src/cpu/via/nano/update_ucode.h @@ -14,7 +14,7 @@ #ifndef __UPDATE_UCODE_H #define __UPDATE_UCODE_H -#include +#include #define MSR_UCODE_UPDATE_STATUS 0x00001205 diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc new file mode 100644 index 0000000000..f726fab506 --- /dev/null +++ b/src/cpu/x86/64bit/entry64.inc @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * For starting coreboot in long mode. + * + * For reference see "AMD64 ArchitectureProgrammer's Manual Volume 2", + * Document 24593-Rev. 3.31-July 2019 Chapter 5.3 + * + * Clobbers: eax, ecx, edx + */ + +#if defined(__x86_64__) + .code32 +#if (CONFIG_ARCH_X86_64_PGTBL_LOC & 0xfff) > 0 +#error pagetables must be 4KiB aligned! +#endif + +#include +#include + +setup_longmode: + /* Get page table address */ + movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax + + /* load identity mapped page tables */ + movl %eax, %cr3 + + /* enable PAE */ + movl %cr4, %eax + btsl $5, %eax + movl %eax, %cr4 + + /* enable long mode */ + movl $(IA32_EFER), %ecx + rdmsr + btsl $8, %eax + wrmsr + + /* enable paging */ + movl %cr0, %eax + btsl $31, %eax + movl %eax, %cr0 + + /* use long jump to switch to 64-bit code segment */ + ljmp $ROM_CODE_SEG64, $__longmode_start +.code64 +__longmode_start: + +#endif diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index a8cf54d89e..85ebd831ea 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -34,12 +34,9 @@ config UDELAY_TSC bool default n -config TSC_CONSTANT_RATE - def_bool n - depends on UDELAY_TSC - help - This option asserts that the TSC ticks at a known constant rate. - Therefore, no TSC calibration is required. +config UNKNOWN_TSC_RATE + bool + default y if LAPIC_MONOTONIC_TIMER config TSC_MONOTONIC_TIMER def_bool n @@ -78,6 +75,16 @@ config XIP_ROM_SIZE depends on !NO_FIXED_XIP_ROM_SIZE default 0x10000 +config SETUP_XIP_CACHE + bool + depends on C_ENVIRONMENT_BOOTBLOCK + depends on !NO_XIP_EARLY_STAGES + help + Select this option to set up an MTRR to cache XIP stages loaded + from the bootblock. This is useful on platforms lacking a + non-eviction mode and therefore need to be careful to avoid + eviction. + config CPU_ADDR_BITS int default 36 diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 668988a70e..e7dfc5798d 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -28,6 +28,7 @@ #include #include #include +#include #include /* This is a lot more paranoid now, since Linux can NOT handle diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index 48360ad532..09cd6f7c30 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -13,6 +13,7 @@ #include #include +#include .text .globl _secondary_start, _secondary_start_end, _secondary_gdt_addr @@ -38,7 +39,7 @@ _secondary_start: orl $0x60000001, %eax /* CD, NW, PE = 1 */ movl %eax, %cr0 - ljmpl $0x10, $__ap_protected_start + ljmpl $RAM_CODE_SEG, $__ap_protected_start /* This will get filled in by C code. */ _secondary_gdt_addr: @@ -51,11 +52,11 @@ _secondary_start_end: ap_protected_start: .code32 lgdt gdtaddr - ljmpl $0x10, $__ap_protected_start + ljmpl $RAM_CODE_SEG, $__ap_protected_start __ap_protected_start: - movw $0x18, %ax + movw $RAM_DATA_SEG, %ax movw %ax, %ds movw %ax, %es movw %ax, %ss diff --git a/src/cpu/x86/mirror_payload.c b/src/cpu/x86/mirror_payload.c index 9dec8dbc68..9987347f33 100644 --- a/src/cpu/x86/mirror_payload.c +++ b/src/cpu/x86/mirror_payload.c @@ -11,13 +11,12 @@ * GNU General Public License for more details. */ -#include -#include #include #include #include #include #include +#include void mirror_payload(struct prog *payload) { diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index caa6e9c5d2..129d05d41b 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -2,8 +2,12 @@ ramstage-y += mtrr.c romstage-y += earlymtrr.c bootblock-y += earlymtrr.c +verstage-y += earlymtrr.c bootblock-y += debug.c romstage-y += debug.c postcar-y += debug.c ramstage-y += debug.c + +bootblock-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c +verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c diff --git a/src/cpu/x86/mtrr/xip_cache.c b/src/cpu/x86/mtrr/xip_cache.c new file mode 100644 index 0000000000..9968eea78e --- /dev/null +++ b/src/cpu/x86/mtrr/xip_cache.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +/* For now this is a good lowest common denominator for the total CPU cache. + TODO: fetch the total amount of cache from CPUID leaf2. */ +#define MAX_CPU_CACHE (256 * KiB) + +/* This makes the 'worst' case assumption that all cachelines covered by + the MTRR, no matter the caching type, are filled and not overlapping. */ +static uint32_t max_cache_used(void) +{ + msr_t msr = rdmsr(MTRR_CAP_MSR); + int i, total_mtrrs = msr.lo & MTRR_CAP_VCNT; + uint32_t total_cache = 0; + + for (i = 0; i < total_mtrrs; i++) { + msr_t mtrr = rdmsr(MTRR_PHYS_MASK(i)); + if (!(mtrr.lo & MTRR_PHYS_MASK_VALID)) + continue; + total_cache += ~(mtrr.lo & 0xfffff000) + 1; + } + return total_cache; +} + +void platform_prog_run(struct prog *prog) +{ + const uint32_t base = region_device_offset(&prog->rdev); + const uint32_t size = region_device_sz(&prog->rdev); + const uint32_t end = base + size; + const uint32_t cache_used = max_cache_used(); + /* This will accumulate MTRR's as XIP stages are run. + For now this includes bootblock which sets ups its own + caching elsewhere, verstage and romstage */ + int mtrr_num = get_free_var_mtrr(); + uint32_t mtrr_base; + uint32_t mtrr_size = 4 * KiB; + struct cpuinfo_x86 cpu_info; + + get_fms(&cpu_info, cpuid_eax(1)); + /* + * An unidentified combination of speculative reads and branch + * predictions inside WRPROT-cacheable memory can cause invalidation + * of cachelines and loss of stack on models based on NetBurst + * microarchitecture. Therefore disable WRPROT region entirely for + * all family F models. + */ + if (cpu_info.x86 == 0xf) { + printk(BIOS_NOTICE, + "PROG_RUN: CPU does not support caching ROM\n" + "The next stage will run slowly!\n"); + return; + } + + if (mtrr_num == -1) { + printk(BIOS_NOTICE, + "PROG_RUN: No MTRR available to cache ROM!\n" + "The next stage will run slowly!\n"); + return; + } + + if (cache_used + mtrr_size > MAX_CPU_CACHE) { + printk(BIOS_NOTICE, + "PROG_RUN: No more cache available for the next stage\n" + "The next stage will run slowly!\n"); + return; + } + + while (1) { + if (ALIGN_DOWN(base, mtrr_size) + mtrr_size >= end) + break; + if (cache_used + mtrr_size * 2 > MAX_CPU_CACHE) + break; + mtrr_size *= 2; + } + + mtrr_base = ALIGN_DOWN(base, mtrr_size); + if (mtrr_base + mtrr_size < end) { + printk(BIOS_NOTICE, "PROG_RUN: Limiting XIP cache to %uKiB!\n", + mtrr_size / KiB); + /* Check if we can cover a bigger range by aligning up. */ + const uint32_t alt_base = ALIGN_UP(base, mtrr_size); + const uint32_t lower_coverage = mtrr_base + mtrr_size - base; + const uint32_t upper_coverage = MIN(alt_base + mtrr_size, end) - alt_base; + if (upper_coverage > lower_coverage) + mtrr_base = alt_base; + } + + printk(BIOS_DEBUG, + "PROG_RUN: Setting MTRR to cache XIP stage. base: 0x%08x, size: 0x%08x\n", + mtrr_base, mtrr_size); + + set_var_mtrr(mtrr_num, mtrr_base, mtrr_size, MTRR_TYPE_WRPROT); +} diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index edc1e779be..f75a1c9815 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -15,15 +15,12 @@ #include #include #include +#include /* The SIPI vector is responsible for initializing the APs in the system. It * loads microcode, sets up MSRs, and enables caching before calling into * C code. */ -/* These segment selectors need to match the gdt entries in c_start.S. */ -#define CODE_SEG 0x10 -#define DATA_SEG 0x18 - .section ".module_parameters", "aw", @progbits ap_start_params: gdtaddr: @@ -83,10 +80,10 @@ _start: orl $CR0_SET_FLAGS, %eax movl %eax, %cr0 - ljmpl $CODE_SEG, $1f + ljmpl $RAM_CODE_SEG, $1f 1: .code32 - movw $DATA_SEG, %ax + movw $RAM_DATA_SEG, %ax movw %ax, %ds movw %ax, %es movw %ax, %ss diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index ab7453f262..b3925b5051 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,6 +1,6 @@ bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c -romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c -verstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c -postcar-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c -smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c +romstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +verstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +postcar-$(CONFIG_UDELAY_TSC) += delay_tsc.c +smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 0784822b30..7aa887ae63 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -12,108 +12,15 @@ */ #include -#include -#include #include +#include #include #include #include -static unsigned long clocks_per_usec CAR_GLOBAL; - -#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */ - -/* ------ Calibrate the TSC ------- - * Too much 64-bit arithmetic here to do this cleanly in C, and for - * accuracy's sake we want to keep the overhead on the CTC speaker (channel 2) - * output busy loop as low as possible. We avoid reading the CTC registers - * directly because of the awkward 8-bit access mechanism of the 82C54 - * device. - */ - -#define CALIBRATE_INTERVAL ((2*CLOCK_TICK_RATE)/1000) /* 2ms */ -#define CALIBRATE_DIVISOR (2*1000) /* 2ms / 2000 == 1usec */ - -static unsigned long calibrate_tsc_with_pit(void) -{ - /* Set the Gate high, disable speaker */ - outb((inb(0x61) & ~0x02) | 0x01, 0x61); - - /* - * Now let's take care of CTC channel 2 - * - * Set the Gate high, program CTC channel 2 for mode 0, - * (interrupt on terminal count mode), binary count, - * load 5 * LATCH count, (LSB and MSB) to begin countdown. - */ - outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */ - - outb(CALIBRATE_INTERVAL & 0xff, 0x42); /* LSB of count */ - outb(CALIBRATE_INTERVAL >> 8, 0x42); /* MSB of count */ - - { - tsc_t start; - tsc_t end; - unsigned long count; - - start = rdtsc(); - count = 0; - do { - count++; - } while ((inb(0x61) & 0x20) == 0); - end = rdtsc(); - - /* Error: ECTCNEVERSET */ - if (count <= 1) - goto bad_ctc; - - /* 64-bit subtract - gcc just messes up with long longs */ - __asm__("subl %2,%0\n\t" - "sbbl %3,%1" - : "=a" (end.lo), "=d" (end.hi) - : "g" (start.lo), "g" (start.hi), - "0" (end.lo), "1" (end.hi)); - - /* Error: ECPUTOOFAST */ - if (end.hi) - goto bad_ctc; - - - /* Error: ECPUTOOSLOW */ - if (end.lo <= CALIBRATE_DIVISOR) - goto bad_ctc; - - return DIV_ROUND_UP(end.lo, CALIBRATE_DIVISOR); - } - - /* - * The CTC wasn't reliable: we got a hit on the very first read, - * or the CPU was so fast/slow that the quotient wouldn't fit in - * 32 bits.. - */ -bad_ctc: - printk(BIOS_ERR, "bad_ctc\n"); - return 0; -} - -static unsigned long calibrate_tsc(void) -{ - if (CONFIG(TSC_CONSTANT_RATE)) - return tsc_freq_mhz(); - else - return calibrate_tsc_with_pit(); -} - void init_timer(void) { - if (!car_get_var(clocks_per_usec)) - car_set_var(clocks_per_usec, calibrate_tsc()); -} - -static inline unsigned long get_clocks_per_usec(void) -{ - init_timer(); - return car_get_var(clocks_per_usec); + (void)tsc_freq_mhz(); } void udelay(unsigned int us) @@ -127,7 +34,7 @@ void udelay(unsigned int us) start = rdtscll(); clocks = us; - clocks *= get_clocks_per_usec(); + clocks *= tsc_freq_mhz(); current = rdtscll(); while ((current - start) < clocks) { cpu_relax(); @@ -165,7 +72,7 @@ void timer_monotonic_get(struct mono_time *mt) current_tick = rdtscll(); ticks_elapsed = current_tick - mono_counter->last_value; - ticks_per_usec = get_clocks_per_usec(); + ticks_per_usec = tsc_freq_mhz(); /* Update current time and tick values only if a full tick occurred. */ if (ticks_elapsed >= ticks_per_usec) { diff --git a/src/device/Kconfig b/src/device/Kconfig index 59a43754f7..abef6a8d15 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -36,6 +36,11 @@ config HAVE_FSP_GOP Selected by drivers that support to run a blob that implements the Graphics Output Protocol (GOP). +config MAINBOARD_NO_FSP_GOP + bool + help + Selected by mainboards that do not have any graphics ports connected to the SoC. + config MAINBOARD_HAS_NATIVE_VGA_INIT def_bool n help @@ -94,7 +99,7 @@ config VGA_ROM_RUN config RUN_FSP_GOP bool "Run a GOP driver" - depends on HAVE_FSP_GOP + depends on HAVE_FSP_GOP && !MAINBOARD_NO_FSP_GOP select HAVE_LINEAR_FRAMEBUFFER help Some platforms (e.g. Intel Braswell and Skylake/Kaby Lake) support @@ -111,6 +116,16 @@ config NO_GFX_INIT endchoice +config ONBOARD_VGA_IS_PRIMARY + bool "Use onboard VGA as primary video device" + default n + depends on PCI + help + This option lets you select which VGA device will be used + to decode legacy VGA cycles. Not all chipsets implement this + however. If not selected, the last adapter found will be used, + else the onboard adapter is used. + config S3_VGA_ROM_RUN bool "Re-run VGA Option ROMs on S3 resume" default y diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index 48c54bc16a..f7decb30ee 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -15,7 +15,6 @@ #include #include #include -#include #include /* diff --git a/src/device/device.c b/src/device/device.c index 44d1f95f75..333f1f0f1d 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -759,6 +759,10 @@ static void set_vga_bridge_bits(void) continue; printk(BIOS_DEBUG, "found VGA at %s\n", dev_path(dev)); + if (dev->bus->no_vga16) { + printk(BIOS_WARNING, + "A bridge on the path doesn't support 16-bit VGA decoding!"); + } if (dev->on_mainboard) { vga_onboard = dev; @@ -797,7 +801,7 @@ static void set_vga_bridge_bits(void) while (bus) { printk(BIOS_DEBUG, "Setting PCI_BRIDGE_CTL_VGA for bridge %s\n", dev_path(bus->dev)); - bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA; + bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_VGA16; bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus; } } diff --git a/src/device/device_util.c b/src/device/device_util.c index df66f5c620..36bcbe9c4d 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -16,6 +16,7 @@ #include #include #include +#include #include /** @@ -24,7 +25,7 @@ * @param apic_id The Local APIC ID number. * @return Pointer to the device structure (if found), 0 otherwise. */ -struct device *dev_find_lapic(unsigned apic_id) +struct device *dev_find_lapic(unsigned int apic_id) { struct device *dev; struct device *result = NULL; @@ -324,7 +325,7 @@ void compact_resources(struct device *dev) * @param index The index of the resource on the device. * @return The resource, if it already exists. */ -struct resource *probe_resource(const struct device *dev, unsigned index) +struct resource *probe_resource(const struct device *dev, unsigned int index) { struct resource *res; @@ -347,7 +348,7 @@ struct resource *probe_resource(const struct device *dev, unsigned index) * @param index The index of the resource on the device. * @return TODO. */ -struct resource *new_resource(struct device *dev, unsigned index) +struct resource *new_resource(struct device *dev, unsigned int index) { struct resource *resource, *tail; @@ -394,7 +395,7 @@ struct resource *new_resource(struct device *dev, unsigned index) * @param index The index of the resource on the device. * return TODO. */ -struct resource *find_resource(const struct device *dev, unsigned index) +struct resource *find_resource(const struct device *dev, unsigned int index) { struct resource *resource; diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 4f99ecc925..07f9decb74 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -111,17 +111,31 @@ int spd_decode_ddr4(dimm_attr *dimm, spd_raw_data spd) return SPD_STATUS_INVALID; } - spd_bytes_total = (spd[0] >> 4) & ((1 << 3) - 1); - spd_bytes_used = spd[0] & ((1 << 4) - 1); + spd_bytes_total = (spd[0] >> 4) & 0x7; + spd_bytes_used = spd[0] & 0xf; if (!spd_bytes_total || !spd_bytes_used) { printk(BIOS_ERR, "SPD failed basic sanity checks\n"); return SPD_STATUS_INVALID; } + if (spd_bytes_total >= 3) + printk(BIOS_WARNING, "SPD Bytes Total value is reserved\n"); + spd_bytes_total = 256 << (spd_bytes_total - 1); + + if (spd_bytes_used > 4) { + printk(BIOS_ERR, "SPD Bytes Used value is reserved\n"); + return SPD_STATUS_INVALID; + } + spd_bytes_used = spd_bytes_used_table[spd_bytes_used]; + if (spd_bytes_used > spd_bytes_total) { + printk(BIOS_ERR, "SPD Bytes Used is greater than SPD Bytes Total\n"); + return SPD_STATUS_INVALID; + } + /* Verify CRC of blocks that have them, do not step over 'used' length */ for (int i = 0; i < ARRAY_SIZE(spd_blocks); i++) { /* this block is not checksumed */ diff --git a/src/device/dram/ddr_common.c b/src/device/dram/ddr_common.c index bc87712ef6..dcfa18df2a 100644 --- a/src/device/dram/ddr_common.c +++ b/src/device/dram/ddr_common.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index 1a8f7e6dc1..03e3375b91 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -21,7 +21,7 @@ struct ht_link { struct device *dev; - unsigned pos; + unsigned int pos; unsigned char ctrl_off, config_off, freq_off, freq_cap_off; }; @@ -64,7 +64,7 @@ static struct device *ht_scan_get_devs(struct device **old_devices) return first; } -static int ht_setup_link(struct ht_link *prev, struct device *dev, unsigned pos) +static int ht_setup_link(struct ht_link *prev, struct device *dev, unsigned int pos) { struct ht_link cur[1]; int linkb_to_host; @@ -113,9 +113,9 @@ static int ht_setup_link(struct ht_link *prev, struct device *dev, unsigned pos) return 0; } -static unsigned ht_lookup_slave_capability(struct device *dev) +static unsigned int ht_lookup_slave_capability(struct device *dev) { - unsigned pos; + unsigned int pos; pos = 0; do { @@ -135,7 +135,7 @@ static unsigned ht_lookup_slave_capability(struct device *dev) } static void ht_collapse_early_enumeration(struct bus *bus, - unsigned offset_unitid) + unsigned int offset_unitid) { unsigned int devfn; struct ht_link prev; @@ -207,7 +207,7 @@ static void ht_collapse_early_enumeration(struct bus *bus, for (devfn = PCI_DEVFN(1, 0); devfn <= 0xff; devfn += 8) { struct device dummy; u32 id; - unsigned pos, flags; + unsigned int pos, flags; dummy.bus = bus; dummy.path.type = DEVICE_PATH_PCI; @@ -236,10 +236,10 @@ static void ht_collapse_early_enumeration(struct bus *bus, } } -static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, - unsigned max_devfn, - unsigned *ht_unitid_base, - unsigned offset_unitid) +static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned int min_devfn, + unsigned int max_devfn, + unsigned int *ht_unitid_base, + unsigned int offset_unitid) { /* * Even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this diff --git a/src/device/i2c.c b/src/device/i2c.c index fb29b7291d..72e5525df1 100644 --- a/src/device/i2c.c +++ b/src/device/i2c.c @@ -14,7 +14,7 @@ #include #include -int i2c_read_field(unsigned bus, uint8_t chip, uint8_t reg, uint8_t *data, +int i2c_read_field(unsigned int bus, uint8_t chip, uint8_t reg, uint8_t *data, uint8_t mask, uint8_t shift) { int ret; @@ -28,7 +28,7 @@ int i2c_read_field(unsigned bus, uint8_t chip, uint8_t reg, uint8_t *data, return ret; } -int i2c_write_field(unsigned bus, uint8_t chip, uint8_t reg, uint8_t data, +int i2c_write_field(unsigned int bus, uint8_t chip, uint8_t reg, uint8_t data, uint8_t mask, uint8_t shift) { int ret; diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 8ba0241ea4..1026ddb7ff 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include diff --git a/src/device/oprom/realmode/x86_asm.S b/src/device/oprom/realmode/x86_asm.S index 8c9e12b143..d68fdc5fca 100644 --- a/src/device/oprom/realmode/x86_asm.S +++ b/src/device/oprom/realmode/x86_asm.S @@ -14,6 +14,8 @@ #define REALMODE_BASE 0x600 #define RELOCATED(x) (x - __realmode_code + REALMODE_BASE) +#include + /* CR0 bits */ #define PE (1 << 0) @@ -106,7 +108,7 @@ __realmode_call: movl %eax, __registers + 20 /* edi */ /* Activate the right segment descriptor real mode. */ - ljmp $0x28, $RELOCATED(1f) + ljmp $RAM_CODE16_SEG, $RELOCATED(1f) 1: .code16 /* 16 bit code from here on... */ @@ -116,7 +118,7 @@ __realmode_call: * configurations (limits, writability, etc.) once * protected mode is turned off. */ - mov $0x30, %ax + mov $RAM_DATA16_SEG, %ax mov %ax, %ds mov %ax, %es mov %ax, %fs @@ -186,10 +188,10 @@ __lcall_instr = RELOCATED(.) /* Now that we are in protected mode * jump to a 32 bit code segment. */ - ljmpl $0x10, $RELOCATED(1f) + ljmpl $RAM_CODE_SEG, $RELOCATED(1f) 1: .code32 - mov $0x18, %ax + mov $RAM_DATA_SEG, %ax mov %ax, %ds mov %ax, %es mov %ax, %fs @@ -242,7 +244,7 @@ __realmode_interrupt: movl %eax, __registers + 20 /* edi */ /* This configures CS properly for real mode. */ - ljmp $0x28, $RELOCATED(1f) + ljmp $RAM_CODE16_SEG, $RELOCATED(1f) 1: .code16 /* 16 bit code from here on... */ @@ -250,7 +252,7 @@ __realmode_interrupt: * descriptors. They will retain these configurations (limits, * writability, etc.) once protected mode is turned off. */ - mov $0x30, %ax + mov $RAM_DATA16_SEG, %ax mov %ax, %ds mov %ax, %es mov %ax, %fs @@ -314,10 +316,10 @@ __intXX_instr = RELOCATED(.) movl %eax, %cr0 /* Now that we are in protected mode jump to a 32-bit code segment. */ - ljmpl $0x10, $RELOCATED(1f) + ljmpl $RAM_CODE_SEG, $RELOCATED(1f) 1: .code32 - mov $0x18, %ax + mov $RAM_DATA_SEG, %ax mov %ax, %ds mov %ax, %es mov %ax, %fs @@ -363,10 +365,10 @@ __interrupt_handler_16bit = RELOCATED(.) movl %eax, %cr0 /* ... and jump to a 32 bit code segment. */ - ljmpl $0x10, $RELOCATED(1f) + ljmpl $RAM_CODE_SEG, $RELOCATED(1f) 1: .code32 - mov $0x18, %ax + mov $RAM_DATA_SEG, %ax mov %ax, %ds mov %ax, %es mov %ax, %fs @@ -380,14 +382,14 @@ __interrupt_handler_16bit = RELOCATED(.) call *%eax /* Now return to real mode ... */ - ljmp $0x28, $RELOCATED(1f) + ljmp $RAM_CODE16_SEG, $RELOCATED(1f) 1: .code16 /* Load the segment registers with properly configured segment * descriptors. They will retain these configurations (limits, * writability, etc.) once protected mode is turned off. */ - mov $0x30, %ax + mov $RAM_DATA16_SEG, %ax mov %ax, %ds mov %ax, %es mov %ax, %fs diff --git a/src/device/oprom/realmode/x86_interrupts.c b/src/device/oprom/realmode/x86_interrupts.c index 4e1c5ed5af..c38da466bd 100644 --- a/src/device/oprom/realmode/x86_interrupts.c +++ b/src/device/oprom/realmode/x86_interrupts.c @@ -15,7 +15,6 @@ #include #include #include -#include /* we use x86emu's register file representation */ #include diff --git a/src/device/oprom/x86emu/decode.c b/src/device/oprom/x86emu/decode.c index b7a6f35b51..3b7bde727a 100644 --- a/src/device/oprom/x86emu/decode.c +++ b/src/device/oprom/x86emu/decode.c @@ -735,7 +735,7 @@ REMARKS: Decodes scale/index of SIB byte and returns relevant offset part of effective address. ****************************************************************************/ -static unsigned decode_sib_si( +static unsigned int decode_sib_si( int scale, int index) { @@ -785,7 +785,7 @@ Offset in memory for the address decoding REMARKS: Decodes SIB addressing byte and returns calculated effective address. ****************************************************************************/ -static unsigned decode_sib_address( +static unsigned int decode_sib_address( int mod) { int sib = fetch_byte_imm(); @@ -874,10 +874,10 @@ NOTE: The code which specifies the corresponding segment (ds vs ss) if a SS access is needed, set this bit. Otherwise, DS access occurs (unless any of the segment override bits are set). ****************************************************************************/ -unsigned decode_rm00_address( +unsigned int decode_rm00_address( int rm) { - unsigned offset; + unsigned int offset; if (M.x86.mode & SYSMODE_PREFIX_ADDR) { /* 32-bit addressing */ @@ -954,7 +954,7 @@ REMARKS: Return the offset given by mod=01 addressing. Also enables the decoding of instructions. ****************************************************************************/ -unsigned decode_rm01_address( +unsigned int decode_rm01_address( int rm) { int displacement; @@ -1043,7 +1043,7 @@ REMARKS: Return the offset given by mod=10 addressing. Also enables the decoding of instructions. ****************************************************************************/ -unsigned decode_rm10_address( +unsigned int decode_rm10_address( int rm) { if (M.x86.mode & SYSMODE_PREFIX_ADDR) { @@ -1136,7 +1136,7 @@ REMARKS: Return the offset given by "mod" addressing. ****************************************************************************/ -unsigned decode_rmXX_address(int mod, int rm) +unsigned int decode_rmXX_address(int mod, int rm) { if (mod == 0) return decode_rm00_address(rm); diff --git a/src/device/oprom/x86emu/decode.h b/src/device/oprom/x86emu/decode.h index 99ed7f6f35..530b7d9a51 100644 --- a/src/device/oprom/x86emu/decode.h +++ b/src/device/oprom/x86emu/decode.h @@ -76,10 +76,10 @@ u8* decode_rm_byte_register(int reg); u16* decode_rm_word_register(int reg); u32* decode_rm_long_register(int reg); u16* decode_rm_seg_register(int reg); -unsigned decode_rm00_address(int rm); -unsigned decode_rm01_address(int rm); -unsigned decode_rm10_address(int rm); -unsigned decode_rmXX_address(int mod, int rm); +unsigned int decode_rm00_address(int rm); +unsigned int decode_rm01_address(int rm); +unsigned int decode_rm10_address(int rm); +unsigned int decode_rmXX_address(int mod, int rm); #ifdef __cplusplus } /* End of "C" linkage for C++ */ diff --git a/src/device/oprom/x86emu/sys.c b/src/device/oprom/x86emu/sys.c index 9c293bc561..06f240c5a7 100644 --- a/src/device/oprom/x86emu/sys.c +++ b/src/device/oprom/x86emu/sys.c @@ -50,7 +50,6 @@ #ifdef IN_MODULE #include "xf86_ansic.h" #else -#include #endif /*------------------------- Global Variables ------------------------------*/ diff --git a/src/device/oprom/x86emu/x86emui.h b/src/device/oprom/x86emu/x86emui.h index 741153c726..b1647c583c 100644 --- a/src/device/oprom/x86emu/x86emui.h +++ b/src/device/oprom/x86emu/x86emui.h @@ -72,7 +72,6 @@ #ifdef IN_MODULE #include #else -#include #endif /*--------------------------- Inline Functions ----------------------------*/ diff --git a/src/device/oprom/yabel/compat/functions.c b/src/device/oprom/yabel/compat/functions.c index fa1b6b7cf6..c9e2e4c60a 100644 --- a/src/device/oprom/yabel/compat/functions.c +++ b/src/device/oprom/yabel/compat/functions.c @@ -36,7 +36,6 @@ */ #include -#include #include #include "../debug.h" #include "../biosemu.h" diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index 9a7fa045c7..a3d736fa93 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -32,6 +32,7 @@ * IBM Corporation - initial implementation *****************************************************************************/ +#include #include #include diff --git a/src/device/pci_class.c b/src/device/pci_class.c index ca36154e44..0aa2f2890a 100644 --- a/src/device/pci_class.c +++ b/src/device/pci_class.c @@ -14,7 +14,6 @@ #include #include #include -#include #include typedef struct { diff --git a/src/device/pci_device.c b/src/device/pci_device.c index f1b52856de..1dfc9cd272 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -345,7 +345,7 @@ static void pci_read_bases(struct device *dev, unsigned int howmany) } static void pci_record_bridge_resource(struct device *dev, resource_t moving, - unsigned index, unsigned long type) + unsigned int index, unsigned long type) { struct resource *resource; unsigned long gran; @@ -679,10 +679,15 @@ void pci_dev_set_subsystem(struct device *dev, unsigned int vendor, } } -static int should_run_oprom(struct device *dev) +static int should_run_oprom(struct device *dev, struct rom_header *rom) { static int should_run = -1; + if (CONFIG(VENDORCODE_ELTAN_VBOOT)) + if (rom != NULL) + if (!verified_boot_should_run_oprom(rom)) + return 0; + if (should_run >= 0) return should_run; @@ -711,7 +716,7 @@ static int should_load_oprom(struct device *dev) return 0; if (CONFIG(ALWAYS_LOAD_OPROM)) return 1; - if (should_run_oprom(dev)) + if (should_run_oprom(dev, NULL)) return 1; return 0; @@ -742,7 +747,7 @@ void pci_dev_init(struct device *dev) return; timestamp_add_now(TS_OPROM_COPY_END); - if (!should_run_oprom(dev)) + if (!should_run_oprom(dev, rom)) return; run_bios(dev, (unsigned long)ram); @@ -787,6 +792,43 @@ struct device_operations default_pci_ops_bus = { .ops_pci = &pci_bus_ops_pci, }; +/** + * Check for compatibility to route legacy VGA cycles through a bridge. + * + * Originally, when decoding i/o ports for legacy VGA cycles, bridges + * should only consider the 10 least significant bits of the port address. + * This means all VGA registers were aliased every 1024 ports! + * e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc. + * + * To avoid this mess, a bridge control bit (VGA16) was introduced in + * 2003 to enable decoding of 16-bit port addresses. As we don't want + * to make this any more complex for now, we use this bit if possible + * and only warn if it's not supported (in set_vga_bridge_bits()). + */ +static void pci_bridge_vga_compat(struct bus *const bus) +{ + uint16_t bridge_ctrl; + + bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL); + + /* Ensure VGA decoding is disabled during probing (it should + be by default, but we run blobs nowadays) */ + bridge_ctrl &= ~PCI_BRIDGE_CTL_VGA; + pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl); + + /* If the upstream bridge doesn't support VGA16, we don't have to check */ + bus->no_vga16 |= bus->dev->bus->no_vga16; + if (bus->no_vga16) + return; + + /* Test if we can enable 16-bit decoding */ + bridge_ctrl |= PCI_BRIDGE_CTL_VGA16; + pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl); + bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL); + + bus->no_vga16 = !(bridge_ctrl & PCI_BRIDGE_CTL_VGA16); +} + /** * Detect the type of downstream bridge. * @@ -1128,8 +1170,8 @@ unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev) * @param min_devfn Minimum devfn to look at in the scan, usually 0x00. * @param max_devfn Maximum devfn to look at in the scan, usually 0xff. */ -void pci_scan_bus(struct bus *bus, unsigned min_devfn, - unsigned max_devfn) +void pci_scan_bus(struct bus *bus, unsigned int min_devfn, + unsigned int max_devfn) { unsigned int devfn; struct device *dev, **prev; @@ -1277,8 +1319,8 @@ static void pci_bridge_route(struct bus *link, scan_state state) */ void do_pci_scan_bridge(struct device *dev, void (*do_scan_bus) (struct bus * bus, - unsigned min_devfn, - unsigned max_devfn)) + unsigned int min_devfn, + unsigned int max_devfn)) { struct bus *bus; @@ -1296,6 +1338,8 @@ void do_pci_scan_bridge(struct device *dev, bus = dev->link_list; + pci_bridge_vga_compat(bus); + pci_bridge_route(bus, PCI_ROUTE_SCAN); do_scan_bus(bus, 0x00, 0xff); diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 01c02e58e6..3676f9cf9b 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -197,10 +197,10 @@ static struct rom_header *check_initialized(struct device *dev) } static unsigned long -pci_rom_acpi_fill_vfct(struct device *device, struct acpi_vfct *vfct_struct, +pci_rom_acpi_fill_vfct(struct device *device, acpi_vfct_t *vfct_struct, unsigned long current) { - struct acpi_vfct_image_hdr *header = &vfct_struct->image_hdr; + acpi_vfct_image_hdr_t *header = &vfct_struct->image_hdr; struct rom_header *rom; rom = check_initialized(device); @@ -245,10 +245,10 @@ pci_rom_write_acpi_tables(struct device *device, unsigned long current, /* AMD/ATI uses VFCT */ if (device->vendor == PCI_VENDOR_ID_ATI) { - struct acpi_vfct *vfct; + acpi_vfct_t *vfct; current = ALIGN_UP(current, 8); - vfct = (struct acpi_vfct *)current; + vfct = (acpi_vfct_t *)current; acpi_create_vfct(device, vfct, pci_rom_acpi_fill_vfct); if (vfct->header.length) { printk(BIOS_DEBUG, "ACPI: * VFCT at %lx\n", current); diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 796830f04a..67b305ec7a 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include @@ -46,7 +45,7 @@ unsigned int pciexp_find_extended_cap(struct device *dev, unsigned int cap) * Re-train a PCIe link */ #define PCIE_TRAIN_RETRY 10000 -static int pciexp_retrain_link(struct device *dev, unsigned cap) +static int pciexp_retrain_link(struct device *dev, unsigned int cap) { unsigned int try; u16 lnk; @@ -91,8 +90,8 @@ static int pciexp_retrain_link(struct device *dev, unsigned cap) * and enable Common Clock Configuration if possible. If CCC is * enabled the link must be retrained. */ -static void pciexp_enable_common_clock(struct device *root, unsigned root_cap, - struct device *endp, unsigned endp_cap) +static void pciexp_enable_common_clock(struct device *root, unsigned int root_cap, + struct device *endp, unsigned int endp_cap) { u16 root_scc, endp_scc, lnkctl; @@ -123,7 +122,7 @@ static void pciexp_enable_common_clock(struct device *root, unsigned root_cap, } } -static void pciexp_enable_clock_power_pm(struct device *endp, unsigned endp_cap) +static void pciexp_enable_clock_power_pm(struct device *endp, unsigned int endp_cap) { /* check if per port clk req is supported in device */ u32 endp_ca; @@ -329,8 +328,8 @@ static void pciexp_config_L1_sub_state(struct device *root, struct device *dev) * by checking both root port and endpoint and returning * the highest latency value. */ -static int pciexp_aspm_latency(struct device *root, unsigned root_cap, - struct device *endp, unsigned endp_cap, +static int pciexp_aspm_latency(struct device *root, unsigned int root_cap, + struct device *endp, unsigned int endp_cap, enum aspm_type type) { int root_lat = 0, endp_lat = 0; @@ -365,8 +364,8 @@ static int pciexp_aspm_latency(struct device *root, unsigned root_cap, /* * Enable ASPM on PCIe root port and endpoint. */ -static void pciexp_enable_aspm(struct device *root, unsigned root_cap, - struct device *endp, unsigned endp_cap) +static void pciexp_enable_aspm(struct device *root, unsigned int root_cap, + struct device *endp, unsigned int endp_cap) { const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" }; enum aspm_type apmc = PCIE_ASPM_NONE; diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 164fc19960..28a45d0692 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -109,7 +109,7 @@ void pnp_read_resources(struct device *dev) static void pnp_set_resource(struct device *dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { - /* The PNP_MSC super IO registers have the IRQ flag set. If no + /* The PNP_MSC Super IO registers have the IRQ flag set. If no value is assigned in the devicetree, the corresponding PNP_MSC register doesn't get written, which should be printed as warning and not as error. */ diff --git a/src/device/root_device.c b/src/device/root_device.c index beeead2dfb..6801b41004 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -19,7 +19,7 @@ const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER; /** - * Scan devices on static buses. + * Enable devices on static buses. * * The enumeration of certain buses is purely static. The existence of * devices on those buses can be completely determined at compile time @@ -36,7 +36,7 @@ const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_ * @param bus Pointer to the device to which the static buses are attached to. */ -void scan_static_bus(struct device *bus) +void enable_static_devices(struct device *bus) { struct device *child; struct bus *link; @@ -56,30 +56,6 @@ void scan_static_bus(struct device *bus) } } -void scan_lpc_bus(struct device *bus) -{ - printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - - scan_static_bus(bus); - - printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); -} - -void scan_usb_bus(struct device *bus) -{ - struct bus *link; - - printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - - scan_static_bus(bus); - - /* Scan bridges in case this device is a hub */ - for (link = bus->link_list; link; link = link->next) - scan_bridges(link); - - printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); -} - void scan_generic_bus(struct device *bus) { struct device *child; @@ -116,20 +92,23 @@ void scan_smbus(struct device *bus) scan_generic_bus(bus); } -/** - * Scan root bus for generic systems. +/* + * Default scan_bus() implementation * - * This function is the default scan_bus() method of the root device. + * This is the default implementation for buses that can't + * be probed at runtime. It simply walks through the topology + * given by the mainboard's `devicetree.cb`. * - * @param root The root device structure. + * First, all direct descendants of the given device are + * enabled. Then, downstream buses are scanned. */ -static void root_dev_scan_bus(struct device *bus) +void scan_static_bus(struct device *bus) { struct bus *link; printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - scan_static_bus(bus); + enable_static_devices(bus); for (link = bus->link_list; link; link = link->next) scan_bridges(link); @@ -162,7 +141,7 @@ struct device_operations default_dev_ops_root = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, - .scan_bus = root_dev_scan_bus, + .scan_bus = scan_static_bus, .reset_bus = root_dev_reset, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = root_dev_acpi_name, diff --git a/src/device/software_i2c.c b/src/device/software_i2c.c index 5dc99906da..3bb9708bfa 100644 --- a/src/device/software_i2c.c +++ b/src/device/software_i2c.c @@ -38,7 +38,7 @@ struct software_i2c_ops *software_i2c[SOFTWARE_I2C_MAX_BUS]; * Waits until either timeout_us have passed or (iff for_scl is set) until SCL * goes high. Will report random line changes during the wait and return SCL. */ -static int __wait(unsigned bus, int timeout_us, int for_scl) +static int __wait(unsigned int bus, int timeout_us, int for_scl) { int us; int sda = software_i2c[bus]->get_sda(bus); @@ -63,13 +63,13 @@ static int __wait(unsigned bus, int timeout_us, int for_scl) } /* Waits the default DELAY_US to allow line state to stabilize. */ -static void wait(unsigned bus) +static void wait(unsigned int bus) { __wait(bus, DELAY_US, 0); } /* Waits until SCL goes high. Prints a contextual error message on timeout. */ -static int wait_for_scl(unsigned bus, const char *error_context) +static int wait_for_scl(unsigned int bus, const char *error_context) { if (!__wait(bus, TIMEOUT_US, 1)) { printk(BIOS_ERR, "software_i2c(%d): ERROR: Clock stretching " @@ -80,7 +80,7 @@ static int wait_for_scl(unsigned bus, const char *error_context) return 0; } -static int start_cond(unsigned bus) +static int start_cond(unsigned int bus) { spew("software_i2c(%d): Sending start condition... ", bus); @@ -112,7 +112,7 @@ static int start_cond(unsigned bus) return 0; } -static int stop_cond(unsigned bus) +static int stop_cond(unsigned int bus) { spew("software_i2c(%d): Sending stop condition... ", bus); @@ -141,7 +141,7 @@ static int stop_cond(unsigned bus) return 0; } -static int out_bit(unsigned bus, int bit) +static int out_bit(unsigned int bus, int bit) { spew("software_i2c(%d): Sending a %d bit... ", bus, bit); @@ -174,7 +174,7 @@ static int out_bit(unsigned bus, int bit) return 0; } -static int in_bit(unsigned bus) +static int in_bit(unsigned int bus) { int bit; @@ -202,9 +202,9 @@ static int in_bit(unsigned bus) } /* Write a byte to I2C bus. Return 0 if ack by the slave. */ -static int out_byte(unsigned bus, u8 byte) +static int out_byte(unsigned int bus, u8 byte) { - unsigned bit; + unsigned int bit; int nack, ret; for (bit = 0; bit < 8; bit++) @@ -220,7 +220,7 @@ static int out_byte(unsigned bus, u8 byte) return nack > 0 ? ERR_NACK : nack; } -static int in_byte(unsigned bus, int ack) +static int in_byte(unsigned int bus, int ack) { u8 byte = 0; int i, ret; @@ -241,7 +241,7 @@ static int in_byte(unsigned bus, int ack) return byte; } -int software_i2c_transfer(unsigned bus, struct i2c_msg *segments, int count) +int software_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int count) { int i, ret; struct i2c_msg *seg; @@ -269,7 +269,7 @@ int software_i2c_transfer(unsigned bus, struct i2c_msg *segments, int count) return 0; } -void software_i2c_wedge_ack(unsigned bus, u8 chip) +void software_i2c_wedge_ack(unsigned int bus, u8 chip) { int i; @@ -292,7 +292,7 @@ void software_i2c_wedge_ack(unsigned bus, u8 chip) software_i2c[bus]->get_scl(bus)); } -void software_i2c_wedge_read(unsigned bus, u8 chip, u8 reg, int bits) +void software_i2c_wedge_read(unsigned int bus, u8 chip, u8 reg, int bits) { int i; @@ -321,7 +321,7 @@ void software_i2c_wedge_read(unsigned bus, u8 chip, u8 reg, int bits) software_i2c[bus]->get_scl(bus)); } -void software_i2c_wedge_write(unsigned bus, u8 chip, u8 reg, int bits) +void software_i2c_wedge_write(unsigned int bus, u8 chip, u8 reg, int bits) { int i; diff --git a/src/drivers/amd/agesa/acpi_tables.c b/src/drivers/amd/agesa/acpi_tables.c index 4cafacf24d..cb8596fca6 100644 --- a/src/drivers/amd/agesa/acpi_tables.c +++ b/src/drivers/amd/agesa/acpi_tables.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 Advanced Micro Devices, Inc. - * Copyright (C) 2016 Kyösti Mälkki - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 4f0bb3fd75..dcb0c43d8e 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c index d247e51240..2e75220e4c 100644 --- a/src/drivers/amd/agesa/def_callouts.c +++ b/src/drivers/amd/agesa/def_callouts.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 887da308d4..df2c73c26d 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2019 Kyösti Mälkki - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c index 9514bcdf5e..3d698ea37e 100644 --- a/src/drivers/amd/agesa/oem_s3.c +++ b/src/drivers/amd/agesa/oem_s3.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index fad49c305c..76a6ea4500 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Kyösti Mälkki - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c index 4df7b05bac..f81485d87a 100644 --- a/src/drivers/amd/agesa/s3_mtrr.c +++ b/src/drivers/amd/agesa/s3_mtrr.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -21,7 +19,7 @@ #include #include -static void write_mtrr(u8 **p_nvram_pos, unsigned idx) +static void write_mtrr(u8 **p_nvram_pos, unsigned int idx) { msr_t msr_data; msr_data = rdmsr(idx); diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 750d192325..a7255ae44a 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 Advanced Micro Devices, Inc. - * Copyright (C) 2016 Kyösti Mälkki - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/ams/as3722rtc.c b/src/drivers/ams/as3722rtc.c index d504b42403..f76360a117 100644 --- a/src/drivers/ams/as3722rtc.c +++ b/src/drivers/ams/as3722rtc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 The Chromium OS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/asmedia/Makefile.inc b/src/drivers/asmedia/Makefile.inc index daa4e895a1..5c49b5081f 100644 --- a/src/drivers/asmedia/Makefile.inc +++ b/src/drivers/asmedia/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 secunet Security Networks AG -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/asmedia/aspm_blacklist.c b/src/drivers/asmedia/aspm_blacklist.c index 6162416e51..6f84d05f48 100644 --- a/src/drivers/asmedia/aspm_blacklist.c +++ b/src/drivers/asmedia/aspm_blacklist.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 secunet Security Networks AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index 59659b8974..b1bd276c74 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/aspeed/common/aspeed_coreboot.h b/src/drivers/aspeed/common/aspeed_coreboot.h index d1dff330a0..d3b6981708 100644 --- a/src/drivers/aspeed/common/aspeed_coreboot.h +++ b/src/drivers/aspeed/common/aspeed_coreboot.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/aspeed/common/ast_dp501.c b/src/drivers/aspeed/common/ast_dp501.c index 2e8b897464..99b087550f 100644 --- a/src/drivers/aspeed/common/ast_dp501.c +++ b/src/drivers/aspeed/common/ast_dp501.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * File taken from the Linux ast driver (v3.18.5) - * coreboot-specific includes added at top and/or contents modified - * as needed to function within the coreboot environment. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -15,6 +11,12 @@ * GNU General Public License for more details. */ +/* + * File taken from the Linux ast driver (v3.18.5) + * coreboot-specific includes added at top and/or contents modified + * as needed to function within the coreboot environment. + */ + #include #include "ast_drv.h" diff --git a/src/drivers/aspeed/common/ast_dram_tables.h b/src/drivers/aspeed/common/ast_dram_tables.h index 1d46ca6378..39495d3d18 100644 --- a/src/drivers/aspeed/common/ast_dram_tables.h +++ b/src/drivers/aspeed/common/ast_dram_tables.h @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * File taken from the Linux ast driver (v3.18.5) - * coreboot-specific includes added at top and/or contents modified - * as needed to function within the coreboot environment. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -15,6 +11,11 @@ * GNU General Public License for more details. */ +/* + * File taken from the Linux ast driver (v3.18.5) + * coreboot-specific includes added at top and/or contents modified + * as needed to function within the coreboot environment. + */ #ifndef AST_DRAM_TABLES_H #define AST_DRAM_TABLES_H diff --git a/src/drivers/aspeed/common/ast_drv.h b/src/drivers/aspeed/common/ast_drv.h index 53640f11e5..c1794694e0 100644 --- a/src/drivers/aspeed/common/ast_drv.h +++ b/src/drivers/aspeed/common/ast_drv.h @@ -1,4 +1,6 @@ /* + * This file is part of the coreboot project. + * * Copyright 2012 Red Hat Inc. * Copyright (C) 2015 Timothy Pearson , Raptor Engineering * diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c index 086b0a4f10..f9fb5e2361 100644 --- a/src/drivers/aspeed/common/ast_main.c +++ b/src/drivers/aspeed/common/ast_main.c @@ -1,4 +1,6 @@ /* + * This file is part of the coreboot project. + * * Copyright 2012 Red Hat Inc. * Copyright (C) 2015 Timothy Pearson , Raptor Engineering * diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c index 5f935b9976..d14082e0ca 100644 --- a/src/drivers/aspeed/common/ast_post.c +++ b/src/drivers/aspeed/common/ast_post.c @@ -1,4 +1,6 @@ /* + * This file is part of the coreboot project. + * * Copyright 2012 Red Hat Inc. * Copyright (C) 2015 Timothy Pearson , Raptor Engineering * @@ -23,9 +25,6 @@ * of the Software. * */ -/* - * Authors: Dave Airlie - */ #define COREBOOT_AST_FAILOVER_TIMEOUT 10000000 diff --git a/src/drivers/aspeed/common/ast_tables.h b/src/drivers/aspeed/common/ast_tables.h index 6c20f362ff..ae3c6d078a 100644 --- a/src/drivers/aspeed/common/ast_tables.h +++ b/src/drivers/aspeed/common/ast_tables.h @@ -1,4 +1,6 @@ /* + * This file is part of the coreboot project. + * * Copyright (c) 2005 ASPEED Technology Inc. * * Permission to use, copy, modify, distribute, and sell this software and its diff --git a/src/drivers/crb/chip.h b/src/drivers/crb/chip.h index 8e74a68f97..2e34cea88f 100644 --- a/src/drivers/crb/chip.h +++ b/src/drivers/crb/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. All Rights Reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/dec/21143/21143.c b/src/drivers/dec/21143/21143.c index 3af334b00f..0230935752 100644 --- a/src/drivers/dec/21143/21143.c +++ b/src/drivers/dec/21143/21143.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Marc Bertens - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/elog/Kconfig b/src/drivers/elog/Kconfig index 4a66e788bb..ced490e8a0 100644 --- a/src/drivers/elog/Kconfig +++ b/src/drivers/elog/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 The Chromium OS Authors. All rights reserved. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/elog/boot_count.c b/src/drivers/elog/boot_count.c index 97d7098eeb..a6efb01465 100644 --- a/src/drivers/elog/boot_count.c +++ b/src/drivers/elog/boot_count.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 9ac2d3c095..c979e0cef9 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/elog/elog_internal.h b/src/drivers/elog/elog_internal.h index afcee5736f..d16d9a3af2 100644 --- a/src/drivers/elog/elog_internal.h +++ b/src/drivers/elog/elog_internal.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/elog/gsmi.c b/src/drivers/elog/gsmi.c index 9f676cb6b6..0c0a214def 100644 --- a/src/drivers/elog/gsmi.c +++ b/src/drivers/elog/gsmi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index 22095efb02..f49b72cdfa 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -15,11 +15,9 @@ #include #include #include -#include #include #include #include -#include #include #include #include diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index ed5a4f4767..43710d9ece 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Vladimir Serbinenko - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of @@ -17,11 +15,9 @@ #include #include #include -#include #include #include #include -#include #include #include #include @@ -201,23 +197,23 @@ write_hidden_dac (uint8_t data) static void cirrus_init_linear_fb(struct device *dev) { uint8_t cr_ext, cr_overlay; - unsigned pitch = (width * 4) / VGA_CR_PITCH_DIVISOR; + unsigned int pitch = (width * 4) / VGA_CR_PITCH_DIVISOR; uint8_t sr_ext = 0, hidden_dac = 0; - unsigned vdisplay_end = height - 2; - unsigned line_compare = 0x3ff; + unsigned int vdisplay_end = height - 2; + unsigned int line_compare = 0x3ff; uint8_t overflow, cell_height_reg; - unsigned horizontal_end = width / VGA_CR_WIDTH_DIVISOR; - unsigned horizontal_total = horizontal_end + 40; - unsigned horizontal_blank_start = horizontal_end; - unsigned horizontal_sync_pulse_start = horizontal_end + 3; - unsigned horizontal_sync_pulse_end = 0; + unsigned int horizontal_end = width / VGA_CR_WIDTH_DIVISOR; + unsigned int horizontal_total = horizontal_end + 40; + unsigned int horizontal_blank_start = horizontal_end; + unsigned int horizontal_sync_pulse_start = horizontal_end + 3; + unsigned int horizontal_sync_pulse_end = 0; - unsigned horizontal_blank_end = 0; - unsigned vertical_blank_start = height + 1; - unsigned vertical_blank_end = 0; - unsigned vertical_sync_start = height + 3; - unsigned vertical_sync_end = 0; - unsigned vertical_total = height + 40; + unsigned int horizontal_blank_end = 0; + unsigned int vertical_blank_start = height + 1; + unsigned int vertical_blank_end = 0; + unsigned int vertical_sync_start = height + 3; + unsigned int vertical_sync_end = 0; + unsigned int vertical_total = height + 40; /* find lfb pci bar */ addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0); diff --git a/src/drivers/emulation/qemu/qemu_debugcon.c b/src/drivers/emulation/qemu/qemu_debugcon.c index b040bd8388..00c3aade3a 100644 --- a/src/drivers/emulation/qemu/qemu_debugcon.c +++ b/src/drivers/emulation/qemu/qemu_debugcon.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Red Hat Inc. - * Written by Gerd Hoffmann - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/generic/adau7002/adau7002.c b/src/drivers/generic/adau7002/adau7002.c index 1aff453396..7f73cef40d 100644 --- a/src/drivers/generic/adau7002/adau7002.c +++ b/src/drivers/generic/adau7002/adau7002.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/generic/adau7002/chip.h b/src/drivers/generic/adau7002/chip.h index f8cab445e3..1b758a242b 100644 --- a/src/drivers/generic/adau7002/chip.h +++ b/src/drivers/generic/adau7002/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/generic/bayhub/bh720.c b/src/drivers/generic/bayhub/bh720.c index 09fa578e86..a1c555aacd 100644 --- a/src/drivers/generic/bayhub/bh720.c +++ b/src/drivers/generic/bayhub/bh720.c @@ -1,10 +1,6 @@ /* - * Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge - * * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -15,6 +11,8 @@ * GNU General Public License for more details. */ +/* Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge */ + #include #include #include @@ -82,12 +80,6 @@ static const struct pci_driver bayhub_bh720 __pci_driver = { .devices = pci_device_ids, }; -static void bh720_enable(struct device *dev) -{ - dev->ops = &bh720_ops; -} - -struct chip_operations bayhub_bh720_ops = { +struct chip_operations drivers_generic_bayhub_ops = { CHIP_NAME("BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge") - .enable_dev = bh720_enable, }; diff --git a/src/drivers/generic/bayhub/bh720.h b/src/drivers/generic/bayhub/bh720.h index ecea513bfb..4ee7b6a7f8 100644 --- a/src/drivers/generic/bayhub/bh720.h +++ b/src/drivers/generic/bayhub/bh720.h @@ -1,10 +1,6 @@ /* - * Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge - * * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -15,6 +11,8 @@ * GNU General Public License for more details. */ +/* Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge */ + #include enum { diff --git a/src/drivers/generic/bayhub/chip.h b/src/drivers/generic/bayhub/chip.h index ea1d3bb135..820ed1c9ec 100644 --- a/src/drivers/generic/bayhub/chip.h +++ b/src/drivers/generic/bayhub/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/generic/generic/chip.h b/src/drivers/generic/generic/chip.h index fc470cec0d..9a59486a71 100644 --- a/src/drivers/generic/generic/chip.h +++ b/src/drivers/generic/generic/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/generic/generic/generic.c b/src/drivers/generic/generic/generic.c index b5541a399d..c68fa3a0d3 100644 --- a/src/drivers/generic/generic/generic.c +++ b/src/drivers/generic/generic/generic.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/generic/gpio_keys/chip.h b/src/drivers/generic/gpio_keys/chip.h index 08acfebf6e..31ba701518 100644 --- a/src/drivers/generic/gpio_keys/chip.h +++ b/src/drivers/generic/gpio_keys/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c index 2cf8f28e0b..753a555a48 100644 --- a/src/drivers/generic/gpio_keys/gpio_keys.c +++ b/src/drivers/generic/gpio_keys/gpio_keys.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/generic/gpio_regulator/Kconfig b/src/drivers/generic/gpio_regulator/Kconfig index 12ab3cb223..39b77e6585 100644 --- a/src/drivers/generic/gpio_regulator/Kconfig +++ b/src/drivers/generic/gpio_regulator/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright 2016 Google Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/generic/gpio_regulator/Makefile.inc b/src/drivers/generic/gpio_regulator/Makefile.inc index 845b19105a..db2e9d4e6c 100644 --- a/src/drivers/generic/gpio_regulator/Makefile.inc +++ b/src/drivers/generic/gpio_regulator/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright 2016 Google Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/generic/gpio_regulator/chip.h b/src/drivers/generic/gpio_regulator/chip.h index 8d655ef6e5..b5535d22ef 100644 --- a/src/drivers/generic/gpio_regulator/chip.h +++ b/src/drivers/generic/gpio_regulator/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/generic/gpio_regulator/gpio_regulator.c b/src/drivers/generic/gpio_regulator/gpio_regulator.c index 3b7718c6f0..23c044de2a 100644 --- a/src/drivers/generic/gpio_regulator/gpio_regulator.c +++ b/src/drivers/generic/gpio_regulator/gpio_regulator.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/generic/ioapic/chip.h b/src/drivers/generic/ioapic/chip.h index a941ae1614..b8a20d1898 100644 --- a/src/drivers/generic/ioapic/chip.h +++ b/src/drivers/generic/ioapic/chip.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle - * Copyright (C) 2012 Alexandru Gagniuc - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index bc58caf045..74dd941cd7 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -1,3 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include #include #include "chip.h" diff --git a/src/drivers/generic/max98357a/chip.h b/src/drivers/generic/max98357a/chip.h index 0abd616c18..ec4e94f3e6 100644 --- a/src/drivers/generic/max98357a/chip.h +++ b/src/drivers/generic/max98357a/chip.h @@ -1,3 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include struct drivers_generic_max98357a_config { @@ -5,9 +18,9 @@ struct drivers_generic_max98357a_config { struct acpi_gpio sdmode_gpio; /* SDMODE Delay */ - unsigned sdmode_delay; + unsigned int sdmode_delay; /* GPIO used to indicate if this device is present */ - unsigned device_present_gpio; - unsigned device_present_gpio_invert; + unsigned int device_present_gpio; + unsigned int device_present_gpio_invert; }; diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 838491dc84..2b0ec3ba04 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/gic/gic.c b/src/drivers/gic/gic.c index 1d416bfc84..9704b5ec03 100644 --- a/src/drivers/gic/gic.c +++ b/src/drivers/gic/gic.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/gic/gic.h b/src/drivers/gic/gic.h index 1f27f19c67..e5b4b11d2e 100644 --- a/src/drivers/gic/gic.h +++ b/src/drivers/gic/gic.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/adm1026/adm1026.c b/src/drivers/i2c/adm1026/adm1026.c index 0a3ac8dfac..c1bd90528c 100644 --- a/src/drivers/i2c/adm1026/adm1026.c +++ b/src/drivers/i2c/adm1026/adm1026.c @@ -1,3 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include #include #include diff --git a/src/drivers/i2c/adm1027/adm1027.c b/src/drivers/i2c/adm1027/adm1027.c index 375b2921e4..397dd77792 100644 --- a/src/drivers/i2c/adm1027/adm1027.c +++ b/src/drivers/i2c/adm1027/adm1027.c @@ -1,3 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include #include #include diff --git a/src/drivers/i2c/adt7463/adt7463.c b/src/drivers/i2c/adt7463/adt7463.c index 93c6f19b90..d1c5819c21 100644 --- a/src/drivers/i2c/adt7463/adt7463.c +++ b/src/drivers/i2c/adt7463/adt7463.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2005 Tyan - * (Written by Yinghai Lu for Tyan) - * Copyright (C) 2007 Ward Vandewege - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index 67760a0d03..102e0e8c7c 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Vladimir Serbinenko - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index 0a6b343e6f..aacdb724c6 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Vladimir Serbinenko - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -118,7 +116,7 @@ const char *smbios_mainboard_product_name(void) void smbios_system_set_uuid(u8 *uuid) { static char result[16]; - unsigned i; + unsigned int i; static int already_read; struct device *dev; const int remap[16] = { diff --git a/src/drivers/i2c/ck505/chip.h b/src/drivers/i2c/ck505/chip.h index 8ce297cb53..a66a103246 100644 --- a/src/drivers/i2c/ck505/chip.h +++ b/src/drivers/i2c/ck505/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/drivers/i2c/ck505/ck505.c b/src/drivers/i2c/ck505/ck505.c index b368d81f30..4baa1bc94a 100644 --- a/src/drivers/i2c/ck505/ck505.c +++ b/src/drivers/i2c/ck505/ck505.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Sven Schnelle - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/drivers/i2c/da7219/chip.h b/src/drivers/i2c/da7219/chip.h index deb1c26b3e..89ee21e217 100644 --- a/src/drivers/i2c/da7219/chip.h +++ b/src/drivers/i2c/da7219/chip.h @@ -1,3 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include /* @@ -12,13 +25,13 @@ struct drivers_i2c_da7219_config { struct acpi_gpio irq_gpio; /* I2C Bus Frequency in Hertz (default 400kHz) */ - unsigned bus_speed; + unsigned int bus_speed; /* * micbias-lvl : Voltage (mV) for Mic Bias * [<1600>, <1800>, <2000>, <2200>, <2400>, <2600>] */ - unsigned micbias_lvl; + unsigned int micbias_lvl; /* * mic-amp-in-sel : Mic input source type @@ -34,30 +47,30 @@ struct drivers_i2c_da7219_config { * micbias-pulse-lvl : Mic bias higher voltage pulse level (mV) * [<2800>, <2900>] */ - unsigned micbias_pulse_lvl; + unsigned int micbias_pulse_lvl; /* * micbias-pulse-time : Mic bias higher voltage pulse duration (ms) */ - unsigned micbias_pulse_time; + unsigned int micbias_pulse_time; /* * btn-cfg : Periodic button press measurements for 4-pole jack (ms) * [<2>, <5>, <10>, <50>, <100>, <200>, <500>] */ - unsigned btn_cfg; + unsigned int btn_cfg; /* * mic-det-thr : Impedance threshold for mic detection measurement (Ohms) * [<200>, <500>, <750>, <1000>] */ - unsigned mic_det_thr; + unsigned int mic_det_thr; /* * jack-ins-deb : Debounce time for jack insertion (ms) * [<5>, <10>, <20>, <50>, <100>, <200>, <500>, <1000>] */ - unsigned jack_ins_deb; + unsigned int jack_ins_deb; /* * jack-det-rate : Jack type detection latency (3/4 pole) @@ -69,43 +82,43 @@ struct drivers_i2c_da7219_config { * jack-rem-deb : Debounce time for jack removal (ms) * [<1>, <5>, <10>, <20>] */ - unsigned jack_rem_deb; + unsigned int jack_rem_deb; /* * a-d-btn-thr : Impedance threshold between buttons A and D * [0x0 - 0xFF] */ - unsigned a_d_btn_thr; + unsigned int a_d_btn_thr; /* * d-b-btn-thr : Impedance threshold between buttons D and B * [0x0 - 0xFF] */ - unsigned d_b_btn_thr; + unsigned int d_b_btn_thr; /* * b-c-btn-thr : Impedance threshold between buttons B and C * [0x0 - 0xFF] */ - unsigned b_c_btn_thr; + unsigned int b_c_btn_thr; /* * c-mic-btn-thr : Impedance threshold between button C and Mic * [0x0 - 0xFF] */ - unsigned c_mic_btn_thr; + unsigned int c_mic_btn_thr; /* * btn-avg : Number of 8-bit readings for averaged button measurement * [<1>, <2>, <4>, <8>] */ - unsigned btn_avg; + unsigned int btn_avg; /* * adc-1bit-rpt : Repeat count for 1-bit button measurement * [<1>, <2>, <4>, <8>] */ - unsigned adc_1bit_rpt; + unsigned int adc_1bit_rpt; /* * mclk-name : Pass the system clk to da7219 diff --git a/src/drivers/i2c/da7219/da7219.c b/src/drivers/i2c/da7219/da7219.c index 2a4d78760e..f82cd9f6e7 100644 --- a/src/drivers/i2c/da7219/da7219.c +++ b/src/drivers/i2c/da7219/da7219.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 760a735380..eb90387955 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2009 Vipin Kumar, ST Microelectronics - * Copyright 2017 Google Inc. - * Copyright 2017 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/designware/dw_i2c.h b/src/drivers/i2c/designware/dw_i2c.h index d78000793e..a4087ef9c7 100644 --- a/src/drivers/i2c/designware/dw_i2c.h +++ b/src/drivers/i2c/designware/dw_i2c.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index 99e599d5ea..ffaf7e14e5 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -26,10 +24,10 @@ struct drivers_i2c_generic_config { const char *cid; /* ACPI _CID */ const char *name; /* ACPI Device Name */ const char *desc; /* Device Description */ - unsigned uid; /* ACPI _UID */ + unsigned int uid; /* ACPI _UID */ enum i2c_speed speed; /* Bus speed in Hz, default is I2C_SPEED_FAST */ const char *compat_string; /* Compatible string for _HID=PRP0001 */ - unsigned wake; /* Wake GPE */ + unsigned int wake; /* Wake GPE */ struct acpi_irq irq; /* Interrupt */ /* Use GPIO based interrupt instead of PIRQ */ @@ -45,8 +43,8 @@ struct drivers_i2c_generic_config { int probed; /* GPIO used to indicate if this device is present */ - unsigned device_present_gpio; - unsigned device_present_gpio_invert; + unsigned int device_present_gpio; + unsigned int device_present_gpio_invert; /* Disable reset and enable GPIO export in _CRS */ bool disable_gpio_export_in_crs; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 9b4f00daa4..0b36e5f11f 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/hid/chip.h b/src/drivers/i2c/hid/chip.h index 7bce167491..06888b63e5 100644 --- a/src/drivers/i2c/hid/chip.h +++ b/src/drivers/i2c/hid/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c index 035e5633c6..b8185d062b 100644 --- a/src/drivers/i2c/hid/hid.c +++ b/src/drivers/i2c/hid/hid.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/i2cmux/i2cmux.c b/src/drivers/i2c/i2cmux/i2cmux.c index ef5ab3a6e9..42b9d31057 100644 --- a/src/drivers/i2c/i2cmux/i2cmux.c +++ b/src/drivers/i2c/i2cmux/i2cmux.c @@ -1,3 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include #include diff --git a/src/drivers/i2c/i2cmux2/i2cmux2.c b/src/drivers/i2c/i2cmux2/i2cmux2.c index 4d1241acb9..c3440afea8 100644 --- a/src/drivers/i2c/i2cmux2/i2cmux2.c +++ b/src/drivers/i2c/i2cmux2/i2cmux2.c @@ -1,3 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include #include diff --git a/src/drivers/i2c/lm63/lm63.c b/src/drivers/i2c/lm63/lm63.c index 5ef70cb9c8..3da38d8cfc 100644 --- a/src/drivers/i2c/lm63/lm63.c +++ b/src/drivers/i2c/lm63/lm63.c @@ -1,3 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include #include diff --git a/src/drivers/i2c/lm96000/chip.h b/src/drivers/i2c/lm96000/chip.h index cbf8601146..30cd4e01f8 100644 --- a/src/drivers/i2c/lm96000/chip.h +++ b/src/drivers/i2c/lm96000/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 secunet Security Networks AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/lm96000/lm96000.c b/src/drivers/i2c/lm96000/lm96000.c index 7fbb31b4e5..5130630fd1 100644 --- a/src/drivers/i2c/lm96000/lm96000.c +++ b/src/drivers/i2c/lm96000/lm96000.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 secunet Security Networks AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/lm96000/lm96000.h b/src/drivers/i2c/lm96000/lm96000.h index 6df4fdeef3..a24d8fe68e 100644 --- a/src/drivers/i2c/lm96000/lm96000.h +++ b/src/drivers/i2c/lm96000/lm96000.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 secunet Security Networks AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/max98373/chip.h b/src/drivers/i2c/max98373/chip.h index dcaf3570cc..3642ebd349 100644 --- a/src/drivers/i2c/max98373/chip.h +++ b/src/drivers/i2c/max98373/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/max98373/max98373.c b/src/drivers/i2c/max98373/max98373.c index 07e23a81f9..48db3e1be4 100644 --- a/src/drivers/i2c/max98373/max98373.c +++ b/src/drivers/i2c/max98373/max98373.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/max98927/chip.h b/src/drivers/i2c/max98927/chip.h index 6d3b9a56da..25c0dd7e35 100644 --- a/src/drivers/i2c/max98927/chip.h +++ b/src/drivers/i2c/max98927/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/max98927/max98927.c b/src/drivers/i2c/max98927/max98927.c index 395b79b4be..1cc72d36cf 100644 --- a/src/drivers/i2c/max98927/max98927.c +++ b/src/drivers/i2c/max98927/max98927.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/nau8825/chip.h b/src/drivers/i2c/nau8825/chip.h index e6c88bc4e7..9fc8e96ac4 100644 --- a/src/drivers/i2c/nau8825/chip.h +++ b/src/drivers/i2c/nau8825/chip.h @@ -1,3 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include #define NAU8825_MAX_BUTTONS 8 @@ -11,19 +24,19 @@ struct drivers_i2c_nau8825_config { struct acpi_irq irq; /* I2C Bus Frequency in Hertz (default 400kHz) */ - unsigned bus_speed; + unsigned int bus_speed; /* Enable jack detection via JKDET pin */ - unsigned jkdet_enable; + unsigned int jkdet_enable; /* Enable JKDET pin pull if set, otherwise high impedance state */ - unsigned jkdet_pull_enable; + unsigned int jkdet_pull_enable; /* Pull-up JKDET pin if set, otherwise pull down */ - unsigned jkdet_pull_up; + unsigned int jkdet_pull_up; /* JKDET pin polarity, 0 => active high, 1 => active low */ - unsigned jkdet_polarity; + unsigned int jkdet_polarity; /* * VREF Impedance selection @@ -32,10 +45,10 @@ struct drivers_i2c_nau8825_config { * 2 - 125 kOhm * 3 - 2.5 kOhm */ - unsigned vref_impedance; + unsigned int vref_impedance; /* Button impedance measurement hysteresis */ - unsigned sar_hysteresis; + unsigned int sar_hysteresis; /* * Reference voltage for button impedance measurement and micbias @@ -48,8 +61,8 @@ struct drivers_i2c_nau8825_config { * 6 - VDDA * 1.53 * 7 - VDDA * 1.53 */ - unsigned micbias_voltage; - unsigned sar_voltage; + unsigned int micbias_voltage; + unsigned int sar_voltage; /* * SAR compare time @@ -58,7 +71,7 @@ struct drivers_i2c_nau8825_config { * 2 - 2 us * 3 - 4 us */ - unsigned sar_compare_time; + unsigned int sar_compare_time; /* * SAR sampling time @@ -67,7 +80,7 @@ struct drivers_i2c_nau8825_config { * 2 - 8 us * 3 - 16 us */ - unsigned sar_sampling_time; + unsigned int sar_sampling_time; /* * Button short key press debounce time @@ -76,16 +89,16 @@ struct drivers_i2c_nau8825_config { * 2 - 100 ms * 3 - 30 ms */ - unsigned short_key_debounce; + unsigned int short_key_debounce; /* Debounce time 2^(n+2) ms (0-7) for jack insert */ - unsigned jack_insert_debounce; + unsigned int jack_insert_debounce; /* Debounce time 2^(n+2) ms (0-7) for jack eject */ - unsigned jack_eject_debounce; + unsigned int jack_eject_debounce; /* Number of buttons supported, up to 8 */ - unsigned sar_threshold_num; + unsigned int sar_threshold_num; /* * Impedance threshold for each button, up to 8 diff --git a/src/drivers/i2c/nau8825/nau8825.c b/src/drivers/i2c/nau8825/nau8825.c index 60c73b147d..33b3421318 100644 --- a/src/drivers/i2c/nau8825/nau8825.c +++ b/src/drivers/i2c/nau8825/nau8825.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/nct7802y/chip.h b/src/drivers/i2c/nct7802y/chip.h index 11db12be35..adff0f512c 100644 --- a/src/drivers/i2c/nct7802y/chip.h +++ b/src/drivers/i2c/nct7802y/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 secunet Security Networks AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/nct7802y/nct7802y.c b/src/drivers/i2c/nct7802y/nct7802y.c index 3681383610..d2cce64fc2 100644 --- a/src/drivers/i2c/nct7802y/nct7802y.c +++ b/src/drivers/i2c/nct7802y/nct7802y.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 secunet Security Networks AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/nct7802y/nct7802y.h b/src/drivers/i2c/nct7802y/nct7802y.h index 16a16840f3..9f3aaef1d0 100644 --- a/src/drivers/i2c/nct7802y/nct7802y.h +++ b/src/drivers/i2c/nct7802y/nct7802y.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 secunet Security Networks AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/nct7802y/nct7802y_fan.c b/src/drivers/i2c/nct7802y/nct7802y_fan.c index f0f3a3ced8..d7cfb908cd 100644 --- a/src/drivers/i2c/nct7802y/nct7802y_fan.c +++ b/src/drivers/i2c/nct7802y/nct7802y_fan.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 secunet Security Networks AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/nct7802y/nct7802y_peci.c b/src/drivers/i2c/nct7802y/nct7802y_peci.c index 26e62a3f09..58d7064635 100644 --- a/src/drivers/i2c/nct7802y/nct7802y_peci.c +++ b/src/drivers/i2c/nct7802y/nct7802y_peci.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 secunet Security Networks AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/pca9538/chip.h b/src/drivers/i2c/pca9538/chip.h index 9c60aab226..40072e1279 100644 --- a/src/drivers/i2c/pca9538/chip.h +++ b/src/drivers/i2c/pca9538/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Siemens AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/pca9538/pca9538.c b/src/drivers/i2c/pca9538/pca9538.c index 95848ad3de..d5cd96d9e8 100644 --- a/src/drivers/i2c/pca9538/pca9538.c +++ b/src/drivers/i2c/pca9538/pca9538.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Siemens AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/pca9538/pca9538.h b/src/drivers/i2c/pca9538/pca9538.h index 6db95be646..9519c9a472 100644 --- a/src/drivers/i2c/pca9538/pca9538.h +++ b/src/drivers/i2c/pca9538/pca9538.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Siemens AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/pcf8523/Kconfig b/src/drivers/i2c/pcf8523/Kconfig index d86364bb26..3bc95fbca4 100644 --- a/src/drivers/i2c/pcf8523/Kconfig +++ b/src/drivers/i2c/pcf8523/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Siemens AG -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/pcf8523/Makefile.inc b/src/drivers/i2c/pcf8523/Makefile.inc index 496b1e3061..312b8f6603 100644 --- a/src/drivers/i2c/pcf8523/Makefile.inc +++ b/src/drivers/i2c/pcf8523/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Siemens AG -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/pcf8523/chip.h b/src/drivers/i2c/pcf8523/chip.h index dde009ce7e..d40ccd7d06 100644 --- a/src/drivers/i2c/pcf8523/chip.h +++ b/src/drivers/i2c/pcf8523/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Siemens AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/pcf8523/pcf8523.c b/src/drivers/i2c/pcf8523/pcf8523.c index 2da8be2a3b..5666042f12 100644 --- a/src/drivers/i2c/pcf8523/pcf8523.c +++ b/src/drivers/i2c/pcf8523/pcf8523.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Siemens AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/pcf8523/pcf8523.h b/src/drivers/i2c/pcf8523/pcf8523.h index 3d863844e2..02659e2cf6 100644 --- a/src/drivers/i2c/pcf8523/pcf8523.h +++ b/src/drivers/i2c/pcf8523/pcf8523.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Siemens AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/rt1011/Kconfig b/src/drivers/i2c/rt1011/Kconfig new file mode 100644 index 0000000000..f7951966f0 --- /dev/null +++ b/src/drivers/i2c/rt1011/Kconfig @@ -0,0 +1,4 @@ +config DRIVERS_I2C_RT1011 + bool + default n + depends on HAVE_ACPI_TABLES diff --git a/src/drivers/i2c/rt1011/Makefile.inc b/src/drivers/i2c/rt1011/Makefile.inc new file mode 100644 index 0000000000..a8b8283f3f --- /dev/null +++ b/src/drivers/i2c/rt1011/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_RT1011) += rt1011.c diff --git a/src/drivers/i2c/rt1011/chip.h b/src/drivers/i2c/rt1011/chip.h new file mode 100644 index 0000000000..6bbddac3fd --- /dev/null +++ b/src/drivers/i2c/rt1011/chip.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Realtek RT1011 audio codec devicetree bindings + */ + +#include + +struct drivers_i2c_rt1011_config { + const char *name; /* ACPI Device Name */ + const char *desc; /* Device Description */ + unsigned int uid; /* ACPI _UID */ + + /* The VPD key of calibrated speaker resistance. */ + const char *r0_calib_key; + /* The VPD key of temperature during speaker calibration. */ + const char *temperature_calib_key; +}; diff --git a/src/drivers/i2c/rt1011/rt1011.c b/src/drivers/i2c/rt1011/rt1011.c new file mode 100644 index 0000000000..792992e355 --- /dev/null +++ b/src/drivers/i2c/rt1011/rt1011.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +#define RT1011_ACPI_HID "10EC1011" + +#define RT1011_DP_INT(key, val) acpi_dp_add_integer(dp, "realtek," key, (val)) + +static void rt1011_fill_ssdt(struct device *dev) +{ + struct drivers_i2c_rt1011_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_dp *dp; + uint64_t r0_value, temp_value; + + if (!dev->enabled || !scope) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", RT1011_ACPI_HID); + acpigen_write_name_integer("_UID", config->uid); + acpigen_write_name_string("_DDN", config->desc); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + acpigen_write_resourcetemplate_footer(); + + /* Device Properties */ + if (CONFIG(CHROMEOS_DSM_CALIB)) { + if (get_dsm_calibration_from_key(config->r0_calib_key, &r0_value) + || get_dsm_calibration_from_key(config->temperature_calib_key, + &temp_value)) { + printk(BIOS_ERR, + "Failed to get dsm_calib parameters from VPD" + " with key %s and %s\n", + config->r0_calib_key, config->temperature_calib_key); + } else { + dp = acpi_dp_new_table("_DSD"); + RT1011_DP_INT("r0_calib", r0_value); + RT1011_DP_INT("temperature_calib", temp_value); + acpi_dp_write(dp); + printk(BIOS_INFO, "set dsm_calib properties\n"); + } + } + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s address 0%xh\n", acpi_device_path(dev), dev->chip_ops->name, + dev->path.i2c.device); +} + +static const char *rt1011_acpi_name(const struct device *dev) +{ + struct drivers_i2c_rt1011_config *config = dev->chip_info; + static char name[5]; + + if (config->name) + return config->name; + + snprintf(name, sizeof(name), "D%03.3X", dev->path.i2c.device); + return name; +} + +static struct device_operations rt1011_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .acpi_name = rt1011_acpi_name, + .acpi_fill_ssdt_generator = rt1011_fill_ssdt, +}; + +static void rt1011_enable(struct device *dev) +{ + struct drivers_i2c_rt1011_config *config = dev->chip_info; + + if (!config) + return; + + dev->ops = &rt1011_ops; + + /* Name the device as per description provided in devicetree */ + if (config->desc) + dev->name = config->desc; +} + +struct chip_operations drivers_i2c_rt1011_ops = { + CHIP_NAME("Realtek RT1011 Codec") + .enable_dev = rt1011_enable +}; diff --git a/src/drivers/i2c/rt5663/chip.h b/src/drivers/i2c/rt5663/chip.h index 5720b185a3..b1ed4b6589 100644 --- a/src/drivers/i2c/rt5663/chip.h +++ b/src/drivers/i2c/rt5663/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/rt5663/rt5663.c b/src/drivers/i2c/rt5663/rt5663.c index 415ae713c9..6f4e032953 100644 --- a/src/drivers/i2c/rt5663/rt5663.c +++ b/src/drivers/i2c/rt5663/rt5663.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/rtd2132/chip.h b/src/drivers/i2c/rtd2132/chip.h index 2906fde17d..a0bb3e6b1b 100644 --- a/src/drivers/i2c/rtd2132/chip.h +++ b/src/drivers/i2c/rtd2132/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. All Rights Reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/rtd2132/rtd2132.c b/src/drivers/i2c/rtd2132/rtd2132.c index 2aaa234d78..168f921e67 100644 --- a/src/drivers/i2c/rtd2132/rtd2132.c +++ b/src/drivers/i2c/rtd2132/rtd2132.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/rx6110sa/chip.h b/src/drivers/i2c/rx6110sa/chip.h index d9960dcf77..f81f4f4d16 100644 --- a/src/drivers/i2c/rx6110sa/chip.h +++ b/src/drivers/i2c/rx6110sa/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Siemens AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.c b/src/drivers/i2c/rx6110sa/rx6110sa.c index 266b5a8ac5..37f306b472 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.c +++ b/src/drivers/i2c/rx6110sa/rx6110sa.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Siemens AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.h b/src/drivers/i2c/rx6110sa/rx6110sa.h index 7e71f24ec3..eb6ca6dfb3 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.h +++ b/src/drivers/i2c/rx6110sa/rx6110sa.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Siemens AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/sx9310/chip.h b/src/drivers/i2c/sx9310/chip.h index c99a8a1539..b1d5a6ebe8 100644 --- a/src/drivers/i2c/sx9310/chip.h +++ b/src/drivers/i2c/sx9310/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/sx9310/registers.h b/src/drivers/i2c/sx9310/registers.h index fb6c764aa8..2c61adbe2e 100644 --- a/src/drivers/i2c/sx9310/registers.h +++ b/src/drivers/i2c/sx9310/registers.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/sx9310/sx9310.c b/src/drivers/i2c/sx9310/sx9310.c index 8157874d07..9da687574f 100644 --- a/src/drivers/i2c/sx9310/sx9310.c +++ b/src/drivers/i2c/sx9310/sx9310.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/tpm/chip.c b/src/drivers/i2c/tpm/chip.c index 7e950321b3..b13f66675b 100644 --- a/src/drivers/i2c/tpm/chip.c +++ b/src/drivers/i2c/tpm/chip.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/tpm/chip.h b/src/drivers/i2c/tpm/chip.h index 149627f8f4..ebe94e557b 100644 --- a/src/drivers/i2c/tpm/chip.h +++ b/src/drivers/i2c/tpm/chip.h @@ -1,3 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include #include diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 19c8f6bcbb..6714bd4a03 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -1,9 +1,5 @@ /* - * Copyright 2016 Google Inc. - * - * Based on Linux Kernel TPM driver by - * Peter Huewe - * Copyright (C) 2011 Infineon Technologies + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -16,6 +12,8 @@ * GNU General Public License for more details. */ +/* Based on Linux Kernel TPM driver */ + /* * cr50 is a TPM 2.0 capable device that requries special * handling for the I2C interface. @@ -31,7 +29,6 @@ #include #include -#include #include #include #include @@ -40,6 +37,8 @@ #include #include #include +#include + #include "tpm.h" #define CR50_MAX_BUFSIZE 63 diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c index fd56adefcc..e466c45c9f 100644 --- a/src/drivers/i2c/tpm/tis.c +++ b/src/drivers/i2c/tpm/tis.c @@ -1,6 +1,5 @@ /* - * Copyright (C) 2011 Infineon Technologies - * Copyright 2013 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/drivers/i2c/tpm/tis_atmel.c b/src/drivers/i2c/tpm/tis_atmel.c index 4456567e4d..42df292615 100644 --- a/src/drivers/i2c/tpm/tis_atmel.c +++ b/src/drivers/i2c/tpm/tis_atmel.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 Intel Corporation + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -13,7 +13,6 @@ */ #include -#include #include #include #include @@ -22,7 +21,9 @@ #include #include #include +#include #include +#include #define RECV_TIMEOUT (1 * 1000) /* 1 second */ #define XMIT_TIMEOUT (1 * 1000) /* 1 second */ diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index 447fc2464f..e0950849fc 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -1,9 +1,18 @@ /* - * Copyright (C) 2011 Infineon Technologies + * This file is part of the coreboot project. * - * Authors: - * Peter Huewe + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation, version 2 of the + * License. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* * Description: * Device driver for TCG/TCPA TPM (trusted platform module). * Specifications at www.trustedcomputinggroup.org @@ -16,18 +25,9 @@ * Dorn, Dave Safford, Reiner Sailer, and Kyleen Hall. * * Version: 2.1.1 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation, version 2 of the - * License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ + #include #include #include diff --git a/src/drivers/i2c/tpm/tpm.h b/src/drivers/i2c/tpm/tpm.h index 1a01e05055..2d7c3855c0 100644 --- a/src/drivers/i2c/tpm/tpm.h +++ b/src/drivers/i2c/tpm/tpm.h @@ -1,17 +1,5 @@ /* - * Copyright (C) 2011 Infineon Technologies - * - * Authors: - * Peter Huewe - * - * Version: 2.1.1 - * - * Description: - * Device driver for TCG/TCPA TPM (trusted platform module). - * Specifications at www.trustedcomputinggroup.org - * - * It is based on the Linux kernel driver tpm.c from Leendert van - * Dorn, Dave Safford, Reiner Sailer, and Kyleen Hall. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -24,6 +12,15 @@ * GNU General Public License for more details. */ +/* + * Description: + * Device driver for TCG/TCPA TPM (trusted platform module). + * Specifications at www.trustedcomputinggroup.org + * + * It is based on the Linux kernel driver tpm.c from Leendert van + * Dorn, Dave Safford, Reiner Sailer, and Kyleen Hall. + */ + #ifndef __DRIVERS_TPM_SLB9635_I2C_TPM_H__ #define __DRIVERS_TPM_SLB9635_I2C_TPM_H__ diff --git a/src/drivers/i2c/w83793/chip.h b/src/drivers/i2c/w83793/chip.h index bf8bb32a1c..9326ed2951 100644 --- a/src/drivers/i2c/w83793/chip.h +++ b/src/drivers/i2c/w83793/chip.h @@ -1,3 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + struct drivers_i2c_w83793_config { u8 mfc; u8 fanin; diff --git a/src/drivers/i2c/w83793/w83793.c b/src/drivers/i2c/w83793/w83793.c index 8b8f3d238f..dd95e183b5 100644 --- a/src/drivers/i2c/w83793/w83793.c +++ b/src/drivers/i2c/w83793/w83793.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/w83793/w83793.h b/src/drivers/i2c/w83793/w83793.h index 014ba3b103..2d149ba71f 100644 --- a/src/drivers/i2c/w83793/w83793.h +++ b/src/drivers/i2c/w83793/w83793.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/w83795/chip.h b/src/drivers/i2c/w83795/chip.h index e3426dec5c..ff1de81526 100644 --- a/src/drivers/i2c/w83795/chip.h +++ b/src/drivers/i2c/w83795/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c index 68696362ef..16cd813170 100644 --- a/src/drivers/i2c/w83795/w83795.c +++ b/src/drivers/i2c/w83795/w83795.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/w83795/w83795.h b/src/drivers/i2c/w83795/w83795.h index 874e86eb75..f3dd1766c1 100644 --- a/src/drivers/i2c/w83795/w83795.h +++ b/src/drivers/i2c/w83795/w83795.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/i2c/ww_ring/ww_ring.c b/src/drivers/i2c/ww_ring/ww_ring.c index 306ac4d264..9957584d28 100644 --- a/src/drivers/i2c/ww_ring/ww_ring.c +++ b/src/drivers/i2c/ww_ring/ww_ring.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Google, Inc. + * This file is part of the coreboot project. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -88,12 +88,12 @@ * the program page size. */ typedef struct { - unsigned i2c_bus; + unsigned int i2c_bus; uint8_t dev_addr; uint8_t data_buffer[LP55231_PROG_PAGE_SIZE + 1]; } TiLp55231; -static void ww_ring_init(unsigned i2c_bus); +static void ww_ring_init(unsigned int i2c_bus); /* Controller descriptors. */ static TiLp55231 lp55231s[WW_RING_NUM_LED_CONTROLLERS]; @@ -142,7 +142,7 @@ static int ledc_transfer(TiLp55231 *ledc, struct i2c_msg *segs, * bytes can be transmitted in one write transaction. */ static int ledc_write(TiLp55231 *ledc, uint8_t start_addr, - const uint8_t *data, unsigned count) + const uint8_t *data, unsigned int count) { struct i2c_msg seg; @@ -220,10 +220,10 @@ static int ledc_reset(TiLp55231 *ledc) * into sections fitting into memory pages. */ static void ledc_write_program(TiLp55231 *ledc, uint8_t load_addr, - const uint8_t *program, unsigned count) + const uint8_t *program, unsigned int count) { uint8_t page_num = load_addr / LP55231_PROG_PAGE_SIZE; - unsigned page_offs = load_addr % LP55231_PROG_PAGE_SIZE; + unsigned int page_offs = load_addr % LP55231_PROG_PAGE_SIZE; if ((load_addr + count) > LP55231_MAX_PROG_SIZE) { printk(BIOS_WARNING, @@ -233,7 +233,7 @@ static void ledc_write_program(TiLp55231 *ledc, uint8_t load_addr, } while (count) { - unsigned segment_size = LP55231_PROG_PAGE_SIZE - page_offs; + unsigned int segment_size = LP55231_PROG_PAGE_SIZE - page_offs; if (segment_size > count) segment_size = count; @@ -334,7 +334,7 @@ static int ledc_init_validate(TiLp55231 *ledc) * Find a program matching screen type, and run it on both controllers, if * found. */ -int ww_ring_display_pattern(unsigned i2c_bus, enum display_pattern pattern) +int ww_ring_display_pattern(unsigned int i2c_bus, enum display_pattern pattern) { static int initted; const WwRingStateProg *wwr_prog; @@ -379,7 +379,7 @@ int ww_ring_display_pattern(unsigned i2c_bus, enum display_pattern pattern) #define LP55231_I2C_BASE_ADDR 0x32 -static void ww_ring_init(unsigned i2c_bus) +static void ww_ring_init(unsigned int i2c_bus) { TiLp55231 *ledc; int i, count = 0; diff --git a/src/drivers/i2c/ww_ring/ww_ring.h b/src/drivers/i2c/ww_ring/ww_ring.h index 3eb1092fe2..a3c3372c1c 100644 --- a/src/drivers/i2c/ww_ring/ww_ring.h +++ b/src/drivers/i2c/ww_ring/ww_ring.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Google, Inc. + * This file is part of the coreboot project. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -30,6 +30,6 @@ enum display_pattern { * * Display pattern on the ring LEDs. */ -int ww_ring_display_pattern(unsigned i2c_bus, enum display_pattern pattern); +int ww_ring_display_pattern(unsigned int i2c_bus, enum display_pattern pattern); #endif diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.c b/src/drivers/i2c/ww_ring/ww_ring_programs.c index 0c70e10a58..e739f9851a 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.c +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Google, Inc. + * This file is part of the coreboot project. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.h b/src/drivers/i2c/ww_ring/ww_ring_programs.h index 5fb8ebf68f..02c2e9bcd8 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.h +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Google, Inc. + * This file is part of the coreboot project. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index aea6f1ff12..32a07771ee 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Sage Electronic Engineering, LLC. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index 604b9bc0a7..038694950a 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. @@ -30,7 +28,7 @@ cbfs-files-y += fsp.bin fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) fsp.bin-position := $(CONFIG_FSP_LOC) fsp.bin-type := fsp -fsp.bin-options := --xip +fsp.bin-options := --xip $(TXTIBB) endif ifeq ($(CONFIG_ENABLE_MRC_CACHE),y) diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc index 7897dd4003..346416fdda 100644 --- a/src/drivers/intel/fsp1_0/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2000,2007 Ronald G. Minnich - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_0/fastboot_cache.c b/src/drivers/intel/fsp1_0/fastboot_cache.c index 7eba875e51..cd0324a2e9 100644 --- a/src/drivers/intel/fsp1_0/fastboot_cache.c +++ b/src/drivers/intel/fsp1_0/fastboot_cache.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index a7f3017230..4b38c01ade 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h index a368c7f089..ca0e8d83d2 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ b/src/drivers/intel/fsp1_0/fsp_util.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_0/fsp_values.h b/src/drivers/intel/fsp1_0/fsp_values.h index 337e751fb7..a16a887760 100644 --- a/src/drivers/intel/fsp1_0/fsp_values.h +++ b/src/drivers/intel/fsp1_0/fsp_values.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_0/hob.c b/src/drivers/intel/fsp1_0/hob.c index 0244d1c821..9b4c0a44f7 100644 --- a/src/drivers/intel/fsp1_0/hob.c +++ b/src/drivers/intel/fsp1_0/hob.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index a8658ec7e6..1d229520b8 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -1,9 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014 Sage Electronic Engineering, LLC. -## Copyright (C) 2018 Eltan B.V. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 1372e98565..85c4e0e608 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -1,9 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# Copyright (C) 2015 Intel Corp. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. @@ -20,7 +17,6 @@ verstage-y += car.c verstage-y += fsp_util.c verstage-$(CONFIG_SEPARATE_VERSTAGE) += verstage.c -bootblock-y += bootblock.c bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S bootblock-y += fsp_util.c @@ -52,7 +48,7 @@ ifeq ($(CONFIG_HAVE_FSP_BIN),y) cbfs-files-y += fsp.bin fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) fsp.bin-type := fsp -fsp.bin-options := --xip +fsp.bin-options := --xip $(TXTIBB) fsp.bin-COREBOOT-position := $(CONFIG_FSP_LOC) endif diff --git a/src/drivers/intel/fsp1_1/bootblock.c b/src/drivers/intel/fsp1_1/bootblock.c deleted file mode 100644 index ce367f774f..0000000000 --- a/src/drivers/intel/fsp1_1/bootblock.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corporation. - * Copryight (C) 2018 Eltan B.V. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -static void fill_temp_ram_init_params(FSP_TEMP_RAM_INIT_PARAMS *params) -{ - params->MicrocodeRegionBase = CONFIG_CPU_MICROCODE_CBFS_LOC; - params->MicrocodeRegionLength = CONFIG_CPU_MICROCODE_CBFS_LEN; - params->CodeRegionBase = 0xFFFFFFFF - CONFIG_ROM_SIZE + 1; - params->CodeRegionLength = CONFIG_ROM_SIZE; -} - -void bootblock_fsp_temp_ram_init(void) -{ - FSP_TEMP_RAM_INIT fsp_temp_ram_init; - FSP_TEMP_RAM_INIT_PARAMS temp_ram_init_params; - FSP_INFO_HEADER *fih; - EFI_STATUS status; - - /* Locate the FSP header */ - fih = find_fsp(CONFIG_FSP_LOC); - /* Check the FSP header */ - if (((uintptr_t)fih >= ERROR_NO_FV_SIG) && - ((uintptr_t)fih <= ERROR_FSP_REV_MISMATCH)) { - printk(BIOS_ERR, "FSP header error %p, ", fih); - fih = NULL; - } - if (fih == NULL) - die("FSP_INFO_HEADER not set!\n"); - - fill_temp_ram_init_params(&temp_ram_init_params); - - /* Perform Temp RAM Init */ - printk(BIOS_DEBUG, "Calling FspTempRamInit\n"); - post_code(POST_FSP_TEMP_RAM_INIT); - fsp_temp_ram_init = (FSP_TEMP_RAM_INIT)(fih->ImageBase - + fih->TempRamInitEntryOffset); - status = fsp_temp_ram_init(&temp_ram_init_params); - printk(BIOS_DEBUG, "FspTempRamInit returned 0x%08x\n", status); - if (status != FSP_SUCCESS) - die("FspTempRamInit failed. Giving up."); - -} diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 3460b9da34..ffafe9b4f3 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -1,12 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2000,2007 Ronald G. Minnich - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018-2019 Eltan B.V. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 8957c99219..2039c9c799 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c index 0e22ee5bb6..eb641516b4 100644 --- a/src/drivers/intel/fsp1_1/fsp_gop.c +++ b/src/drivers/intel/fsp1_1/fsp_gop.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/fsp_relocate.c b/src/drivers/intel/fsp1_1/fsp_relocate.c index 398520d2cc..b78ecad216 100644 --- a/src/drivers/intel/fsp1_1/fsp_relocate.c +++ b/src/drivers/intel/fsp1_1/fsp_relocate.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index ab9f28f93f..2889f3f6fc 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2015 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index 0a123cff78..d6878e3780 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2015 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/include/fsp/api.h b/src/drivers/intel/fsp1_1/include/fsp/api.h index 103b4064b8..96fb0d07d9 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/api.h +++ b/src/drivers/intel/fsp1_1/include/fsp/api.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index 3d99fa6dc9..84f2fd841c 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h index 13769b3b2d..1c9210b464 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 2caceebfa0..ac8247c845 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation - * Copyright (C) 2018 Eltan B.V. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h index ab1270da6c..a4563f448f 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/include/fsp/stack.h b/src/drivers/intel/fsp1_1/include/fsp/stack.h index e60360d490..dc4834d106 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/stack.h +++ b/src/drivers/intel/fsp1_1/include/fsp/stack.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc - * Copyright (C) 2015 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h b/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h index 2352d0ad78..b13b99832c 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h +++ b/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index 45b8eda243..dca6d560a4 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2015 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/mma_core.c b/src/drivers/intel/fsp1_1/mma_core.c index c0d100bbd3..d62893d344 100644 --- a/src/drivers/intel/fsp1_1/mma_core.c +++ b/src/drivers/intel/fsp1_1/mma_core.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 7b893d269e..59a60cfb83 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014-2016 Intel Corporation - * Copyright (C) 2018-2019 Eltan B.V. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 57068cf2e9..d278d08ed2 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 67bea32eff..d441ca7008 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. - * Copyright (C) 2018 Eltan B.V. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/temp_ram_exit.c b/src/drivers/intel/fsp1_1/temp_ram_exit.c index c1535e0bc0..eff157bc0e 100644 --- a/src/drivers/intel/fsp1_1/temp_ram_exit.c +++ b/src/drivers/intel/fsp1_1/temp_ram_exit.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/fsp1_1/vbt.c b/src/drivers/intel/fsp1_1/vbt.c index 51d0f59324..c84adc50b8 100644 --- a/src/drivers/intel/fsp1_1/vbt.c +++ b/src/drivers/intel/fsp1_1/vbt.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp1_1/verstage.c b/src/drivers/intel/fsp1_1/verstage.c index d7cdfdf248..78866a19f7 100644 --- a/src/drivers/intel/fsp1_1/verstage.c +++ b/src/drivers/intel/fsp1_1/verstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 1e84dabbbe..765d6435f7 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2018 Intel Corp. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index b0a1f2b4e2..8e69377789 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2016 Intel Corp. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. @@ -50,14 +48,14 @@ cbfs-files-$(CONFIG_FSP_CAR) += $(CONFIG_FSP_T_CBFS) $(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE)) $(CONFIG_FSP_T_CBFS)-type := fsp ifeq ($(CONFIG_FSP_T_XIP),y) -$(CONFIG_FSP_T_CBFS)-options := --xip +$(CONFIG_FSP_T_CBFS)-options := --xip $(TXTIBB) endif cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS) $(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE)) $(CONFIG_FSP_M_CBFS)-type := fsp ifeq ($(CONFIG_FSP_M_XIP),y) -$(CONFIG_FSP_M_CBFS)-options := --xip +$(CONFIG_FSP_M_CBFS)-options := --xip $(TXTIBB) endif cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_S_CBFS) diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index a2a9345474..44ad735be2 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -1,12 +1,15 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index 55dc6dfddc..be7afdb084 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -1,15 +1,18 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2016 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ +#include #include #include #include diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 3539d18f73..65ceb2058c 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -1,13 +1,15 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2018 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include @@ -187,9 +189,10 @@ int fsp_find_range_hob(struct range_entry *re, const uint8_t guid[16]) return 0; } -int fsp_find_reserved_memory(struct range_entry *re) +void fsp_find_reserved_memory(struct range_entry *re) { - return fsp_find_range_hob(re, fsp_reserved_memory_guid); + if (fsp_find_range_hob(re, fsp_reserved_memory_guid)) + die("9.1: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); } const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size) diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c index 15bba78282..926b2ae540 100644 --- a/src/drivers/intel/fsp2_0/header_display.c +++ b/src/drivers/intel/fsp2_0/header_display.c @@ -1,14 +1,15 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) - * (Written by Andrey Petrov for Intel Corp.) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include diff --git a/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch b/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch index fc95f63a9f..dd8f05f935 100644 --- a/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch +++ b/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch @@ -1,11 +1,6 @@ /* - * Semantic patch for fspupdvpd_sanitize.sh. Please call the script directly. - * * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -17,6 +12,8 @@ * GNU General Public License for more details. */ +/* Semantic patch for fspupdvpd_sanitize.sh. Please call the script directly. */ + @ kill_pragma_pack @ @@ - #pragma pack(...) diff --git a/src/drivers/intel/fsp2_0/header_util/fspupdvpd_sanitize.sh b/src/drivers/intel/fsp2_0/header_util/fspupdvpd_sanitize.sh index 2b500539b7..728703a73b 100755 --- a/src/drivers/intel/fsp2_0/header_util/fspupdvpd_sanitize.sh +++ b/src/drivers/intel/fsp2_0/header_util/fspupdvpd_sanitize.sh @@ -1,13 +1,5 @@ -# -# Convert the FspUpdVpd.h header file into a format usable by coreboot -# Usage: -# fspupdvpd_sanitize.sh -# # This file is part of the coreboot project. # -# Copyright (C) 2015-2016 Intel Corp. -# (Written by Alexandru Gagniuc for Intel Corp.) -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or @@ -18,6 +10,12 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. +# +# Convert the FspUpdVpd.h header file into a format usable by coreboot +# Usage: +# fspupdvpd_sanitize.sh +# + PWD=$(dirname "${BASH_SOURCE[0]}") SPATCH=spatch diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c index 10c2f1290b..c4f04aed42 100644 --- a/src/drivers/intel/fsp2_0/hob_display.c +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -1,12 +1,15 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index 317b2c9173..e2937d7f7a 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -1,21 +1,25 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include #include #include -int fsp_find_bootloader_tolum(struct range_entry *re) +void fsp_find_bootloader_tolum(struct range_entry *re) { - return fsp_find_range_hob(re, fsp_bootloader_tolum_guid); + if (fsp_find_range_hob(re, fsp_bootloader_tolum_guid)) + die("9.3: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); } void fsp_verify_memory_init_hobs(void) @@ -23,9 +27,8 @@ void fsp_verify_memory_init_hobs(void) struct range_entry fsp_mem; struct range_entry tolum; - /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ - if (fsp_find_bootloader_tolum(&tolum)) - die("9.3: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); + /* Verify the size of the TOLUM range */ + fsp_find_bootloader_tolum(&tolum); if (range_entry_size(&tolum) < cbmem_overhead_size()) { printk(BIOS_CRIT, "FSP_BOOTLOADER_TOLUM_SIZE: 0x%08llx < 0x%08zx\n", @@ -33,11 +36,8 @@ void fsp_verify_memory_init_hobs(void) die("FSP_BOOTLOADER_TOLUM_HOB too small!\n"); } - /* Locate the FSP reserved memory area */ - if (fsp_find_reserved_memory(&fsp_mem)) - die("9.1: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); - /* Verify the bootloader tolum is above the FSP reserved area */ + fsp_find_reserved_memory(&fsp_mem); if (range_entry_end(&tolum) <= range_entry_base(&fsp_mem)) { printk(BIOS_CRIT, "TOLUM end: 0x%08llx != 0x%08llx: FSP rsvd base\n", diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index b905b6908b..b63cd046de 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -1,13 +1,15 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef _FSP2_0_API_H_ diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index ef7131e1c2..fa859556b6 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -1,12 +1,15 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef _FSP2_0_DEBUG_H_ @@ -56,7 +59,6 @@ void fsp_print_resource_descriptor(const void *base); const char *fsp_get_hob_type_name(const struct hob_header *hob); const char *fsp_get_guid_name(const uint8_t *guid); void fsp_print_guid_extension_hob(const struct hob_header *hob); -int fsp_find_bootloader_tolum(struct range_entry *re); /* * Writes number_of_bytes data bytes from buffer to the console. diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 3e86b29c8d..d9ca73fd7a 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -1,13 +1,15 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef _FSP2_0_INFO_HEADER_H_ diff --git a/src/drivers/intel/fsp2_0/include/fsp/memory_init.h b/src/drivers/intel/fsp2_0/include/fsp/memory_init.h index 05ea440275..b2ad0cbfa3 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/memory_init.h +++ b/src/drivers/intel/fsp2_0/include/fsp/memory_init.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Facebook Inc - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h b/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h index 8ad5660d59..4b0579bad0 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h +++ b/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h index c7fad95aed..931e427188 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h index 19c542307e..46a930d2f8 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/upd.h +++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h @@ -1,12 +1,15 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef _FSP2_0_UPD_H_ diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index ef7ecd163f..303bafe458 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -1,13 +1,15 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2018 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef _FSP2_0_UTIL_H_ @@ -77,11 +79,13 @@ const void *fsp_find_nv_storage_data(size_t *size); enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); int fsp_find_range_hob(struct range_entry *re, const uint8_t guid[16]); void fsp_display_fvi_version_hob(void); -int fsp_find_reserved_memory(struct range_entry *re); +void fsp_find_reserved_memory(struct range_entry *re); const struct hob_resource *fsp_hob_header_to_resource( const struct hob_header *hob); const struct hob_header *fsp_next_hob(const struct hob_header *parent); bool fsp_guid_compare(const uint8_t guid1[16], const uint8_t guid2[16]); +void fsp_find_bootloader_tolum(struct range_entry *re); + /* Fill in header and validate sanity of component within region device. */ enum cb_err fsp_validate_component(struct fsp_header *hdr, diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index a075f01879..455dfa5029 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -1,14 +1,15 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corp. - * (Written by Andrey Petrov for Intel Corp.) - * (Written by Alexandru Gagniuc for Intel Corp.) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include @@ -73,8 +74,7 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) { struct range_entry fsp_mem; - if (fsp_find_reserved_memory(&fsp_mem)) - die("Failed to find FSP_RESERVED_MEMORY_RESOURCE_HOB!\n"); + fsp_find_reserved_memory(&fsp_mem); /* initialize cbmem by adding FSP reserved memory first thing */ if (!s3wake) { @@ -390,7 +390,7 @@ void fsp_memory_init(bool s3wake) struct region_device file_data; const char *name = CONFIG_FSP_M_CBFS; struct memranges memmap; - struct range_entry freeranges[2]; + struct range_entry prog_ranges[2]; elog_boot_notify(s3wake); @@ -402,9 +402,10 @@ void fsp_memory_init(bool s3wake) cbfs_file_data(&file_data, &file_desc); /* Build up memory map of romstage address space including CAR. */ - memranges_init_empty(&memmap, &freeranges[0], ARRAY_SIZE(freeranges)); - memranges_insert(&memmap, (uintptr_t)_car_region_start, - _car_unallocated_start - _car_region_start, 0); + memranges_init_empty(&memmap, &prog_ranges[0], ARRAY_SIZE(prog_ranges)); + if (ENV_CACHE_AS_RAM) + memranges_insert(&memmap, (uintptr_t)_car_region_start, + _car_unallocated_start - _car_region_start, 0); memranges_insert(&memmap, (uintptr_t)_program, REGION_SIZE(program), 0); if (!CONFIG(FSP_M_XIP)) diff --git a/src/drivers/intel/fsp2_0/mma_core.c b/src/drivers/intel/fsp2_0/mma_core.c index dfb1a1f108..b5590a6bc4 100644 --- a/src/drivers/intel/fsp2_0/mma_core.c +++ b/src/drivers/intel/fsp2_0/mma_core.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 34d7e89c7b..dea3de5313 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -1,13 +1,15 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corp. - * (Written by Andrey Petrov for Intel Corp.) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include diff --git a/src/drivers/intel/fsp2_0/ppi/Kconfig b/src/drivers/intel/fsp2_0/ppi/Kconfig index a95877e830..a344fee5ac 100644 --- a/src/drivers/intel/fsp2_0/ppi/Kconfig +++ b/src/drivers/intel/fsp2_0/ppi/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2019 Intel Corp. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp2_0/ppi/Makefile.inc b/src/drivers/intel/fsp2_0/ppi/Makefile.inc index 67c4966dc7..a7154c8d4e 100644 --- a/src/drivers/intel/fsp2_0/ppi/Makefile.inc +++ b/src/drivers/intel/fsp2_0/ppi/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2019 Intel Corp. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index e26701b099..7699ebcd24 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -14,7 +12,6 @@ */ #include -#include #include #include #include diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index ecc6e96ace..f58851d8c0 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -1,13 +1,15 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corp. - * (Written by Andrey Petrov for Intel Corp.) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include @@ -70,15 +72,12 @@ static void do_silicon_init(struct fsp_header *hdr) /* Handle any errors returned by FspSiliconInit */ fsp_handle_reset(status); if (status != FSP_SUCCESS) { - if (vbt_get()) { - /* Attempted to initialize graphics. Assume failure - * is related to a video failure. - */ + /* Assume video failure if attempted to initialize graphics */ + if (CONFIG(RUN_FSP_GOP) && vbt_get()) postcode = POST_VIDEO_FAILURE; - } else { - /* Other silicon initialization failed */ - postcode = POST_HW_INIT_FAILURE; - } + else + postcode = POST_HW_INIT_FAILURE; /* else generic */ + printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); die_with_post_code(postcode, "FspSiliconInit returned an error!\n"); diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index 342fc357fa..1dfe1ba7b7 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -1,12 +1,15 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include diff --git a/src/drivers/intel/fsp2_0/upd_display.c b/src/drivers/intel/fsp2_0/upd_display.c index 363ee361b4..defedab376 100644 --- a/src/drivers/intel/fsp2_0/upd_display.c +++ b/src/drivers/intel/fsp2_0/upd_display.c @@ -1,12 +1,15 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index f670e6facd..5239f9be94 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -1,14 +1,15 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corp. - * (Written by Alexandru Gagniuc for Intel Corp.) - * (Written by Andrey Petrov for Intel Corp.) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 75d268723b..207135139c 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -1,9 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2013 Google Inc. -## Copyright 2016-2017 secunet Security Networks AG -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index cea319e976..2945d0021c 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/gma/acpi.c b/src/drivers/intel/gma/acpi.c index 65117aa730..3f71a5ea84 100644 --- a/src/drivers/intel/gma/acpi.c +++ b/src/drivers/intel/gma/acpi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/gma/acpi/common.asl b/src/drivers/intel/gma/acpi/common.asl index 009e3a54cd..3932a88e87 100644 --- a/src/drivers/intel/gma/acpi/common.asl +++ b/src/drivers/intel/gma/acpi/common.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl index 23637b0612..3ec74119f1 100644 --- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl +++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Nico Huber - * Copyright (C) 2018 Nico Huber - * Copyright (C) 2018 Patrick Rudolph - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/gma/acpi/non-pch.asl b/src/drivers/intel/gma/acpi/non-pch.asl index c35d251c0f..4a4aad9962 100644 --- a/src/drivers/intel/gma/acpi/non-pch.asl +++ b/src/drivers/intel/gma/acpi/non-pch.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/drivers/intel/gma/acpi/pch.asl b/src/drivers/intel/gma/acpi/pch.asl index b7bb324b60..6ec5fbb220 100644 --- a/src/drivers/intel/gma/acpi/pch.asl +++ b/src/drivers/intel/gma/acpi/pch.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 6c464ee332..4d4aec3a6e 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Sebastian Grzywna - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2, or (at your option) @@ -30,7 +27,7 @@ static void wait_rdy(u8 *mmio) { - unsigned try = 100; + unsigned int try = 100; while (try--) { if (read32(GMBUS2_ADDR) & GMBUS_HW_RDY) diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index 0ddb2dea85..e02a230854 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2012 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/gma/int15.c b/src/drivers/intel/gma/int15.c index 80949d1bf8..7e0ece3382 100644 --- a/src/drivers/intel/gma/int15.c +++ b/src/drivers/intel/gma/int15.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index 9e9bd9727c..563f01bee6 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 2e200ff828..56449d0a11 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2, or (at your option) diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h index 87ae5a3d76..496769134b 100644 --- a/src/drivers/intel/gma/opregion.h +++ b/src/drivers/intel/gma/opregion.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * (Written by Abhay Kumar for Intel Corp.) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c index fa50ae9921..603044a4c8 100644 --- a/src/drivers/intel/gma/vbt.c +++ b/src/drivers/intel/gma/vbt.c @@ -1,13 +1,10 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013, 2014 Vladimir Serbinenko - * Copyright (C) 2017 secunet Security Networks AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 or (at your option) - * any later version of the License. + * any later version of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of diff --git a/src/drivers/intel/i210/Makefile.inc b/src/drivers/intel/i210/Makefile.inc index 13ed127ca5..336288a4fe 100644 --- a/src/drivers/intel/i210/Makefile.inc +++ b/src/drivers/intel/i210/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Siemens AG -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c index 32d27f7912..232a826b4c 100644 --- a/src/drivers/intel/i210/i210.c +++ b/src/drivers/intel/i210/i210.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014-2017 Siemens AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/i210/i210.h b/src/drivers/intel/i210/i210.h index e3179b7e1a..f4a8faf5fc 100644 --- a/src/drivers/intel/i210/i210.h +++ b/src/drivers/intel/i210/i210.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Siemens AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/ish/chip.h b/src/drivers/intel/ish/chip.h index ae3fb35b8d..69926f09f0 100644 --- a/src/drivers/intel/ish/chip.h +++ b/src/drivers/intel/ish/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index f506a7c4de..e9d5ae96b1 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index 903c48062a..0cada814e9 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index 741ae8e1a1..167c71aa0d 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/ptt/ptt.h b/src/drivers/intel/ptt/ptt.h index ed5e90f599..e0a901fccf 100644 --- a/src/drivers/intel/ptt/ptt.h +++ b/src/drivers/intel/ptt/ptt.h @@ -9,7 +9,9 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + */ + +/* * This driver checks if the PTT Bit is set correctly within the FWSTS4 * register. This is needed in order to use the iTPM, because we have to * check prior using the interface that this bit is set correctly - otherwise diff --git a/src/drivers/intel/wifi/chip.h b/src/drivers/intel/wifi/chip.h index 21803108ca..ed25d8f9d1 100644 --- a/src/drivers/intel/wifi/chip.h +++ b/src/drivers/intel/wifi/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Intel Corporation - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index 926905c26b..e5efbe15fb 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2018 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 or (at your option) @@ -15,7 +12,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/drivers/ipmi/Makefile.inc b/src/drivers/ipmi/Makefile.inc index a29c2e2d0e..9d5b3d418f 100644 --- a/src/drivers/ipmi/Makefile.inc +++ b/src/drivers/ipmi/Makefile.inc @@ -1,2 +1,3 @@ ramstage-$(CONFIG_IPMI_KCS) += ipmi_kcs.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_kcs_ops.c +ramstage-$(CONFIG_IPMI_KCS) += ipmi_ops.c diff --git a/src/drivers/ipmi/chip.h b/src/drivers/ipmi/chip.h index 1c5afe7b59..b3bb5a5d8a 100644 --- a/src/drivers/ipmi/chip.h +++ b/src/drivers/ipmi/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/ipmi/ipmi_kcs.c b/src/drivers/ipmi/ipmi_kcs.c index 4d1e3e105b..d3916198a6 100644 --- a/src/drivers/ipmi/ipmi_kcs.c +++ b/src/drivers/ipmi/ipmi_kcs.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Sven Schnelle - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/drivers/ipmi/ipmi_kcs.h b/src/drivers/ipmi/ipmi_kcs.h index a194dd22e9..f35802e27b 100644 --- a/src/drivers/ipmi/ipmi_kcs.h +++ b/src/drivers/ipmi/ipmi_kcs.h @@ -1,10 +1,6 @@ -#ifndef __IPMI_KCS_H -#define __IPMI_KCS_H /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Sven Schnelle - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of @@ -16,6 +12,9 @@ * GNU General Public License for more details. */ +#ifndef __IPMI_KCS_H +#define __IPMI_KCS_H + #define IPMI_NETFN_CHASSIS 0x00 #define IPMI_NETFN_BRIDGE 0x02 #define IPMI_NETFN_SENSOREVENT 0x04 diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index baa72a82c5..90f19dddb8 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 9elements Agency GmbH - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of @@ -12,7 +10,9 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + */ + +/* * Place in devicetree.cb: * * chip drivers/ipmi diff --git a/src/drivers/ipmi/ipmi_ops.c b/src/drivers/ipmi/ipmi_ops.c new file mode 100644 index 0000000000..784daeb1fb --- /dev/null +++ b/src/drivers/ipmi/ipmi_ops.c @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Wiwynn Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "ipmi_ops.h" + +enum cb_err ipmi_init_and_start_bmc_wdt(const int port, uint16_t countdown, + uint8_t action) +{ + int ret; + struct ipmi_wdt_req req = {0}; + struct ipmi_rsp rsp; + printk(BIOS_INFO, "Initializing IPMI BMC watchdog timer\n"); + /* BIOS FRB2 */ + req.timer_use = 1; + req.timer_actions = action; + /* clear BIOS FRB2 expiration flag */ + req.timer_use_expiration_flags_clr = 2; + req.initial_countdown_val = countdown; + ret = ipmi_kcs_message(port, IPMI_NETFN_APPLICATION, 0x0, + IPMI_BMC_SET_WDG_TIMER, + (const unsigned char *) &req, sizeof(req), + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s set wdt command failed " + "(ret=%d resp=0x%x), failed to initialize and start " + "IPMI BMC watchdog timer\n", __func__, + ret, rsp.completion_code); + return CB_ERR; + } + + /* Reset command to start timer */ + ret = ipmi_kcs_message(port, IPMI_NETFN_APPLICATION, 0x0, + IPMI_BMC_RESET_WDG_TIMER, NULL, 0, + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s reset wdt command failed " + "(ret=%d resp=0x%x), failed to initialize and start " + "IPMI BMC watchdog timer\n", __func__, + ret, rsp.completion_code); + return CB_ERR; + } + + printk(BIOS_INFO, "IPMI BMC watchdog initialized and started.\n"); + return CB_SUCCESS; +} + +enum cb_err ipmi_stop_bmc_wdt(const int port) +{ + int ret; + struct ipmi_wdt_req req; + struct ipmi_wdt_rsp rsp = {0}; + struct ipmi_rsp resp; + + /* Get current timer first */ + ret = ipmi_kcs_message(port, IPMI_NETFN_APPLICATION, 0x0, + IPMI_BMC_GET_WDG_TIMER, NULL, 0, + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s get wdt command failed " + "(ret=%d resp=0x%x), IPMI BMC watchdog timer may still " + "be running\n", __func__, ret, + rsp.resp.completion_code); + return CB_ERR; + } + /* If bit 6 in timer_use is 0 then it's already stopped. */ + if (!(rsp.data.timer_use & (1 << 6))) { + printk(BIOS_DEBUG, "IPMI BMC watchdog is already stopped\n"); + return CB_SUCCESS; + } + /* Set timer stop running by clearing bit 6. */ + rsp.data.timer_use &= ~(1 << 6); + rsp.data.initial_countdown_val = 0; + req = rsp.data; + ret = ipmi_kcs_message(port, IPMI_NETFN_APPLICATION, 0x0, + IPMI_BMC_SET_WDG_TIMER, + (const unsigned char *) &req, sizeof(req), + (unsigned char *) &resp, sizeof(resp)); + + if (ret < sizeof(struct ipmi_rsp) || resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s set wdt command stop timer failed " + "(ret=%d resp=0x%x), failed to stop IPMI " + "BMC watchdog timer\n", __func__, ret, + resp.completion_code); + return CB_ERR; + } + printk(BIOS_DEBUG, "IPMI BMC watchdog is stopped\n"); + + return CB_SUCCESS; +} diff --git a/src/drivers/ipmi/ipmi_ops.h b/src/drivers/ipmi/ipmi_ops.h new file mode 100644 index 0000000000..f293075e90 --- /dev/null +++ b/src/drivers/ipmi/ipmi_ops.h @@ -0,0 +1,57 @@ +#ifndef __IPMI_OPS_H +#define __IPMI_OPS_H +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Wiwynn Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "ipmi_kcs.h" +#define IPMI_BMC_RESET_WDG_TIMER 0x22 +#define IPMI_BMC_SET_WDG_TIMER 0x24 +#define IPMI_BMC_GET_WDG_TIMER 0x25 + +/* BMC watchdog timeout action */ +enum ipmi_bmc_timeout_action_type { + TIMEOUT_NO_ACTION = 0x00, + TIMEOUT_HARD_RESET = 0x01, + TIMEOUT_POWER_DOWN = 0x02, + TIMEOUT_POWER_CYCLE = 0x03, +}; +/* BMC Watchdog timer */ +struct ipmi_wdt_req { + uint8_t timer_use; + uint8_t timer_actions; + uint8_t pretimeout_interval; + uint8_t timer_use_expiration_flags_clr; + uint16_t initial_countdown_val; +} __packed; + +struct ipmi_wdt_rsp { + struct ipmi_rsp resp; + struct ipmi_wdt_req data; + uint16_t present_countdown_val; +} __packed; + +/* + * Initialize and start BMC FRB2 watchdog timer with the + * provided timer countdown and action values. + * Returns CB_SUCCESS on success and CB_ERR if an error occurred + */ +enum cb_err ipmi_init_and_start_bmc_wdt(const int port, uint16_t countdown, + uint8_t action); +/* Returns CB_SUCCESS on success and CB_ERR if an error occurred */ +enum cb_err ipmi_stop_bmc_wdt(const int port); + +#endif diff --git a/src/drivers/lenovo/hybrid_graphics/chip.h b/src/drivers/lenovo/hybrid_graphics/chip.h index 96d7f9c1a9..6926e6f626 100644 --- a/src/drivers/lenovo/hybrid_graphics/chip.h +++ b/src/drivers/lenovo/hybrid_graphics/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c index b6d22415f5..6cc7a79d30 100644 --- a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h index b238440caa..11085d1913 100644 --- a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h +++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/lenovo/hybrid_graphics/romstage.c b/src/drivers/lenovo/hybrid_graphics/romstage.c index 35cb384301..6a44000e49 100644 --- a/src/drivers/lenovo/hybrid_graphics/romstage.c +++ b/src/drivers/lenovo/hybrid_graphics/romstage.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Patrick Rudolph - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/lenovo/lenovo.h b/src/drivers/lenovo/lenovo.h index 4c441198b7..cf8c71f13f 100644 --- a/src/drivers/lenovo/lenovo.h +++ b/src/drivers/lenovo/lenovo.h @@ -1,3 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + int drivers_lenovo_is_wacom_present(void); void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, int have_dock_serial); diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index 9dcbf15d93..442089814c 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2, or (at your diff --git a/src/drivers/maxim/max77686/Kconfig b/src/drivers/maxim/max77686/Kconfig index 71708508ab..5517b61a63 100644 --- a/src/drivers/maxim/max77686/Kconfig +++ b/src/drivers/maxim/max77686/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 The ChromiumOS Authors -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/maxim/max77686/Makefile.inc b/src/drivers/maxim/max77686/Makefile.inc index fae5f2635f..b857955433 100644 --- a/src/drivers/maxim/max77686/Makefile.inc +++ b/src/drivers/maxim/max77686/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 The ChromiumOS Authors -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/maxim/max77686/max77686.c b/src/drivers/maxim/max77686/max77686.c index 7519082abd..54e3a6c912 100644 --- a/src/drivers/maxim/max77686/max77686.c +++ b/src/drivers/maxim/max77686/max77686.c @@ -1,6 +1,5 @@ /* - * Copyright (C) 2012 Samsung Electronics - * Alim Akhtar + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/drivers/maxim/max77686/max77686.h b/src/drivers/maxim/max77686/max77686.h index 63cdf6930a..a5f46b3bf8 100644 --- a/src/drivers/maxim/max77686/max77686.h +++ b/src/drivers/maxim/max77686/max77686.h @@ -1,6 +1,5 @@ /* - * Copyright (C) 2012 Samsung Electronics - * Alim Akhtar + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/drivers/maxim/max77802/max77802.h b/src/drivers/maxim/max77802/max77802.h index 1284a1d98a..a19d85f197 100644 --- a/src/drivers/maxim/max77802/max77802.h +++ b/src/drivers/maxim/max77802/max77802.h @@ -1,6 +1,5 @@ /* - * Copyright (C) 2012 Samsung Electronics - * Rajeshwari Shinde + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 582c5c64cf..ca0f447523 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c index 097b768b12..51470b0a78 100644 --- a/src/drivers/net/atl1e.c +++ b/src/drivers/net/atl1e.c @@ -1,11 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Atheros Corporation. All rights reserved. - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2016 Damien Zammit - * Copyright (C) 2018 Arthur Heymans - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/net/chip.h b/src/drivers/net/chip.h index 985a85aac8..430bc334a5 100644 --- a/src/drivers/net/chip.h +++ b/src/drivers/net/chip.h @@ -18,7 +18,7 @@ struct drivers_net_config { uint16_t customized_leds; - unsigned wake; /* Wake pin for ACPI _PRW */ + unsigned int wake; /* Wake pin for ACPI _PRW */ /* * There maybe many NIC cards in a system. * This parameter is for driver to identify what diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index c7b53e4e7b..35d45ea624 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -31,7 +31,6 @@ SMC8416 PIO support added by Andrew Bettison (andrewb@zip.com.au) on 4/3/02 #include #include #include -#include #include #include #include diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 3188778900..bc0132fc13 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2016 Damien Zammit - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/parade/ps8625/Kconfig b/src/drivers/parade/ps8625/Kconfig index f39e380f30..f8235e5b60 100644 --- a/src/drivers/parade/ps8625/Kconfig +++ b/src/drivers/parade/ps8625/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/parade/ps8625/Makefile.inc b/src/drivers/parade/ps8625/Makefile.inc index 650de11611..9be29f3ca8 100644 --- a/src/drivers/parade/ps8625/Makefile.inc +++ b/src/drivers/parade/ps8625/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Google Inc. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/parade/ps8625/ps8625.c b/src/drivers/parade/ps8625/ps8625.c index 3e90cbb3e4..c86c4d4100 100644 --- a/src/drivers/parade/ps8625/ps8625.c +++ b/src/drivers/parade/ps8625/ps8625.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -19,7 +17,7 @@ #include "ps8625.h" -void parade_ps8625_bridge_setup(unsigned bus, unsigned chip_base, +void parade_ps8625_bridge_setup(unsigned int bus, unsigned int chip_base, const struct parade_write *parade_writes, int parade_write_count) { diff --git a/src/drivers/parade/ps8625/ps8625.h b/src/drivers/parade/ps8625/ps8625.h index a5132f1244..7eb8b98df2 100644 --- a/src/drivers/parade/ps8625/ps8625.h +++ b/src/drivers/parade/ps8625/ps8625.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -24,7 +22,7 @@ struct parade_write { uint8_t val; }; -void parade_ps8625_bridge_setup(unsigned bus, unsigned chip_base, +void parade_ps8625_bridge_setup(unsigned int bus, unsigned int chip_base, const struct parade_write *, int parade_write_count); diff --git a/src/drivers/parade/ps8640/Kconfig b/src/drivers/parade/ps8640/Kconfig index f0d71bbf25..bb0206a680 100644 --- a/src/drivers/parade/ps8640/Kconfig +++ b/src/drivers/parade/ps8640/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2015 MediaTek Inc. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/parade/ps8640/Makefile.inc b/src/drivers/parade/ps8640/Makefile.inc index 9bfe1e7068..1ca394b4f8 100644 --- a/src/drivers/parade/ps8640/Makefile.inc +++ b/src/drivers/parade/ps8640/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2015 MediaTek Inc. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/parade/ps8640/ps8640.c b/src/drivers/parade/ps8640/ps8640.c index c8f414002a..88688ee7ad 100644 --- a/src/drivers/parade/ps8640/ps8640.c +++ b/src/drivers/parade/ps8640/ps8640.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/parade/ps8640/ps8640.h b/src/drivers/parade/ps8640/ps8640.h index 4540122420..6fdd46641f 100644 --- a/src/drivers/parade/ps8640/ps8640.h +++ b/src/drivers/parade/ps8640/ps8640.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc index 8c348e323e..bd56cd43a1 100644 --- a/src/drivers/pc80/pc/Makefile.inc +++ b/src/drivers/pc80/pc/Makefile.inc @@ -1,7 +1,6 @@ ifeq ($(CONFIG_ARCH_X86),y) ramstage-y += isa-dma.c -ramstage-y += i8254.c ramstage-y += i8259.c ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c romstage-$(CONFIG_UDELAY_IO) += udelay_io.c @@ -9,4 +8,11 @@ ramstage-y += keyboard.c ramstage-$(CONFIG_SPKMODEM) += spkmodem.c romstage-$(CONFIG_SPKMODEM) += spkmodem.c +bootblock-y += i8254.c +verstage-y += i8254.c +romstage-y += i8254.c +ramstage-y += i8254.c +postcar-y += i8254.c +smm-y += i8254.c + endif diff --git a/src/drivers/pc80/pc/i8254.c b/src/drivers/pc80/pc/i8254.c index 4b81d58e46..654f84a6d7 100644 --- a/src/drivers/pc80/pc/i8254.c +++ b/src/drivers/pc80/pc/i8254.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,7 +11,10 @@ * GNU General Public License for more details. */ +#include #include +#include +#include #include /* Initialize i8254 timers */ @@ -48,3 +49,99 @@ void udelay(int usecs) ; } #endif + +#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */ + +/* ------ Calibrate the TSC ------- + * Too much 64-bit arithmetic here to do this cleanly in C, and for + * accuracy's sake we want to keep the overhead on the CTC speaker (channel 2) + * output busy loop as low as possible. We avoid reading the CTC registers + * directly because of the awkward 8-bit access mechanism of the 82C54 + * device. + */ + +#define CALIBRATE_INTERVAL ((2*CLOCK_TICK_RATE)/1000) /* 2ms */ +#define CALIBRATE_DIVISOR (2*1000) /* 2ms / 2000 == 1usec */ + +unsigned long calibrate_tsc_with_pit(void) +{ + /* Set the Gate high, disable speaker */ + outb((inb(0x61) & ~0x02) | 0x01, 0x61); + + /* + * Now let's take care of CTC channel 2 + * + * Set the Gate high, program CTC channel 2 for mode 0, + * (interrupt on terminal count mode), binary count, + * load 5 * LATCH count, (LSB and MSB) to begin countdown. + */ + outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */ + + outb(CALIBRATE_INTERVAL & 0xff, 0x42); /* LSB of count */ + outb(CALIBRATE_INTERVAL >> 8, 0x42); /* MSB of count */ + + { + tsc_t start; + tsc_t end; + unsigned long count; + + start = rdtsc(); + count = 0; + do { + count++; + } while ((inb(0x61) & 0x20) == 0); + end = rdtsc(); + + /* Error: ECTCNEVERSET */ + if (count <= 1) + goto bad_ctc; + + /* 64-bit subtract - gcc just messes up with long longs */ + __asm__("subl %2,%0\n\t" + "sbbl %3,%1" + : "=a" (end.lo), "=d" (end.hi) + : "g" (start.lo), "g" (start.hi), + "0" (end.lo), "1" (end.hi)); + + /* Error: ECPUTOOFAST */ + if (end.hi) + goto bad_ctc; + + + /* Error: ECPUTOOSLOW */ + if (end.lo <= CALIBRATE_DIVISOR) + goto bad_ctc; + + return DIV_ROUND_UP(end.lo, CALIBRATE_DIVISOR); + } + + /* + * The CTC wasn't reliable: we got a hit on the very first read, + * or the CPU was so fast/slow that the quotient wouldn't fit in + * 32 bits.. + */ +bad_ctc: + return 0; +} + +#if CONFIG(UNKNOWN_TSC_RATE) +static u32 g_timer_tsc CAR_GLOBAL; + +unsigned long tsc_freq_mhz(void) +{ + u32 tsc; + + tsc = car_get_var(g_timer_tsc); + if (tsc > 0) + return tsc; + + tsc = calibrate_tsc_with_pit(); + + /* Set some semi-ridiculous rate if approximation fails. */ + if (tsc == 0) + tsc = 5000; + + car_set_var(g_timer_tsc, tsc); + return tsc; +} +#endif diff --git a/src/drivers/pc80/pc/i8259.c b/src/drivers/pc80/pc/i8259.c index 4261d5bec4..b96f1d02f4 100644 --- a/src/drivers/pc80/pc/i8259.c +++ b/src/drivers/pc80/pc/i8259.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/pc80/pc/isa-dma.c b/src/drivers/pc80/pc/isa-dma.c index b64f125f3a..c7290e0341 100644 --- a/src/drivers/pc80/pc/isa-dma.c +++ b/src/drivers/pc80/pc/isa-dma.c @@ -1,3 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include #include diff --git a/src/drivers/pc80/pc/keyboard.c b/src/drivers/pc80/pc/keyboard.c index bfd05c19d1..cf40e65531 100644 --- a/src/drivers/pc80/pc/keyboard.c +++ b/src/drivers/pc80/pc/keyboard.c @@ -1,11 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Raptor Engineering - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2003 Ollie Lo - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/pc80/pc/ps2_controller.asl b/src/drivers/pc80/pc/ps2_controller.asl index a4984cfdb9..3c0c70d49c 100644 --- a/src/drivers/pc80/pc/ps2_controller.asl +++ b/src/drivers/pc80/pc/ps2_controller.asl @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2013 Vladimir Serbinenko - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/drivers/pc80/pc/spkmodem.c b/src/drivers/pc80/pc/spkmodem.c index c1b8fc8bf9..d7db44c475 100644 --- a/src/drivers/pc80/pc/spkmodem.c +++ b/src/drivers/pc80/pc/spkmodem.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Vladimir Serbinenko - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or diff --git a/src/drivers/pc80/pc/udelay_io.c b/src/drivers/pc80/pc/udelay_io.c index 3305e4c3a3..4fe1caeed9 100644 --- a/src/drivers/pc80/pc/udelay_io.c +++ b/src/drivers/pc80/pc/udelay_io.c @@ -1,3 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include #include @@ -5,7 +18,7 @@ void init_timer(void) { } -void udelay(unsigned usecs) +void udelay(unsigned int usecs) { int i; diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 9ea5414f2d..6edffe0cd0 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2018-2019 Eltan B.V. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -22,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -245,7 +240,7 @@ static enum cb_err get_cmos_value(unsigned long bit, unsigned long length, static enum cb_err locate_cmos_layout(struct region_device *rdev) { uint32_t cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT; - struct cbfsf fh; + MAYBE_STATIC_BSS struct cbfsf fh = {}; /* * In case VBOOT is enabled and this function is called from SMM, @@ -254,11 +249,13 @@ static enum cb_err locate_cmos_layout(struct region_device *rdev) * * Support only one CMOS layout in the 'COREBOOT' region for now. */ - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "cmos_layout.bin", - &cbfs_type)) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " + if (!region_device_sz(&(fh.data))) { + if (cbfs_locate_file_in_region(&fh, "COREBOOT", "cmos_layout.bin", + &cbfs_type)) { + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " "Options are disabled\n"); - return CB_CMOS_LAYOUT_NOT_FOUND; + return CB_CMOS_LAYOUT_NOT_FOUND; + } } cbfs_file_data(rdev, &fh); diff --git a/src/drivers/pc80/rtc/mc146818rtc_romcc.c b/src/drivers/pc80/rtc/mc146818rtc_romcc.c index eb8bf0022a..4405443501 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_romcc.c +++ b/src/drivers/pc80/rtc/mc146818rtc_romcc.c @@ -1,3 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include #include #include @@ -61,10 +74,10 @@ static inline __attribute__((unused)) int do_normal_boot(void) return boot_use_normal(byte); } -unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def) +unsigned int read_option_lowlevel(unsigned int start, unsigned int size, unsigned int def) { #if CONFIG(USE_OPTION_TABLE) - unsigned byte; + unsigned int byte; byte = cmos_read(start/8); return (byte >> (start & 7U)) & ((1U << size) - 1U); diff --git a/src/drivers/pc80/tpm/chip.h b/src/drivers/pc80/tpm/chip.h index b13d23c85e..e79ba16f33 100644 --- a/src/drivers/pc80/tpm/chip.h +++ b/src/drivers/pc80/tpm/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. All Rights Reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 23de003b47..5927377d15 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2018 Eltan B.V. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -468,7 +465,7 @@ static u32 tis_senddata(const u8 *const data, u32 len) burst = tpm_read_burst_count(locality); while (1) { - unsigned count; + unsigned int count; /* Wait till the device is ready to accept more data. */ while (!burst) { diff --git a/src/drivers/pc80/vga/vga.c b/src/drivers/pc80/vga/vga.c index 6e225e9786..6d0b674833 100644 --- a/src/drivers/pc80/vga/vga.c +++ b/src/drivers/pc80/vga/vga.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007-2009 Luc Verhaegen + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free diff --git a/src/drivers/pc80/vga/vga.h b/src/drivers/pc80/vga/vga.h index a6fb2b4886..a1c566204c 100644 --- a/src/drivers/pc80/vga/vga.h +++ b/src/drivers/pc80/vga/vga.h @@ -1,3 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #ifndef _VGA_H #define _VGA_H diff --git a/src/drivers/pc80/vga/vga_font_8x16.c b/src/drivers/pc80/vga/vga_font_8x16.c index 3b0d288d66..b267c4a59f 100644 --- a/src/drivers/pc80/vga/vga_font_8x16.c +++ b/src/drivers/pc80/vga/vga_font_8x16.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007-2009 Luc Verhaegen + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free diff --git a/src/drivers/pc80/vga/vga_io.c b/src/drivers/pc80/vga/vga_io.c index 455b0d331e..842419e0fd 100644 --- a/src/drivers/pc80/vga/vga_io.c +++ b/src/drivers/pc80/vga/vga_io.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007-2009 Luc Verhaegen + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free diff --git a/src/drivers/pc80/vga/vga_palette.c b/src/drivers/pc80/vga/vga_palette.c index 2189361f58..748a7c9159 100644 --- a/src/drivers/pc80/vga/vga_palette.c +++ b/src/drivers/pc80/vga/vga_palette.c @@ -1,15 +1,15 @@ /* - * Copyright (C) 2007-2009 Luc Verhaegen + * This file is part of the coreboot project. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include "vga.h" diff --git a/src/drivers/ricoh/rce822/chip.h b/src/drivers/ricoh/rce822/chip.h index 832a3d31e5..d7f8a67c64 100644 --- a/src/drivers/ricoh/rce822/chip.h +++ b/src/drivers/ricoh/rce822/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/drivers/ricoh/rce822/rce822.c b/src/drivers/ricoh/rce822/rce822.c index 72862f5174..fd425824c0 100644 --- a/src/drivers/ricoh/rce822/rce822.c +++ b/src/drivers/ricoh/rce822/rce822.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Vladimir Serbinenko - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of @@ -71,3 +69,7 @@ static const struct pci_driver rce822 __pci_driver = { .vendor = PCI_VENDOR_ID_RICOH, .devices = pci_device_ids, }; + +struct chip_operations drivers_ricoh_rce822_ops = { + CHIP_NAME("RICOH RCE822") +}; diff --git a/src/drivers/siemens/nc_fpga/Makefile.inc b/src/drivers/siemens/nc_fpga/Makefile.inc index 5c3aabc398..572884dc74 100644 --- a/src/drivers/siemens/nc_fpga/Makefile.inc +++ b/src/drivers/siemens/nc_fpga/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2016 Siemens AG -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.c b/src/drivers/siemens/nc_fpga/nc_fpga.c index fb681adb2d..355e0f90a8 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.c +++ b/src/drivers/siemens/nc_fpga/nc_fpga.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Siemens AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.h b/src/drivers/siemens/nc_fpga/nc_fpga.h index f1982d2e38..2cfe1ce243 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.h +++ b/src/drivers/siemens/nc_fpga/nc_fpga.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016-2017 Siemens AG - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/sil/3114/sil_sata.c b/src/drivers/sil/3114/sil_sata.c index dd6481a204..5fc58c8a35 100644 --- a/src/drivers/sil/3114/sil_sata.c +++ b/src/drivers/sil/3114/sil_sata.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003-2004 Tyan Computer - Yinghai Lu - * Copyright (C) 2010 Rudolf Marek - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/smmstore/Kconfig b/src/drivers/smmstore/Kconfig index e59e78decc..668f876164 100644 --- a/src/drivers/smmstore/Kconfig +++ b/src/drivers/smmstore/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 The Chromium OS Authors. All rights reserved. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/smmstore/smi.c b/src/drivers/smmstore/smi.c index 3bcf564e1a..93acbcb675 100644 --- a/src/drivers/smmstore/smi.c +++ b/src/drivers/smmstore/smi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 The Chromium OS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index ad3eeff614..f7e744a25f 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 The Chromium OS Authors. All rights reserved. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -20,6 +18,8 @@ #include #include #include +#include +#include /* * The region format is still not finalized, but so far it looks like this: diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index b15a502cfd..8b9c25ee98 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 The Chromium OS Authors. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/spi/acpi/Kconfig b/src/drivers/spi/acpi/Kconfig index c1653d55e4..ca255da18a 100644 --- a/src/drivers/spi/acpi/Kconfig +++ b/src/drivers/spi/acpi/Kconfig @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright 2017 Google Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/spi/acpi/Makefile.inc b/src/drivers/spi/acpi/Makefile.inc index 7ae6e459d9..154d52e800 100644 --- a/src/drivers/spi/acpi/Makefile.inc +++ b/src/drivers/spi/acpi/Makefile.inc @@ -1,8 +1,6 @@ # # This file is part of the coreboot project. # -# Copyright 2017 Google Inc. -# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index 7c8a887242..7e107d6f67 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/spi/acpi/chip.h b/src/drivers/spi/acpi/chip.h index fa7d8a15d2..57c1a5cad1 100644 --- a/src/drivers/spi/acpi/chip.h +++ b/src/drivers/spi/acpi/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -23,11 +21,11 @@ struct drivers_spi_acpi_config { const char *cid; /* ACPI _CID */ const char *name; /* ACPI Device Name */ const char *desc; /* Device Description */ - unsigned uid; /* ACPI _UID */ - unsigned speed; /* Bus speed in Hz (default 1MHz) */ + unsigned int uid; /* ACPI _UID */ + unsigned int speed; /* Bus speed in Hz (default 1MHz) */ const char *compat_string; /* Compatible string for _HID=PRP0001 */ struct acpi_irq irq; /* Interrupt */ - unsigned wake; /* Wake GPE */ + unsigned int wake; /* Wake GPE */ /* Use GPIO based interrupt instead of PIRQ */ struct acpi_gpio irq_gpio; diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index c74fd701c9..695bdab2ea 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -1,13 +1,20 @@ /* - * adesto.c - * Driver for Adesto Technologies SPI flash - * Copyright 2014 Orion Technologies, LLC - * Author: Chris Douglass oriontechnologies.com> + * This file is part of the coreboot project. * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Driver for Adesto Technologies SPI flash * based on winbond.c - * Copyright 2008, Network Appliance Inc. - * Author: Jason McMullan netapp.com> - * Licensed under the GPL-2 or later. */ #include diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index 6e1234baa7..4943779a1a 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -1,11 +1,15 @@ /* - * Copyright (C) 2014 Idwer Vollering + * This file is part of the coreboot project. * - * Based on winbond.c + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. * - * Copyright 2008, Network Appliance Inc. - * Author: Jason McMullan netapp.com> - * Licensed under the GPL-2 or later. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index ac7f0d92e7..8f88880ad6 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -1,9 +1,15 @@ /* - * Copyright 2008, Network Appliance Inc. - * Copyright 2014, Sage Electronic Engineering, LLC. + * This file is part of the coreboot project. * - * Author: Jason McMullan netapp.com> - * Licensed under the GPL-2 or later. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include diff --git a/src/drivers/spi/bitbang.c b/src/drivers/spi/bitbang.c index d858345859..d0caa04816 100644 --- a/src/drivers/spi/bitbang.c +++ b/src/drivers/spi/bitbang.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/spi/boot_device_rw_nommap.c b/src/drivers/spi/boot_device_rw_nommap.c index cc8fbf7c5d..47683144a8 100644 --- a/src/drivers/spi/boot_device_rw_nommap.c +++ b/src/drivers/spi/boot_device_rw_nommap.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/spi/cbfs_spi.c b/src/drivers/spi/cbfs_spi.c index ad282c695b..fca61004ff 100644 --- a/src/drivers/spi/cbfs_spi.c +++ b/src/drivers/spi/cbfs_spi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index c6fdba17b8..5b527d1211 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -1,9 +1,15 @@ /* - * (C) Copyright 2010, ucRobotics Inc. - * Copyright (c) 2014, Sage Electronic Engineering, LLC - * . - * Author: Chong Huang - * Licensed under the GPL-2 or later. + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c index 3109012bd4..8874812449 100644 --- a/src/drivers/spi/flashconsole.c +++ b/src/drivers/spi/flashconsole.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -19,6 +17,8 @@ #include #include #include +#include +#include #define LINE_BUFFER_SIZE 128 #define READ_BUFFER_SIZE 0x100 diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 71433cc1ed..05a73df77c 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -1,10 +1,5 @@ /* - * Copyright (c) 2012, Google Inc. - * - * Based on drivers/spi/winbond.c - * - * Copyright 2008, Network Appliance Inc. - * Jason McMullan + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index a41e96f671..25784b4dc3 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -1,14 +1,5 @@ /* - * Copyright 2009(C) Marvell International Ltd. and its affiliates - * Prafulla Wadaskar - * - * Based on drivers/mtd/spi/stmicro.c - * - * Copyright 2008, Network Appliance Inc. - * Jason McMullan - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index c3a071e956..cee93b2ac6 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -1,10 +1,5 @@ /* - * Copyright (C) 2009 Freescale Semiconductor, Inc. - * - * Author: Mingkai Hu (Mingkai.hu@freescale.com) - * Based on stmicro.c by Wolfgang Denk (wd@denx.de), - * TsiChung Liew (Tsi-Chung.Liew@freescale.com), - * and Jason McMullan (mcmullan@netapp.com) + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 84a42d1c9c..05bfb82bf8 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -16,6 +14,8 @@ #include #include +#include +#include #include int spi_claim_bus(const struct spi_slave *slave) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 5dbe1f4d8e..7b5266a280 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -1,22 +1,28 @@ /* - * SPI flash interface + * This file is part of the coreboot project. * - * Copyright (C) 2008 Atmel Corporation - * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * - * Licensed under the GPL-2 or later. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include #include #include +#include #include #include -#include #include #include #include #include +#include #include "spi_flash_internal.h" @@ -100,8 +106,8 @@ int spi_flash_cmd(const struct spi_slave *spi, u8 cmd, void *response, size_t le #pragma GCC diagnostic push #if defined(__GNUC__) && !defined(__clang__) #pragma GCC diagnostic ignored "-Wstack-usage=" -#pragma GCC diagnostic ignored "-Wvla" #endif +#pragma GCC diagnostic ignored "-Wvla" int spi_flash_cmd_write(const struct spi_slave *spi, const u8 *cmd, size_t cmd_len, const void *data, size_t data_len) { diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index 95c51a8b05..36fa66d67c 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -1,7 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + /* * SPI flash internal definitions - * - * Copyright (C) 2008 Atmel Corporation */ #ifndef SPI_FLASH_INTERNAL_H diff --git a/src/drivers/spi/spi_winbond.h b/src/drivers/spi/spi_winbond.h index e21571c56c..73029527ee 100644 --- a/src/drivers/spi/spi_winbond.h +++ b/src/drivers/spi/spi_winbond.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2008, Network Appliance Inc. - * Author: Jason McMullan netapp.com> - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/spi/spiconsole.c b/src/drivers/spi/spiconsole.c index ef9902475e..fffeafaaea 100644 --- a/src/drivers/spi/spiconsole.c +++ b/src/drivers/spi/spiconsole.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 429afa095d..348d06c3e8 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -1,15 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + /* * Driver for SST serial flashes - * - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Copyright 2008, Network Appliance Inc. - * Jason McMullan - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * Copyright (c) 2008-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. */ #include diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 98f6e4e5b2..ddff859d38 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -1,12 +1,5 @@ /* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright 2008, Network Appliance Inc. - * Jason McMullan - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index aad7610313..270b15b471 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -103,7 +103,7 @@ static int tpm_sync(void) * * Returns 1 on success, 0 on failure (TPM SPI flow control timeout.) */ -static int start_transaction(int read_write, size_t bytes, unsigned addr) +static int start_transaction(int read_write, size_t bytes, unsigned int addr) { spi_frame_header header; uint8_t byte; @@ -291,7 +291,7 @@ static void read_bytes(void *buffer, size_t bytes) * * Returns one to indicate success, zero to indicate failure. */ -static int tpm2_write_reg(unsigned reg_number, const void *buffer, size_t bytes) +static int tpm2_write_reg(unsigned int reg_number, const void *buffer, size_t bytes) { struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); trace_dump("W", reg_number, bytes, buffer, 0); @@ -309,7 +309,7 @@ static int tpm2_write_reg(unsigned reg_number, const void *buffer, size_t bytes) * Returns one to indicate success, zero to indicate failure. In case of * failure zero out the user buffer. */ -static int tpm2_read_reg(unsigned reg_number, void *buffer, size_t bytes) +static int tpm2_read_reg(unsigned int reg_number, void *buffer, size_t bytes) { struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); if (!start_transaction(true, bytes, reg_number)) { diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 3e0a2669d9..00a7bf90cd 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -1,6 +1,5 @@ /* - * Copyright 2008, Network Appliance Inc. - * Jason McMullan + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/drivers/ti/tps65090/Kconfig b/src/drivers/ti/tps65090/Kconfig index 76ebff01b3..06819d4035 100644 --- a/src/drivers/ti/tps65090/Kconfig +++ b/src/drivers/ti/tps65090/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 The ChromiumOS Authors -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/ti/tps65090/Makefile.inc b/src/drivers/ti/tps65090/Makefile.inc index 5a5ea3f66c..bfd7dddf24 100644 --- a/src/drivers/ti/tps65090/Makefile.inc +++ b/src/drivers/ti/tps65090/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 The ChromiumOS Authors -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/ti/tps65913/Kconfig b/src/drivers/ti/tps65913/Kconfig index 5da17931b1..6d2b58a48f 100644 --- a/src/drivers/ti/tps65913/Kconfig +++ b/src/drivers/ti/tps65913/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/ti/tps65913/Makefile.inc b/src/drivers/ti/tps65913/Makefile.inc index f46f7445ce..55c605a24a 100644 --- a/src/drivers/ti/tps65913/Makefile.inc +++ b/src/drivers/ti/tps65913/Makefile.inc @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2014 Google Inc. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/ti/tps65913/tps65913rtc.c b/src/drivers/ti/tps65913/tps65913rtc.c index b25fe3590f..47f08c5ec3 100644 --- a/src/drivers/ti/tps65913/tps65913rtc.c +++ b/src/drivers/ti/tps65913/tps65913rtc.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c index 4d8b0a35a4..b6546667a9 100644 --- a/src/drivers/tpm/tpm.c +++ b/src/drivers/tpm/tpm.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Facebook Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c index 2f40c3f863..999c6baec9 100644 --- a/src/drivers/uart/oxpcie.c +++ b/src/drivers/uart/oxpcie.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -16,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index eb6f8804a0..f6b4040807 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -17,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index ad00d7c3bd..d2c7c4b597 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google, Inc. - * Copyright 2018-present Facebook, Inc. - * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. diff --git a/src/drivers/uart/sifive.c b/src/drivers/uart/sifive.c index ca8b73b59d..b527ecca9d 100644 --- a/src/drivers/uart/sifive.c +++ b/src/drivers/uart/sifive.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Jonathan Neuschäfer - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 614a849f7a..58e014170a 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -32,30 +29,30 @@ #define SINGLE_CHAR_TIMEOUT (50 * 1000) #define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) -static int uart8250_can_tx_byte(unsigned base_port) +static int uart8250_can_tx_byte(unsigned int base_port) { return inb(base_port + UART8250_LSR) & UART8250_LSR_THRE; } -static void uart8250_tx_byte(unsigned base_port, unsigned char data) +static void uart8250_tx_byte(unsigned int base_port, unsigned char data) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while (i-- && !uart8250_can_tx_byte(base_port)); outb(data, base_port + UART8250_TBR); } -static void uart8250_tx_flush(unsigned base_port) +static void uart8250_tx_flush(unsigned int base_port) { unsigned long int i = FIFO_TIMEOUT; while (i-- && !(inb(base_port + UART8250_LSR) & UART8250_LSR_TEMT)); } -static int uart8250_can_rx_byte(unsigned base_port) +static int uart8250_can_rx_byte(unsigned int base_port) { return inb(base_port + UART8250_LSR) & UART8250_LSR_DR; } -static unsigned char uart8250_rx_byte(unsigned base_port) +static unsigned char uart8250_rx_byte(unsigned int base_port) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while (i && !uart8250_can_rx_byte(base_port)) @@ -67,7 +64,7 @@ static unsigned char uart8250_rx_byte(unsigned base_port) return 0x0; } -static void uart8250_init(unsigned base_port, unsigned divisor) +static void uart8250_init(unsigned int base_port, unsigned int divisor) { DISABLE_TRACE; /* Disable interrupts */ @@ -90,7 +87,7 @@ static void uart8250_init(unsigned base_port, unsigned divisor) ENABLE_TRACE; } -static const unsigned bases[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; +static const unsigned int bases[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; uintptr_t uart_platform_base(int idx) { diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index a5aa74a332..c519b4d53e 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -91,7 +88,7 @@ static unsigned char uart8250_mem_rx_byte(void *base) return 0x0; } -static void uart8250_mem_init(void *base, unsigned divisor) +static void uart8250_mem_init(void *base, unsigned int divisor) { /* Disable interrupts */ uart8250_write(base, UART8250_IER, 0x0); diff --git a/src/drivers/uart/uart8250reg.h b/src/drivers/uart/uart8250reg.h index ef41bf5b37..865611d4ae 100644 --- a/src/drivers/uart/uart8250reg.h +++ b/src/drivers/uart/uart8250reg.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2003 Eric Biederman - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/usb/Makefile.inc b/src/drivers/usb/Makefile.inc index c8d319bbdc..fa995c33cc 100644 --- a/src/drivers/usb/Makefile.inc +++ b/src/drivers/usb/Makefile.inc @@ -1,4 +1,5 @@ bootblock-$(CONFIG_USBDEBUG) += ehci_debug.c pci_ehci.c console.c gadget.c +verstage-$(CONFIG_USBDEBUG) += ehci_debug.c console.c romstage-$(CONFIG_USBDEBUG) += ehci_debug.c pci_ehci.c console.c gadget.c postcar-$(CONFIG_USBDEBUG) += ehci_debug.c console.c diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 512893d207..bce73c6755 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index 31a7a7f30b..a312c88b69 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -85,7 +83,7 @@ static struct device_operations usb_acpi_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .scan_bus = scan_usb_bus, + .scan_bus = scan_static_bus, .acpi_fill_ssdt_generator = usb_acpi_fill_ssdt_generator, }; diff --git a/src/drivers/usb/console.c b/src/drivers/usb/console.c index 7b25dee55f..090c9312b7 100644 --- a/src/drivers/usb/console.c +++ b/src/drivers/usb/console.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2006 Eric Biederman (ebiederm@xmission.com) - * Copyright (C) 2007 AMD - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/usb/ehci.h b/src/drivers/usb/ehci.h index e86286a3e3..efda0a22b5 100644 --- a/src/drivers/usb/ehci.h +++ b/src/drivers/usb/ehci.h @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * It was taken from the Linux kernel (include/linux/usb/ehci_def.h). - * - * Copyright (C) 2001-2002 David Brownell - * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -16,6 +12,8 @@ * for more details. */ + /* This came from the Linux kernel (include/linux/usb/ehci_def.h). */ + #ifndef EHCI_H #define EHCI_H diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 059679590f..ff237265eb 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2006 Eric Biederman (ebiederm@xmission.com) - * Copyright (C) 2007 AMD - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -112,7 +109,7 @@ static void dbgp_breath(void) } static int dbgp_wait_until_done(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe, - unsigned ctrl, const int timeout) + unsigned int ctrl, const int timeout) { u32 rd_ctrl, rd_pids; u32 ctrl_prev = 0, pids_prev = 0; @@ -315,7 +312,7 @@ void dbgp_mdelay(int ms) } } -int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requesttype, +int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned int devnum, int requesttype, int request, int value, int index, void *data, int size) { struct ehci_debug_info *info = dbgp_ehci_info(); @@ -438,7 +435,7 @@ static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port) -static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info) +static int usbdebug_init_(unsigned int ehci_bar, unsigned int offset, struct ehci_debug_info *info) { struct ehci_caps *ehci_caps; struct ehci_regs *ehci_regs; @@ -657,7 +654,7 @@ void dbgp_put(struct dbgp_pipe *pipe) } #if ENV_RAMSTAGE -void usbdebug_re_enable(unsigned ehci_base) +void usbdebug_re_enable(unsigned int ehci_base) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); u64 diff; diff --git a/src/drivers/usb/ehci_debug.h b/src/drivers/usb/ehci_debug.h index 0ac94bfe6f..0f20c2f5fb 100644 --- a/src/drivers/usb/ehci_debug.h +++ b/src/drivers/usb/ehci_debug.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -19,13 +16,13 @@ #include -void usbdebug_re_enable(unsigned ehci_base); +void usbdebug_re_enable(unsigned int ehci_base); void usbdebug_disable(void); /* Returns 0 on success and sets MMIO base and dbg_offset if EHCI debug * capability was found and enabled. Returns non-zero on error. */ -int ehci_debug_hw_enable(unsigned *base, unsigned *dbg_offset); +int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset); void ehci_debug_select_port(unsigned int port); #define DBGP_EP_VALID (1<<0) @@ -63,7 +60,7 @@ int dbgp_ep_is_active(struct dbgp_pipe *pipe); int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size); int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size); -int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, +int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned int devnum, int requesttype, int request, int value, int index, void *data, int size); void dbgp_mdelay(int ms); diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index 1e755249b1..a740d50dbf 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2006 Eric Biederman (ebiederm@xmission.com) - * Copyright (C) 2007 AMD - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/usb/usb_ch9.h b/src/drivers/usb/usb_ch9.h index 79f165461b..34f7a6077e 100644 --- a/src/drivers/usb/usb_ch9.h +++ b/src/drivers/usb/usb_ch9.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/vpd/Kconfig b/src/drivers/vpd/Kconfig index 21e9eaf5f1..ad3bd727fb 100644 --- a/src/drivers/vpd/Kconfig +++ b/src/drivers/vpd/Kconfig @@ -1,8 +1,6 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 The Chromium OS Authors. All rights reserved. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/vpd/vpd.h b/src/drivers/vpd/vpd.h index 14b002c8f6..244a7be6d7 100644 --- a/src/drivers/vpd/vpd.h +++ b/src/drivers/vpd/vpd.h @@ -7,6 +7,8 @@ #ifndef __VPD_H__ #define __VPD_H__ +#include + #define GOOGLE_VPD_2_0_OFFSET 0x600 enum vpd_region { diff --git a/src/drivers/vpd/vpd_premem.c b/src/drivers/vpd/vpd_premem.c index 14e803281a..7117288cc8 100644 --- a/src/drivers/vpd/vpd_premem.c +++ b/src/drivers/vpd/vpd_premem.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2019 Facebook, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,7 +11,6 @@ * GNU General Public License for more details. */ -#include #include #include "vpd.h" diff --git a/src/drivers/wifi/generic.c b/src/drivers/wifi/generic.c index fc88f4a629..9f9f4faae7 100644 --- a/src/drivers/wifi/generic.c +++ b/src/drivers/wifi/generic.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 or (at your option) diff --git a/src/drivers/wifi/generic_wifi.h b/src/drivers/wifi/generic_wifi.h index 5f17c3e297..f14051b473 100644 --- a/src/drivers/wifi/generic_wifi.h +++ b/src/drivers/wifi/generic_wifi.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/drivers/xgi/common/XGI_main.c b/src/drivers/xgi/common/XGI_main.c index b0b92d9d9f..d4650998fc 100644 --- a/src/drivers/xgi/common/XGI_main.c +++ b/src/drivers/xgi/common/XGI_main.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Code taken from the Linux xgifb driver (v3.18.5) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -14,6 +12,7 @@ */ /* + * Code taken from the Linux xgifb driver (v3.18.5) * Select functions taken from the Linux xgifb driver file XGI_main_26.c * * Original file header: diff --git a/src/drivers/xgi/common/XGI_main.h b/src/drivers/xgi/common/XGI_main.h index 08c0010719..cb758ee082 100644 --- a/src/drivers/xgi/common/XGI_main.h +++ b/src/drivers/xgi/common/XGI_main.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * File taken from the Linux xgifb driver (v3.18.5) - * coreboot-specific includes added at top - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -14,6 +11,8 @@ * GNU General Public License for more details. */ +/* File taken from the Linux xgifb driver (v3.18.5) */ + #ifndef _XGIFB_MAIN #define _XGIFB_MAIN diff --git a/src/drivers/xgi/common/XGIfb.h b/src/drivers/xgi/common/XGIfb.h index e3b998a3d6..a528dae4b9 100644 --- a/src/drivers/xgi/common/XGIfb.h +++ b/src/drivers/xgi/common/XGIfb.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * File taken verbatim from the Linux xgifb driver (v3.18.5) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,6 +11,8 @@ * GNU General Public License for more details. */ +/* File taken from the Linux xgifb driver (v3.18.5) */ + #ifndef _LINUX_XGIFB #define _LINUX_XGIFB #include "vgatypes.h" diff --git a/src/drivers/xgi/common/vb_def.h b/src/drivers/xgi/common/vb_def.h index c07a8c90c2..4a98d5d714 100644 --- a/src/drivers/xgi/common/vb_def.h +++ b/src/drivers/xgi/common/vb_def.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * File taken verbatim from the Linux xgifb driver (v3.18.5) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,6 +11,8 @@ * GNU General Public License for more details. */ +/* File taken from the Linux xgifb driver (v3.18.5) */ + #ifndef _VB_DEF_ #define _VB_DEF_ diff --git a/src/drivers/xgi/common/vb_init.c b/src/drivers/xgi/common/vb_init.c index b9191abe3d..ab27439b9b 100644 --- a/src/drivers/xgi/common/vb_init.c +++ b/src/drivers/xgi/common/vb_init.c @@ -1,12 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * File taken from the Linux xgifb driver (v3.18.5) - * coreboot-specific includes added at top - * XGINew_SetDRAMSize_340 slightly modified for coreboot text mode - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -17,6 +11,7 @@ * GNU General Public License for more details. */ +/* File taken from the Linux xgifb driver (v3.18.5) */ /* coreboot related includes come indirectly from xgi_coreboot.h */ #include "xgi_coreboot.h" diff --git a/src/drivers/xgi/common/vb_init.h b/src/drivers/xgi/common/vb_init.h index 17bcb96387..8d2e2be019 100644 --- a/src/drivers/xgi/common/vb_init.h +++ b/src/drivers/xgi/common/vb_init.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * File taken verbatim from the Linux xgifb driver (v3.18.5) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,6 +11,8 @@ * GNU General Public License for more details. */ +/* File taken from the Linux xgifb driver (v3.18.5) */ + #ifndef _VBINIT_ #define _VBINIT_ extern unsigned char XGIInitNew(struct pci_dev *pdev); diff --git a/src/drivers/xgi/common/vb_setmode.c b/src/drivers/xgi/common/vb_setmode.c index 64412566a1..fdb7039013 100644 --- a/src/drivers/xgi/common/vb_setmode.c +++ b/src/drivers/xgi/common/vb_setmode.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * File taken from the Linux xgifb driver (v3.18.5) - * coreboot-specific includes added at top - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -14,7 +11,7 @@ * GNU General Public License for more details. */ -/* coreboot related includes come indirectly from xgi_coreboot.h */ +/* File taken from the Linux xgifb driver (v3.18.5) */ #include "xgi_coreboot.h" #include "vstruct.h" diff --git a/src/drivers/xgi/common/vb_setmode.h b/src/drivers/xgi/common/vb_setmode.h index 00b3f29839..140b3b61d7 100644 --- a/src/drivers/xgi/common/vb_setmode.h +++ b/src/drivers/xgi/common/vb_setmode.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * File taken verbatim from the Linux xgifb driver (v3.18.5) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,6 +11,8 @@ * GNU General Public License for more details. */ +/* File taken from the Linux xgifb driver (v3.18.5) */ + #ifndef _VBSETMODE_ #define _VBSETMODE_ diff --git a/src/drivers/xgi/common/vb_struct.h b/src/drivers/xgi/common/vb_struct.h index f1fe5c8c99..705a1aed59 100644 --- a/src/drivers/xgi/common/vb_struct.h +++ b/src/drivers/xgi/common/vb_struct.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * File taken verbatim from the Linux xgifb driver (v3.18.5) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,6 +11,8 @@ * GNU General Public License for more details. */ +/* File taken from the Linux xgifb driver (v3.18.5) */ + #ifndef _VB_STRUCT_ #define _VB_STRUCT_ diff --git a/src/drivers/xgi/common/vb_table.h b/src/drivers/xgi/common/vb_table.h index 4d26976c92..c4d1df06b1 100644 --- a/src/drivers/xgi/common/vb_table.h +++ b/src/drivers/xgi/common/vb_table.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * File taken verbatim from the Linux xgifb driver (v3.18.5) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,6 +11,8 @@ * GNU General Public License for more details. */ +/* File taken from the Linux xgifb driver (v3.18.5) */ + #ifndef _VB_TABLE_ #define _VB_TABLE_ static const struct SiS_MCLKData XGI340New_MCLKData[] = { diff --git a/src/drivers/xgi/common/vb_util.c b/src/drivers/xgi/common/vb_util.c index 248b8af5f8..dbaaa0c907 100644 --- a/src/drivers/xgi/common/vb_util.c +++ b/src/drivers/xgi/common/vb_util.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * File taken from the Linux xgifb driver (v3.18.5) - * coreboot-specific includes added at top - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -14,7 +11,7 @@ * GNU General Public License for more details. */ -/* coreboot related includes come indirectly from xgi_coreboot.h */ +/* File taken from the Linux xgifb driver (v3.18.5) */ #include "xgi_coreboot.h" #include "vgatypes.h" @@ -36,7 +33,7 @@ u8 xgifb_reg_get(unsigned long port, u8 index) } void xgifb_reg_and_or(unsigned long port, u8 index, - unsigned data_and, unsigned data_or) + unsigned int data_and, unsigned int data_or) { u8 temp; @@ -45,7 +42,7 @@ void xgifb_reg_and_or(unsigned long port, u8 index, xgifb_reg_set(port, index, temp); } -void xgifb_reg_and(unsigned long port, u8 index, unsigned data_and) +void xgifb_reg_and(unsigned long port, u8 index, unsigned int data_and) { u8 temp; @@ -54,7 +51,7 @@ void xgifb_reg_and(unsigned long port, u8 index, unsigned data_and) xgifb_reg_set(port, index, temp); } -void xgifb_reg_or(unsigned long port, u8 index, unsigned data_or) +void xgifb_reg_or(unsigned long port, u8 index, unsigned int data_or) { u8 temp; diff --git a/src/drivers/xgi/common/vb_util.h b/src/drivers/xgi/common/vb_util.h index d5d30ed6c2..c71b0df5d8 100644 --- a/src/drivers/xgi/common/vb_util.h +++ b/src/drivers/xgi/common/vb_util.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * File taken verbatim from the Linux xgifb driver (v3.18.5) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,11 +11,13 @@ * GNU General Public License for more details. */ +/* File taken from the Linux xgifb driver (v3.18.5) */ + #ifndef _VBUTIL_ #define _VBUTIL_ extern void xgifb_reg_set(unsigned long, u8, u8); extern u8 xgifb_reg_get(unsigned long, u8); -extern void xgifb_reg_or(unsigned long, u8, unsigned); -extern void xgifb_reg_and(unsigned long, u8, unsigned); -extern void xgifb_reg_and_or(unsigned long, u8, unsigned, unsigned); +extern void xgifb_reg_or(unsigned long, u8, unsigned int); +extern void xgifb_reg_and(unsigned long, u8, unsigned int); +extern void xgifb_reg_and_or(unsigned long, u8, unsigned int, unsigned int); #endif diff --git a/src/drivers/xgi/common/vgatypes.h b/src/drivers/xgi/common/vgatypes.h index 3262daa494..db10f4d5af 100644 --- a/src/drivers/xgi/common/vgatypes.h +++ b/src/drivers/xgi/common/vgatypes.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * File taken verbatim from the Linux xgifb driver (v3.18.5) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,6 +11,8 @@ * GNU General Public License for more details. */ +/* File taken from the Linux xgifb driver (v3.18.5) */ + #ifndef _VGATYPES_ #define _VGATYPES_ diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c index 5aba472eb7..caeb59d749 100644 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ b/src/drivers/xgi/common/xgi_coreboot.c @@ -1,11 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * xgifb_probe taken from the Linux xgifb driver (v3.18.5) and adapted for coreboot - * xgifb_modeset cobbled together from other portions of the same driver - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -16,6 +11,8 @@ * GNU General Public License for more details. */ + /* Code taken from the Linux xgifb driver (v3.18.5) */ + #include #include #include diff --git a/src/drivers/xgi/common/xgi_coreboot.h b/src/drivers/xgi/common/xgi_coreboot.h index 5e593eb1c2..a850087260 100644 --- a/src/drivers/xgi/common/xgi_coreboot.h +++ b/src/drivers/xgi/common/xgi_coreboot.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -22,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/src/drivers/xgi/z9s/z9s.c b/src/drivers/xgi/z9s/z9s.c index 1925514043..62c80aa271 100644 --- a/src/drivers/xgi/z9s/z9s.c +++ b/src/drivers/xgi/z9s/z9s.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/ec/acpi/Makefile.inc b/src/ec/acpi/Makefile.inc index fae8fbf6b3..34c113b7ea 100644 --- a/src/ec/acpi/Makefile.inc +++ b/src/ec/acpi/Makefile.inc @@ -1,7 +1,9 @@ ifeq ($(CONFIG_EC_ACPI),y) -ramstage-y += ec.c +bootblock-y += ec.c +verstage-y += ec.c romstage-y += ec.c +ramstage-y += ec.c smm-y += ec.c endif diff --git a/src/ec/compal/ene932/acpi/superio.asl b/src/ec/compal/ene932/acpi/superio.asl index f152bbab57..034f6ded94 100644 --- a/src/ec/compal/ene932/acpi/superio.asl +++ b/src/ec/compal/ene932/acpi/superio.asl @@ -18,7 +18,6 @@ Device (SIO) { Name (_HID, EisaId("PNP0A05")) Name (_UID, 0) - Name (_ADR, 0) // Keyboard or AUX port (a.k.a Mouse) #ifdef SIO_EC_ENABLE_PS2K diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl index c521a3a894..9c0fa68141 100644 --- a/src/ec/google/chromeec/acpi/superio.asl +++ b/src/ec/google/chromeec/acpi/superio.asl @@ -40,7 +40,6 @@ Device (SIO) { Device (ECMM) { Name (_HID, EISAID ("PNP0C02")) Name (_UID, 4) - Name (_ADR, 0) Method (_STA, 0, NotSerialized) { Return (0x0F) @@ -64,7 +63,6 @@ Device (SIO) { Device (ECUI) { Name (_HID, EISAID ("PNP0C02")) Name (_UID, 3) - Name (_ADR, 0) Method (_STA, 0, NotSerialized) { Return (0x0F) @@ -109,7 +107,6 @@ Device (SIO) { Device (COM1) { Name (_HID, EISAID ("PNP0501")) Name (_UID, 1) - Name (_ADR, 0) Method (_STA, 0, NotSerialized) { Return (0x0F) @@ -137,7 +134,6 @@ Device (SIO) { Device (PS2K) // Keyboard { Name (_UID, 0) - Name (_ADR, 0) Name (_HID, "GOOG000A") Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } ) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 1b0f7eee03..a9921467f4 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -97,7 +97,7 @@ void log_recovery_mode_switch(void) static void google_chromeec_elog_add_recovery_event(void *unused) { uint64_t *events = cbmem_find(CBMEM_ID_EC_HOSTEVENT); - uint8_t event_byte = EC_EVENT_KEYBOARD_RECOVERY; + uint8_t event_byte = EC_HOST_EVENT_KEYBOARD_RECOVERY; if (!events) return; @@ -107,7 +107,7 @@ static void google_chromeec_elog_add_recovery_event(void *unused) if (*events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)) - event_byte = EC_EVENT_KEYBOARD_RECOVERY_HWREINIT; + event_byte = EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT; elog_add_event_byte(ELOG_TYPE_EC_EVENT, event_byte); } @@ -126,30 +126,30 @@ uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size) int google_chromeec_kbbacklight(int percent) { - struct chromeec_command cec_cmd; - struct ec_params_pwm_set_keyboard_backlight cmd_backlight; - struct ec_response_pwm_get_keyboard_backlight rsp_backlight; - /* if they were dumb, help them out */ - percent = percent % 101; - cec_cmd.cmd_code = EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT; - cec_cmd.cmd_version = 0; - cmd_backlight.percent = percent; - cec_cmd.cmd_data_in = &cmd_backlight; - cec_cmd.cmd_data_out = &rsp_backlight; - cec_cmd.cmd_size_in = sizeof(cmd_backlight); - cec_cmd.cmd_size_out = sizeof(rsp_backlight); - cec_cmd.cmd_dev_index = 0; - google_chromeec_command(&cec_cmd); - printk(BIOS_DEBUG, "Google Chrome set keyboard backlight: %x status (%x)\n", - rsp_backlight.percent, cec_cmd.cmd_code); - return cec_cmd.cmd_code; + struct ec_params_pwm_set_keyboard_backlight params = { + .percent = percent % 101, + }; + struct ec_response_pwm_get_keyboard_backlight resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT, + .cmd_version = 0, + .cmd_data_in = ¶ms, + .cmd_data_out = &resp, + .cmd_size_in = sizeof(params), + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + google_chromeec_command(&cmd); + printk(BIOS_DEBUG, "Google Chrome set keyboard backlight: %x status (%x)\n", + resp.percent, cmd.cmd_code); + return cmd.cmd_code; } -void google_chromeec_post(u8 postcode) +void google_chromeec_post(uint8_t postcode) { - /* backlight is a percent. postcode is a u8. - * Convert the u8 to %. + /* backlight is a percent. postcode is a uint8_t. + * Convert the uint8_t to %. */ postcode = (postcode/4) + (postcode/8); google_chromeec_kbbacklight(postcode); @@ -163,63 +163,65 @@ static int google_chromeec_uhepi_cmd(uint8_t mask, uint8_t action, uint64_t *value) { int ret; - struct ec_params_host_event req; - struct ec_response_host_event rsp; - struct chromeec_command cmd; + struct ec_params_host_event params = { + .action = action, + .mask_type = mask, + }; + struct ec_response_host_event resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_HOST_EVENT, + .cmd_version = 0, + .cmd_data_in = ¶ms, + .cmd_size_in = sizeof(params), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; - req.action = action; - req.mask_type = mask; if (action != EC_HOST_EVENT_GET) - req.value = *value; + params.value = *value; else *value = 0; - cmd.cmd_code = EC_CMD_HOST_EVENT; - cmd.cmd_version = 0; - cmd.cmd_data_in = &req; - cmd.cmd_size_in = sizeof(req); - cmd.cmd_data_out = &rsp; - cmd.cmd_size_out = sizeof(rsp); - cmd.cmd_dev_index = 0; ret = google_chromeec_command(&cmd); if (action != EC_HOST_EVENT_GET) return ret; if (ret == 0) - *value = rsp.value; + *value = resp.value; return ret; } static int google_chromeec_handle_non_uhepi_cmd(uint8_t hcmd, uint8_t action, - uint64_t *value) + uint64_t *value) { int ret = -1; - struct ec_params_host_event_mask req; - struct ec_response_host_event_mask rsp; - struct chromeec_command cmd; + struct ec_params_host_event_mask params = {}; + struct ec_response_host_event_mask resp = {}; + struct chromeec_command cmd = { + .cmd_code = hcmd, + .cmd_version = 0, + .cmd_data_in = ¶ms, + .cmd_size_in = sizeof(params), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; if (hcmd == INVALID_HCMD) return ret; if (action != EC_HOST_EVENT_GET) - req.mask = (uint32_t)*value; + params.mask = (uint32_t)*value; else *value = 0; - cmd.cmd_code = hcmd; - cmd.cmd_version = 0; - cmd.cmd_data_in = &req; - cmd.cmd_size_in = sizeof(req); - cmd.cmd_data_out = &rsp; - cmd.cmd_size_out = sizeof(rsp); - cmd.cmd_dev_index = 0; - ret = google_chromeec_command(&cmd); if (action != EC_HOST_EVENT_GET) return ret; if (ret == 0) - *value = rsp.mask; + *value = resp.mask; return ret; } @@ -242,9 +244,9 @@ bool google_chromeec_is_uhepi_supported(void) return uhepi_support == UHEPI_SUPPORTED; } -static uint64_t google_chromeec_get_mask(u8 type) +static uint64_t google_chromeec_get_mask(uint8_t type) { - u64 value = 0; + uint64_t value = 0; if (google_chromeec_is_uhepi_supported()) { google_chromeec_uhepi_cmd(type, EC_HOST_EVENT_GET, &value); @@ -256,7 +258,8 @@ static uint64_t google_chromeec_get_mask(u8 type) } return value; } -static int google_chromeec_clear_mask(u8 type, u64 mask) + +static int google_chromeec_clear_mask(uint8_t type, uint64_t mask) { if (google_chromeec_is_uhepi_supported()) return google_chromeec_uhepi_cmd(type, @@ -267,7 +270,8 @@ static int google_chromeec_clear_mask(u8 type, u64 mask) event_map[type].clear_cmd, EC_HOST_EVENT_CLEAR, &mask); } -static int __unused google_chromeec_set_mask(u8 type, u64 mask) + +static int __unused google_chromeec_set_mask(uint8_t type, uint64_t mask) { if (google_chromeec_is_uhepi_supported()) return google_chromeec_uhepi_cmd(type, @@ -331,15 +335,15 @@ int google_chromeec_clear_events_b(uint64_t mask) int google_chromeec_get_mkbp_event(struct ec_response_get_next_event *event) { - struct chromeec_command cmd; - - cmd.cmd_code = EC_CMD_GET_NEXT_EVENT; - cmd.cmd_version = 0; - cmd.cmd_data_in = NULL; - cmd.cmd_size_in = 0; - cmd.cmd_data_out = event; - cmd.cmd_size_out = sizeof(*event); - cmd.cmd_dev_index = 0; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_GET_NEXT_EVENT, + .cmd_version = 0, + .cmd_data_in = NULL, + .cmd_size_in = 0, + .cmd_data_out = event, + .cmd_size_out = sizeof(*event), + .cmd_dev_index = 0, + }; return google_chromeec_command(&cmd); } @@ -347,40 +351,43 @@ int google_chromeec_get_mkbp_event(struct ec_response_get_next_event *event) /* Get the current device event mask */ uint64_t google_chromeec_get_device_enabled_events(void) { - struct ec_params_device_event req; - struct ec_response_device_event rsp; - struct chromeec_command cmd; - - req.param = EC_DEVICE_EVENT_PARAM_GET_ENABLED_EVENTS; - cmd.cmd_code = EC_CMD_DEVICE_EVENT; - cmd.cmd_version = 0; - cmd.cmd_data_in = &req; - cmd.cmd_size_in = sizeof(req); - cmd.cmd_data_out = &rsp; - cmd.cmd_size_out = sizeof(rsp); - cmd.cmd_dev_index = 0; + struct ec_params_device_event params = { + .param = EC_DEVICE_EVENT_PARAM_GET_ENABLED_EVENTS, + }; + struct ec_response_device_event resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_DEVICE_EVENT, + .cmd_version = 0, + .cmd_data_in = ¶ms, + .cmd_size_in = sizeof(params), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; if (google_chromeec_command(&cmd) == 0) - return rsp.event_mask; + return resp.event_mask; + return 0; } /* Set the current device event mask */ int google_chromeec_set_device_enabled_events(uint64_t mask) { - struct ec_params_device_event req; - struct ec_response_device_event rsp; - struct chromeec_command cmd; - - req.event_mask = (uint32_t)mask; - req.param = EC_DEVICE_EVENT_PARAM_SET_ENABLED_EVENTS; - cmd.cmd_code = EC_CMD_DEVICE_EVENT; - cmd.cmd_version = 0; - cmd.cmd_data_in = &req; - cmd.cmd_size_in = sizeof(req); - cmd.cmd_data_out = &rsp; - cmd.cmd_size_out = sizeof(rsp); - cmd.cmd_dev_index = 0; + struct ec_params_device_event params = { + .event_mask = (uint32_t)mask, + .param = EC_DEVICE_EVENT_PARAM_SET_ENABLED_EVENTS, + }; + struct ec_response_device_event resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_DEVICE_EVENT, + .cmd_version = 0, + .cmd_data_in = ¶ms, + .cmd_size_in = sizeof(params), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; return google_chromeec_command(&cmd); } @@ -388,21 +395,23 @@ int google_chromeec_set_device_enabled_events(uint64_t mask) /* Read and clear pending device events */ uint64_t google_chromeec_get_device_current_events(void) { - struct ec_params_device_event req; - struct ec_response_device_event rsp; - struct chromeec_command cmd; - - req.param = EC_DEVICE_EVENT_PARAM_GET_CURRENT_EVENTS; - cmd.cmd_code = EC_CMD_DEVICE_EVENT; - cmd.cmd_version = 0; - cmd.cmd_data_in = &req; - cmd.cmd_size_in = sizeof(req); - cmd.cmd_data_out = &rsp; - cmd.cmd_size_out = sizeof(rsp); - cmd.cmd_dev_index = 0; + struct ec_params_device_event params = { + .param = EC_DEVICE_EVENT_PARAM_GET_CURRENT_EVENTS, + }; + struct ec_response_device_event resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_DEVICE_EVENT, + .cmd_version = 0, + .cmd_data_in = ¶ms, + .cmd_size_in = sizeof(params), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; if (google_chromeec_command(&cmd) == 0) - return rsp.event_mask; + return resp.event_mask; + return 0; } @@ -474,44 +483,322 @@ void google_chromeec_events_init(const struct google_chromeec_event_info *info, /* Clear wake event mask. */ google_chromeec_set_wake_mask(0); - } int google_chromeec_check_feature(int feature) { - struct chromeec_command cmd; - struct ec_response_get_features r; + struct ec_response_get_features resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_GET_FEATURES, + .cmd_version = 0, + .cmd_size_in = 0, + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; - cmd.cmd_code = EC_CMD_GET_FEATURES; + if (google_chromeec_command(&cmd) != 0) + return -1; + + if (feature >= 8 * sizeof(resp.flags)) + return -1; + + return resp.flags[feature / 32] & EC_FEATURE_MASK_0(feature); +} + +int google_chromeec_get_cmd_versions(int command, uint32_t *pmask) +{ + struct ec_params_get_cmd_versions_v1 params = { + .cmd = command, + }; + struct ec_response_get_cmd_versions resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_GET_CMD_VERSIONS, + .cmd_version = 1, + .cmd_size_in = sizeof(params), + .cmd_data_in = ¶ms, + .cmd_size_out = sizeof(resp), + .cmd_data_out = &resp, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd) != 0) + return -1; + + *pmask = resp.version_mask; + return 0; +} + +int google_chromeec_get_vboot_hash(uint32_t offset, + struct ec_response_vboot_hash *resp) +{ + struct ec_params_vboot_hash params = { + .cmd = EC_VBOOT_HASH_GET, + .offset = offset, + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_VBOOT_HASH, + .cmd_version = 0, + .cmd_size_in = sizeof(params), + .cmd_data_in = ¶ms, + .cmd_size_out = sizeof(*resp), + .cmd_data_out = resp, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd) != 0) + return -1; + + return 0; +} + +int google_chromeec_start_vboot_hash(enum ec_vboot_hash_type hash_type, + uint32_t hash_offset, + struct ec_response_vboot_hash *resp) +{ + struct ec_params_vboot_hash params = { + .cmd = EC_VBOOT_HASH_START, + .hash_type = hash_type, + .nonce_size = 0, + .offset = hash_offset, + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_VBOOT_HASH, + .cmd_version = 0, + .cmd_size_in = sizeof(params), + .cmd_data_in = ¶ms, + .cmd_size_out = sizeof(*resp), + .cmd_data_out = resp, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd) != 0) + return -1; + + return 0; +} + +int google_chromeec_flash_protect(uint32_t mask, uint32_t flags, + struct ec_response_flash_protect *resp) +{ + struct ec_params_flash_protect params = { + .mask = mask, + .flags = flags, + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_FLASH_PROTECT, + .cmd_version = EC_VER_FLASH_PROTECT, + .cmd_size_in = sizeof(params), + .cmd_data_in = ¶ms, + .cmd_size_out = sizeof(*resp), + .cmd_data_out = resp, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd) != 0) + return -1; + + return 0; +} + +int google_chromeec_flash_region_info(enum ec_flash_region region, + uint32_t *offset, uint32_t *size) +{ + struct ec_params_flash_region_info params = { + .region = region, + }; + struct ec_response_flash_region_info resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_FLASH_REGION_INFO, + .cmd_version = EC_VER_FLASH_REGION_INFO, + .cmd_size_in = sizeof(params), + .cmd_data_in = ¶ms, + .cmd_size_out = sizeof(resp), + .cmd_data_out = &resp, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd) != 0) + return -1; + + if (offset) + *offset = resp.offset; + if (size) + *size = resp.size; + + return 0; +} + +int google_chromeec_flash_erase(uint32_t offset, uint32_t size) +{ + struct ec_params_flash_erase params = { + .offset = offset, + .size = size, + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_FLASH_ERASE, + .cmd_version = 0, + .cmd_size_in = sizeof(params), + .cmd_data_in = ¶ms, + .cmd_size_out = 0, + .cmd_data_out = NULL, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd) != 0) + return -1; + + return 0; +} + +int google_chromeec_flash_info(struct ec_response_flash_info *info) +{ + struct chromeec_command cmd; + + cmd.cmd_code = EC_CMD_FLASH_INFO; cmd.cmd_version = 0; cmd.cmd_size_in = 0; - cmd.cmd_data_out = &r; - cmd.cmd_size_out = sizeof(r); + cmd.cmd_data_in = NULL; + cmd.cmd_size_out = sizeof(*info); + cmd.cmd_data_out = info; cmd.cmd_dev_index = 0; if (google_chromeec_command(&cmd) != 0) return -1; - if (feature >= 8 * sizeof(r.flags)) - return -1; - - return r.flags[feature / 32] & EC_FEATURE_MASK_0(feature); + return 0; } -int google_chromeec_set_sku_id(u32 skuid) +/* + * Write a block into EC flash. Expects params_data to be a buffer where + * the first N bytes are a struct ec_params_flash_write, and the rest of it + * is the data to write to flash. +*/ +int google_chromeec_flash_write_block(const uint8_t *params_data, + uint32_t bufsize) { - struct chromeec_command cmd; - struct ec_sku_id_info set_skuid = { - .sku_id = skuid + struct chromeec_command cmd = { + .cmd_code = EC_CMD_FLASH_WRITE, + .cmd_version = EC_VER_FLASH_WRITE, + .cmd_size_out = 0, + .cmd_data_out = NULL, + .cmd_size_in = bufsize, + .cmd_data_in = params_data, + .cmd_dev_index = 0, }; - cmd.cmd_code = EC_CMD_SET_SKU_ID; - cmd.cmd_version = 0; - cmd.cmd_size_in = sizeof(set_skuid); - cmd.cmd_data_in = &set_skuid; - cmd.cmd_data_out = NULL; - cmd.cmd_size_out = 0; - cmd.cmd_dev_index = 0; + assert(params_data); + + return google_chromeec_command(&cmd); +} + +/* + * EFS verification of flash. + */ +int google_chromeec_efs_verify(enum ec_flash_region region) +{ + struct ec_params_efs_verify params = { + .region = region, + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_EFS_VERIFY, + .cmd_version = 0, + .cmd_size_in = sizeof(params), + .cmd_data_in = ¶ms, + .cmd_size_out = 0, + .cmd_data_out = NULL, + .cmd_dev_index = 0, + }; + int rv; + + /* It's okay if the EC doesn't support EFS */ + rv = google_chromeec_command(&cmd); + if (rv != 0 && (cmd.cmd_code == EC_RES_INVALID_COMMAND)) + return 0; + else if (rv != 0) + return -1; + + return 0; +} + +int google_chromeec_battery_cutoff(uint8_t flags) +{ + struct ec_params_battery_cutoff params = { + .flags = flags, + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_BATTERY_CUT_OFF, + .cmd_version = 1, + .cmd_size_in = sizeof(params), + .cmd_data_in = ¶ms, + .cmd_data_out = NULL, + .cmd_size_out = 0, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd) != 0) + return -1; + + return 0; +} + +int google_chromeec_read_limit_power_request(int *limit_power) +{ + struct ec_params_charge_state params = { + .cmd = CHARGE_STATE_CMD_GET_PARAM, + .get_param.param = CS_PARAM_LIMIT_POWER, + }; + struct ec_response_charge_state resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_CHARGE_STATE, + .cmd_version = 0, + .cmd_size_in = sizeof(params), + .cmd_data_in = ¶ms, + .cmd_size_out = sizeof(resp), + .cmd_data_out = &resp, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + *limit_power = resp.get_param.value; + return 0; +} + +int google_chromeec_get_protocol_info( + struct ec_response_get_protocol_info *resp) +{ + struct chromeec_command cmd = { + .cmd_code = EC_CMD_GET_PROTOCOL_INFO, + .cmd_version = 0, + .cmd_size_in = 0, + .cmd_data_in = NULL, + .cmd_data_out = resp, + .cmd_size_out = sizeof(*resp), + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + return 0; +} + +int google_chromeec_set_sku_id(uint32_t skuid) +{ + struct ec_sku_id_info params = { + .sku_id = skuid + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_SET_SKU_ID, + .cmd_version = 0, + .cmd_size_in = sizeof(params), + .cmd_data_in = ¶ms, + .cmd_data_out = NULL, + .cmd_size_out = 0, + .cmd_dev_index = 0, + }; if (google_chromeec_command(&cmd) != 0) return -1; @@ -522,63 +809,64 @@ int google_chromeec_set_sku_id(u32 skuid) #if CONFIG(EC_GOOGLE_CHROMEEC_RTC) int rtc_get(struct rtc_time *time) { - struct chromeec_command cmd; - struct ec_response_rtc r; - - cmd.cmd_code = EC_CMD_RTC_GET_VALUE; - cmd.cmd_version = 0; - cmd.cmd_size_in = 0; - cmd.cmd_data_out = &r; - cmd.cmd_size_out = sizeof(r); - cmd.cmd_dev_index = 0; + struct ec_response_rtc resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_RTC_GET_VALUE, + .cmd_version = 0, + .cmd_size_in = 0, + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; if (google_chromeec_command(&cmd) != 0) return -1; - return rtc_to_tm(r.time, time); + return rtc_to_tm(resp.time, time); } #endif int google_chromeec_reboot(int dev_idx, enum ec_reboot_cmd type, uint8_t flags) { - struct ec_params_reboot_ec reboot_ec = { + struct ec_params_reboot_ec params = { .cmd = type, .flags = flags, }; - struct ec_response_get_version cec_resp = { }; - struct chromeec_command cec_cmd = { + struct ec_response_get_version resp = {}; + struct chromeec_command cmd = { .cmd_code = EC_CMD_REBOOT_EC, .cmd_version = 0, - .cmd_data_in = &reboot_ec, - .cmd_data_out = &cec_resp, - .cmd_size_in = sizeof(reboot_ec), + .cmd_data_in = ¶ms, + .cmd_data_out = &resp, + .cmd_size_in = sizeof(params), .cmd_size_out = 0, /* ignore response, if any */ .cmd_dev_index = dev_idx, }; - return google_chromeec_command(&cec_cmd); + return google_chromeec_command(&cmd); } static int cbi_get_uint32(uint32_t *id, uint32_t tag) { - struct chromeec_command cmd; - struct ec_params_get_cbi p; + struct ec_params_get_cbi params = { + .tag = tag, + }; uint32_t r = 0; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_GET_CROS_BOARD_INFO, + .cmd_version = 0, + .cmd_data_in = ¶ms, + .cmd_data_out = &r, + .cmd_size_in = sizeof(params), + .cmd_size_out = sizeof(r), + .cmd_dev_index = 0, + }; int rv; - p.tag = tag; - - cmd.cmd_code = EC_CMD_GET_CROS_BOARD_INFO; - cmd.cmd_version = 0; - cmd.cmd_data_in = &p; - cmd.cmd_data_out = &r; - cmd.cmd_size_in = sizeof(p); - cmd.cmd_size_out = sizeof(r); - cmd.cmd_dev_index = 0; - rv = google_chromeec_command(&cmd); if (rv != 0) return rv; + *id = r; return 0; } @@ -595,15 +883,15 @@ int google_chromeec_cbi_get_oem_id(uint32_t *id) static int cbi_get_string(char *buf, size_t bufsize, uint32_t tag) { - struct ec_params_get_cbi p = { + struct ec_params_get_cbi params = { .tag = tag, }; struct chromeec_command cmd = { .cmd_code = EC_CMD_GET_CROS_BOARD_INFO, .cmd_version = 0, - .cmd_data_in = &p, + .cmd_data_in = ¶ms, .cmd_data_out = buf, - .cmd_size_in = sizeof(p), + .cmd_size_in = sizeof(params), .cmd_size_out = bufsize, }; int rv; @@ -630,101 +918,102 @@ int google_chromeec_cbi_get_oem_name(char *buf, size_t bufsize) int google_chromeec_get_board_version(uint32_t *version) { - struct chromeec_command cmd; - struct ec_response_board_version board_v; - - cmd.cmd_code = EC_CMD_GET_BOARD_VERSION; - cmd.cmd_version = 0; - cmd.cmd_size_in = 0; - cmd.cmd_size_out = sizeof(board_v); - cmd.cmd_data_out = &board_v; - cmd.cmd_dev_index = 0; + struct ec_response_board_version resp; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_GET_BOARD_VERSION, + .cmd_version = 0, + .cmd_size_in = 0, + .cmd_size_out = sizeof(resp), + .cmd_data_out = &resp, + .cmd_dev_index = 0, + }; if (google_chromeec_command(&cmd)) return -1; - *version = board_v.board_version; + *version = resp.board_version; return 0; } -u32 google_chromeec_get_sku_id(void) +uint32_t google_chromeec_get_sku_id(void) { - struct chromeec_command cmd; - struct ec_sku_id_info sku_v; - - cmd.cmd_code = EC_CMD_GET_SKU_ID; - cmd.cmd_version = 0; - cmd.cmd_size_in = 0; - cmd.cmd_size_out = sizeof(sku_v); - cmd.cmd_data_out = &sku_v; - cmd.cmd_dev_index = 0; + struct ec_sku_id_info resp; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_GET_SKU_ID, + .cmd_version = 0, + .cmd_size_in = 0, + .cmd_size_out = sizeof(resp), + .cmd_data_out = &resp, + .cmd_dev_index = 0, + }; if (google_chromeec_command(&cmd) != 0) return 0; - return sku_v.sku_id; + return resp.sku_id; } int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len) { - struct chromeec_command cec_cmd; - struct ec_params_vbnvcontext cmd_vbnvcontext; - struct ec_response_vbnvcontext rsp_vbnvcontext; + struct ec_params_vbnvcontext params = { + .op = is_read ? EC_VBNV_CONTEXT_OP_READ : + EC_VBNV_CONTEXT_OP_WRITE, + }; + struct ec_response_vbnvcontext resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_VBNV_CONTEXT, + .cmd_version = EC_VER_VBNV_CONTEXT, + .cmd_data_in = ¶ms, + .cmd_data_out = &resp, + .cmd_size_in = sizeof(params), + .cmd_size_out = is_read ? sizeof(resp) : 0, + .cmd_dev_index = 0, + }; int retries = 3; if (len != EC_VBNV_BLOCK_SIZE) return -1; -retry: - cec_cmd.cmd_code = EC_CMD_VBNV_CONTEXT; - cec_cmd.cmd_version = EC_VER_VBNV_CONTEXT; - cec_cmd.cmd_data_in = &cmd_vbnvcontext; - cec_cmd.cmd_data_out = &rsp_vbnvcontext; - cec_cmd.cmd_size_in = sizeof(cmd_vbnvcontext); - cec_cmd.cmd_size_out = is_read ? sizeof(rsp_vbnvcontext) : 0; - cec_cmd.cmd_dev_index = 0; - - cmd_vbnvcontext.op = is_read ? EC_VBNV_CONTEXT_OP_READ : - EC_VBNV_CONTEXT_OP_WRITE; - if (!is_read) - memcpy(&cmd_vbnvcontext.block, data, EC_VBNV_BLOCK_SIZE); + memcpy(¶ms.block, data, EC_VBNV_BLOCK_SIZE); +retry: - if (google_chromeec_command(&cec_cmd)) { + if (google_chromeec_command(&cmd)) { printk(BIOS_ERR, "ERROR: failed to %s vbnv_ec context: %d\n", - is_read ? "read" : "write", (int)cec_cmd.cmd_code); + is_read ? "read" : "write", (int)cmd.cmd_code); mdelay(10); /* just in case */ if (--retries) goto retry; } if (is_read) - memcpy(data, &rsp_vbnvcontext.block, EC_VBNV_BLOCK_SIZE); + memcpy(data, &resp.block, EC_VBNV_BLOCK_SIZE); - return cec_cmd.cmd_code; + return cmd.cmd_code; } static uint16_t google_chromeec_get_uptime_info( - struct ec_response_uptime_info *rsp) + struct ec_response_uptime_info *resp) { struct chromeec_command cmd = { .cmd_code = EC_CMD_GET_UPTIME_INFO, .cmd_version = 0, .cmd_data_in = NULL, .cmd_size_in = 0, - .cmd_data_out = rsp, - .cmd_size_out = sizeof(*rsp), + .cmd_data_out = resp, + .cmd_size_out = sizeof(*resp), .cmd_dev_index = 0, }; + google_chromeec_command(&cmd); return cmd.cmd_code; } bool google_chromeec_get_ap_watchdog_flag(void) { - struct ec_response_uptime_info rsp; - return (!google_chromeec_get_uptime_info(&rsp) && - (rsp.ec_reset_flags & EC_RESET_FLAG_AP_WATCHDOG)); + struct ec_response_uptime_info resp; + return (!google_chromeec_get_uptime_info(&resp) && + (resp.ec_reset_flags & EC_RESET_FLAG_AP_WATCHDOG)); } int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen, @@ -840,66 +1129,69 @@ uint64_t google_chromeec_get_wake_mask(void) return google_chromeec_get_mask(EC_HOST_EVENT_ACTIVE_WAKE_MASK); } -int google_chromeec_set_usb_charge_mode(u8 port_id, enum usb_charge_mode mode) +int google_chromeec_set_usb_charge_mode(uint8_t port_id, enum usb_charge_mode mode) { - struct chromeec_command cmd; - struct ec_params_usb_charge_set_mode set_mode = { + struct ec_params_usb_charge_set_mode params = { .usb_port_id = port_id, .mode = mode, }; - - cmd.cmd_code = EC_CMD_USB_CHARGE_SET_MODE; - cmd.cmd_version = 0; - cmd.cmd_size_in = sizeof(set_mode); - cmd.cmd_data_in = &set_mode; - cmd.cmd_size_out = 0; - cmd.cmd_data_out = NULL; - cmd.cmd_dev_index = 0; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_USB_CHARGE_SET_MODE, + .cmd_version = 0, + .cmd_size_in = sizeof(params), + .cmd_data_in = ¶ms, + .cmd_size_out = 0, + .cmd_data_out = NULL, + .cmd_dev_index = 0, + }; return google_chromeec_command(&cmd); } /* Get charger power info in Watts. Also returns type of charger */ int google_chromeec_get_usb_pd_power_info(enum usb_chg_type *type, - u32 *max_watts) + uint32_t *max_watts) { - struct ec_params_usb_pd_power_info req = { + struct ec_params_usb_pd_power_info params = { .port = PD_POWER_CHARGING_PORT, }; - struct ec_response_usb_pd_power_info rsp; + struct ec_response_usb_pd_power_info resp = {}; struct chromeec_command cmd = { .cmd_code = EC_CMD_USB_PD_POWER_INFO, .cmd_version = 0, - .cmd_data_in = &req, - .cmd_size_in = sizeof(req), - .cmd_data_out = &rsp, - .cmd_size_out = sizeof(rsp), + .cmd_data_in = ¶ms, + .cmd_size_in = sizeof(params), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), .cmd_dev_index = 0, }; struct usb_chg_measures m; - int rv = google_chromeec_command(&cmd); + int rv; + + rv = google_chromeec_command(&cmd); if (rv != 0) return rv; + /* values are given in milliAmps and milliVolts */ - *type = rsp.type; - m = rsp.meas; + *type = resp.type; + m = resp.meas; *max_watts = (m.current_max * m.voltage_max) / 1000000; return 0; } -int google_chromeec_override_dedicated_charger_limit(u16 current_lim, - u16 voltage_lim) +int google_chromeec_override_dedicated_charger_limit(uint16_t current_lim, + uint16_t voltage_lim) { - struct ec_params_dedicated_charger_limit p = { + struct ec_params_dedicated_charger_limit params = { .current_lim = current_lim, .voltage_lim = voltage_lim, }; struct chromeec_command cmd = { .cmd_code = EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT, .cmd_version = 0, - .cmd_data_in = &p, - .cmd_size_in = sizeof(p), + .cmd_data_in = ¶ms, + .cmd_size_in = sizeof(params), .cmd_data_out = NULL, .cmd_size_out = 0, .cmd_dev_index = 0, @@ -908,45 +1200,52 @@ int google_chromeec_override_dedicated_charger_limit(u16 current_lim, return google_chromeec_command(&cmd); } -int google_chromeec_set_usb_pd_role(u8 port, enum usb_pd_control_role role) +int google_chromeec_set_usb_pd_role(uint8_t port, enum usb_pd_control_role role) { - struct ec_params_usb_pd_control req = { + struct ec_params_usb_pd_control params = { .port = port, .role = role, .mux = USB_PD_CTRL_MUX_NO_CHANGE, .swap = USB_PD_CTRL_SWAP_NONE, }; - struct ec_response_usb_pd_control rsp; + struct ec_response_usb_pd_control resp; struct chromeec_command cmd = { .cmd_code = EC_CMD_USB_PD_CONTROL, .cmd_version = 0, - .cmd_data_in = &req, - .cmd_size_in = sizeof(req), - .cmd_data_out = &rsp, - .cmd_size_out = sizeof(rsp), + .cmd_data_in = ¶ms, + .cmd_size_in = sizeof(params), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), .cmd_dev_index = 0, }; return google_chromeec_command(&cmd); } -static int google_chromeec_hello(void) +int google_chromeec_hello(void) { - struct chromeec_command cec_cmd; - struct ec_params_hello cmd_hello; - struct ec_response_hello rsp_hello; - cmd_hello.in_data = 0x10203040; - cec_cmd.cmd_code = EC_CMD_HELLO; - cec_cmd.cmd_version = 0; - cec_cmd.cmd_data_in = &cmd_hello.in_data; - cec_cmd.cmd_data_out = &rsp_hello.out_data; - cec_cmd.cmd_size_in = sizeof(cmd_hello.in_data); - cec_cmd.cmd_size_out = sizeof(rsp_hello.out_data); - cec_cmd.cmd_dev_index = 0; - google_chromeec_command(&cec_cmd); - printk(BIOS_DEBUG, "Google Chrome EC: Hello got back %x status (%x)\n", - rsp_hello.out_data, cec_cmd.cmd_code); - return cec_cmd.cmd_code; + struct ec_params_hello params = { + .in_data = 0x10203040, + }; + struct ec_response_hello resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_HELLO, + .cmd_version = 0, + .cmd_data_in = ¶ms, + .cmd_data_out = &resp, + .cmd_size_in = sizeof(params), + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + + int rv = google_chromeec_command(&cmd); + if (rv) + return -1; + + if (resp.out_data != (params.in_data + 0x01020304)) + return -1; + + return 0; } /* @@ -1063,48 +1362,57 @@ static void google_chromeec_log_uptimeinfo(void) if ((cmd_resp.ec_reset_flags & (1 << flag)) != 0) { if (flag_count) printk(BIOS_DEBUG, " | "); - printk(BIOS_DEBUG, reset_flag_strings[flag]); + printk(BIOS_DEBUG, "%s", reset_flag_strings[flag]); flag_count++; } } printk(BIOS_DEBUG, "\n"); } -static int ec_image_type; /* Cached EC image type (ro or rw). */ +/* Cache and retrieve the EC image type (ro or rw) */ +enum ec_current_image google_chromeec_get_current_image(void) +{ + MAYBE_STATIC_BSS enum ec_current_image ec_image_type = EC_IMAGE_UNKNOWN; + + if (ec_image_type != EC_IMAGE_UNKNOWN) + return ec_image_type; + + struct ec_response_get_version resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_GET_VERSION, + .cmd_version = 0, + .cmd_data_out = &resp, + .cmd_size_in = 0, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + + google_chromeec_command(&cmd); + + if (cmd.cmd_code) { + printk(BIOS_DEBUG, + "Google Chrome EC: version command failed!\n"); + } else { + printk(BIOS_DEBUG, "Google Chrome EC: version:\n"); + printk(BIOS_DEBUG, " ro: %s\n", resp.version_string_ro); + printk(BIOS_DEBUG, " rw: %s\n", resp.version_string_rw); + printk(BIOS_DEBUG, " running image: %d\n", + resp.current_image); + ec_image_type = resp.current_image; + } + + /* Will still be UNKNOWN if command failed */ + return ec_image_type; +} void google_chromeec_init(void) { - struct chromeec_command cec_cmd; - struct ec_response_get_version cec_resp = {{0}}; - - google_chromeec_hello(); - - cec_cmd.cmd_code = EC_CMD_GET_VERSION; - cec_cmd.cmd_version = 0; - cec_cmd.cmd_data_out = &cec_resp; - cec_cmd.cmd_size_in = 0; - cec_cmd.cmd_size_out = sizeof(cec_resp); - cec_cmd.cmd_dev_index = 0; - google_chromeec_command(&cec_cmd); - - if (cec_cmd.cmd_code) { - printk(BIOS_DEBUG, - "Google Chrome EC: version command failed!\n"); - } else { - printk(BIOS_DEBUG, "Google Chrome EC: version:\n"); - printk(BIOS_DEBUG, " ro: %s\n", cec_resp.version_string_ro); - printk(BIOS_DEBUG, " rw: %s\n", cec_resp.version_string_rw); - printk(BIOS_DEBUG, " running image: %d\n", - cec_resp.current_image); - ec_image_type = cec_resp.current_image; - } - google_chromeec_log_uptimeinfo(); } int google_ec_running_ro(void) { - return (ec_image_type == EC_IMAGE_RO); + return (google_chromeec_get_current_image() == EC_IMAGE_RO); } /** @@ -1115,50 +1423,50 @@ int google_ec_running_ro(void) */ int google_chromeec_pd_get_amode(uint16_t svid) { - struct ec_response_usb_pd_ports r; - struct chromeec_command cmd; + struct ec_response_usb_pd_ports resp; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_USB_PD_PORTS, + .cmd_version = 0, + .cmd_data_in = NULL, + .cmd_size_in = 0, + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; int i; - cmd.cmd_code = EC_CMD_USB_PD_PORTS; - cmd.cmd_version = 0; - cmd.cmd_data_in = NULL; - cmd.cmd_size_in = 0; - cmd.cmd_data_out = &r; - cmd.cmd_size_out = sizeof(r); - cmd.cmd_dev_index = 0; if (google_chromeec_command(&cmd) < 0) return -1; - for (i = 0; i < r.num_ports; i++) { - struct ec_params_usb_pd_get_mode_request p; - struct ec_params_usb_pd_get_mode_response res; + for (i = 0; i < resp.num_ports; i++) { + struct ec_params_usb_pd_get_mode_request params; + struct ec_params_usb_pd_get_mode_response resp2; int svid_idx = 0; do { /* Reset cmd in each iteration in case google_chromeec_command changes it. */ - p.port = i; - p.svid_idx = svid_idx; + params.port = i; + params.svid_idx = svid_idx; cmd.cmd_code = EC_CMD_USB_PD_GET_AMODE; cmd.cmd_version = 0; - cmd.cmd_data_in = &p; - cmd.cmd_size_in = sizeof(p); - cmd.cmd_data_out = &res; - cmd.cmd_size_out = sizeof(res); + cmd.cmd_data_in = ¶ms; + cmd.cmd_size_in = sizeof(params); + cmd.cmd_data_out = &resp2; + cmd.cmd_size_out = sizeof(resp2); cmd.cmd_dev_index = 0; if (google_chromeec_command(&cmd) < 0) return -1; - if (res.svid == svid) + if (resp2.svid == svid) return 1; svid_idx++; - } while (res.svid); + } while (resp2.svid); } return 0; } - #define USB_SID_DISPLAYPORT 0xff01 /** diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 019f9c1eb0..9fb9c391cc 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -30,11 +30,12 @@ uint64_t google_chromeec_get_wake_mask(void); int google_chromeec_set_sci_mask(uint64_t mask); int google_chromeec_set_smi_mask(uint64_t mask); int google_chromeec_set_wake_mask(uint64_t mask); -u8 google_chromeec_get_event(void); +uint8_t google_chromeec_get_event(void); /* Check if EC supports feature EC_FEATURE_UNIFIED_WAKE_MASKS */ bool google_chromeec_is_uhepi_supported(void); int google_ec_running_ro(void); +enum ec_current_image google_chromeec_get_current_image(void); void google_chromeec_init(void); int google_chromeec_pd_get_amode(uint16_t svid); int google_chromeec_wait_for_displayport(long timeout); @@ -56,12 +57,12 @@ uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size); * This function is used to get the board version information from EC. */ int google_chromeec_get_board_version(uint32_t *version); -u32 google_chromeec_get_sku_id(void); -int google_chromeec_set_sku_id(u32 skuid); +uint32_t google_chromeec_get_sku_id(void); +int google_chromeec_set_sku_id(uint32_t skuid); uint64_t google_chromeec_get_events_b(void); int google_chromeec_clear_events_b(uint64_t mask); int google_chromeec_kbbacklight(int percent); -void google_chromeec_post(u8 postcode); +void google_chromeec_post(uint8_t postcode); int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len); uint8_t google_chromeec_get_switches(void); bool google_chromeec_get_ap_watchdog_flag(void); @@ -95,8 +96,8 @@ int google_chromeec_cbi_get_oem_name(char *buf, size_t bufsize); #define MEC_EMI_RANGE_START EC_HOST_CMD_REGION0 #define MEC_EMI_RANGE_END (EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE) -int google_chromeec_set_usb_charge_mode(u8 port_id, enum usb_charge_mode mode); -int google_chromeec_set_usb_pd_role(u8 port, enum usb_pd_control_role role); +int google_chromeec_set_usb_charge_mode(uint8_t port_id, enum usb_charge_mode mode); +int google_chromeec_set_usb_pd_role(uint8_t port, enum usb_pd_control_role role); /* * Retrieve the charger type and max wattage. * @@ -105,7 +106,7 @@ int google_chromeec_set_usb_pd_role(u8 port, enum usb_pd_control_role role); * @return non-zero for error, otherwise 0. */ int google_chromeec_get_usb_pd_power_info(enum usb_chg_type *type, - u32 *max_watts); + uint32_t *max_watts); /* * Set max current and voltage of a dedicated charger. @@ -114,8 +115,8 @@ int google_chromeec_get_usb_pd_power_info(enum usb_chg_type *type, * @param voltage_lim Max voltage in mV * @return non-zero for error, otherwise 0. */ -int google_chromeec_override_dedicated_charger_limit(u16 current_lim, - u16 voltage_lim); +int google_chromeec_override_dedicated_charger_limit(uint16_t current_lim, + uint16_t voltage_lim); /* internal structure to send a command to the EC and wait for response. */ struct chromeec_command { @@ -149,6 +150,13 @@ typedef int (*crosec_io_t)(size_t req_size, size_t resp_size, void *context); int crosec_command_proto(struct chromeec_command *cec_command, crosec_io_t crosec_io, void *context); +/** + * Performs light verification of the EC<->AP communcation channel. + * + * @return 0 on success, -1 on error + */ +int google_chromeec_hello(void); + /** * Send a command to a CrOS EC * @@ -178,4 +186,117 @@ int google_chromeec_get_mkbp_event(struct ec_response_get_next_event *event); /* Log host events to eventlog based on the mask provided. */ void google_chromeec_log_events(uint64_t mask); +/** + * Protect/un-protect EC flash regions. + * + * @param mask Set/clear the requested bits in 'flags' + * @param flags Flash protection flags + * @param resp Pointer to response structure + * @return 0 on success, -1 on error + */ +int google_chromeec_flash_protect(uint32_t mask, uint32_t flags, + struct ec_response_flash_protect *resp); +/** + * Calculate image hash for vboot. + * + * @param hash_type The hash types supported by the EC for vboot + * @param offset The offset to start hashing in flash + * @param resp Pointer to response structure + * @return 0 on success, -1 on error + */ +int google_chromeec_start_vboot_hash(enum ec_vboot_hash_type hash_type, + uint32_t offset, + struct ec_response_vboot_hash *resp); +/** + * Return the EC's vboot image hash. + * + * @param offset Get hash for flash region beginning here + * @param resp Pointer to response structure + * @return 0 on success, -1 on error + * + */ +int google_chromeec_get_vboot_hash(uint32_t offset, + struct ec_response_vboot_hash *resp); + +/** + * Get offset and size of the specified EC flash region. + * + * @param region Which region of EC flash + * @param offset Gets filled with region's offset + * @param size Gets filled with region's size + * @return 0 on success, -1 on error + */ +int google_chromeec_flash_region_info(enum ec_flash_region region, + uint32_t *offset, uint32_t *size); +/** + * Erase a region of EC flash. + * + * @param offset Where to begin erasing + * @param size Size of area to erase + * @return 0 on success, -1 on error + */ +int google_chromeec_flash_erase(uint32_t region_offset, uint32_t region_size); + +/** + * Return information about the entire flash. + * + * @param info Pointer to response structure + * @return 0 on success, -1 on error + */ +int google_chromeec_flash_info(struct ec_response_flash_info *info); + +/** + * Write a block into EC flash. + * + * @param data Pointer to data to write to flash, prefixed by a + * struct ec_params_flash_write + * @param offset Offset to begin writing data + * @param size Number of bytes to be written to flash from data + * @return 0 on success, -1 on error + */ +int google_chromeec_flash_write_block(const uint8_t *data, uint32_t size); + +/** + * Verify flash using EFS if available. + * + * @param region Which flash region to verify + * @return 0 on success, -1 on error + */ +int google_chromeec_efs_verify(enum ec_flash_region region); + +/** + * Command EC to perform battery cutoff. + * + * @param flags Flags to pass to the EC + * @return 0 on success, -1 on error + */ +int google_chromeec_battery_cutoff(uint8_t flags); + +/** + * Check if the EC is requesting the system to limit input power. + * + * @param limit_power If successful, limit_power is 1 if EC is requesting + * input power limits, otherwise 0. + * @return 0 on success, -1 on error + */ +int google_chromeec_read_limit_power_request(int *limit_power); + +/** + * Get information about the protocol that the EC speaks. + * + * @param resp Filled with host command protocol information. + * @return 0 on success, -1 on error + */ +int google_chromeec_get_protocol_info( + struct ec_response_get_protocol_info *resp); + +/** + * Get available versions of the specified command. + * + * @param command Command ID + * @param pmask Pointer to version mask + * @return 0 on success, -1 on error + */ +int google_chromeec_get_cmd_versions(int command, uint32_t *pmask); + #endif /* _EC_GOOGLE_CHROMEEC_EC_H */ diff --git a/src/ec/google/wilco/acpi/superio.asl b/src/ec/google/wilco/acpi/superio.asl index 0995d6a173..42575bd654 100644 --- a/src/ec/google/wilco/acpi/superio.asl +++ b/src/ec/google/wilco/acpi/superio.asl @@ -25,7 +25,6 @@ Device (SIO) { Name (_HID, EisaId ("PNP0501")) Name (_UID, 1) - Name (_ADR, 0) Method (_STA, 0, NotSerialized) { @@ -57,7 +56,6 @@ Device (SIO) Name (_HID, EisaId ("PNP0303")) Name (_CID, EisaId ("PNP030B")) Name (_UID, 0) - Name (_ADR, 0) Method (_STA, 0, NotSerialized) { @@ -90,7 +88,6 @@ Device (SIO) { Name (_HID, EisaId ("PNP0F13")) Name (_UID, 0) - Name (_ADR, 0) Method (_STA, 0, NotSerialized) { diff --git a/src/ec/google/wilco/acpi/ucsi.asl b/src/ec/google/wilco/acpi/ucsi.asl index f69e5924e7..0d2c5a6336 100644 --- a/src/ec/google/wilco/acpi/ucsi.asl +++ b/src/ec/google/wilco/acpi/ucsi.asl @@ -19,7 +19,6 @@ Device (UCSI) Name (_CID, EisaId ("PNP0CA0")) Name (_DDN, "Wilco EC UCSI") Name (_UID, One) - Name (_ADR, Zero) Name (_STA, 0xf) /* Value written to EC control register to start UCSI command */ diff --git a/src/ec/quanta/ene_kb3940q/acpi/superio.asl b/src/ec/quanta/ene_kb3940q/acpi/superio.asl index 2f5298a056..88dccc907a 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/superio.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/superio.asl @@ -24,7 +24,6 @@ Device (SIO) { Device (PS2K) // Keyboard { Name (_UID, 0) - Name (_ADR, 0) Name (_HID, EISAID("PNP0303")) Name (_CID, EISAID("PNP030B")) diff --git a/src/ec/quanta/it8518/acpi/superio.asl b/src/ec/quanta/it8518/acpi/superio.asl index e912e049fc..8b93aa440e 100644 --- a/src/ec/quanta/it8518/acpi/superio.asl +++ b/src/ec/quanta/it8518/acpi/superio.asl @@ -19,13 +19,11 @@ Device (SIO) { Name (_HID, EisaId("PNP0A05")) Name (_UID, 0) - Name (_ADR, 0) #ifdef SIO_EC_ENABLE_PS2K Device (PS2K) // Keyboard { Name (_UID, 0) - Name (_ADR, 0) Name (_HID, EISAID("PNP0303")) Name (_CID, EISAID("PNP030B")) diff --git a/src/include/boot/tables.h b/src/include/boot/tables.h index 9e82e3f6c8..b440c8bbc4 100644 --- a/src/include/boot/tables.h +++ b/src/include/boot/tables.h @@ -1,7 +1,7 @@ #ifndef BOOT_TABLES_H #define BOOT_TABLES_H -#include +#include /* * Write architecture specific tables as well as the common diff --git a/src/include/cbmem.h b/src/include/cbmem.h index f972ba6503..a22c420ad3 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -71,10 +71,20 @@ void cbmem_top_init(void); /* Return the top address for dynamic cbmem. The address returned needs to * be consistent across romstage and ramstage, and it is required to be * below 4GiB for 32bit coreboot builds. On 64bit coreboot builds there's no - * upper limit. - * x86 boards or chipsets must return NULL before the cbmem backing store has - * been initialized. */ + * upper limit. This should not be called before memory is initialized. + */ +/* The assumption is made that the result of cbmem_top_romstage fits in the size + of uintptr_t in the ramstage. */ +extern uintptr_t _cbmem_top_ptr; void *cbmem_top(void); +/* With CONFIG_RAMSTAGE_CBMEM_TOP_ARG set, the result of cbmem_top is passed via + * calling arguments to the next stage and saved in the global _cbmem_top_ptr + * global variable. Only a romstage callback needs to be implemented by the + * platform. It is up to the stages after romstage to save the calling argument + * in the _cbmem_top_ptr symbol. Without CONFIG_RAMSTAGE_CBMEM_TOP_ARG the same + * implementation as used in romstage will be used. + */ +void *cbmem_top_chipset(void); /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index c1917adaff..1813c9e5a2 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -417,177 +417,4 @@ */ #define POST_DIE 0xff - -/* - * The following POST codes are taken from src/include/cpu/amd/geode_post_code.h - * They overlap with previous codes, and most are not even used - * Some mainboards still require them, but they are deprecated. We want to - * consolidate our own POST code structure with the codes above. - * - * standard AMD post definitions for the AMD Geode - */ -/* port to write post codes to */ -#define POST_Output_Port (0x080) - -#define POST_preSioInit (0x000) -#define POST_clockInit (0x001) -#define POST_CPURegInit (0x002) -#define POST_UNREAL (0x003) -#define POST_CPUMemRegInit (0x004) -#define POST_CPUTest (0x005) -#define POST_memSetup (0x006) -#define POST_memSetUpStack (0x007) -#define POST_memTest (0x008) -#define POST_shadowRom (0x009) -#define POST_memRAMoptimize (0x00A) -#define POST_cacheInit (0x00B) -#define POST_northBridgeInit (0x00C) -#define POST_chipsetInit (0x00D) -#define POST_sioTest (0x00E) -#define POST_pcATjunk (0x00F) - -#define POST_intTable (0x010) -#define POST_memInfo (0x011) -#define POST_romCopy (0x012) -#define POST_PLLCheck (0x013) -#define POST_keyboardInit (0x014) -#define POST_cpuCacheOff (0x015) -#define POST_BDAInit (0x016) -#define POST_pciScan (0x017) -#define POST_optionRomInit (0x018) -#define POST_ResetLimits (0x019) -#define POST_summary_screen (0x01A) -#define POST_Boot (0x01B) -#define POST_SystemPreInit (0x01C) -#define POST_ClearRebootFlag (0x01D) -#define POST_GLIUInit (0x01E) -#define POST_BootFailed (0x01F) - -#define POST_CPU_ID (0x020) -#define POST_COUNTERBROKEN (0x021) -#define POST_DIFF_DIMMS (0x022) -#define POST_WIGGLE_MEM_LINES (0x023) -#define POST_NO_GLIU_DESC (0x024) -#define POST_CPU_LCD_CHECK (0x025) -#define POST_CPU_LCD_PASS (0x026) -#define POST_CPU_LCD_FAIL (0x027) -#define POST_CPU_STEPPING (0x028) -#define POST_CPU_DM_BIST_FAILURE (0x029) -#define POST_CPU_FLAGS (0x02A) -#define POST_CHIPSET_ID (0x02B) -#define POST_CHIPSET_ID_PASS (0x02C) -#define POST_CHIPSET_ID_FAIL (0x02D) -#define POST_CPU_ID_GOOD (0x02E) -#define POST_CPU_ID_FAIL (0x02F) - -/* PCI config*/ -#define P80_PCICFG (0x030) - -/* PCI io*/ -#define P80_PCIIO (0x040) - -/* PCI memory*/ -#define P80_PCIMEM (0x050) - -/* SIO*/ -#define P80_SIO (0x060) - -/* Memory Setp*/ -#define P80_MEM_SETUP (0x070) -#define POST_MEM_SETUP (0x070) -#define ERROR_32BIT_DIMMS (0x071) -#define POST_MEM_SETUP2 (0x072) -#define POST_MEM_SETUP3 (0x073) -#define POST_MEM_SETUP4 (0x074) -#define POST_MEM_SETUP5 (0x075) -#define POST_MEM_ENABLE (0x076) -#define ERROR_NO_DIMMS (0x077) -#define ERROR_DIFF_DIMMS (0x078) -#define ERROR_BAD_LATENCY (0x079) -#define ERROR_SET_PAGE (0x07A) -#define ERROR_DENSITY_DIMM (0x07B) -#define ERROR_UNSUPPORTED_DIMM (0x07C) -#define ERROR_BANK_SET (0x07D) -#define POST_MEM_SETUP_GOOD (0x07E) -#define POST_MEM_SETUP_FAIL (0x07F) - -#define POST_UserPreInit (0x080) -#define POST_UserPostInit (0x081) -#define POST_Equipment_check (0x082) -#define POST_InitNVRAMBX (0x083) -#define POST_NoPIRTable (0x084) -#define POST_ChipsetFingerPrintPass (0x085) -#define POST_ChipsetFingerPrintFail (0x086) -#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) -#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) -#define POST_CPU_FPU_BIST_FAILURE (0x089) -#define POST_CPU_BTB_BIST_FAILURE (0x08A) -#define POST_CPU_EX_BIST_FAILURE (0x08B) -#define POST_Chipset_PI_Test_Fail (0x08C) -#define POST_Chipset_SMBus_SDA_Test_Fail (0x08D) -#define POST_BIT_CLK_Fail (0x08E) - -#define POST_STACK_SETUP (0x090) -#define POST_CPU_PF_BIST_FAILURE (0x091) -#define POST_CPU_L2_BIST_FAILURE (0x092) -#define POST_CPU_GLCP_BIST_FAILURE (0x093) -#define POST_CPU_DF_BIST_FAILURE (0x094) -#define POST_CPU_VG_BIST_FAILURE (0x095) -#define POST_CPU_VIP_BIST_FAILURE (0x096) -#define POST_STACK_SETUP_PASS (0x09E) -#define POST_STACK_SETUP_FAIL (0x09F) - -#define POST_PLL_INIT (0x0A0) -#define POST_PLL_MANUAL (0x0A1) -#define POST_PLL_STRAP (0x0A2) -#define POST_PLL_RESET_FAIL (0x0A3) -#define POST_PLL_PCI_FAIL (0x0A4) -#define POST_PLL_MEM_FAIL (0x0A5) -#define POST_PLL_CPU_VER_FAIL (0x0A6) - -#define POST_MEM_TESTMEM (0x0B0) -#define POST_MEM_TESTMEM1 (0x0B1) -#define POST_MEM_TESTMEM2 (0x0B2) -#define POST_MEM_TESTMEM3 (0x0B3) -#define POST_MEM_TESTMEM4 (0x0B4) -#define POST_MEM_TESTMEM_PASS (0x0BE) -#define POST_MEM_TESTMEM_FAIL (0x0BF) - -#define POST_SECUROM_SECBOOT_START (0x0C0) -#define POST_SECUROM_BOOTSRCSETUP (0x0C1) -#define POST_SECUROM_REMAP_FAIL (0x0C2) -#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) -#define POST_SECUROM_DCACHESETUP (0x0C4) -#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) -#define POST_SECUROM_ICACHESETUP (0x0C6) -#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) -#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) -#define POST_SECUROM_PLATFORMSETUP (0x0C9) -#define POST_SECUROM_SIGCHECKBIOS (0x0CA) -#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) -#define POST_SECUROM_PASS (0x0CC) -#define POST_SECUROM_FAIL (0x0CD) - -#define POST_RCONFInitError (0x0CE) -#define POST_CacheInitError (0x0CF) - -#define POST_ROM_PREUNCOMPRESS (0x0D0) -#define POST_ROM_UNCOMPRESS (0x0D1) -#define POST_ROM_SMM_INIT (0x0D2) -#define POST_ROM_VID_BIOS (0x0D3) -#define POST_ROM_LCDINIT (0x0D4) -#define POST_ROM_SPLASH (0x0D5) -#define POST_ROM_HDDINIT (0x0D6) -#define POST_ROM_SYS_INIT (0x0D7) -#define POST_ROM_DMM_INIT (0x0D8) -#define POST_ROM_TVINIT (0x0D9) -#define POST_ROM_POSTUNCOMPRESS (0x0DE) - -#define P80_CHIPSET_INIT (0x0E0) -#define POST_PreChipsetInit (0x0E1) -#define POST_LateChipsetInit (0x0E2) -#define POST_NORTHB_INIT (0x0E8) - -#define POST_INTR_SEG_JUMP (0x0F0) - #endif /* POST_CODES_H */ diff --git a/src/include/console/usb.h b/src/include/console/usb.h index f4f8bd73ed..33edbf6e5f 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -31,6 +31,7 @@ int usb_can_rx_byte(int idx); ((ENV_BOOTBLOCK && CONFIG(USBDEBUG_IN_PRE_RAM)) || \ (ENV_ROMSTAGE && CONFIG(USBDEBUG_IN_PRE_RAM)) || \ (ENV_POSTCAR && CONFIG(USBDEBUG_IN_PRE_RAM)) || \ + (ENV_VERSTAGE && CONFIG(USBDEBUG_IN_PRE_RAM)) || \ ENV_RAMSTAGE)) #define USB_PIPE_FOR_CONSOLE 0 diff --git a/src/include/cpu/intel/em64t101_save_state.h b/src/include/cpu/intel/em64t101_save_state.h index b8bb2db58f..7493c85049 100644 --- a/src/include/cpu/intel/em64t101_save_state.h +++ b/src/include/cpu/intel/em64t101_save_state.h @@ -20,6 +20,7 @@ /* Intel Revision 30101 SMM State-Save Area * The following processor architectures use this: + * - Nehalem * - SandyBridge * - IvyBridge * - Haswell diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 8c558ce8ac..2710e7f1fc 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -301,5 +301,25 @@ static inline enum mca_err_code_types mca_err_type(msr_t reg) return MCA_ERRTYPE_UNKNOWN; } + +/* Helper for setting single MSR bits */ +static inline void msr_set_bit(unsigned int reg, unsigned int bit) +{ + msr_t msr = rdmsr(reg); + + if (bit < 32) { + if (msr.lo & (1 << bit)) + return; + msr.lo |= 1 << bit; + } else { + if (msr.hi & (1 << (bit - 32))) + return; + msr.hi |= 1 << (bit - 32); + } + + wrmsr(reg, msr); +} + + #endif /* __ASSEMBLER__ */ #endif /* CPU_X86_MSR_H */ diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index dd333e8930..c18f8782f0 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -63,4 +63,9 @@ static inline uint64_t tsc_to_uint64(tsc_t tstamp) /* Provided by CPU/chipset code for the TSC rate in MHz. */ unsigned long tsc_freq_mhz(void); +static inline int tsc_constant_rate(void) +{ + return !CONFIG(UNKNOWN_TSC_RATE); +} + #endif /* CPU_X86_TSC_H */ diff --git a/src/include/device/device.h b/src/include/device/device.h index f22bed5d58..e0e8ea5bdd 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -94,6 +94,7 @@ struct bus { unsigned int reset_needed : 1; unsigned int disable_relaxed_ordering : 1; unsigned int ht_link_up : 1; + unsigned int no_vga16 : 1; /* No support for 16-bit VGA decoding */ }; /* @@ -327,11 +328,10 @@ static inline DEVTREE_CONST void *config_of_soc(void) return config_of(pcidev_on_root(0, 0)); } +void enable_static_devices(struct device *bus); void scan_smbus(struct device *bus); void scan_generic_bus(struct device *bus); void scan_static_bus(struct device *bus); -void scan_lpc_bus(struct device *bus); -void scan_usb_bus(struct device *bus); #endif /* !defined(__ROMCC__) */ diff --git a/src/include/device/dram/common.h b/src/include/device/dram/common.h index 4c6f02eb00..e5fb534551 100644 --- a/src/include/device/dram/common.h +++ b/src/include/device/dram/common.h @@ -18,6 +18,9 @@ #ifndef DEVICE_DRAM_COMMON_H #define DEVICE_DRAM_COMMON_H +#include +#include + /** * \brief Convenience definitions for TCK values * diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index 7b95a3cd74..df36eb6f96 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -63,6 +63,10 @@ static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo, * - high_bit: highest bit that's part of the bit field. * - low_bit: lowest bit in the bit field. * + * To define a field with a single bit: + * + * DEFINE_BIT(name, bit) + * * To extract one field value from a raw reg value: * * EXTRACT_BITFIELD(value, name); @@ -85,7 +89,7 @@ static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo, * Examples: * * DEFINE_BITFIELD(DISP_TYPE, 2, 1) - * DEFINE_BITFIELD(DISP_EN, 0, 0) + * DEFINE_BIT(DISP_EN, 0) * * SET32_BITFIELDS(&disp_regs.ctrl, DISP_TYPE, 2); * SET32_BITFIELDS(&disp_regs.ctrl, DISP_EN, 0); @@ -118,6 +122,8 @@ static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo, name##_BITFIELD_SIZE = (high_bit) - (low_bit) + 1, \ }; +#define DEFINE_BIT(name, bit) DEFINE_BITFIELD(name, bit, bit) + #define _BF_MASK(name, value) \ (((1 << name##_BITFIELD_SIZE) - 1) << name##_BITFIELD_SHIFT) diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index c9c9575b01..bd723404e2 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -138,6 +138,7 @@ #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ +#define PCI_BRIDGE_CTL_VGA16 0x10 /* Enable 16-bit i/o port decoding */ #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ /* Fast Back2Back enabled on secondary interface */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e6b8b1879d..3cab86bd1c 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -456,6 +456,7 @@ #define PCI_DEVICE_ID_AMD_PCO_LPC 0x790e #define PCI_DEVICE_ID_AMD_PCO_HDA0 0x15de #define PCI_DEVICE_ID_AMD_PCO_HDA1 0x15e3 +#define PCI_DEVICD_ID_AMD_PCO_ACP 0x15e2 #define PCI_DEVICE_ID_AMD_PCO_XHCI0 0x15e0 #define PCI_DEVICE_ID_AMD_PCO_XHCI1 0x15e1 @@ -3097,19 +3098,37 @@ #define PCI_DEVICE_ID_INTEL_CMP_HWSEQ_SPI 0x02a4 /* Intel IGD device Ids */ +#define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 #define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM 0x1906 +#define PCI_DEVICE_ID_INTEL_SKL_GT1F_SHALM 0x190B #define PCI_DEVICE_ID_INTEL_SKL_GT2_DT2P1 0x1912 -#define PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM 0x191E #define PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM 0x1916 #define PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM 0x191B #define PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM 0x191D +#define PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM 0x191E +#define PCI_DEVICE_ID_INTEL_SKL_GT3_SULTM 0x1923 +#define PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_1 0x1926 +#define PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_2 0x1927 +#define PCI_DEVICE_ID_INTEL_SKL_GT3FE_SSRVM 0x192D #define PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM 0x193B +#define PCI_DEVICE_ID_INTEL_SKL_GT4E_SWSTM 0x193D +#define PCI_DEVICE_ID_INTEL_KBL_GT1F_DT2 0x5902 #define PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM 0x5906 +#define PCI_DEVICE_ID_INTEL_KBL_GT1_SHALM_1 0x5908 +#define PCI_DEVICE_ID_INTEL_KBL_GT1_SSRVM 0x590A +#define PCI_DEVICE_ID_INTEL_KBL_GT1_SHALM_2 0x590B #define PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2 0x5912 -#define PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM 0x591E #define PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM 0x5916 #define PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR 0x5917 +#define PCI_DEVICE_ID_INTEL_KBL_GT2F_SULTM 0x5921 +#define PCI_DEVICE_ID_INTEL_KBL_GT2_SSRVM 0x591A #define PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM 0x591B +#define PCI_DEVICE_ID_INTEL_KBL_GT2_SWSTM 0x591D +#define PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM 0x591E +#define PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1 0x5926 +#define PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2 0x5927 +#define PCI_DEVICE_ID_INTEL_KBL_GT4_SHALM 0x593B + #define PCI_DEVICE_ID_INTEL_AML_GT2_ULX 0x591C #define PCI_DEVICE_ID_INTEL_APL_IGD_HD_505 0x5a84 #define PCI_DEVICE_ID_INTEL_APL_IGD_HD_500 0x5a85 @@ -3247,6 +3266,9 @@ #define PCI_DEVICE_ID_INTEL_GLK_P2SB 0x3192 #define PCI_DEVICE_ID_INTEL_LWB_P2SB 0xa1a0 #define PCI_DEVICE_ID_INTEL_LWB_P2SB_SUPER 0xa220 +#define PCI_DEVICE_ID_INTEL_SKL_LP_P2SB 0x9d20 +#define PCI_DEVICE_ID_INTEL_SKL_P2SB 0xa120 +#define PCI_DEVICE_ID_INTEL_KBL_P2SB 0xa2a0 #define PCI_DEVICE_ID_INTEL_CNL_P2SB 0x9da0 #define PCI_DEVICE_ID_INTEL_CNP_H_P2SB 0xa320 #define PCI_DEVICE_ID_INTEL_ICL_P2SB 0x34a0 diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index a4aa52aa09..82f3c40005 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -47,4 +47,5 @@ void pci_rom_ssdt(struct device *device); u32 map_oprom_vendev(u32 vendev); +int verified_boot_should_run_oprom(struct rom_header *rom_header); #endif diff --git a/src/include/elog.h b/src/include/elog.h index 0574819e0d..1692a809fc 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -61,37 +61,6 @@ /* Embedded controller event */ #define ELOG_TYPE_EC_EVENT 0x91 -#define EC_EVENT_LID_CLOSED 0x01 -#define EC_EVENT_LID_OPEN 0x02 -#define EC_EVENT_POWER_BUTTON 0x03 -#define EC_EVENT_AC_CONNECTED 0x04 -#define EC_EVENT_AC_DISCONNECTED 0x05 -#define EC_EVENT_BATTERY_LOW 0x06 -#define EC_EVENT_BATTERY_CRITICAL 0x07 -#define EC_EVENT_BATTERY 0x08 -#define EC_EVENT_THERMAL_THRESHOLD 0x09 -#define EC_EVENT_DEVICE_EVENT 0x0a -#define EC_EVENT_THERMAL 0x0b -#define EC_EVENT_USB_CHARGER 0x0c -#define EC_EVENT_KEY_PRESSED 0x0d -#define EC_EVENT_INTERFACE_READY 0x0e -#define EC_EVENT_KEYBOARD_RECOVERY 0x0f -#define EC_EVENT_THERMAL_SHUTDOWN 0x10 -#define EC_EVENT_BATTERY_SHUTDOWN 0x11 -#define EC_EVENT_FAN_ERROR 0x12 -#define EC_EVENT_THROTTLE_STOP 0x13 -#define EC_EVENT_HANG_DETECT 0x14 -#define EC_EVENT_HANG_REBOOT 0x15 -#define EC_EVENT_PD_MCU 0x16 -#define EC_EVENT_BATTERY_STATUS 0x17 -#define EC_EVENT_PANIC 0x18 -#define EC_EVENT_KEYBOARD_FASTBOOT 0x19 -#define EC_EVENT_RTC 0x1a -#define EC_EVENT_MKBP 0x1b -#define EC_EVENT_USB_MUX 0x1c -#define EC_EVENT_MODE_CHANGE 0x1d -#define EC_EVENT_KEYBOARD_RECOVERY_HWREINIT 0x1e -#define EC_EVENT_EXTENDED 0x1f /* Power */ #define ELOG_TYPE_POWER_FAIL 0x92 @@ -149,6 +118,18 @@ #define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d #define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e #define ELOG_WAKE_SOURCE_PME_WIFI 0x1f +#define ELOG_WAKE_SOURCE_PME_PCIE13 0x20 +#define ELOG_WAKE_SOURCE_PME_PCIE14 0x21 +#define ELOG_WAKE_SOURCE_PME_PCIE15 0x22 +#define ELOG_WAKE_SOURCE_PME_PCIE16 0x23 +#define ELOG_WAKE_SOURCE_PME_PCIE17 0x24 +#define ELOG_WAKE_SOURCE_PME_PCIE18 0x25 +#define ELOG_WAKE_SOURCE_PME_PCIE19 0x26 +#define ELOG_WAKE_SOURCE_PME_PCIE20 0x27 +#define ELOG_WAKE_SOURCE_PME_PCIE21 0x28 +#define ELOG_WAKE_SOURCE_PME_PCIE22 0x29 +#define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a +#define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b struct elog_event_data_wake { u8 source; diff --git a/src/include/pc80/i8254.h b/src/include/pc80/i8254.h index 794945c244..21e47c2ece 100644 --- a/src/include/pc80/i8254.h +++ b/src/include/pc80/i8254.h @@ -55,5 +55,6 @@ #define PPCB_T2GATE 0x01 /* Bit 0 */ void setup_i8254(void); +unsigned long calibrate_tsc_with_pit(void); #endif /* PC80_I8254_H */ diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 6dec1920b8..1b71fadb1b 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -3,6 +3,7 @@ * * Copyright 2015 Google Inc. * Copyright (C) 2014 Imagination Technologies + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -136,8 +137,19 @@ static inline void prog_set_entry(struct prog *prog, void *e, void *arg) prog->arg = arg; } +static inline void prog_set_arg(struct prog *prog, void *arg) +{ + prog->arg = arg; +} + /* Locate the identified program to run. Return 0 on success. < 0 on error. */ int prog_locate(struct prog *prog); +/* The prog_locate_hook() is called prior to CBFS traversal. The hook can be + * used to implement policy that allows or prohibits further progress through + * prog_locate(). The type and name field within struct prog are the only valid + * fields. A 0 return value allows further progress while a non-zero return + * value prohibits further progress */ +int prog_locate_hook(struct prog *prog); /* Run the program described by prog. */ void prog_run(struct prog *prog); diff --git a/src/include/smbios.h b/src/include/smbios.h index 0bba0a7f9e..d230fb2e1e 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -53,6 +53,9 @@ const char *smbios_system_version(void); void smbios_system_set_uuid(u8 *uuid); const char *smbios_system_sku(void); +unsigned int smbios_cpu_get_max_speed_mhz(void); +unsigned int smbios_cpu_get_current_speed_mhz(void); + const char *smbios_mainboard_manufacturer(void); const char *smbios_mainboard_product_name(void); const char *smbios_mainboard_serial_number(void); @@ -62,7 +65,6 @@ const char *smbios_mainboard_bios_version(void); const char *smbios_mainboard_asset_tag(void); u8 smbios_mainboard_feature_flags(void); const char *smbios_mainboard_location_in_chassis(void); -u8 smbios_mainboard_enclosure_type(void); #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) @@ -139,6 +141,7 @@ typedef enum { MEMORY_FORMFACTOR_SODIMM = 0x0d, MEMORY_FORMFACTOR_SRIMM = 0x0e, MEMORY_FORMFACTOR_FBDIMM = 0x0f, + MEMORY_FORMFACTOR_DIE = 0x10, } smbios_memory_form_factor; typedef enum { @@ -170,6 +173,8 @@ typedef enum { MEMORY_TYPE_LPDDR3 = 0x1d, MEMORY_TYPE_LPDDR4 = 0x1e, MEMORY_TYPE_LOGICAL_NON_VOLATILE_DEVICE = 0x1f, + MEMORY_TYPE_HBM = 0x20, + MEMORY_TYPE_HBM2 = 0x21, } smbios_memory_type; typedef enum { @@ -313,7 +318,7 @@ struct smbios_type2 { u8 eos[2]; } __packed; -enum { +typedef enum { SMBIOS_ENCLOSURE_OTHER = 0x01, SMBIOS_ENCLOSURE_UNKNOWN = 0x02, SMBIOS_ENCLOSURE_DESKTOP = 0x03, @@ -350,7 +355,7 @@ enum { SMBIOS_ENCLOSURE_EMBEDDED_PC = 0x22, SMBIOS_ENCLOSURE_MINI_PC = 0x23, SMBIOS_ENCLOSURE_STICK_PC = 0x24, -}; +} smbios_enclosure_type; struct smbios_type3 { u8 type; @@ -550,7 +555,13 @@ enum misc_slot_type { SlotTypePciExpressGen3X2 = 0xB3, SlotTypePciExpressGen3X4 = 0xB4, SlotTypePciExpressGen3X8 = 0xB5, - SlotTypePciExpressGen3X16 = 0xB6 + SlotTypePciExpressGen3X16 = 0xB6, + SlotTypePciExpressGen4 = 0xB8, + SlotTypePciExpressGen4x1 = 0xB9, + SlotTypePciExpressGen4x2 = 0xBA, + SlotTypePciExpressGen4x4 = 0xBB, + SlotTypePciExpressGen4x8 = 0xBC, + SlotTypePciExpressGen4x16 = 0xBD }; /* System Slots - Slot Data Bus Width. */ @@ -786,5 +797,6 @@ void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t); smbios_board_type smbios_mainboard_board_type(void); +smbios_enclosure_type smbios_mainboard_enclosure_type(void); #endif diff --git a/src/include/superio/hwm5_conf.h b/src/include/superio/hwm5_conf.h new file mode 100644 index 0000000000..bfec0fdef9 --- /dev/null +++ b/src/include/superio/hwm5_conf.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DEVICE_PNP_HWM5_CONF_H +#define DEVICE_PNP_HWM5_CONF_H + +#include + +/* The address/data register pair for the indirect/indexed IO space of the + * hardware monitor (HWM) that does temperature and voltage sensing and fan + * control in ITE, Nuvoton and Winbond super IO chips aren't at offset 0 and 1 + * of the corresponding IO address region, but at offset 5 and 6. */ + +/* + * u8 pnp_read_hwm5_index(u16 port, u8 reg) + * Description: + * This routine reads indexed I/O registers. The reg byte is written + * to the index register at I/O address = port + 5. The result is then + * read from the data register at I/O address = port + 6. + * + * Parameters: + * @param[in] u16 base = The I/O address of the port index register. + * @param[in] u8 reg = The offset within the indexed space. + * @param[out] u8 result = The value read back from the data register. + */ +static inline u8 pnp_read_hwm5_index(u16 base, u8 reg) +{ + return pnp_read_index(base + 5, reg); +} + +/* + * void pnp_write_hwm5_index(u16 port, u8 reg, u8 value) + * Description: + * This routine writes indexed I/O registers. The reg byte is written + * to the index register at I/O address = port + 5. The value byte is then + * written to the data register at I/O address = port + 6. + * + * Parameters: + * @param[in] u16 base = The address of the port index register. + * @param[in] u8 reg = The offset within the indexed space. + * @param[in] u8 value = The value to be written to the data register. + */ +static inline void pnp_write_hwm5_index(u16 base, u8 reg, u8 value) +{ + pnp_write_index(base + 5, reg, value); +} + +#endif /* DEVICE_PNP_HWM5_CONF_H */ diff --git a/src/include/uuid.h b/src/include/uuid.h index 0209055e9e..b8827b0510 100644 --- a/src/include/uuid.h +++ b/src/include/uuid.h @@ -18,6 +18,22 @@ #include +#define UUID_LEN 16 +#define UUID_STRLEN 36 + +/* + * Parses a canonical UUID string into the common byte representation + * where the first three words are interpreted as little endian: + * + * The UUID + * "00112233-4455-6677-8899-aabbccddeeff" + * is stored as + * 33 22 11 00 55 44 77 66 88 99 aa bb cc dd ee ff + * + * Returns negative value on error, 0 on success. + */ +int parse_uuid(uint8_t *uuid, const char *uuid_str); + typedef struct { uint8_t b[16]; } __packed guid_t; diff --git a/src/include/vbe.h b/src/include/vbe.h index cfae7e4025..9497ec68ae 100644 --- a/src/include/vbe.h +++ b/src/include/vbe.h @@ -13,7 +13,8 @@ #ifndef VBE_H #define VBE_H -#include +#include + // these structs are for input from and output to OF typedef struct { u8 display_type; // 0 = NONE, 1 = analog, 2 = digital diff --git a/src/lib/Kconfig b/src/lib/Kconfig index cb1e4a5cc8..b94ac495b7 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -24,6 +24,12 @@ config RAMSTAGE_LIBHWBASE help Selected by features that require `libhwbase` in ramstage. +config RAMSTAGE_CBMEM_TOP_ARG + bool + help + Select this if stages run after romstage get the cbmem_top + pointer as the function arguments when called from romstage. + config FLATTENED_DEVICE_TREE bool help diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e5678ffdf1..da7b4bbdbc 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -346,3 +346,5 @@ cbfs-files-$(CONFIG_GENERIC_SPD_BIN) += spd.bin spd.bin-file := $(LIB_SPD_BIN) spd.bin-type := spd endif + +ramstage-y += uuid.c diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 91368fb67d..9ac1bc084b 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -256,7 +256,7 @@ int cbfs_prog_stage_load(struct prog *pstage) /* Hacky way to not load programs over read only media. The stages * that would hit this path initialize themselves. */ - if (ENV_VERSTAGE && !CONFIG(NO_XIP_EARLY_STAGES) && + if ((ENV_BOOTBLOCK || ENV_VERSTAGE) && !CONFIG(NO_XIP_EARLY_STAGES) && CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) { void *mapping = rdev_mmap(fh, foffset, fsize); rdev_munmap(fh, mapping); @@ -302,7 +302,7 @@ static int cbfs_master_header_props(struct cbfs_props *props) if (rdev_readat(bdev, &rel_offset, offset, sizeof(int32_t)) < 0) return -1; - offset = fmap_top + rel_offset; + offset = fmap_top + (int32_t)le32_to_cpu(rel_offset); if (rdev_readat(bdev, &header, offset, sizeof(header)) < 0) return -1; diff --git a/src/lib/edid.c b/src/lib/edid.c index 964dce260e..fd7f5ba252 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -36,7 +36,6 @@ #include #include #include -#include #include struct edid_context { diff --git a/src/lib/fit.c b/src/lib/fit.c index f1052e8f23..831e5180f0 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -261,12 +261,12 @@ static void update_reserve_map(uint64_t start, uint64_t end, } struct entry_params { - unsigned addr_cells; - unsigned size_cells; + unsigned int addr_cells; + unsigned int size_cells; void *data; }; -static uint64_t max_range(unsigned size_cells) +static uint64_t max_range(unsigned int size_cells) { /* * Split up ranges who's sizes are too large to fit in #size-cells. diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 2ff2b8c874..51ff330d84 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -256,7 +257,12 @@ static void bs_report_time(struct boot_state *state) run_time = mono_time_diff_microseconds(&samples[1], &samples[2]); exit_time = mono_time_diff_microseconds(&samples[2], &samples[3]); - printk(BIOS_DEBUG, "BS: %s times (us): entry %ld run %ld exit %ld\n", + /* Report with millisecond precision to reduce log diffs. */ + entry_time = DIV_ROUND_CLOSEST(entry_time, USECS_PER_MSEC); + run_time = DIV_ROUND_CLOSEST(run_time, USECS_PER_MSEC); + exit_time = DIV_ROUND_CLOSEST(exit_time, USECS_PER_MSEC); + + printk(BIOS_DEBUG, "BS: %s times (ms): entry %ld run %ld exit %ld\n", state->name, entry_time, run_time, exit_time); } #else diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index f04e0862fe..cbd4b8f887 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include +#include #include #include #include @@ -43,6 +45,28 @@ (!CONFIG(ARCH_X86) || ENV_RAMSTAGE || ENV_POSTCAR || \ !CONFIG(CAR_GLOBAL_MIGRATION)) +/* The program loader passes on cbmem_top and the program entry point + has to fill in the _cbmem_top_ptr symbol based on the calling arguments. */ +uintptr_t _cbmem_top_ptr; + +void *cbmem_top(void) +{ + if (ENV_ROMSTAGE + || ((ENV_POSTCAR || ENV_RAMSTAGE) + && !CONFIG(RAMSTAGE_CBMEM_TOP_ARG))) { + MAYBE_STATIC_BSS void *top = NULL; + if (top) + return top; + top = cbmem_top_chipset(); + return top; + } + if ((ENV_POSTCAR || ENV_RAMSTAGE) && CONFIG(RAMSTAGE_CBMEM_TOP_ARG)) + return (void *)_cbmem_top_ptr; + + dead_code(); +} + + static inline struct imd *cbmem_get_imd(void) { if (CAN_USE_GLOBALS) { diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 2ef6bdfc32..183a22bff0 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2015 Google Inc. + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,6 +39,9 @@ int prog_locate(struct prog *prog) { struct cbfsf file; + if (prog_locate_hook(prog)) + return -1; + cbfs_prepare_program_locate(); if (cbfs_boot_locate(&file, prog_name(prog), NULL)) @@ -74,6 +78,8 @@ fail: halt(); } +int __weak prog_locate_hook(struct prog *prog) { return 0; } + static void ramstage_cache_invalid(void) { printk(BIOS_ERR, "ramstage cache invalid.\n"); @@ -90,6 +96,8 @@ static void run_ramstage_from_resume(struct prog *ramstage) /* Load the cached ramstage to runtime location. */ stage_cache_load_stage(STAGE_RAMSTAGE, ramstage); + prog_set_arg(ramstage, cbmem_top()); + if (prog_entry(ramstage) != NULL) { printk(BIOS_DEBUG, "Jumping to image.\n"); prog_run(ramstage); @@ -142,6 +150,9 @@ void run_ramstage(void) timestamp_add_now(TS_END_COPYRAM); + /* This overrides the arg fetched from the relocatable module */ + prog_set_arg(&ramstage, cbmem_top()); + prog_run(&ramstage); fail: diff --git a/src/lib/uuid.c b/src/lib/uuid.c new file mode 100644 index 0000000000..b5c00d7efb --- /dev/null +++ b/src/lib/uuid.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +int parse_uuid(uint8_t *const uuid, const char *const uuid_str) +{ + const uint8_t order[] = { 3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15 }; + uint8_t uuid_binstr[UUID_LEN]; + unsigned int i; + + if (strlen(uuid_str) != UUID_STRLEN) + return -1; + if (uuid_str[8] != '-' || uuid_str[13] != '-' || + uuid_str[18] != '-' || uuid_str[23] != '-') + return -1; + if (hexstrtobin(uuid_str, uuid_binstr, UUID_LEN) != UUID_LEN) + return -1; + for (i = 0; i < UUID_LEN; ++i) + uuid[i] = uuid_binstr[order[i]]; + + return 0; +} diff --git a/src/mainboard/adi/rcc-dff/acpi/platform.asl b/src/mainboard/adi/rcc-dff/acpi/platform.asl index 6ba95ce465..059cd740ff 100644 --- a/src/mainboard/adi/rcc-dff/acpi/platform.asl +++ b/src/mainboard/adi/rcc-dff/acpi/platform.asl @@ -14,44 +14,6 @@ * GNU General Public License for more details. */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _WAK method is called on system wakeup */ Method(_WAK,1) diff --git a/src/mainboard/adi/rcc-dff/dsdt.asl b/src/mainboard/adi/rcc-dff/dsdt.asl index 310ad04741..4aad8a8b15 100644 --- a/src/mainboard/adi/rcc-dff/dsdt.asl +++ b/src/mainboard/adi/rcc-dff/dsdt.asl @@ -31,6 +31,7 @@ DefinitionBlock( #include // Some generic macros + #include #include "acpi/platform.asl" // global NVS and variables @@ -49,5 +50,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/advansus/a785e-i/acpi/cpstate.asl b/src/mainboard/advansus/a785e-i/acpi/cpstate.asl index 5d71c8164f..eb4eac1027 100644 --- a/src/mainboard/advansus/a785e-i/acpi/cpstate.asl +++ b/src/mainboard/advansus/a785e-i/acpi/cpstate.asl @@ -22,17 +22,25 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/advansus/a785e-i/dsdt.asl b/src/mainboard/advansus/a785e-i/dsdt.asl index 4eececb1ab..8015ec6f32 100644 --- a/src/mainboard/advansus/a785e-i/dsdt.asl +++ b/src/mainboard/advansus/a785e-i/dsdt.asl @@ -58,39 +58,24 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - CPU0, /* name space name */ - 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "acpi/cpstate.asl" } - - Processor( - CPU1, /* name space name */ - 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "acpi/cpstate.asl" } - - Processor( - CPU2, /* name space name */ - 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "acpi/cpstate.asl" } - - Processor( - CPU3, /* name space name */ - 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c index 40dec74d93..af943f1212 100644 --- a/src/mainboard/amd/bettong/mptable.c +++ b/src/mainboard/amd/bettong/mptable.c @@ -22,7 +22,7 @@ #include #include -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; mc->mpc_entry_count++; diff --git a/src/mainboard/amd/bimini_fam10/acpi/cpstate.asl b/src/mainboard/amd/bimini_fam10/acpi/cpstate.asl index 206dd686f5..acaa5bae32 100644 --- a/src/mainboard/amd/bimini_fam10/acpi/cpstate.asl +++ b/src/mainboard/amd/bimini_fam10/acpi/cpstate.asl @@ -22,17 +22,25 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/amd/bimini_fam10/dsdt.asl b/src/mainboard/amd/bimini_fam10/dsdt.asl index ed181a36dc..c7196229fd 100644 --- a/src/mainboard/amd/bimini_fam10/dsdt.asl +++ b/src/mainboard/amd/bimini_fam10/dsdt.asl @@ -58,39 +58,24 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - CPU0, /* name space name */ - 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "acpi/cpstate.asl" } - - Processor( - CPU1, /* name space name */ - 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "acpi/cpstate.asl" } - - Processor( - CPU2, /* name space name */ - 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "acpi/cpstate.asl" } - - Processor( - CPU3, /* name space name */ - 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/mahogany_fam10/acpi/cpstate.asl b/src/mainboard/amd/mahogany_fam10/acpi/cpstate.asl index 206dd686f5..acaa5bae32 100644 --- a/src/mainboard/amd/mahogany_fam10/acpi/cpstate.asl +++ b/src/mainboard/amd/mahogany_fam10/acpi/cpstate.asl @@ -22,17 +22,25 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/amd/mahogany_fam10/dsdt.asl b/src/mainboard/amd/mahogany_fam10/dsdt.asl index 9528e01080..63748d7e01 100644 --- a/src/mainboard/amd/mahogany_fam10/dsdt.asl +++ b/src/mainboard/amd/mahogany_fam10/dsdt.asl @@ -58,39 +58,24 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - CPU0, /* name space name */ - 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "acpi/cpstate.asl" } - - Processor( - CPU1, /* name space name */ - 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "acpi/cpstate.asl" } - - Processor( - CPU2, /* name space name */ - 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "acpi/cpstate.asl" } - - Processor( - CPU3, /* name space name */ - 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index c87749e2d4..75d026e00a 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -39,7 +39,7 @@ u8 intr_data[0x54] = { 0x10,0x11,0x12,0x13 }; -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; mc->mpc_entry_count++; diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c index cc5fa304a2..b04f5acb81 100644 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ b/src/mainboard/amd/olivehillplus/mptable.c @@ -39,7 +39,7 @@ u8 intr_data[0x54] = { 0x10,0x11,0x12,0x13 }; -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; mc->mpc_entry_count++; diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index a7d47c2cdd..ea1862495c 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -39,7 +39,7 @@ u8 intr_data[0x54] = { 0x10,0x11,0x12,0x13 }; -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; mc->mpc_entry_count++; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl b/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl index e04bf1d25b..29b146b0d0 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl +++ b/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl @@ -18,10 +18,22 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, OEM_ID, ACPI_TABLE_CREATOR, 100925440) // Scope (_PR) // { -// Processor (CPU0, 0x00, 0x0000C010, 0x06) {} -// Processor (CPU1, 0x01, 0x00000000, 0x00) {} -// Processor (CPU2, 0x02, 0x00000000, 0x00) {} -// Processor (CPU3, 0x03, 0x00000000, 0x00) {} +// Device (CPU0) { +// Name (_HID, "ACPI0007") +// Name (_UID, 0) +// } +// Device (CPU1) { +// Name (_HID, "ACPI0007") +// Name (_UID, 1) +// } +// Device (CPU2) { +// Name (_HID, "ACPI0007") +// Name (_UID, 2) +// } +// Device (CPU3) { +// Name (_HID, "ACPI0007") +// Name (_UID, 3) +// } // } Method (FWSO, 0, NotSerialized) { } @@ -46,7 +58,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, OEM_ID, ACPI_TABLE_CREATOR, 100925440) External (CBB2) Name (_HID, EisaId ("PNP0A03")) - Name (_ADR, 0x00000000) Name (_UID, 0x01) Name (HCIN, 0x00) // HC1 @@ -118,7 +129,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, OEM_ID, ACPI_TABLE_CREATOR, 100925440) Device (PCI1) { Name (_HID, "PNP0A03") - Name (_ADR, 0x00000000) Name (_UID, 0x02) Method (_STA, 0, NotSerialized) { @@ -133,7 +143,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, OEM_ID, ACPI_TABLE_CREATOR, 100925440) Device (PCI2) { Name (_HID, "PNP0A03") - Name (_ADR, 0x00000000) Name (_UID, 0x02) Method (_STA, 0, NotSerialized) { diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c index 845af71c92..9f6d48c151 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c @@ -35,7 +35,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ /* Prepare the header */ memset((void *)fadt,0,sizeof(acpi_fadt_t)); memcpy(header->signature,"FACP",4); - header->length = 244; + header->length = sizeof(acpi_fadt_t); header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); diff --git a/src/mainboard/amd/thatcher/acpi/cpstate.asl b/src/mainboard/amd/thatcher/acpi/cpstate.asl index 69de2d86a3..3cbc0ad60b 100644 --- a/src/mainboard/amd/thatcher/acpi/cpstate.asl +++ b/src/mainboard/amd/thatcher/acpi/cpstate.asl @@ -22,17 +22,25 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index 403a282d55..f7698bb16f 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -39,7 +39,7 @@ u8 intr_data[0x54] = { 0x10,0x11,0x12,0x13 }; -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; mc->mpc_entry_count++; diff --git a/src/mainboard/amd/tilapia_fam10/acpi/cpstate.asl b/src/mainboard/amd/tilapia_fam10/acpi/cpstate.asl index 206dd686f5..acaa5bae32 100644 --- a/src/mainboard/amd/tilapia_fam10/acpi/cpstate.asl +++ b/src/mainboard/amd/tilapia_fam10/acpi/cpstate.asl @@ -22,17 +22,25 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/amd/tilapia_fam10/dsdt.asl b/src/mainboard/amd/tilapia_fam10/dsdt.asl index f174976491..f9f7e18abb 100644 --- a/src/mainboard/amd/tilapia_fam10/dsdt.asl +++ b/src/mainboard/amd/tilapia_fam10/dsdt.asl @@ -58,39 +58,24 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - CPU0, /* name space name */ - 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "acpi/cpstate.asl" } - - Processor( - CPU1, /* name space name */ - 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "acpi/cpstate.asl" } - - Processor( - CPU2, /* name space name */ - 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "acpi/cpstate.asl" } - - Processor( - CPU3, /* name space name */ - 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index 9626ec66fa..48f8e1fe30 100644 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -45,33 +45,21 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ - 0, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (C000) { + Name (_HID, "ACPI0007") + Name (_UID, 0) } - Processor( - C001, /* name space name */ - 1, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (C001) { + Name (_HID, "ACPI0007") + Name (_UID, 1) } - Processor( - C002, /* name space name */ - 2, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (C002) { + Name (_HID, "ACPI0007") + Name (_UID, 2) } - Processor( - C003, /* name space name */ - 3, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (C003) { + Name (_HID, "ACPI0007") + Name (_UID, 3) } } /* End _PR scope */ diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index 9e33c07fc8..08763bd82a 100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c @@ -49,8 +49,8 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) /* Prepare the header */ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); - header->length = 244; - header->revision = 1; + header->length = sizeof(acpi_fadt_t); + header->revision = ACPI_FADT_REV_ACPI_1_0; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index 743651e1f0..811154379f 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -43,7 +43,7 @@ u8 intr_data[] = { 0x10,0x11,0x12,0x13 }; -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; mc->mpc_entry_count++; @@ -64,9 +64,9 @@ static void *smp_write_config_table(void *v) struct mp_config_table *mc; int bus_isa; int boot_apic_id; - unsigned apic_version; - unsigned cpu_features; - unsigned cpu_feature_flags; + unsigned int apic_version; + unsigned int cpu_features; + unsigned int cpu_feature_flags; struct cpuid_result result; unsigned long cpu_flag; diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl index af8012efe8..4fde2442e9 100644 --- a/src/mainboard/aopen/dxplplusu/dsdt.asl +++ b/src/mainboard/aopen/dxplplusu/dsdt.asl @@ -28,7 +28,6 @@ Scope(\_SB) { Device(PCI0) { Name (_HID, EISAID("PNP0A03")) - Name (_ADR, 0x00) Name (_PRT, Package() { Package() { 0x001dffff, 0, 0, 16 }, Package() { 0x001dffff, 1, 0, 19 }, diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index 830c0c8741..40af217c47 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -46,5 +46,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 32a7871ecf..34cd378839 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -175,12 +175,12 @@ static void early_ich7_init(void) uint32_t reg32; /* program secondary mlt XXX byte? */ - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); /* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); /* usb transient disconnect */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); @@ -195,31 +195,7 @@ static void early_ich7_init(void) reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - /* next step only on ich7m b0 and later: */ - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) @@ -250,9 +226,8 @@ void mainboard_romstage_entry(void) /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(); sdram_initialize(s3resume ? 2 : 0, spd_addrmap); diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c index 88cc4c0eb6..6e8601b434 100644 --- a/src/mainboard/apple/macbook21/smihandler.c +++ b/src/mainboard/apple/macbook21/smihandler.c @@ -21,30 +21,6 @@ #define GPE_EC_SCI 12 -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); -} - -int mainboard_io_trap_handler(int smif) -{ - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - - switch (smif) { - default: - return 0; - } - - /* On success, the IO Trap Handler returns 1 - * On failure, the IO Trap Handler returns a value != 1 */ - return 1; -} - int mainboard_smi_apmc(u8 data) { switch (data) { diff --git a/src/mainboard/apple/macbookair4_2/dsdt.asl b/src/mainboard/apple/macbookair4_2/dsdt.asl index 65ce63ea6e..91e0b2087f 100644 --- a/src/mainboard/apple/macbookair4_2/dsdt.asl +++ b/src/mainboard/apple/macbookair4_2/dsdt.asl @@ -27,10 +27,10 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/asrock/b75pro3-m/dsdt.asl b/src/mainboard/asrock/b75pro3-m/dsdt.asl index 467a001dac..e1b28db377 100644 --- a/src/mainboard/asrock/b75pro3-m/dsdt.asl +++ b/src/mainboard/asrock/b75pro3-m/dsdt.asl @@ -30,10 +30,10 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c index cbd26a52ac..da895b31fd 100644 --- a/src/mainboard/asrock/b75pro3-m/romstage.c +++ b/src/mainboard/asrock/b75pro3-m/romstage.c @@ -25,9 +25,6 @@ void pch_enable_lpc(void) { - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0000); } void mainboard_rcba_config(void) diff --git a/src/mainboard/asrock/g41c-gs/Kconfig b/src/mainboard/asrock/g41c-gs/Kconfig index e7cbf7aeb1..81b0995988 100644 --- a/src/mainboard/asrock/g41c-gs/Kconfig +++ b/src/mainboard/asrock/g41c-gs/Kconfig @@ -30,9 +30,6 @@ config BOARD_SPECIFIC_OPTIONS || BOARD_ASROCK_G41M_VS3_R2_0 select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_L1_SUB_STATE select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME diff --git a/src/mainboard/asrock/g41c-gs/acpi/platform.asl b/src/mainboard/asrock/g41c-gs/acpi/platform.asl deleted file mode 100644 index 6c92a4ed47..0000000000 --- a/src/mainboard/asrock/g41c-gs/acpi/platform.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Method(_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store(Arg0, PICM) -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) /* SMI Function */ - Store (0, TRP0) /* Generate trap */ - Return (SMIF) /* Return value of SMI handler */ -} diff --git a/src/mainboard/asrock/g41c-gs/dsdt.asl b/src/mainboard/asrock/g41c-gs/dsdt.asl index 002dfcaeb6..31e7c10d3e 100644 --- a/src/mainboard/asrock/g41c-gs/dsdt.asl +++ b/src/mainboard/asrock/g41c-gs/dsdt.asl @@ -25,7 +25,7 @@ DefinitionBlock( ) { // global NVS and variables - #include "acpi/platform.asl" + #include #include Scope (\_SB) { @@ -38,5 +38,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 0228499181..bb7a342d75 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -36,7 +36,6 @@ static void mb_lpc_setup(void) { - u32 reg32; /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); @@ -65,11 +64,7 @@ static void mb_lpc_setup(void) RCBA8(OIC) = 0x03; RCBA8(OIC); - reg32 = RCBA32(GCS); - reg32 |= (1 << 5); - RCBA32(GCS) = reg32; - - RCBA32(CG) = 0x00000001; + ich7_setup_cir(); } static void ich7_enable_lpc(void) diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index acb2a9e629..b2a2d72df2 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -415,10 +415,10 @@ chip soc/intel/skylake device pnp 2e.14 off end # SVID, Port 80 UART device pnp 2e.16 off end # DS5 device pnp 2e.116 off end # DS3 - device pnp 2e.316 off end # PCHDSW + device pnp 2e.316 on end # PCHDSW device pnp 2e.416 off end # DSWWOPT - device pnp 2e.516 off end # DS3OPT - device pnp 2e.616 off end # DSDSS + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 on end # DSDSS device pnp 2e.716 off end # DSPU end # superio/nuvoton/nct6791d chip drivers/pc80/tpm diff --git a/src/mainboard/asrock/h110m/dsdt.asl b/src/mainboard/asrock/h110m/dsdt.asl index f3e216d4c1..0b3baf6153 100644 --- a/src/mainboard/asrock/h110m/dsdt.asl +++ b/src/mainboard/asrock/h110m/dsdt.asl @@ -48,7 +48,7 @@ DefinitionBlock( } // Chipset specific sleep states - #include + #include // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/asrock/h81m-hds/dsdt.asl b/src/mainboard/asrock/h81m-hds/dsdt.asl index f76c393bb0..8c4d5b8d5d 100644 --- a/src/mainboard/asrock/h81m-hds/dsdt.asl +++ b/src/mainboard/asrock/h81m-hds/dsdt.asl @@ -25,9 +25,9 @@ DefinitionBlock( ) { #include "acpi/platform.asl" - #include + #include #include - #include + #include #include Scope (\_SB) diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index b64198092e..a3c8e517bb 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -40,7 +40,7 @@ u8 intr_data[0x54] = { 0x10,0x11,0x12,0x13 }; -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; mc->mpc_entry_count++; diff --git a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl index 69de2d86a3..3cbc0ad60b 100644 --- a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl +++ b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl @@ -22,17 +22,25 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index 238ab5163d..f13e3e8ba7 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -54,7 +54,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 14.1 off end # unused device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x780e - chip superio/nuvoton/nct5572d + chip superio/nuvoton/nct6779d device pnp 2e.0 off end # FDC device pnp 2e.1 off end # LPT1 device pnp 2e.2 on # COM1 diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index 0811fd2e1c..8bfe4d535a 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -39,7 +39,7 @@ u8 intr_data[0x54] = { 0x10,0x11,0x12,0x13 }; -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; mc->mpc_entry_count++; diff --git a/src/mainboard/asus/h61m-cs/dsdt.asl b/src/mainboard/asus/h61m-cs/dsdt.asl index 8452191676..dc7a3674ae 100644 --- a/src/mainboard/asus/h61m-cs/dsdt.asl +++ b/src/mainboard/asus/h61m-cs/dsdt.asl @@ -27,10 +27,10 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Device (\_SB.PCI0) { #include diff --git a/src/mainboard/asus/h61m-cs/romstage.c b/src/mainboard/asus/h61m-cs/romstage.c index 94f58c1e36..2064f14e22 100644 --- a/src/mainboard/asus/h61m-cs/romstage.c +++ b/src/mainboard/asus/h61m-cs/romstage.c @@ -29,7 +29,6 @@ void pch_enable_lpc(void) { - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN); } void mainboard_rcba_config(void) diff --git a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c index dd7ebc962c..62f1af6ac2 100644 --- a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c +++ b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c @@ -32,11 +32,11 @@ */ /* busnum is default */ unsigned char bus_ck804[6]; -unsigned apicid_ck804; +unsigned int apicid_ck804; void get_bus_conf(void) { - unsigned apicid_base, sbdn; + unsigned int apicid_base, sbdn; struct device *dev; int i; diff --git a/src/mainboard/asus/kfsn4-dre/irq_tables.c b/src/mainboard/asus/kfsn4-dre/irq_tables.c index c1bd3058ab..3fa72d732c 100644 --- a/src/mainboard/asus/kfsn4-dre/irq_tables.c +++ b/src/mainboard/asus/kfsn4-dre/irq_tables.c @@ -64,7 +64,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) { struct irq_routing_table *pirq; struct irq_info *pirq_info; - unsigned slot_num, sbdn; + unsigned int slot_num, sbdn; uint8_t *v, sum = 0; int i; diff --git a/src/mainboard/asus/kfsn4-dre/mptable.c b/src/mainboard/asus/kfsn4-dre/mptable.c index 10a379844d..7ceb72062a 100644 --- a/src/mainboard/asus/kfsn4-dre/mptable.c +++ b/src/mainboard/asus/kfsn4-dre/mptable.c @@ -29,12 +29,12 @@ #include extern unsigned char bus_ck804[6]; -extern unsigned apicid_ck804; +extern unsigned int apicid_ck804; static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - unsigned sbdn; + unsigned int sbdn; int bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 22eb1157b9..7d710d73a2 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -65,7 +65,7 @@ int spd_read_byte(unsigned int device, unsigned int address) * @param[in] bus target bus number * @return southbridge device number */ -unsigned int get_sbdn(unsigned bus) +unsigned int get_sbdn(unsigned int bus) { pci_devfn_t dev; @@ -114,7 +114,7 @@ static const unsigned int ctrl_conf_enable_msi_mapping[] = { static void ck804_control(const unsigned int *values, u32 size, uint8_t bus_unit_id) { - unsigned busn[4], io_base[4]; + unsigned int busn[4], io_base[4]; int i, ck804_num = 0; for (i = 0; i < 4; i++) { diff --git a/src/mainboard/asus/m4a78-em/acpi/cpstate.asl b/src/mainboard/asus/m4a78-em/acpi/cpstate.asl index 206dd686f5..acaa5bae32 100644 --- a/src/mainboard/asus/m4a78-em/acpi/cpstate.asl +++ b/src/mainboard/asus/m4a78-em/acpi/cpstate.asl @@ -22,17 +22,25 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/asus/m4a78-em/dsdt.asl b/src/mainboard/asus/m4a78-em/dsdt.asl index 3059be9a37..eec3093b8e 100644 --- a/src/mainboard/asus/m4a78-em/dsdt.asl +++ b/src/mainboard/asus/m4a78-em/dsdt.asl @@ -58,39 +58,24 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - CPU0, /* name space name */ - 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "acpi/cpstate.asl" } - - Processor( - CPU1, /* name space name */ - 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "acpi/cpstate.asl" } - - Processor( - CPU2, /* name space name */ - 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "acpi/cpstate.asl" } - - Processor( - CPU3, /* name space name */ - 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/asus/m4a785-m/acpi/cpstate.asl b/src/mainboard/asus/m4a785-m/acpi/cpstate.asl index 206dd686f5..acaa5bae32 100644 --- a/src/mainboard/asus/m4a785-m/acpi/cpstate.asl +++ b/src/mainboard/asus/m4a785-m/acpi/cpstate.asl @@ -22,17 +22,25 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/asus/m4a785-m/dsdt.asl b/src/mainboard/asus/m4a785-m/dsdt.asl index 3059be9a37..eec3093b8e 100644 --- a/src/mainboard/asus/m4a785-m/dsdt.asl +++ b/src/mainboard/asus/m4a785-m/dsdt.asl @@ -58,39 +58,24 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - CPU0, /* name space name */ - 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "acpi/cpstate.asl" } - - Processor( - CPU1, /* name space name */ - 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "acpi/cpstate.asl" } - - Processor( - CPU2, /* name space name */ - 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "acpi/cpstate.asl" } - - Processor( - CPU3, /* name space name */ - 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl index f8cfda2424..e9a93c0466 100644 --- a/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl +++ b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl @@ -22,17 +22,25 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl index debbb8cffd..20d74d0426 100644 --- a/src/mainboard/asus/m4a785t-m/dsdt.asl +++ b/src/mainboard/asus/m4a785t-m/dsdt.asl @@ -58,39 +58,24 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - CPU0, /* name space name */ - 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "acpi/cpstate.asl" } - - Processor( - CPU1, /* name space name */ - 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "acpi/cpstate.asl" } - - Processor( - CPU2, /* name space name */ - 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "acpi/cpstate.asl" } - - Processor( - CPU3, /* name space name */ - 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/asus/m5a88-v/acpi/cpstate.asl b/src/mainboard/asus/m5a88-v/acpi/cpstate.asl index 5d71c8164f..eb4eac1027 100644 --- a/src/mainboard/asus/m5a88-v/acpi/cpstate.asl +++ b/src/mainboard/asus/m5a88-v/acpi/cpstate.asl @@ -22,17 +22,25 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/asus/m5a88-v/dsdt.asl b/src/mainboard/asus/m5a88-v/dsdt.asl index 0b5f25af56..3d2a781a9a 100644 --- a/src/mainboard/asus/m5a88-v/dsdt.asl +++ b/src/mainboard/asus/m5a88-v/dsdt.asl @@ -58,39 +58,24 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - CPU0, /* name space name */ - 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "acpi/cpstate.asl" } - - Processor( - CPU1, /* name space name */ - 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "acpi/cpstate.asl" } - - Processor( - CPU2, /* name space name */ - 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "acpi/cpstate.asl" } - - Processor( - CPU3, /* name space name */ - 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl index e3abc26303..0cdc58c0ef 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl +++ b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl @@ -26,9 +26,9 @@ DefinitionBlock( { #include "acpi/platform.asl" #include - #include + #include #include - #include + #include Scope (\_SB) { diff --git a/src/mainboard/asus/maximus_iv_gene-z/romstage.c b/src/mainboard/asus/maximus_iv_gene-z/romstage.c index f0506fb84e..fcf78d2e68 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/romstage.c +++ b/src/mainboard/asus/maximus_iv_gene-z/romstage.c @@ -42,7 +42,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { void pch_enable_lpc(void) { - pci_or_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN); } void mainboard_rcba_config(void) diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl index 89cc66d834..83e1df6bc4 100644 --- a/src/mainboard/asus/p2b-ls/dsdt.asl +++ b/src/mainboard/asus/p2b-ls/dsdt.asl @@ -128,7 +128,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) Device (PCI0) { Name (_HID, EisaId ("PNP0A03")) - Name (_ADR, 0x00) Name (_UID, 0x00) Name (_BBN, 0x00) diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 4a58c0781a..279f772e96 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -124,7 +124,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) Device (PCI0) { Name (_HID, EisaId ("PNP0A03")) - Name (_ADR, 0x00) Name (_UID, 0x00) Name (_BBN, 0x00) diff --git a/src/mainboard/asus/p5gc-mx/dsdt.asl b/src/mainboard/asus/p5gc-mx/dsdt.asl index 7b6bdf81a7..66f0efe49d 100644 --- a/src/mainboard/asus/p5gc-mx/dsdt.asl +++ b/src/mainboard/asus/p5gc-mx/dsdt.asl @@ -50,5 +50,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 632ef05573..58dac6e71c 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -125,12 +125,12 @@ static void early_ich7_init(void) uint32_t reg32; // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); // usb transient disconnect reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); @@ -145,31 +145,7 @@ static void early_ich7_init(void) reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030509; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) diff --git a/src/mainboard/asus/p5qc/acpi/platform.asl b/src/mainboard/asus/p5qc/acpi/platform.asl deleted file mode 100644 index 6c92a4ed47..0000000000 --- a/src/mainboard/asus/p5qc/acpi/platform.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Method(_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store(Arg0, PICM) -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) /* SMI Function */ - Store (0, TRP0) /* Generate trap */ - Return (SMIF) /* Return value of SMI handler */ -} diff --git a/src/mainboard/asus/p5qc/dsdt.asl b/src/mainboard/asus/p5qc/dsdt.asl index 5ec7c19be7..b9b5adcc24 100644 --- a/src/mainboard/asus/p5qc/dsdt.asl +++ b/src/mainboard/asus/p5qc/dsdt.asl @@ -25,7 +25,7 @@ DefinitionBlock( ) { // global NVS and variables - #include "acpi/platform.asl" + #include #include Scope (\_SB) { @@ -38,5 +38,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/asus/p5qpl-am/Kconfig b/src/mainboard/asus/p5qpl-am/Kconfig index 7eee9cddca..7cdfea9048 100644 --- a/src/mainboard/asus/p5qpl-am/Kconfig +++ b/src/mainboard/asus/p5qpl-am/Kconfig @@ -25,9 +25,6 @@ config BOARD_SPECIFIC_OPTIONS select SUPERIO_WINBOND_W83627DHG select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_L1_SUB_STATE select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME diff --git a/src/mainboard/asus/p5qpl-am/acpi/platform.asl b/src/mainboard/asus/p5qpl-am/acpi/platform.asl deleted file mode 100644 index 6c92a4ed47..0000000000 --- a/src/mainboard/asus/p5qpl-am/acpi/platform.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Method(_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store(Arg0, PICM) -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) /* SMI Function */ - Store (0, TRP0) /* Generate trap */ - Return (SMIF) /* Return value of SMI handler */ -} diff --git a/src/mainboard/asus/p5qpl-am/dsdt.asl b/src/mainboard/asus/p5qpl-am/dsdt.asl index 002dfcaeb6..31e7c10d3e 100644 --- a/src/mainboard/asus/p5qpl-am/dsdt.asl +++ b/src/mainboard/asus/p5qpl-am/dsdt.asl @@ -25,7 +25,7 @@ DefinitionBlock( ) { // global NVS and variables - #include "acpi/platform.asl" + #include #include Scope (\_SB) { @@ -38,5 +38,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index dc589a5918..30480ad3d5 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -131,7 +131,6 @@ static int setup_sio_gpio(void) static void mb_lpc_setup(void) { - u32 reg32; /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); @@ -142,10 +141,7 @@ static void mb_lpc_setup(void) RCBA8(0x31ff) = 0x03; RCBA8(0x31ff); - reg32 = RCBA32(GCS); - reg32 |= (1 << 5); - RCBA32(GCS) = reg32; - RCBA32(CG) = 0x00000001; + ich7_setup_cir(); } static void ich7_enable_lpc(void) diff --git a/src/mainboard/asus/p8h61-m_lx/dsdt.asl b/src/mainboard/asus/p8h61-m_lx/dsdt.asl index e3abc26303..0cdc58c0ef 100644 --- a/src/mainboard/asus/p8h61-m_lx/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_lx/dsdt.asl @@ -26,9 +26,9 @@ DefinitionBlock( { #include "acpi/platform.asl" #include - #include + #include #include - #include + #include Scope (\_SB) { diff --git a/src/mainboard/asus/p8h61-m_pro/dsdt.asl b/src/mainboard/asus/p8h61-m_pro/dsdt.asl index d9861ef607..c2b46f333b 100644 --- a/src/mainboard/asus/p8h61-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_pro/dsdt.asl @@ -28,11 +28,11 @@ DefinitionBlock( #include "acpi/platform.asl" #include "acpi/superio.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl index 89ad30c997..62d44eabe9 100644 --- a/src/mainboard/asus/p8z77-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8z77-m_pro/dsdt.asl @@ -29,10 +29,10 @@ DefinitionBlock( #include "acpi/platform.asl" #include "acpi/superio.asl" #include - #include + #include #include - #include + #include Device (\_SB.PCI0) { diff --git a/src/mainboard/asus/p8z77-m_pro/romstage.c b/src/mainboard/asus/p8z77-m_pro/romstage.c index b5593ec23c..9c5e443908 100644 --- a/src/mainboard/asus/p8z77-m_pro/romstage.c +++ b/src/mainboard/asus/p8z77-m_pro/romstage.c @@ -32,12 +32,6 @@ void pch_enable_lpc(void) { - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF1_LPC_EN | CNF2_LPC_EN | - KBC_LPC_EN | COMB_LPC_EN); - - /* Set COMB/COM2 IO range to 2F8h-2FFh */ - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); } void mainboard_rcba_config(void) diff --git a/src/mainboard/avalue/eax-785e/acpi/cpstate.asl b/src/mainboard/avalue/eax-785e/acpi/cpstate.asl index 5d71c8164f..eb4eac1027 100644 --- a/src/mainboard/avalue/eax-785e/acpi/cpstate.asl +++ b/src/mainboard/avalue/eax-785e/acpi/cpstate.asl @@ -22,17 +22,25 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/avalue/eax-785e/dsdt.asl b/src/mainboard/avalue/eax-785e/dsdt.asl index 4eececb1ab..8015ec6f32 100644 --- a/src/mainboard/avalue/eax-785e/dsdt.asl +++ b/src/mainboard/avalue/eax-785e/dsdt.asl @@ -58,39 +58,24 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - CPU0, /* name space name */ - 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "acpi/cpstate.asl" } - - Processor( - CPU1, /* name space name */ - 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "acpi/cpstate.asl" } - - Processor( - CPU2, /* name space name */ - 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "acpi/cpstate.asl" } - - Processor( - CPU3, /* name space name */ - 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/bap/ode_e21XX/mptable.c b/src/mainboard/bap/ode_e21XX/mptable.c index cc5fa304a2..b04f5acb81 100644 --- a/src/mainboard/bap/ode_e21XX/mptable.c +++ b/src/mainboard/bap/ode_e21XX/mptable.c @@ -39,7 +39,7 @@ u8 intr_data[0x54] = { 0x10,0x11,0x12,0x13 }; -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; mc->mpc_entry_count++; diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c index c87749e2d4..75d026e00a 100644 --- a/src/mainboard/biostar/a68n_5200/mptable.c +++ b/src/mainboard/biostar/a68n_5200/mptable.c @@ -39,7 +39,7 @@ u8 intr_data[0x54] = { 0x10,0x11,0x12,0x13 }; -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; mc->mpc_entry_count++; diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index 721df67d1d..c83a86585d 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -24,8 +24,6 @@ #include #include - -#define ITE_CONFIG_REG_CC 0x02 #define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) #define ENVC_DEV PNP_DEV(0x2e, IT8728F_EC) @@ -34,62 +32,42 @@ #define MMIO_NON_POSTED_END 0xfedfffff #define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) - -static void it_sio_write(pnp_devfn_t dev, u8 reg, u8 value) -{ - pnp_set_logical_device(dev); - pnp_write_config(dev, reg, value); -} - -static void ite_enter_conf(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void ite_exit_conf(pnp_devfn_t dev) -{ - it_sio_write(dev, ITE_CONFIG_REG_CC, 0x02); -} - static void ite_evc_conf(pnp_devfn_t dev) { - ite_enter_conf(dev); - it_sio_write(dev, 0xf1, 0x40); - it_sio_write(dev, 0xf4, 0x80); - it_sio_write(dev, 0xf5, 0x00); - it_sio_write(dev, 0xf6, 0xf0); - it_sio_write(dev, 0xf9, 0x48); - it_sio_write(dev, 0xfa, 0x00); - it_sio_write(dev, 0xfb, 0x00); - ite_exit_conf(dev); + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_write_config(dev, 0xf1, 0x40); + pnp_write_config(dev, 0xf4, 0x80); + pnp_write_config(dev, 0xf5, 0x00); + pnp_write_config(dev, 0xf6, 0xf0); + pnp_write_config(dev, 0xf9, 0x48); + pnp_write_config(dev, 0xfa, 0x00); + pnp_write_config(dev, 0xfb, 0x00); + pnp_exit_conf_state(dev); } static void ite_gpio_conf(pnp_devfn_t dev) { - ite_enter_conf (dev); - it_sio_write(dev, 0x25, 0x80); - it_sio_write(dev, 0x26, 0x07); - it_sio_write(dev, 0x28, 0x81); - it_sio_write(dev, 0x2c, 0x06); - it_sio_write(dev, 0x72, 0x00); - it_sio_write(dev, 0x73, 0x00); - it_sio_write(dev, 0xb3, 0x01); - it_sio_write(dev, 0xb8, 0x00); - it_sio_write(dev, 0xc0, 0x00); - it_sio_write(dev, 0xc3, 0x00); - it_sio_write(dev, 0xc8, 0x00); - it_sio_write(dev, 0xc9, 0x07); - it_sio_write(dev, 0xcb, 0x01); - it_sio_write(dev, 0xf0, 0x10); - it_sio_write(dev, 0xf4, 0x27); - it_sio_write(dev, 0xf8, 0x20); - it_sio_write(dev, 0xf9, 0x01); - ite_exit_conf(dev); + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_write_config(dev, 0x25, 0x80); + pnp_write_config(dev, 0x26, 0x07); + pnp_write_config(dev, 0x28, 0x81); + pnp_write_config(dev, 0x2c, 0x06); + pnp_write_config(dev, 0x72, 0x00); + pnp_write_config(dev, 0x73, 0x00); + pnp_write_config(dev, 0xb3, 0x01); + pnp_write_config(dev, 0xb8, 0x00); + pnp_write_config(dev, 0xc0, 0x00); + pnp_write_config(dev, 0xc3, 0x00); + pnp_write_config(dev, 0xc8, 0x00); + pnp_write_config(dev, 0xc9, 0x07); + pnp_write_config(dev, 0xcb, 0x01); + pnp_write_config(dev, 0xf0, 0x10); + pnp_write_config(dev, 0xf4, 0x27); + pnp_write_config(dev, 0xf8, 0x20); + pnp_write_config(dev, 0xf9, 0x01); + pnp_exit_conf_state(dev); } void board_BeforeAgesa(struct sysinfo *cb) diff --git a/src/mainboard/compulab/intense_pc/dsdt.asl b/src/mainboard/compulab/intense_pc/dsdt.asl index ad0940c275..4e4351670b 100644 --- a/src/mainboard/compulab/intense_pc/dsdt.asl +++ b/src/mainboard/compulab/intense_pc/dsdt.asl @@ -30,10 +30,10 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index 74f00c21d1..f74e94d042 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -26,9 +26,6 @@ void pch_enable_lpc(void) { pci_devfn_t dev = PCH_LPC_DEV; - /* Set COM1/COM2 decode range */ - pci_write_config16(dev, LPC_IO_DEC, 0x0010); - /* Enable SuperIO */ u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN; pci_write_config16(dev, LPC_EN, lpc_config); diff --git a/src/mainboard/emulation/qemu-aarch64/Makefile.inc b/src/mainboard/emulation/qemu-aarch64/Makefile.inc index 38ecdd1a7b..dc0e9f462f 100644 --- a/src/mainboard/emulation/qemu-aarch64/Makefile.inc +++ b/src/mainboard/emulation/qemu-aarch64/Makefile.inc @@ -6,7 +6,6 @@ # SPDX-License-Identifier: GPL-2.0-or-later romstage-y += cbmem.c -ramstage-y += cbmem.c bootblock-y += media.c romstage-y += media.c diff --git a/src/mainboard/emulation/qemu-aarch64/cbmem.c b/src/mainboard/emulation/qemu-aarch64/cbmem.c index c50254df29..43894333e4 100644 --- a/src/mainboard/emulation/qemu-aarch64/cbmem.c +++ b/src/mainboard/emulation/qemu-aarch64/cbmem.c @@ -10,7 +10,7 @@ #include #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc index d5742e1aad..c62915bc78 100644 --- a/src/mainboard/emulation/qemu-armv7/Makefile.inc +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -15,7 +15,6 @@ romstage-y += romstage.c romstage-y += cbmem.c -ramstage-y += cbmem.c bootblock-y += media.c romstage-y += media.c diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c index 542e08d05e..143e11b88c 100644 --- a/src/mainboard/emulation/qemu-armv7/cbmem.c +++ b/src/mainboard/emulation/qemu-armv7/cbmem.c @@ -15,7 +15,7 @@ #include #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/mainboard/emulation/qemu-i440fx/dsdt.asl b/src/mainboard/emulation/qemu-i440fx/dsdt.asl index e4be1139f3..9bef7d9c18 100644 --- a/src/mainboard/emulation/qemu-i440fx/dsdt.asl +++ b/src/mainboard/emulation/qemu-i440fx/dsdt.asl @@ -34,7 +34,6 @@ DefinitionBlock ( Scope(\_SB) { Device(PCI0) { Name(_HID, EisaId("PNP0A03")) - Name(_ADR, 0x00) Name(_UID, 1) } } diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index 8209379bef..098b3c2632 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -52,7 +52,7 @@ unsigned long qemu_get_memory_size(void) return tomk; } -void *cbmem_top(void) +void *cbmem_top_chipset(void) { uintptr_t top = 0; diff --git a/src/mainboard/emulation/qemu-power8/Makefile.inc b/src/mainboard/emulation/qemu-power8/Makefile.inc index 5c6c56e5de..307cb191bd 100644 --- a/src/mainboard/emulation/qemu-power8/Makefile.inc +++ b/src/mainboard/emulation/qemu-power8/Makefile.inc @@ -15,7 +15,6 @@ bootblock-y += bootblock.c bootblock-y += uart.c romstage-y += cbmem.c -ramstage-y += cbmem.c romstage-y += romstage.c ramstage-y += timer.c romstage-y += uart.c diff --git a/src/mainboard/emulation/qemu-power8/cbmem.c b/src/mainboard/emulation/qemu-power8/cbmem.c index 3df6b802e7..7d6d4a80d9 100644 --- a/src/mainboard/emulation/qemu-power8/cbmem.c +++ b/src/mainboard/emulation/qemu-power8/cbmem.c @@ -15,7 +15,7 @@ #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ /* For now, last 1M of 4G */ diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl index a861aed55c..ea17df21e2 100644 --- a/src/mainboard/emulation/qemu-q35/dsdt.asl +++ b/src/mainboard/emulation/qemu-q35/dsdt.asl @@ -49,7 +49,6 @@ DefinitionBlock ( Device(PCI0) { Name(_HID, EisaId("PNP0A08")) Name(_CID, EisaId("PNP0A03")) - Name(_ADR, 0x00) Name(_UID, 1) // _OSC: based on sample of ACPI3.0b spec diff --git a/src/mainboard/emulation/qemu-riscv/romstage.c b/src/mainboard/emulation/qemu-riscv/romstage.c index 684b2490a0..52c69f93d6 100644 --- a/src/mainboard/emulation/qemu-riscv/romstage.c +++ b/src/mainboard/emulation/qemu-riscv/romstage.c @@ -13,11 +13,13 @@ * GNU General Public License for more details. */ +#include #include #include void main(void) { console_init(); + cbmem_initialize_empty(); run_ramstage(); } diff --git a/src/mainboard/emulation/spike-riscv/romstage.c b/src/mainboard/emulation/spike-riscv/romstage.c index 205c89e155..b3d1b4d559 100644 --- a/src/mainboard/emulation/spike-riscv/romstage.c +++ b/src/mainboard/emulation/spike-riscv/romstage.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include @@ -20,6 +21,8 @@ void main(void) { console_init(); + cbmem_initialize_empty(); + //query_mem(configstring(), &base, &size); //printk(BIOS_SPEW, "0x%zx bytes of memory at 0x%llx\n", size, base); diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c index eeb0b5798a..b44c7b3496 100644 --- a/src/mainboard/emulation/spike-riscv/uart.c +++ b/src/mainboard/emulation/spike-riscv/uart.c @@ -15,7 +15,6 @@ #include #include -#include uintptr_t uart_platform_base(int idx) { diff --git a/src/mainboard/esd/atom15/dsdt.asl b/src/mainboard/esd/atom15/dsdt.asl index 3719154bdd..bea6af7973 100644 --- a/src/mainboard/esd/atom15/dsdt.asl +++ b/src/mainboard/esd/atom15/dsdt.asl @@ -48,7 +48,7 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include #include "acpi/mainboard.asl" } diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index ce90758462..3ade727409 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -30,22 +30,14 @@ config BOARD_SPECIFIC_OPTIONS select DISABLE_HPET select INTEL_GMA_HAVE_VBT select GENERIC_SPD_BIN - -choice - prompt "Onboard memory manufacturer" - default ONBOARD_MICRON_MEM + select USE_VENDORCODE_ELTAN config ONBOARD_SAMSUNG_MEM - bool "Samsung" + bool "Onboard memory manufacturer Samsung" + default n help Samsung K4B8G1646D memory -config ONBOARD_MICRON_MEM - bool "Micron" - help - Micron MT41K512M16HA memory -endchoice - config MAINBOARD_DIR string default facebook/fbg1701 @@ -77,9 +69,18 @@ config FSP_LOC default 0xfff9c000 config FSP1_1_DISPLAY_LOGO - bool + bool "Enable logo" default n +config FSP1_1_LOGO_FILE_NAME + string "Logo file" + depends on FSP1_1_DISPLAY_LOGO + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/logo.bmp" + +config VENDORCODE_ELTAN_OEM_MANIFEST_LOC + hex + default 0xFFFE9000 + config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n @@ -96,4 +97,20 @@ config C_ENV_BOOTBLOCK_SIZE hex "C Bootblock Size" default 0x4000 +config VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST + bool + default y + +config VENDORCODE_ELTAN_VBOOT_MANIFEST + string + default "mainboard/facebook/fbg1701/manifest.h" + +config VENDORCODE_ELTAN_VBOOT_KEY_LOCATION + hex + default 0xFFFF9C00 + +config DRIVERS_INTEL_WIFI + bool + default n + endif # BOARD_FACEBOOK_FBG1701 diff --git a/src/mainboard/facebook/fbg1701/Makefile.inc b/src/mainboard/facebook/fbg1701/Makefile.inc index 07309c564c..a273f41682 100644 --- a/src/mainboard/facebook/fbg1701/Makefile.inc +++ b/src/mainboard/facebook/fbg1701/Makefile.inc @@ -15,8 +15,16 @@ ## GNU General Public License for more details. ## +ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += board_verified_boot.c +postcar-y += board_verified_boot.c +ramstage-y += board_verified_boot.c +romstage-y += board_verified_boot.c +endif + bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += com_init.c +ramstage-y += cpld.c ramstage-y += gpio.c ramstage-y += hda_verb.c ramstage-y += irqroute.c @@ -24,6 +32,8 @@ ramstage-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.c ramstage-y += ramstage.c ramstage-y += w25q64.c +romstage-y += cpld.c + cbfs-files-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.bmp logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP1_1_LOGO_FILE_NAME)) logo.bmp-type := raw @@ -32,3 +42,4 @@ logo.bmp-compression := LZMA # Order of names in SPD_SOURCES is important! SPD_SOURCES = SAMSUNG_K4B8G1646D-MYKO SPD_SOURCES += MICRON_MT41K512M16HA-125A +SPD_SOURCES += KINGSTON_B5116ECMDXGGB diff --git a/src/mainboard/facebook/fbg1701/acpi/superio.asl b/src/mainboard/facebook/fbg1701/acpi/superio.asl index 468c95c531..bdaa912fd7 100644 --- a/src/mainboard/facebook/fbg1701/acpi/superio.asl +++ b/src/mainboard/facebook/fbg1701/acpi/superio.asl @@ -21,7 +21,6 @@ Device (COM1) { Name (_HID, EISAID ("PNP0501")) Name (_UID, 1) - Name (_ADR, 0) Method (_STA, 0, NotSerialized) { diff --git a/src/mainboard/facebook/fbg1701/board_mboot.h b/src/mainboard/facebook/fbg1701/board_mboot.h new file mode 100644 index 0000000000..5a23630570 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/board_mboot.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const mboot_measure_item_t mb_log_list[] = { + { "config", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_0, EV_NO_ACTION, NULL }, + { "revision", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_0, EV_NO_ACTION, NULL }, + { "cmos_layout.bin", CBFS_COMPONENT_CMOS_LAYOUT, MBOOT_PCR_INDEX_0, + EV_NO_ACTION, NULL }, +#if CONFIG(VENDORCODE_ELTAN_VBOOT) + { "oemmanifest.bin", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_7, EV_NO_ACTION, + NULL }, +#if CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST) + { "vboot_public_key.bin", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_6, + EV_NO_ACTION, NULL }, +#endif +#endif +}; diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.c b/src/mainboard/facebook/fbg1701/board_verified_boot.c new file mode 100644 index 0000000000..1ccb0b8ea3 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.c @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "board_verified_boot.h" + +#ifdef __BOOTBLOCK__ +/* The items verified by the bootblock, the bootblock will not measure the + * items to the TPM + */ +const verify_item_t bootblock_verify_list[] = { + { VERIFY_FILE, ROMSTAGE, { { NULL, CBFS_TYPE_STAGE } }, + HASH_IDX_ROM_STAGE, MBOOT_PCR_INDEX_0 }, + { VERIFY_BLOCK, "BootBlock", + { { (void *)0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, + CONFIG_C_ENV_BOOTBLOCK_SIZE, } }, HASH_IDX_BOOTBLOCK, + MBOOT_PCR_INDEX_0 }, + { VERIFY_BLOCK, "PublicKey", + { { (void *)CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION, + CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_SIZE, } }, HASH_IDX_PUBLICKEY, + MBOOT_PCR_INDEX_0 }, + { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } +}; +#endif + +#if defined(__ROMSTAGE__) || defined(__POSTCAR__) +/* The FSP is already checked in romstage */ +static const verify_item_t ram_stage_additional_list[] = { + { VERIFY_FILE, OP_ROM_VBT, { { NULL, CBFS_TYPE_RAW } }, + HASH_IDX_OPROM, MBOOT_PCR_INDEX_2 }, + { VERIFY_FILE, "logo.bmp", { { NULL, CBFS_TYPE_RAW } }, + HASH_IDX_LOGO, MBOOT_PCR_INDEX_2 }, + { VERIFY_FILE, "fallback/dsdt.aml", { { NULL, CBFS_TYPE_RAW } }, + HASH_IDX_DSDT, MBOOT_PCR_INDEX_2 }, + { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } + }; +#endif + +#ifdef __ROMSTAGE__ +/* The items used by the romstage */ +const verify_item_t romstage_verify_list[] = { + { VERIFY_FILE, ROMSTAGE, { { NULL, CBFS_TYPE_STAGE } }, + HASH_IDX_ROM_STAGE, MBOOT_PCR_INDEX_0 }, + { VERIFY_FILE, MICROCODE, { { NULL, CBFS_TYPE_MICROCODE } }, + HASH_IDX_MICROCODE, MBOOT_PCR_INDEX_1 }, + { VERIFY_FILE, FSP, { { NULL, CBFS_TYPE_FSP } }, HASH_IDX_FSP, + MBOOT_PCR_INDEX_1 }, + { VERIFY_FILE, "spd.bin", { { NULL, CBFS_TYPE_SPD } }, + HASH_IDX_SPD0, MBOOT_PCR_INDEX_1 }, +#if CONFIG(POSTCAR_STAGE) + { VERIFY_FILE, POSTCAR, { { NULL, CBFS_TYPE_STAGE } }, + HASH_IDX_POSTCAR_STAGE, MBOOT_PCR_INDEX_0 }, +#endif + { VERIFY_BLOCK, "BootBlock", + { { (void *)0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, + CONFIG_C_ENV_BOOTBLOCK_SIZE, } }, HASH_IDX_BOOTBLOCK, + MBOOT_PCR_INDEX_0 }, + { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } +}; + +/* The items used by the ramstage */ +const verify_item_t ramstage_verify_list[] = { + { VERIFY_FILE, RAMSTAGE, { { ram_stage_additional_list, + CBFS_TYPE_STAGE } }, HASH_IDX_RAM_STAGE, MBOOT_PCR_INDEX_0 }, + { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } +}; +#endif + +#ifdef __POSTCAR__ +/* POSTSTAGE */ +/* The items used by the postcar stage */ +const verify_item_t postcar_verify_list[] = { + { VERIFY_FILE, RAMSTAGE, { { ram_stage_additional_list, + CBFS_TYPE_STAGE } }, HASH_IDX_RAM_STAGE, MBOOT_PCR_INDEX_0 }, + { VERIFY_FILE, MICROCODE, { { NULL, CBFS_TYPE_MICROCODE } }, + HASH_IDX_MICROCODE, MBOOT_PCR_INDEX_1 }, + { VERIFY_FILE, FSP, { { NULL, CBFS_TYPE_FSP } }, HASH_IDX_FSP, + MBOOT_PCR_INDEX_1 }, + { VERIFY_FILE, "spd.bin", { { NULL, CBFS_TYPE_SPD } }, HASH_IDX_SPD0, + MBOOT_PCR_INDEX_1 }, + { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } +}; +#endif + +#ifdef __RAMSTAGE__ +/* RAMSTAGE */ +const verify_item_t payload_verify_list[] = { + { VERIFY_FILE, PAYLOAD, { { NULL, CBFS_TYPE_SELF | + VERIFIED_BOOT_COPY_BLOCK } }, HASH_IDX_PAYLOAD, + MBOOT_PCR_INDEX_3 }, + { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } +}; + +const verify_item_t oprom_verify_list[] = { + { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } +}; +#endif diff --git a/src/soc/intel/cannonlake/acpi/ipu.asl b/src/mainboard/facebook/fbg1701/board_verified_boot.h similarity index 72% rename from src/soc/intel/cannonlake/acpi/ipu.asl rename to src/mainboard/facebook/fbg1701/board_verified_boot.h index 68a0f3d0e2..30fcd8b1c2 100644 --- a/src/soc/intel/cannonlake/acpi/ipu.asl +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,11 +13,11 @@ * GNU General Public License for more details. */ -/* IPU3 input system - Device 05, Function 0 */ -Device (IMGU) -{ - Name (_ADR, 0x00050000) - Name (_DDN, "Imaging Unit") - Name (_CCA, ZERO) - Name (CAMD, 0x01) -} +#ifndef BOARD_VERIFIED_BOOT_H +#define BOARD_VERIFIED_BOOT_H + +#include +#include +#include "onboard.h" + +#endif diff --git a/src/mainboard/facebook/fbg1701/cpld.c b/src/mainboard/facebook/fbg1701/cpld.c new file mode 100644 index 0000000000..7d1117f6ad --- /dev/null +++ b/src/mainboard/facebook/fbg1701/cpld.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "cpld.h" + +/* CPLD definitions */ +#define CPLD_PCB_VERSION_PORT 0x283 +#define CPLD_PCB_VERSION_MASK 0xF0 +#define CPLD_PCB_VERSION_BIT 4 + +#define CPLD_RESET_PORT 0x287 +#define CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE 0x20 +#define CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE 0x00 + +/* Reset DSI bridge */ +void cpld_reset_bridge(void) +{ + outb(CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE, CPLD_RESET_PORT); + outb(CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE, CPLD_RESET_PORT); +} + +/* Read PCB version */ +unsigned int cpld_read_pcb_version(void) +{ + return ((inb(CPLD_PCB_VERSION_PORT) & CPLD_PCB_VERSION_MASK) >> CPLD_PCB_VERSION_BIT); +} diff --git a/src/mainboard/facebook/fbg1701/cpld.h b/src/mainboard/facebook/fbg1701/cpld.h new file mode 100644 index 0000000000..9604cfbc51 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/cpld.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef CPLD_H +#define CPLD_H + +unsigned int cpld_read_pcb_version(void); +void cpld_reset_bridge(void); + +#endif diff --git a/src/mainboard/facebook/fbg1701/logo.c b/src/mainboard/facebook/fbg1701/logo.c index 678d2e2923..3823c71fdc 100644 --- a/src/mainboard/facebook/fbg1701/logo.c +++ b/src/mainboard/facebook/fbg1701/logo.c @@ -17,7 +17,7 @@ #include #include #include -#include "mainboard.h" +#include "logo.h" static char logo_data[1 * MiB]; static size_t logo_data_sz = 0; @@ -32,16 +32,15 @@ void *load_logo(size_t *logo_size) return (void *)logo_data; } - logo_data_sz = cbfs_boot_load_file(filename, logo_data, - sizeof(logo_data), CBFS_TYPE_RAW); + logo_data_sz = + cbfs_boot_load_file(filename, logo_data, sizeof(logo_data), CBFS_TYPE_RAW); if (logo_data_sz == 0) return NULL; if (logo_size) *logo_size = logo_data_sz; - printk(BIOS_DEBUG, "Found a Logo of %zu bytes after decompression\n", - logo_data_sz); + printk(BIOS_DEBUG, "Found a Logo of %zu bytes after decompression\n", logo_data_sz); return (void *)logo_data; } diff --git a/src/mainboard/facebook/fbg1701/mainboard.h b/src/mainboard/facebook/fbg1701/logo.h similarity index 82% rename from src/mainboard/facebook/fbg1701/mainboard.h rename to src/mainboard/facebook/fbg1701/logo.h index 3cace548b3..0682d3fa2d 100644 --- a/src/mainboard/facebook/fbg1701/mainboard.h +++ b/src/mainboard/facebook/fbg1701/logo.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Eltan B.V. + * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,10 +13,9 @@ * GNU General Public License for more details. */ -#ifndef MAINBOARD_H -#define MAINBOARD_H +#ifndef LOGO_H +#define LOGO_H -unsigned int mainboard_read_pcb_version(void); void *load_logo(size_t *logo_size); #endif diff --git a/src/mainboard/facebook/fbg1701/mainboard.c b/src/mainboard/facebook/fbg1701/mainboard.c index a8cb34c744..8524b24000 100644 --- a/src/mainboard/facebook/fbg1701/mainboard.c +++ b/src/mainboard/facebook/fbg1701/mainboard.c @@ -16,10 +16,7 @@ * GNU General Public License for more details. */ -#include #include -#include "mainboard.h" -#include "onboard.h" /* * Declare the resources we are using @@ -39,13 +36,6 @@ static void mainboard_reserve_resources(struct device *dev) res->flags = IORESOURCE_IRQ | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -/* Read PCB version */ -unsigned int mainboard_read_pcb_version(void) -{ - return ((inb(CPLD_PCB_VERSION_PORT) & CPLD_PCB_VERSION_MASK) >> - CPLD_PCB_VERSION_BIT); -} - /* * mainboard_enable is executed as first thing after * enumerate_buses(). diff --git a/src/mainboard/facebook/fbg1701/manifest.h b/src/mainboard/facebook/fbg1701/manifest.h new file mode 100644 index 0000000000..caf9e5ecd6 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/manifest.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MANIFEST_H__ +#define __MANIFEST_H__ + +/** + * Make sure the index matches the actual order in the manifest generated + * using the HashCb.cmd file + */ +#define HASH_IDX_ROM_STAGE 0 +#define HASH_IDX_RAM_STAGE 1 +#define HASH_IDX_PAYLOAD 2 +#define HASH_IDX_OPROM 3 +#define HASH_IDX_FSP 4 +#define HASH_IDX_MICROCODE 5 +#define HASH_IDX_SPD0 6 +#define HASH_IDX_LOGO 7 +#define HASH_IDX_DSDT 8 +#define HASH_IDX_POSTCAR_STAGE 9 +#define HASH_IDX_PUBLICKEY 10 +#define HASH_IDX_BOOTBLOCK 11 /* Should always be the last one */ +#endif diff --git a/src/mainboard/facebook/fbg1701/onboard.h b/src/mainboard/facebook/fbg1701/onboard.h index d1fd0509a6..cb784daf69 100644 --- a/src/mainboard/facebook/fbg1701/onboard.h +++ b/src/mainboard/facebook/fbg1701/onboard.h @@ -19,18 +19,19 @@ #define ONBOARD_H /* SD CARD gpio */ -#define SDCARD_CD 81 /* Not used */ +#define SDCARD_CD 81 /* Not used */ -#define ITE8528_CMD_PORT 0x6E -#define ITE8528_DATA_PORT 0x6F +#define ITE8528_CMD_PORT 0x6E +#define ITE8528_DATA_PORT 0x6F -/* CPLD definitions */ -#define CPLD_PCB_VERSION_PORT 0x283 -#define CPLD_PCB_VERSION_MASK 0xF0 -#define CPLD_PCB_VERSION_BIT 4 - -#define CPLD_RESET_PORT 0x287 -#define CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE 0x20 -#define CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE 0x00 +/* Define the items to be measured or verified */ +#define FSP (const char *)"fsp.bin" +#define CMOS_LAYOUT (const char *)"cmos_layout.bin" +#define RAMSTAGE (const char *)"fallback/ramstage" +#define ROMSTAGE (const char *)"fallback/romstage" +#define PAYLOAD (const char *)"fallback/payload" +#define POSTCAR (const char *)"fallback/postcar" +#define OP_ROM_VBT (const char *)"vbt.bin" +#define MICROCODE (const char *)"cpu_microcode_blob.bin" #endif diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index c5fb79881a..9b25b983f7 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -18,8 +18,8 @@ #include #include #include -#include "mainboard.h" -#include "onboard.h" +#include "cpld.h" +#include "logo.h" struct edp_data { u8 payload_length; @@ -31,318 +31,321 @@ struct edp_data { static const struct edp_data b101uan01_table[] = { /* set eDP bridge to 1200x1920 */ /* IO */ - { 6, 0x68, { 0x08, 0x00, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x08, 0x00, 0x01, 0x00, 0x00, 0x00} }, /* Boot */ - { 6, 0x68, { 0x10, 0x00, 0x78, 0x69, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x04, 0x02, 0x08, 0x02, 0x00 } }, - { 6, 0x68, { 0x10, 0x08, 0x23, 0x00, 0x87, 0x02 } }, - { 6, 0x68, { 0x10, 0x0C, 0x19, 0x04, 0x00, 0x23 } }, - { 6, 0x68, { 0x10, 0x10, 0x06, 0x00, 0x67, 0x00 } }, - { 6, 0x68, { 0x10, 0x14, 0x01, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {6, 0x68, {0x10, 0x00, 0x78, 0x69, 0x00, 0x00} }, + {6, 0x68, {0x10, 0x04, 0x02, 0x08, 0x02, 0x00} }, + {6, 0x68, {0x10, 0x08, 0x23, 0x00, 0x87, 0x02} }, + {6, 0x68, {0x10, 0x0C, 0x19, 0x04, 0x00, 0x23} }, + {6, 0x68, {0x10, 0x10, 0x06, 0x00, 0x67, 0x00} }, + {6, 0x68, {0x10, 0x14, 0x01, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} }, /* Internal */ - { 3, 0x68, { 0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x06, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x07, 0x16, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x08, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x09, 0x21, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x14, 0x03, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {3, 0x68, {0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB0, 0x06, 0x03, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB0, 0x07, 0x16, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB0, 0x08, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB0, 0x09, 0x21, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x10, 0x14, 0x03, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} }, /* eDP */ - { 3, 0x68, { 0x80, 0x03, 0x41, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0x80, 0x03, 0x41, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00} }, /* DPRX */ - { 3, 0x68, { 0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x26, 0x02, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x01, 0x20, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x33, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x10, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x38, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x60, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x15, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x65, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x42, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x47, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x24, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x74, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x29, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x51, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x79, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x56, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x90, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x93, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x96, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x99, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x96, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x97, 0x04, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x0E, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x14, 0x07, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {3, 0x68, {0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x26, 0x02, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x01, 0x20, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x33, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x10, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x38, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x60, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x15, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x65, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x42, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x47, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x24, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x74, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x29, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x51, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x79, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x56, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x90, 0x10, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x93, 0x10, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x96, 0x10, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x99, 0x10, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x96, 0x03, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x97, 0x04, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00} }, + {3, 0x68, {0x80, 0x0E, 0x00, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x10, 0x14, 0x07, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} }, /* Video size */ - { 6, 0x68, { 0x01, 0x48, 0xB0, 0x04, 0x00, 0x00 } }, - { 6, 0x68, { 0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E } }, + {6, 0x68, {0x01, 0x48, 0xB0, 0x04, 0x00, 0x00} }, + {6, 0x68, {0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E} }, /* eDP */ - { 3, 0x68, { 0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x01, 0x14, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x02, 0x02, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x87, 0x00, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x50, 0x10, 0x00, 0x00, 0x9D, 0x00 } }, - { 6, 0x68, { 0x00, 0x8C, 0x40, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x80, 0x02, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00} }, + {3, 0x68, {0x80, 0x01, 0x14, 0x00, 0x00, 0x00} }, + {3, 0x68, {0x80, 0x02, 0x02, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00} }, + {3, 0x68, {0x87, 0x00, 0x00, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x50, 0x10, 0x00, 0x00, 0x9D, 0x00} }, + {6, 0x68, {0x00, 0x8C, 0x40, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x00, 0x80, 0x02, 0x00, 0x00, 0x00} }, /* Link Training */ - { 3, 0x68, { 0x82, 0x02, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x82, 0x03, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x82, 0x04, 0xFF, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x21, 0x58, 0x09, 0x00, 0x28, 0x00 } }, - { 6, 0x68, { 0x21, 0x60, 0x07, 0x00, 0x0F, 0x00 } }, - { 6, 0x68, { 0x21, 0x64, 0x28, 0x23, 0x00, 0x00 } }, - { 6, 0x68, { 0x21, 0x68, 0x0E, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0x82, 0x02, 0xFF, 0x00, 0x00, 0x00} }, + {3, 0x68, {0x82, 0x03, 0xFF, 0x00, 0x00, 0x00} }, + {3, 0x68, {0x82, 0x04, 0xFF, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x21, 0x58, 0x09, 0x00, 0x28, 0x00} }, + {6, 0x68, {0x21, 0x60, 0x07, 0x00, 0x0F, 0x00} }, + {6, 0x68, {0x21, 0x64, 0x28, 0x23, 0x00, 0x00} }, + {6, 0x68, {0x21, 0x68, 0x0E, 0x00, 0x00, 0x00} }, /* DSI */ - { 6, 0x68, { 0x20, 0x7C, 0x81, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x50, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x1C, 0x01, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF } }, + {6, 0x68, {0x20, 0x7C, 0x81, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x20, 0x50, 0x00, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x20, 0x1C, 0x01, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF} }, /* GPIO */ - { 6, 0x68, { 0x08, 0x04, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x08, 0x04, 0x00, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x00, 0x80, 0x0F, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x00, 0x84, 0x0F, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x00, 0x84, 0x00, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x00, 0x84, 0x0F, 0x00, 0x00, 0x00} }, /* DSI clock */ - { 6, 0x68, { 0x20, 0x50, 0x20, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x20, 0x50, 0x20, 0x00, 0x00, 0x00} }, /* LCD init */ - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x01, 0x00, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x8C, 0x80, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0xC7, 0x50, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0xC5, 0x50, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x85, 0x04, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x86, 0x08, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x84, 0x11, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x9C, 0x10, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0xA9, 0x4B, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x05, 0x11, 0x00, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x05, 0x29, 0x00, 0x81 } }, - { 6, 0x68, { 0x2A, 0x10, 0x10, 0x00, 0x04, 0x80 } }, - { 6, 0x68, { 0x2A, 0x04, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x22, 0xFC, 0x15, 0x01, 0x00, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x15, 0x8C, 0x80, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x15, 0xC7, 0x50, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x15, 0xC5, 0x50, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x15, 0x85, 0x04, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x15, 0x86, 0x08, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x15, 0x84, 0x11, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x15, 0x9C, 0x10, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x15, 0xA9, 0x4B, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x05, 0x11, 0x00, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x05, 0x29, 0x00, 0x81} }, + {6, 0x68, {0x2A, 0x10, 0x10, 0x00, 0x04, 0x80} }, + {6, 0x68, {0x2A, 0x04, 0x01, 0x00, 0x00, 0x00} }, /* Check Video */ - { 6, 0x68, { 0x01, 0x54, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x01, 0x54, 0x01, 0x00, 0x00, 0x00} }, /* End of table */ - { 0, 0x00, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }, + {0, 0x00, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, }; static const struct edp_data b101uan08_table[] = { /* set eDP bridge to 1200x1920 */ /* IO Voltage Setting */ - { 6, 0x68, { 0x08, 0x00, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x08, 0x00, 0x01, 0x00, 0x00, 0x00} }, /* Boot Settings */ - { 6, 0x68, { 0x10, 0x00, 0x78, 0x69, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x04, 0x02, 0x08, 0x02, 0x00 } }, - { 6, 0x68, { 0x10, 0x08, 0x22, 0x00, 0xA0, 0x02 } }, - { 6, 0x68, { 0x10, 0x0C, 0x50, 0x04, 0x00, 0x03 } }, - { 6, 0x68, { 0x10, 0x10, 0x10, 0x0D, 0x06, 0x01 } }, - { 6, 0x68, { 0x10, 0x14, 0x01, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {6, 0x68, {0x10, 0x00, 0x78, 0x69, 0x00, 0x00} }, + {6, 0x68, {0x10, 0x04, 0x02, 0x08, 0x02, 0x00} }, + {6, 0x68, {0x10, 0x08, 0x22, 0x00, 0xA0, 0x02} }, + {6, 0x68, {0x10, 0x0C, 0x50, 0x04, 0x00, 0x03} }, + {6, 0x68, {0x10, 0x10, 0x10, 0x0D, 0x06, 0x01} }, + {6, 0x68, {0x10, 0x14, 0x01, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} }, /* Internal PCLK settings for Non Present or REFCLK=26MHz */ - { 3, 0x68, { 0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x06, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x07, 0x16, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x08, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x09, 0x21, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB0, 0x06, 0x03, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB0, 0x07, 0x16, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB0, 0x08, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB0, 0x09, 0x21, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00} }, /* DSI Clock setting for Non Preset or REFCLK=26MHz */ - { 6, 0x68, { 0x41, 0xB0, 0xC1, 0x22, 0x04, 0x00 } }, - { 6, 0x68, { 0x41, 0xBC, 0x01, 0x0E, 0x00, 0x00 } }, - { 6, 0x68, { 0x41, 0xC0, 0x30, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x14, 0x03, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {6, 0x68, {0x41, 0xB0, 0xC1, 0x22, 0x04, 0x00} }, + {6, 0x68, {0x41, 0xBC, 0x01, 0x0E, 0x00, 0x00} }, + {6, 0x68, {0x41, 0xC0, 0x30, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x10, 0x14, 0x03, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} }, /* Additional Settng for eDP */ - { 3, 0x68, { 0x80, 0x03, 0x41, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0x80, 0x03, 0x41, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00} }, /* DPRX CAD Register Setting */ - { 3, 0x68, { 0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x26, 0x02, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x01, 0x20, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x33, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x10, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x38, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x60, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x15, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x65, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x42, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x47, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x24, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x74, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x29, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x51, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x79, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x56, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x90, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x93, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x96, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x99, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x96, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x97, 0x04, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x0E, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x14, 0x07, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {3, 0x68, {0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x26, 0x02, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x01, 0x20, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x33, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x10, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x38, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x60, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x15, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x65, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x42, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x47, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x24, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x74, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x29, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x51, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x79, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x56, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x90, 0x10, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x93, 0x10, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x96, 0x10, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x99, 0x10, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x96, 0x03, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x97, 0x04, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00} }, + {3, 0x68, {0x80, 0x0E, 0x00, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x10, 0x14, 0x07, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} }, /* Video size Related Settings for Non Present */ - { 6, 0x68, { 0x01, 0x48, 0xB0, 0x04, 0x00, 0x00 } }, - { 6, 0x68, { 0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E } }, + {6, 0x68, {0x01, 0x48, 0xB0, 0x04, 0x00, 0x00} }, + {6, 0x68, {0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E} }, /* eDP Settings for Link Training*/ - { 3, 0x68, { 0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x01, 0x14, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x02, 0x02, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x87, 0x00, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x50, 0x10, 0x00, 0x00, 0x9D, 0x00 } }, - { 6, 0x68, { 0x00, 0x8C, 0x40, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x80, 0x02, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00} }, + {3, 0x68, {0x80, 0x01, 0x14, 0x00, 0x00, 0x00} }, + {3, 0x68, {0x80, 0x02, 0x02, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00} }, + {3, 0x68, {0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00} }, + {3, 0x68, {0x87, 0x00, 0x00, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x50, 0x10, 0x00, 0x00, 0x9D, 0x00} }, + {6, 0x68, {0x00, 0x8C, 0x40, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x00, 0x80, 0x02, 0x00, 0x00, 0x00} }, /* Link Training */ - { 3, 0x68, { 0x82, 0x02, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x82, 0x03, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x82, 0x04, 0xFF, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0x82, 0x02, 0xFF, 0x00, 0x00, 0x00} }, + {3, 0x68, {0x82, 0x03, 0xFF, 0x00, 0x00, 0x00} }, + {3, 0x68, {0x82, 0x04, 0xFF, 0x00, 0x00, 0x00} }, /* DSI Transition Time Setting for Non Preset */ - { 6, 0x68, { 0x21, 0x54, 0x0D, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x21, 0x58, 0x06, 0x00, 0x2A, 0x00 } }, - { 6, 0x68, { 0x21, 0x5C, 0x07, 0x00, 0x0E, 0x00 } }, - { 6, 0x68, { 0x21, 0x60, 0x07, 0x00, 0x10, 0x00 } }, - { 6, 0x68, { 0x21, 0x64, 0x10, 0x27, 0x00, 0x00 } }, - { 6, 0x68, { 0x21, 0x68, 0x0E, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x21, 0x6C, 0x0A, 0x00, 0x0E, 0x00 } }, - { 6, 0x68, { 0x21, 0x78, 0x0E, 0x00, 0x0D, 0x00 } }, + {6, 0x68, {0x21, 0x54, 0x0D, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x21, 0x58, 0x06, 0x00, 0x2A, 0x00} }, + {6, 0x68, {0x21, 0x5C, 0x07, 0x00, 0x0E, 0x00} }, + {6, 0x68, {0x21, 0x60, 0x07, 0x00, 0x10, 0x00} }, + {6, 0x68, {0x21, 0x64, 0x10, 0x27, 0x00, 0x00} }, + {6, 0x68, {0x21, 0x68, 0x0E, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x21, 0x6C, 0x0A, 0x00, 0x0E, 0x00} }, + {6, 0x68, {0x21, 0x78, 0x0E, 0x00, 0x0D, 0x00} }, /* DSI Start */ - { 6, 0x68, { 0x20, 0x7C, 0x81, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x50, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x1C, 0x01, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF } }, + {6, 0x68, {0x20, 0x7C, 0x81, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x20, 0x50, 0x00, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x20, 0x1C, 0x01, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF} }, /* GPIO for LCD control*/ - { 6, 0x68, { 0x08, 0x04, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x08, 0x04, 0x00, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x00, 0x80, 0x0F, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x00, 0x84, 0x0F, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x00, 0x84, 0x00, 0x00, 0x00, 0x00} }, + {6, 0x68, {0x00, 0x84, 0x0F, 0x00, 0x00, 0x00} }, /* DSI Hs Clock Mode */ - { 6, 0x68, { 0x20, 0x50, 0x20, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x20, 0x50, 0x20, 0x00, 0x00, 0x00} }, /* LCD Initialization */ - { 6, 0x68, { 0x22, 0xFC, 0x15, 0xBF, 0xA5, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x01, 0x00, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x8F, 0xA5, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x84, 0x11, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0xA9, 0x48, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x83, 0x00, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x84, 0x00, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x8F, 0x00, 0x81 } }, - { 6, 0x68, { 0x2A, 0x10, 0x10, 0x00, 0x04, 0x80 } }, - { 6, 0x68, { 0x2A, 0x04, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x22, 0xFC, 0x15, 0xBF, 0xA5, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x15, 0x01, 0x00, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x15, 0x8F, 0xA5, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x15, 0x84, 0x11, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x15, 0xA9, 0x48, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x15, 0x83, 0x00, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x15, 0x84, 0x00, 0x81} }, + {6, 0x68, {0x22, 0xFC, 0x15, 0x8F, 0x00, 0x81} }, + {6, 0x68, {0x2A, 0x10, 0x10, 0x00, 0x04, 0x80} }, + {6, 0x68, {0x2A, 0x04, 0x01, 0x00, 0x00, 0x00} }, /* Check if eDP video is coming */ - { 6, 0x68, { 0x01, 0x54, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x01, 0x54, 0x01, 0x00, 0x00, 0x00} }, /* End of table */ - { 0, 0x00, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }, + {0, 0x00, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, }; static void mainboard_configure_edp_bridge(void) { const struct edp_data *edptable; unsigned int loops; + unsigned int pcb_version; int status; - if (mainboard_read_pcb_version() < 7) + pcb_version = cpld_read_pcb_version(); + printk(BIOS_DEBUG, "PCB version: %x\n", pcb_version); + + if (pcb_version < 7) edptable = b101uan01_table; else edptable = b101uan08_table; /* reset bridge */ - outb(CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE, CPLD_RESET_PORT); - outb(CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE, CPLD_RESET_PORT); + cpld_reset_bridge(); while (edptable->payload_length) { loops = 5; do { status = smbus_i2c_block_write(edptable->address, - edptable->payload_length, - (u8 *)&edptable->data[0]); + edptable->payload_length, + (u8 *)&edptable->data[0]); } while (--loops && (status < 0)); if (loops == 0) { diff --git a/src/mainboard/facebook/fbg1701/romstage.c b/src/mainboard/facebook/fbg1701/romstage.c index e2e37d6387..c10e8666bf 100644 --- a/src/mainboard/facebook/fbg1701/romstage.c +++ b/src/mainboard/facebook/fbg1701/romstage.c @@ -15,24 +15,35 @@ * GNU General Public License for more details. */ +#include #include #include #include #include +#if CONFIG(VENDORCODE_ELTAN_MBOOT) +#include +#endif #include #include #include #include #include +#include "cpld.h" + void mainboard_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) + MEMORY_INIT_UPD *memory_params) { struct region_device spd_rdev; u8 spd_index = 0; - if (CONFIG(ONBOARD_MICRON_MEM)) - spd_index = 1; + if (!CONFIG(ONBOARD_SAMSUNG_MEM)) { + if (cpld_read_pcb_version() <= 7) + spd_index = 1; + else + spd_index = 2; + } + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) die("spd.bin not found\n"); @@ -49,3 +60,44 @@ void mainboard_after_memory_init(void) /* Disable the Braswell UART hardware for COM1. */ pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, 0); } + +#if CONFIG(VENDORCODE_ELTAN_MBOOT) +/** + * mb_crtm + * + * Measures the crtm version. This consists of a string than can be defined + * using make menuconfig and automatically generated version information. + * + * @param[in] activePcr bitmap of the support + * + * @retval TPM_SUCCESS Operation completed successfully. + * @retval TPM_E_IOERROR Unexpected device behavior. + */ + +static const uint8_t crtm_version[] = + CONFIG_VENDORCODE_ELTAN_CRTM_VERSION_STRING COREBOOT_VERSION COREBOOT_EXTRA_VERSION + " " COREBOOT_BUILD; + +int mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr) +{ + int status = TPM_E_IOERROR; + TCG_PCR_EVENT2_HDR tcgEventHdr; + + /* Use FirmwareVersion string to represent CRTM version. */ + printk(BIOS_DEBUG, "%s: Measure CRTM Version\n", __func__); + memset(&tcgEventHdr, 0, sizeof(tcgEventHdr)); + tcgEventHdr.pcrIndex = MBOOT_PCR_INDEX_0; + tcgEventHdr.eventType = EV_S_CRTM_VERSION; + tcgEventHdr.eventSize = sizeof(crtm_version); + printk(BIOS_DEBUG, "%s: EventSize - %u\n", __func__, tcgEventHdr.eventSize); + + status = mboot_hash_extend_log(activePcr, 0, (uint8_t *)crtm_version, + tcgEventHdr.eventSize, &tcgEventHdr, + (uint8_t *)crtm_version, 0); + if (status) { + printk(BIOS_DEBUG, "Measure CRTM Version returned 0x%x\n", status); + } + + return status; +} +#endif diff --git a/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex new file mode 100644 index 0000000000..c018620d3b --- /dev/null +++ b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -0,0 +1,258 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Facebook, Inc. +# Copyright (C) 2019 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# +# 8 Gb DDR3 (1600 MHz 11-11-11) Kingston B5116ECMDXGGB +# +# SINGLE DIE +# + +# 64Mx16x8 ( 8 bank, 16 Rows, 10 Col, 2 KB page size ) +# 6-7-8-9-10-11 +# DDR3L-1600 +# tCk 1.25ns +# tRCD 13.75ns +# tRP 13.75ns +# tRAS 35ns +# tRC 48.75ns +# CL-tRCD-tRP 11-11-11 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 3 = 384 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +23 + +# 1 SPD Revision +# 0x10 = Revision 1.0 +10 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0c = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SODIMM +# bits[6:4]: 0 = Not hybrid +# bits[7]: 0 = Not hybrid +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bits[7]: reserverd +05 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 4 = 16 Row Address Bits +# bits[7:6]: 0 = reserved +21 + +# 6 Module Nominal Voltage +# bits[0]: 0 = 1.5V operable +# bits[1]: 1 = 1.35V operable +# bits[2]: 0 = NOT 1.25V operable +# bits[7:3]: reserved +02 + +# 7 Module Organization +# bits[2:0]: 010b = 16 bits SDRAM device +# bits[5:3]: 000b = 1 ranks +# bits[7:6]: reserved +02 + +# 8 Module Memory Bus width +# bits[2:0]: 3 = 64 bits pirmary bus width +# bits[4:3]: 0 = 0 bits bus witdth extension +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) dividend / divisor +# bits[3:0]: 1 = Divisor +# bits[7:4]: 1 = Dividend +11 + +# 10 Medium Timebase (MTB) dividend +# bits[7:0]: 0 = 1 (timebase 0.125ns) +01 + +# 11 Medium Timebase (MTB) divisor +# bits[7:0]: 8 (timebase 0.125ns) +08 + +# 12 SDRAM Minimum cycle time (tCKmin) +# 0xA tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +0A + +# 13 Reserved +00 + +# 14 CAS Latencies supported, Least Significate Byte +# Support 6,7,8,9,10,11 +FC + +# 15 CAS Latencies supported, Most Significate Byte +# No supporting CL 12-18 +00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x69 tAA = 13.125ns (offset = 00) DDR3-1600K downbin +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 tWR = 15 ns +78 + +# 18 Minimum RAS to CAS Delay Time (tRCDmin) +# 0x69 tRCD = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x3C tRRD = 7.5ns DDR3-1600, 2KB +3C + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x69 tRP = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 21 Upper Nibble for tRAS and tRC +# 3:0 : 1 higher tRAS = 35ns +# 7:0 : 1 higher tRC = 48.125ns +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant byte +# lower 0x118 : tRAS = 35ns DDR3-1600 +18 + +# 23 Minimum Active to Precharge Delay Time (tRCmin), Most Significant byte +# lower 0x181 : tRC = 48.125ns (offset 00) DDR3-1600K downbin +81 + +# 24 Minimum Refresh Recovery Delay time (tRFCmin), Least Significant byte +# lower 0xAF0 : tRFC = 350ns 8 Gb +F0 + +# 25 Minimum Refresh Recovery Delay time (tRFCmin), Most Significant byte +# higher 0xAF0 : tRFC = 350ns 8 Gb +0A + +# 26 tWTRmin +# 0x3C : tWTR = 7.5 ns (DDR3) +3C + +# 27 tRTPmin +# 0x3C : tRTP = 7.5 ns (DDR3) +3C + +# 28 Upper Nibble for tFAW +# Bit [3:0] : 1 = higher 0x140 tFAW = 40ns +01 + +# 29 tFAWmin Lower +# lower 0x140 : tFAW = 40ns +40 + +# 30 SDRAM Optional Features +# byte [0] : 1 = RZQ/6 is support +# byte [1] : 1 = RZQ/7 is supported +# byte [7] : 1 = DLL-Off Mode support +83 + +# 31 Thermal options +# byte [0] : 1 = 0 - 95C +# byte [2] : 0 = Auto Self Refresh (ASR) is not supported +# byte [7] : 0 = Partial Array Self Refres (PASR) is not supported +01 + +# 32 Module Thermal support +# byte [0] : 0 = Thermal sensor accuracy undefined +# byte [7] : 0 = No thermal sensor +00 + +# 33 SDRAM device type +# byte [1:0] : 00b = Signal Loading not specified +# byte [6:4] : 000b = Die count not specified +# byte [7] : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine tCKmin +# 0x00 tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +00 + +# 35 Fine tAAmin +# 0x00 tAA = 13.125ns (tAAmin offset = 00) DDR3-1600K downbin +00 + +# 36 Fine tRCDmin +# 0x00 tRCD = 13.125ns DDR3-1600K downbin +00 + +# 37 Fine tRPmin +# 0x00 tRP = 13.125ns (offset 00) DDR3-1600K downbin +00 + +# 38 Fine tRCmin +# 0x00 tRC = 48.125ns (offset 00) DDR3-1600K downbin +00 + +# 39-59 reserved, general section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60-116 Module specific section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 + +# 117-118 Module Manufacturer +01 98 + +# 119 Module Manufacturing Location +00 + +# 120-121 Module Manufacturing Date +13 0A + +# 122-125 Module Serial number +00 00 00 00 + +# 126-127 SPD CRC +00 00 + +# 128-145 Module Part number +66 53 49 49 54 69 67 77 68 88 71 71 66 00 00 00 +00 00 + +# 145-146 Module revision code +00 00 + +# 148-149 DRAM Manufacturer ID code +01 98 + +# 150-175 Manufacturer Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 + +# 176-255 Open for Customer Use + +# 176 - 255 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/foxconn/d41s/acpi/platform.asl b/src/mainboard/foxconn/d41s/acpi/platform.asl deleted file mode 100644 index 6c92a4ed47..0000000000 --- a/src/mainboard/foxconn/d41s/acpi/platform.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Method(_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store(Arg0, PICM) -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) /* SMI Function */ - Store (0, TRP0) /* Generate trap */ - Return (SMIF) /* Return value of SMI handler */ -} diff --git a/src/mainboard/foxconn/d41s/dsdt.asl b/src/mainboard/foxconn/d41s/dsdt.asl index 8dc11942a0..e07ecc2801 100644 --- a/src/mainboard/foxconn/d41s/dsdt.asl +++ b/src/mainboard/foxconn/d41s/dsdt.asl @@ -24,7 +24,7 @@ DefinitionBlock( 0x20090419 // OEM revision ) { - #include "acpi/platform.asl" + #include #include #include @@ -38,5 +38,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/foxconn/g41s-k/Kconfig b/src/mainboard/foxconn/g41s-k/Kconfig index f74fcd6bf3..3597e4c82f 100644 --- a/src/mainboard/foxconn/g41s-k/Kconfig +++ b/src/mainboard/foxconn/g41s-k/Kconfig @@ -29,9 +29,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE select MAINBOARD_HAS_LPC_TPM - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_L1_SUB_STATE select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT diff --git a/src/mainboard/foxconn/g41s-k/acpi/platform.asl b/src/mainboard/foxconn/g41s-k/acpi/platform.asl deleted file mode 100644 index bda0df74b1..0000000000 --- a/src/mainboard/foxconn/g41s-k/acpi/platform.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Method(_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store(Arg0, PICM) -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) /* SMI Function */ - Store (0, TRP0) /* Generate trap */ - Return (SMIF) /* Return value of SMI handler */ -} diff --git a/src/mainboard/foxconn/g41s-k/dsdt.asl b/src/mainboard/foxconn/g41s-k/dsdt.asl index 002dfcaeb6..31e7c10d3e 100644 --- a/src/mainboard/foxconn/g41s-k/dsdt.asl +++ b/src/mainboard/foxconn/g41s-k/dsdt.asl @@ -25,7 +25,7 @@ DefinitionBlock( ) { // global NVS and variables - #include "acpi/platform.asl" + #include #include Scope (\_SB) { @@ -38,5 +38,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index a22c90c1f1..0bfbbfe28c 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -67,7 +67,8 @@ static void mb_lpc_setup(void) RCBA8(OIC); RCBA32(FD) |= FD_INTLAN; - RCBA32(CG) = 0x00000001; + + ich7_setup_cir(); } static void ich7_enable_lpc(void) diff --git a/src/mainboard/getac/p470/dsdt.asl b/src/mainboard/getac/p470/dsdt.asl index 4471ef2dbd..4e75968f91 100644 --- a/src/mainboard/getac/p470/dsdt.asl +++ b/src/mainboard/getac/p470/dsdt.asl @@ -55,5 +55,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index a7c64bd98b..dfc97d814c 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -90,13 +90,6 @@ static void pnp_exit_ext_func_mode(pnp_devfn_t dev) outb(0xaa, port); } -static void pnp_write_register(pnp_devfn_t dev, int reg, int val) -{ - unsigned int port = dev >> 8; - outb(reg, port); - outb(val, port+1); -} - static void early_superio_config(void) { pnp_devfn_t dev; @@ -104,40 +97,40 @@ static void early_superio_config(void) dev = PNP_DEV(0x4e, 0x00); pnp_enter_ext_func_mode(dev); - pnp_write_register(dev, 0x02, 0x0e); // UART power - pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base - pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base - pnp_write_register(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ - pnp_write_register(dev, 0x1e, 1); // no 32khz clock - pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base - pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ - pnp_write_register(dev, 0x2c, 0); // DMA0 FIR - pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base + pnp_write_config(dev, 0x02, 0x0e); // UART power + pnp_write_config(dev, 0x1b, (0x3e8 >> 2)); // UART3 base + pnp_write_config(dev, 0x1c, (0x2e8 >> 2)); // UART4 base + pnp_write_config(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ + pnp_write_config(dev, 0x1e, 1); // no 32khz clock + pnp_write_config(dev, 0x24, (0x3f8 >> 2)); // UART1 base + pnp_write_config(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ + pnp_write_config(dev, 0x2c, 0); // DMA0 FIR + pnp_write_config(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base - pnp_write_register(dev, 0x31, 0xce); // GPIO1 DIR - pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL - pnp_write_register(dev, 0x33, 0x0f); // GPIO2 DIR - pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL - pnp_write_register(dev, 0x35, 0xa8); // GPIO3 DIR - pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL - pnp_write_register(dev, 0x37, 0xa8); // GPIO4 DIR - pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL + pnp_write_config(dev, 0x31, 0xce); // GPIO1 DIR + pnp_write_config(dev, 0x32, 0x00); // GPIO1 POL + pnp_write_config(dev, 0x33, 0x0f); // GPIO2 DIR + pnp_write_config(dev, 0x34, 0x00); // GPIO2 POL + pnp_write_config(dev, 0x35, 0xa8); // GPIO3 DIR + pnp_write_config(dev, 0x36, 0x00); // GPIO3 POL + pnp_write_config(dev, 0x37, 0xa8); // GPIO4 DIR + pnp_write_config(dev, 0x38, 0x00); // GPIO4 POL - pnp_write_register(dev, 0x39, 0x00); // GPIO1 OUT - pnp_write_register(dev, 0x40, 0x80); // GPIO2/MISC OUT - pnp_write_register(dev, 0x41, 0x00); // GPIO5 OUT - pnp_write_register(dev, 0x42, 0xa8); // GPIO5 DIR - pnp_write_register(dev, 0x43, 0x00); // GPIO5 POL - pnp_write_register(dev, 0x44, 0x00); // GPIO ALT1 - pnp_write_register(dev, 0x45, 0x50); // GPIO ALT2 - pnp_write_register(dev, 0x46, 0x00); // GPIO ALT3 + pnp_write_config(dev, 0x39, 0x00); // GPIO1 OUT + pnp_write_config(dev, 0x40, 0x80); // GPIO2/MISC OUT + pnp_write_config(dev, 0x41, 0x00); // GPIO5 OUT + pnp_write_config(dev, 0x42, 0xa8); // GPIO5 DIR + pnp_write_config(dev, 0x43, 0x00); // GPIO5 POL + pnp_write_config(dev, 0x44, 0x00); // GPIO ALT1 + pnp_write_config(dev, 0x45, 0x50); // GPIO ALT2 + pnp_write_config(dev, 0x46, 0x00); // GPIO ALT3 - pnp_write_register(dev, 0x48, 0x55); // GPIO ALT5 - pnp_write_register(dev, 0x49, 0x55); // GPIO ALT6 - pnp_write_register(dev, 0x4a, 0x55); // GPIO ALT7 - pnp_write_register(dev, 0x4b, 0x55); // GPIO ALT8 - pnp_write_register(dev, 0x4c, 0x55); // GPIO ALT9 - pnp_write_register(dev, 0x4d, 0x55); // GPIO ALT10 + pnp_write_config(dev, 0x48, 0x55); // GPIO ALT5 + pnp_write_config(dev, 0x49, 0x55); // GPIO ALT6 + pnp_write_config(dev, 0x4a, 0x55); // GPIO ALT7 + pnp_write_config(dev, 0x4b, 0x55); // GPIO ALT8 + pnp_write_config(dev, 0x4c, 0x55); // GPIO ALT9 + pnp_write_config(dev, 0x4d, 0x55); // GPIO ALT10 pnp_exit_ext_func_mode(dev); } @@ -184,12 +177,12 @@ static void early_ich7_init(void) uint32_t reg32; // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); // usb transient disconnect reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); @@ -204,31 +197,7 @@ static void early_ich7_init(void) reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); - reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl index 95ed8d913d..afc53861bb 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl @@ -50,5 +50,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index eaf05a2c38..3a2c86da87 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -87,12 +87,12 @@ static void early_ich7_init(void) uint32_t reg32; // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); // usb transient disconnect reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); @@ -107,31 +107,7 @@ static void early_ich7_init(void) reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030509; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl index c00ee30e6b..8b81ebff61 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -21,7 +21,7 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/mainboard.asl" @@ -30,7 +30,7 @@ DefinitionBlock( #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index b35a8b4af9..ecbd393b2b 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -27,11 +27,6 @@ void pch_enable_lpc(void) { - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | - CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/platform.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/platform.asl deleted file mode 100644 index 6c92a4ed47..0000000000 --- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/platform.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Method(_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store(Arg0, PICM) -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) /* SMI Function */ - Store (0, TRP0) /* Generate trap */ - Return (SMIF) /* Return value of SMI handler */ -} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl index 002dfcaeb6..31e7c10d3e 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl +++ b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl @@ -25,7 +25,7 @@ DefinitionBlock( ) { // global NVS and variables - #include "acpi/platform.asl" + #include #include Scope (\_SB) { @@ -38,5 +38,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 989a0cb941..d4ce9401c1 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -96,16 +96,7 @@ static void mb_gpio_init(void) RCBA8(OIC) = 0x03; RCBA8(OIC); - RCBA32(GCS) = 0x00190464; - RCBA32(CG) = 0x00000000; - RCBA32(0x3430) = 0x00000001; - RCBA32(0x3e00) = 0xff000001; - RCBA32(0x3e08) = 0x00000080; - RCBA32(0x3e0c) = 0x00800000; - RCBA32(0x3e40) = 0xff000001; - RCBA32(0x3e48) = 0x00000080; - RCBA32(0x3e4c) = 0x00800000; - RCBA32(0x3f00) = 0x0000000b; + ich7_setup_cir(); } static void ich7_enable_lpc(void) diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl index dbf8c96f51..b1ecdfd076 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl @@ -31,11 +31,11 @@ DefinitionBlock( #include "acpi/superio.asl" #include "acpi/thermal.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Device (\_SB.PCI0) { diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c index a51595f4ff..8a17ac9a56 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c @@ -25,12 +25,6 @@ void pch_enable_lpc(void) { - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | CNF1_LPC_EN); - - if (!CONFIG(NO_UART_ON_SUPERIO)) { - pci_or_config16(PCH_LPC_DEV, LPC_EN, COMA_LPC_EN); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - } } void mainboard_rcba_config(void) diff --git a/src/mainboard/gigabyte/ma785gm/acpi/cpstate.asl b/src/mainboard/gigabyte/ma785gm/acpi/cpstate.asl index 206dd686f5..acaa5bae32 100644 --- a/src/mainboard/gigabyte/ma785gm/acpi/cpstate.asl +++ b/src/mainboard/gigabyte/ma785gm/acpi/cpstate.asl @@ -22,17 +22,25 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/gigabyte/ma785gm/dsdt.asl b/src/mainboard/gigabyte/ma785gm/dsdt.asl index 3059be9a37..eec3093b8e 100644 --- a/src/mainboard/gigabyte/ma785gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gm/dsdt.asl @@ -58,39 +58,24 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - CPU0, /* name space name */ - 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "acpi/cpstate.asl" } - - Processor( - CPU1, /* name space name */ - 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "acpi/cpstate.asl" } - - Processor( - CPU2, /* name space name */ - 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "acpi/cpstate.asl" } - - Processor( - CPU3, /* name space name */ - 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/gigabyte/ma785gmt/acpi/cpstate.asl b/src/mainboard/gigabyte/ma785gmt/acpi/cpstate.asl index 206dd686f5..af0092ae73 100644 --- a/src/mainboard/gigabyte/ma785gmt/acpi/cpstate.asl +++ b/src/mainboard/gigabyte/ma785gmt/acpi/cpstate.asl @@ -16,23 +16,31 @@ /* This file defines the processor and performance state capability * for each core in the system. It is included into the DSDT for each * core. It assumes that each core of the system has the same performance - * characteristics. + * charateristics. */ /* #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/gigabyte/ma785gmt/dsdt.asl b/src/mainboard/gigabyte/ma785gmt/dsdt.asl index 3059be9a37..eec3093b8e 100644 --- a/src/mainboard/gigabyte/ma785gmt/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gmt/dsdt.asl @@ -58,39 +58,24 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - CPU0, /* name space name */ - 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "acpi/cpstate.asl" } - - Processor( - CPU1, /* name space name */ - 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "acpi/cpstate.asl" } - - Processor( - CPU2, /* name space name */ - 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "acpi/cpstate.asl" } - - Processor( - CPU3, /* name space name */ - 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/gigabyte/ma78gm/acpi/cpstate.asl b/src/mainboard/gigabyte/ma78gm/acpi/cpstate.asl index 206dd686f5..acaa5bae32 100644 --- a/src/mainboard/gigabyte/ma78gm/acpi/cpstate.asl +++ b/src/mainboard/gigabyte/ma78gm/acpi/cpstate.asl @@ -22,17 +22,25 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/gigabyte/ma78gm/dsdt.asl b/src/mainboard/gigabyte/ma78gm/dsdt.asl index 3059be9a37..eec3093b8e 100644 --- a/src/mainboard/gigabyte/ma78gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma78gm/dsdt.asl @@ -58,39 +58,24 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - CPU0, /* name space name */ - 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "acpi/cpstate.asl" } - - Processor( - CPU1, /* name space name */ - 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "acpi/cpstate.asl" } - - Processor( - CPU2, /* name space name */ - 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "acpi/cpstate.asl" } - - Processor( - CPU3, /* name space name */ - 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index 7a2aad9a4b..9a5dcc7826 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -51,7 +51,7 @@ DefinitionBlock( #include // Chipset specific sleep states - #include + #include // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index 568c4c819c..d5687f211c 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb index b31d82979c..f6ec15a617 100644 --- a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb @@ -9,9 +9,8 @@ chip soc/intel/broadwell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc b/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc index 26e1a75ca0..44edc70dbb 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc @@ -41,7 +41,7 @@ SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb index 3c00ec954f..db02565b27 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb @@ -9,9 +9,8 @@ chip soc/intel/broadwell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc b/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc index 26e1a75ca0..44edc70dbb 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc @@ -41,7 +41,7 @@ SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/google/auron/variants/buddy/devicetree.cb b/src/mainboard/google/auron/variants/buddy/devicetree.cb index f75da84eee..e12882f413 100644 --- a/src/mainboard/google/auron/variants/buddy/devicetree.cb +++ b/src/mainboard/google/auron/variants/buddy/devicetree.cb @@ -9,9 +9,8 @@ chip soc/intel/broadwell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/gandof/devicetree.cb b/src/mainboard/google/auron/variants/gandof/devicetree.cb index 118e646ee0..230f5bd009 100644 --- a/src/mainboard/google/auron/variants/gandof/devicetree.cb +++ b/src/mainboard/google/auron/variants/gandof/devicetree.cb @@ -9,9 +9,8 @@ chip soc/intel/broadwell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc b/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc index f3a2162ad7..23d0b4e0c3 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc @@ -33,7 +33,7 @@ SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/google/auron/variants/lulu/devicetree.cb b/src/mainboard/google/auron/variants/lulu/devicetree.cb index 622ea3488d..1983045983 100644 --- a/src/mainboard/google/auron/variants/lulu/devicetree.cb +++ b/src/mainboard/google/auron/variants/lulu/devicetree.cb @@ -9,9 +9,8 @@ chip soc/intel/broadwell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc b/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc index bc1454f202..86cb2d2119 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc @@ -42,7 +42,7 @@ SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/google/auron/variants/samus/devicetree.cb b/src/mainboard/google/auron/variants/samus/devicetree.cb index a6c2feae56..434ecc80b9 100644 --- a/src/mainboard/google/auron/variants/samus/devicetree.cb +++ b/src/mainboard/google/auron/variants/samus/devicetree.cb @@ -9,9 +9,8 @@ chip soc/intel/broadwell # Enable DDI2 Hotplug with 6ms pulse register "gpu_dp_c_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000200" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/samus/spd/Makefile.inc b/src/mainboard/google/auron/variants/samus/spd/Makefile.inc index 6a357c0cf0..a026ef3c66 100644 --- a/src/mainboard/google/auron/variants/samus/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/samus/spd/Makefile.inc @@ -41,7 +41,7 @@ SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/google/beltino/acpi/platform.asl b/src/mainboard/google/beltino/acpi/platform.asl index cbe0c6f3ca..54a9cd43e1 100644 --- a/src/mainboard/google/beltino/acpi/platform.asl +++ b/src/mainboard/google/beltino/acpi/platform.asl @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include +#include /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/google/beltino/dsdt.asl b/src/mainboard/google/beltino/dsdt.asl index 41f908fcf7..7b369d8fd7 100644 --- a/src/mainboard/google/beltino/dsdt.asl +++ b/src/mainboard/google/beltino/dsdt.asl @@ -53,5 +53,5 @@ DefinitionBlock( #include // Chipset specific sleep states - #include + #include } diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index f193d83de9..e6cc01f01e 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/butterfly/acpi/mainboard.asl b/src/mainboard/google/butterfly/acpi/mainboard.asl index 4721f2a0d1..2b1d6373e3 100644 --- a/src/mainboard/google/butterfly/acpi/mainboard.asl +++ b/src/mainboard/google/butterfly/acpi/mainboard.asl @@ -29,7 +29,6 @@ Scope (\_SB) { Device (TPAD) { - Name (_ADR, 0x0) Name (_UID, 1) // Report as a Sleep Button device so Linux will diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 1f5939eddb..ea4b8ac04f 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl index dd18e95ae6..8a9d71b560 100644 --- a/src/mainboard/google/butterfly/dsdt.asl +++ b/src/mainboard/google/butterfly/dsdt.asl @@ -24,7 +24,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/platform.asl" @@ -54,5 +54,5 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 067ea4ef94..b5f96b4145 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -24,7 +24,6 @@ #include #include #include -#include #include "onboard.h" #include "ec.h" #include diff --git a/src/mainboard/google/cyan/acpi/codec_maxim.asl b/src/mainboard/google/cyan/acpi/codec_maxim.asl index b412551a4a..b3eb25aeb0 100644 --- a/src/mainboard/google/cyan/acpi/codec_maxim.asl +++ b/src/mainboard/google/cyan/acpi/codec_maxim.asl @@ -20,7 +20,6 @@ Scope (\_SB.PCI0.I2C2) /* Maxim Audio Codec */ Device (MAXM) /* Audio Codec driver I2C */ { - Name (_ADR, 0) Name (_HID, AUDIO_CODEC_HID) Name (_CID, AUDIO_CODEC_CID) Name (_DDN, AUDIO_CODEC_DDN) @@ -64,7 +63,6 @@ Scope (\_SB.PCI0.I2C2) } Device (TISW) /* TI Switch driver I2C */ { - Name (_ADR, 0) Name (_HID, TI_SWITCH_HID) Name (_CID, TI_SWITCH_CID) Name (_DDN, TI_SWITCH_DDN) diff --git a/src/mainboard/google/cyan/acpi/codec_realtek.asl b/src/mainboard/google/cyan/acpi/codec_realtek.asl index d697aace3e..0d188701e7 100644 --- a/src/mainboard/google/cyan/acpi/codec_realtek.asl +++ b/src/mainboard/google/cyan/acpi/codec_realtek.asl @@ -20,7 +20,6 @@ Scope (\_SB.PCI0.I2C5) /* Realtek Audio Codec */ Device (RTEK) /* Audio Codec driver I2C */ { - Name (_ADR, 0) Name (_HID, AUDIO_CODEC_HID) Name (_CID, AUDIO_CODEC_CID) Name (_DDN, AUDIO_CODEC_DDN) diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index 3afdaaab55..7aa62f8fb4 100644 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -62,7 +62,7 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include #include "acpi/mainboard.asl" } diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index 974cd49f25..3525a9813e 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 46939b70e9..30f8805c41 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -330,9 +330,9 @@ static void mainboard_enable(struct device *dev) mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); dcache_mmu_enable(); - const unsigned epll_hz = 192000000; - const unsigned sample_rate = 48000; - const unsigned lr_frame_size = 256; + const unsigned int epll_hz = 192000000; + const unsigned int sample_rate = 48000; + const unsigned int lr_frame_size = 256; clock_epll_set_rate(epll_hz); clock_select_i2s_clk_source(); clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size); diff --git a/src/mainboard/google/dragonegg/Makefile.inc b/src/mainboard/google/dragonegg/Makefile.inc index dcd8cbccbc..8cb746e0a0 100644 --- a/src/mainboard/google/dragonegg/Makefile.inc +++ b/src/mainboard/google/dragonegg/Makefile.inc @@ -24,7 +24,6 @@ romstage-y += romstage_fsp_params.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c -ramstage-y += ramstage.c smm-y += smihandler.c diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl index ab0b977c87..4318dc35f3 100644 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include // global NVS and variables - #include + #include // CPU #include @@ -49,7 +49,7 @@ DefinitionBlock( #endif // Chipset specific sleep states - #include + #include /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/dragonegg/mainboard.c b/src/mainboard/google/dragonegg/mainboard.c index c4df94b1f5..df83f38c3e 100644 --- a/src/mainboard/google/dragonegg/mainboard.c +++ b/src/mainboard/google/dragonegg/mainboard.c @@ -23,6 +23,12 @@ static void mainboard_init(void *chip_info) { + size_t num; + const struct pad_config *gpio_table; + + gpio_table = variant_gpio_table(&num); + gpio_configure_pads(gpio_table, num); + mainboard_ec_init(); } diff --git a/src/mainboard/google/dragonegg/spd/Makefile.inc b/src/mainboard/google/dragonegg/spd/Makefile.inc index 7aa9505e9e..2fdd9d47f8 100644 --- a/src/mainboard/google/dragonegg/spd/Makefile.inc +++ b/src/mainboard/google/dragonegg/spd/Makefile.inc @@ -30,7 +30,7 @@ endif $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 35f7150836..256f8cbdae 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -84,7 +84,9 @@ config MAX_CPUS config UART_FOR_CONSOLE int - default 0 + default 2 if BOARD_GOOGLE_ARCADA_CML + default 2 if BOARD_GOOGLE_SARIEN_CML + default 0 if BOARD_GOOGLE_DRALLION config VARIANT_DIR string diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd index 8bab919c6d..6e9170ed41 100644 --- a/src/mainboard/google/drallion/chromeos.fmd +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -40,8 +40,8 @@ FLASH@0xfe000000 0x2000000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x300000 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3ec000 } } } diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 2568800f91..0a092cff0f 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -29,7 +29,7 @@ DefinitionBlock( #include /* global NVS and variables */ - #include + #include /* CPU */ #include @@ -54,7 +54,7 @@ DefinitionBlock( #endif /* Chipset specific sleep states */ - #include + #include /* Low power idle table */ #include diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index b3bf10296a..6d3ebb46cb 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -66,7 +66,7 @@ static const struct pad_config gpio_unused[] = { /* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), }; -void mainboard_silicon_init_params(FSP_S_CONFIG *params) +static void mainboard_init(void *chip_info) { const struct pad_config *gpio_table; size_t num_gpios; @@ -85,5 +85,6 @@ static void mainboard_enable(struct device *dev) } struct chip_operations mainboard_ops = { + .init = mainboard_init, .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/drallion/spd/Makefile.inc b/src/mainboard/google/drallion/spd/Makefile.inc index e35544bc7d..9ab7394b30 100644 --- a/src/mainboard/google/drallion/spd/Makefile.inc +++ b/src/mainboard/google/drallion/spd/Makefile.inc @@ -25,7 +25,7 @@ endif $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex b/src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex new file mode 100644 index 0000000000..4fe4d0e657 --- /dev/null +++ b/src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 40 36 +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 7D 21 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 34 41 54 46 35 31 32 +36 34 48 5A 2D 33 47 32 45 31 20 20 20 31 80 2C +45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index ef3d54d185..ccbcb08da8 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -22,6 +22,7 @@ SPD_SOURCES += hynix_dimm_H5AN8G6NCJR-VKC # 0b10001 SPD_SOURCES += hynix_dimm_H5ANAG6NCMR-VKC # 0b11001 SPD_SOURCES += samsung_dimm_K4A8G165WC-BCTD # 0b10011 SPD_SOURCES += samsung_dimm_K4AAG165WB-MCTD # 0b11011 +SPD_SOURCES += micron_dimm_MT40A1G16KD-062EE # 0b11010 bootblock-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index db3f36bc8d..ed44f4fec1 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -322,13 +322,15 @@ chip soc/intel/cannonlake register "generic.desc" = ""Wacom Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "generic.reset_delay_ms" = "20" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.stop_delay_ms" = "20" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "generic.enable_delay_ms" = "55" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x1" + register "generic.device_present_gpio" = "GPP_B4" + register "generic.device_present_gpio_invert" = "1" device i2c 0A on end end chip drivers/i2c/hid @@ -336,9 +338,9 @@ chip soc/intel/cannonlake register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" - register "generic.reset_gpio" = + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "generic.reset_delay_ms" = "10" + register "generic.stop_delay_ms" = "10" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "generic.enable_delay_ms" = "55" @@ -353,8 +355,8 @@ chip soc/intel/cannonlake register "desc" = ""Melfas Touchscreen"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "reset_delay_ms" = "10" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "stop_delay_ms" = "10" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "enable_delay_ms" = "55" register "has_power_resource" = "1" @@ -371,6 +373,13 @@ chip soc/intel/cannonlake register "probed" = "1" device i2c 2c on end end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "probed" = "1" + device i2c 15 on end + end end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index f0fc55e8d4..5657eeaae1 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -39,13 +39,13 @@ static const struct pad_config gpio_table[] = { /* ESPI_RESET# */ /* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* SD_1P8_SEL */ PAD_CFG_GPI(GPP_A16, NONE, PLTRST), /* 2.7MM_CAM_DET# */ -/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF2), +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), /* ISH_ACC1_INT# */ /* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* ISH_ACC2_INT# */ /* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), -/* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), /* ISH_NB_MODE */ /* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /* ISH_LID_CL#_NB */ @@ -63,11 +63,10 @@ static const struct pad_config gpio_table[] = { /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN_CLKREQ_CPU_N */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), - /* WWAN_CLKREQ_CPU_N */ -/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), /* SSD_CKLREQ_CPU_N */ /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, PLTRST), /* 3.3V_CAM_EN# */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), @@ -78,7 +77,7 @@ static const struct pad_config gpio_table[] = { /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), -/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, PLTRST), /* PCH_3.3V_TS_EN */ +/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 0, PLTRST), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), @@ -154,7 +153,7 @@ static const struct pad_config gpio_table[] = { /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ -/* DDPE_HPD3 */ PAD_CFG_GPO(GPP_E16, 1, PLTRST), /* HDMI_PD# */ +/* DDPE_HPD3 */ PAD_CFG_GPO(GPP_E16, 1, DEEP), /* HDMI_PD# */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl index 41121d28fe..dbe487e8ac 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl @@ -15,6 +15,7 @@ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 +#define HDMI_PD GPP_E16 /* Method called from LPIT prior to enter s0ix state */ Method (MS0X, 1) @@ -22,9 +23,13 @@ Method (MS0X, 1) If (Arg0) { /* Turn off camera power */ \_SB.PCI0.STXS (CAM_EN) + /* Turn off HDMI power */ + \_SB.PCI0.CTXS (HDMI_PD) } Else { /* Turn on camera power */ \_SB.PCI0.CTXS (CAM_EN) + /* Turn on HDMI power */ + \_SB.PCI0.STXS (HDMI_PD) } } @@ -35,6 +40,8 @@ Method (MPTS, 1) /* Clear touch screen pd pin to avoid leakage */ \_SB.PCI0.CTXS (TS_PD) + /* Clear HDMI power to avoid leakage */ + \_SB.PCI0.CTXS (HDMI_PD) } /* Method called from _WAK prior to wakeup */ diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c index 37d009adf9..9c4135dfdc 100644 --- a/src/mainboard/google/drallion/variants/drallion/memory.c +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -24,7 +24,7 @@ static const int spd_index[32] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, 6, 1, 0, 0, 0, - 0, 5, 0, 7, 2, 0, 0, 0 + 0, 5, 8, 7, 2, 0, 0, 0 }; const struct cnl_mb_cfg *get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg) diff --git a/src/mainboard/google/eve/Makefile.inc b/src/mainboard/google/eve/Makefile.inc index d853404a45..d137f92b2d 100644 --- a/src/mainboard/google/eve/Makefile.inc +++ b/src/mainboard/google/eve/Makefile.inc @@ -23,7 +23,6 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c -ramstage-y += ramstage.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c smm-y += smihandler.c diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index a705457826..3e9d570705 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -48,7 +48,7 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/eve/mainboard.c b/src/mainboard/google/eve/mainboard.c index 9b9ccdd05f..aceb7b7f6d 100644 --- a/src/mainboard/google/eve/mainboard.c +++ b/src/mainboard/google/eve/mainboard.c @@ -21,6 +21,8 @@ #include #include +#include "gpio.h" + #define SUBSYSTEM_ID 0x1AE0006B static const char *oem_id_maxim = "GOOGLE"; @@ -74,6 +76,12 @@ static void mainboard_enable(struct device *dev) dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } +static void mainboard_chip_init(void *chip_info) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + struct chip_operations mainboard_ops = { + .init = mainboard_chip_init, .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/eve/spd/Makefile.inc b/src/mainboard/google/eve/spd/Makefile.inc index c97a818b55..cb4f8a8124 100644 --- a/src/mainboard/google/eve/spd/Makefile.inc +++ b/src/mainboard/google/eve/spd/Makefile.inc @@ -32,7 +32,7 @@ SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f). $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/google/fizz/Makefile.inc b/src/mainboard/google/fizz/Makefile.inc index 5514090d4e..3e030c3270 100644 --- a/src/mainboard/google/fizz/Makefile.inc +++ b/src/mainboard/google/fizz/Makefile.inc @@ -23,7 +23,6 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c -ramstage-y += ramstage.c smm-y += smihandler.c diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl index 03df2b9c8b..44d544c378 100644 --- a/src/mainboard/google/fizz/dsdt.asl +++ b/src/mainboard/google/fizz/dsdt.asl @@ -48,7 +48,7 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 89e692741e..6a7d452942 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -26,8 +27,11 @@ #include #include #include +#include #include +#include + #define FIZZ_SKU_ID_I7_U42 0x4 #define FIZZ_SKU_ID_I5_U42 0x5 #define FIZZ_SKU_ID_I3_U42 0x6 @@ -230,6 +234,50 @@ static void mainboard_enable(struct device *dev) dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } +#define GPIO_HDMI_HPD GPP_E13 +#define GPIO_DP_HPD GPP_E14 + +/* TODO: This can be moved to common directory */ +static void wait_for_hpd(gpio_t gpio, long timeout) +{ + struct stopwatch sw; + + printk(BIOS_INFO, "Waiting for HPD\n"); + gpio_input(gpio); + + stopwatch_init_msecs_expire(&sw, timeout); + while (!gpio_get(gpio)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_WARNING, + "HPD not ready after %ldms. Abort.\n", timeout); + return; + } + mdelay(200); + } + printk(BIOS_INFO, "HPD ready after %lu ms\n", + stopwatch_duration_msecs(&sw)); +} + +static void mainboard_chip_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + static const long display_timeout_ms = 3000; + + /* This is reconfigured back to whatever FSP-S expects by + gpio_configure_pads. */ + gpio_input(GPIO_HDMI_HPD); + if (display_init_required() && !gpio_get(GPIO_HDMI_HPD)) { + /* This has to be done before FSP-S runs. */ + if (google_chromeec_wait_for_displayport(display_timeout_ms)) + wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); + } + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + struct chip_operations mainboard_ops = { + .init = mainboard_chip_init, .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/fizz/ramstage.c b/src/mainboard/google/fizz/ramstage.c deleted file mode 100644 index d42f68cad4..0000000000 --- a/src/mainboard/google/fizz/ramstage.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#define GPIO_HDMI_HPD GPP_E13 -#define GPIO_DP_HPD GPP_E14 - -/* TODO: This can be moved to common directory */ -static void wait_for_hpd(gpio_t gpio, long timeout) -{ - struct stopwatch sw; - - printk(BIOS_INFO, "Waiting for HPD\n"); - gpio_input(gpio); - - stopwatch_init_msecs_expire(&sw, timeout); - while (!gpio_get(gpio)) { - if (stopwatch_expired(&sw)) { - printk(BIOS_WARNING, - "HPD not ready after %ldms. Abort.\n", timeout); - return; - } - mdelay(200); - } - printk(BIOS_INFO, "HPD ready after %lu ms\n", - stopwatch_duration_msecs(&sw)); -} - -void mainboard_silicon_init_params(FSP_SIL_UPD *params) -{ - const struct pad_config *pads; - size_t num; - static const long display_timeout_ms = 3000; - - /* This is reconfigured back to whatever FSP-S expects by - gpio_configure_pads. */ - gpio_input(GPIO_HDMI_HPD); - if (display_init_required() && !gpio_get(GPIO_HDMI_HPD)) { - /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms)) - wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); - } - - pads = variant_gpio_table(&num); - gpio_configure_pads(pads, num); -} diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 7ce1300509..e14fbcb791 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -18,7 +18,6 @@ #include #include #include -#include #include void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/foster/mainboard.c b/src/mainboard/google/foster/mainboard.c index daddf5c04f..14de42ef36 100644 --- a/src/mainboard/google/foster/mainboard.c +++ b/src/mainboard/google/foster/mainboard.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index 13e2a4743f..6435317a22 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -34,7 +34,7 @@ struct max77620_init_reg { u8 delay; }; -static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay) +static void pmic_write_reg(unsigned int bus, uint8_t reg, uint8_t val, int delay) { if (i2c_writeb(bus, MAX77620_I2C_ADDR, reg, val)) { printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", @@ -47,7 +47,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay) } } -void pmic_init(unsigned bus) +void pmic_init(unsigned int bus) { /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */ pmic_write_reg(bus, MAX77620_GPIO5_REG, 0x09, 1); diff --git a/src/mainboard/google/foster/pmic.h b/src/mainboard/google/foster/pmic.h index 13ca1ee600..b4735bde95 100644 --- a/src/mainboard/google/foster/pmic.h +++ b/src/mainboard/google/foster/pmic.h @@ -65,6 +65,6 @@ #define MAX77620_CID4_REG 0x5C #define MAX77620_CID5_REG 0x5D -void pmic_init(unsigned bus); +void pmic_init(unsigned int bus); #endif /* __MAINBOARD_GOOGLE_FOSTER_PMIC_H__ */ diff --git a/src/mainboard/google/gale/cdp.c b/src/mainboard/google/gale/cdp.c index 11a0f687eb..2b1d145d86 100644 --- a/src/mainboard/google/gale/cdp.c +++ b/src/mainboard/google/gale/cdp.c @@ -20,7 +20,7 @@ #include #include -void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count) +void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count) { int i; diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 8e48dc710f..fe7359f59f 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -62,6 +62,9 @@ config DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +config INTEL_GMA_VBT_FILE + default "3rdparty/fsp/KabylakeFspBinPkg/SampleCode/Vbt/Vbt.bin" + config MAX_CPUS int default 8 diff --git a/src/mainboard/google/glados/Makefile.inc b/src/mainboard/google/glados/Makefile.inc index da9de29521..323e68baa2 100644 --- a/src/mainboard/google/glados/Makefile.inc +++ b/src/mainboard/google/glados/Makefile.inc @@ -27,7 +27,6 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c -ramstage-y += ramstage.c smm-y += smihandler.c diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index af5f99d815..6dab56ea77 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -49,7 +49,7 @@ DefinitionBlock( #include // Chipset specific sleep states - #include + #include // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index 8b04a65c8d..ebc50f41e2 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -115,6 +115,14 @@ static void mainboard_enable(struct device *dev) dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } +static void mainboard_chip_init(void *chip_info) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + struct chip_operations mainboard_ops = { + .init = mainboard_chip_init, .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/glados/ramstage.c b/src/mainboard/google/glados/ramstage.c deleted file mode 100644 index 27d674d713..0000000000 --- a/src/mainboard/google/glados/ramstage.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corporation - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void mainboard_silicon_init_params(SILICON_INIT_UPD *params) -{ - /* Configure pads prior to SiliconInit() in case there's any - * dependencies during hardware initialization. */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -} diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index f2daa38d00..113d28bd50 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -25,18 +25,18 @@ #include "spd/spd_util.h" #include "spd/spd.h" -void mainboard_pre_raminit(struct romstage_params *params) + +void mainboard_memory_init_params(FSPM_UPD *mupd) { + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + #ifdef EC_ENABLE_KEYBOARD_BACKLIGHT /* Turn on keyboard backlight to indicate we are booting */ - if (params->power_state->prev_sleep_state != ACPI_S3) + const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; + if (arch_upd->BootMode != FSP_BOOT_ON_S3_RESUME) google_chromeec_kbbacklight(25); #endif -} -void mainboard_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) -{ /* Get SPD index */ const gpio_t spd_gpios[] = { GPIO_MEM_CONFIG_0, @@ -46,9 +46,9 @@ void mainboard_memory_init_params(struct romstage_params *params, }; const int spd_idx = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); - memory_params->MemorySpdDataLen = SPD_LEN; - memory_params->DqPinsInterleaved = FALSE; + mem_cfg->MemorySpdDataLen = SPD_LEN; + mem_cfg->DqPinsInterleaved = FALSE; - spd_memory_init_params(memory_params, spd_idx); - variant_memory_init_params(memory_params, spd_idx); + spd_memory_init_params(mupd, spd_idx); + variant_memory_init_params(mupd, spd_idx); } diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index 9503582c9a..324d3be866 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -83,8 +83,10 @@ __weak int is_dual_channel(const int spd_index) } /* Copy SPD data for on-board memory */ -void spd_memory_init_params(MEMORY_INIT_UPD *const memory_params, int spd_index) +void spd_memory_init_params(FSPM_UPD *mupd, int spd_index) { + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; uint8_t *spd_file; size_t spd_file_len; @@ -112,9 +114,9 @@ void spd_memory_init_params(MEMORY_INIT_UPD *const memory_params, int spd_index) die("Invalid SPD data."); /* Assume same memory in both channels */ - memory_params->MemorySpdPtr00 = (uintptr_t)spd_file + spd_offset; + mem_cfg->MemorySpdPtr00 = (uintptr_t)spd_file + spd_offset; if (is_dual_channel(spd_index)) - memory_params->MemorySpdPtr10 = memory_params->MemorySpdPtr00; + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; mainboard_print_spd_info(spd_file + spd_offset); } diff --git a/src/mainboard/google/glados/spd/spd_util.h b/src/mainboard/google/glados/spd/spd_util.h index 90dbd5ff98..b1e9a7a8a2 100644 --- a/src/mainboard/google/glados/spd/spd_util.h +++ b/src/mainboard/google/glados/spd/spd_util.h @@ -16,6 +16,6 @@ #include -void spd_memory_init_params(MEMORY_INIT_UPD *, int spd_index); +void spd_memory_init_params(FSPM_UPD *mupd, int spd_index); #endif /* SPD_UTIL_H */ diff --git a/src/mainboard/google/glados/variants/asuka/data.vbt b/src/mainboard/google/glados/variants/asuka/data.vbt deleted file mode 100644 index 8f2a7b0614..0000000000 Binary files a/src/mainboard/google/glados/variants/asuka/data.vbt and /dev/null differ diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb index cddb10d11a..27bbebaa57 100644 --- a/src/mainboard/google/glados/variants/asuka/devicetree.cb +++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb @@ -60,20 +60,20 @@ chip soc/intel/skylake register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -100,19 +100,6 @@ chip soc/intel/skylake .voltage_limit = 1520, }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), - .voltage_limit = 1520, - }" - register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), diff --git a/src/mainboard/google/glados/variants/asuka/variant.c b/src/mainboard/google/glados/variants/asuka/variant.c index fdef81c5cd..75e0ea689d 100644 --- a/src/mainboard/google/glados/variants/asuka/variant.c +++ b/src/mainboard/google/glados/variants/asuka/variant.c @@ -18,10 +18,13 @@ #include #include #include +#include -void variant_memory_init_params( - MEMORY_INIT_UPD *const memory_params, const int spd_index) +void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index) { + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + /* DQ byte map */ const u8 dq_map[2][12] = { { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, @@ -39,18 +42,12 @@ void variant_memory_init_params( /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map[0], - sizeof(memory_params->DqByteMapCh0)); - memcpy(memory_params->DqByteMapCh1, dq_map[1], - sizeof(memory_params->DqByteMapCh1)); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], - sizeof(memory_params->DqsMapCpu2DramCh0)); - memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], - sizeof(memory_params->DqsMapCpu2DramCh1)); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0)); + memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1)); + memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0)); + memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1)); + memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget)); } int is_dual_channel(const int spd_index) diff --git a/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h b/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h index 72eef684b8..45636acad2 100644 --- a/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h +++ b/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h @@ -19,6 +19,6 @@ int is_dual_channel(const int spd_index); void mainboard_gpio_smi_sleep(void); -void variant_memory_init_params(MEMORY_INIT_UPD *memory_params, int spd_index); +void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index); #endif /* GLADOS_VARIANT_H */ diff --git a/src/mainboard/google/glados/variants/caroline/data.vbt b/src/mainboard/google/glados/variants/caroline/data.vbt deleted file mode 100644 index 02e1cd10f6..0000000000 Binary files a/src/mainboard/google/glados/variants/caroline/data.vbt and /dev/null differ diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb index aabf179b93..6314af8661 100644 --- a/src/mainboard/google/glados/variants/caroline/devicetree.cb +++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb @@ -71,20 +71,20 @@ chip soc/intel/skylake register "SlowSlewRateForSa" = "0" # Fast/2 register "FastPkgCRampDisable" = "0" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 4A | 24A | 24A | 24A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -111,19 +111,6 @@ chip soc/intel/skylake .voltage_limit = 1520, }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), - .voltage_limit = 1520, - }" - register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), diff --git a/src/mainboard/google/glados/variants/caroline/variant.c b/src/mainboard/google/glados/variants/caroline/variant.c index ab6bd2c1bd..4338d55602 100644 --- a/src/mainboard/google/glados/variants/caroline/variant.c +++ b/src/mainboard/google/glados/variants/caroline/variant.c @@ -21,9 +21,11 @@ #include #include -void variant_memory_init_params( - MEMORY_INIT_UPD *const memory_params, const int spd_index) +void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index) { + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + /* DQ byte map */ const u8 dq_map[2][12] = { { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, @@ -41,19 +43,12 @@ void variant_memory_init_params( /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map[0], - sizeof(memory_params->DqByteMapCh0)); - memcpy(memory_params->DqByteMapCh1, dq_map[1], - sizeof(memory_params->DqByteMapCh1)); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], - sizeof(memory_params->DqsMapCpu2DramCh0)); - memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], - sizeof(memory_params->DqsMapCpu2DramCh1)); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); - memory_params->DdrFreqLimit = 1600; + memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0)); + memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1)); + memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0)); + memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1)); + memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget)); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/cave/data.vbt b/src/mainboard/google/glados/variants/cave/data.vbt deleted file mode 100644 index 02e1cd10f6..0000000000 Binary files a/src/mainboard/google/glados/variants/cave/data.vbt and /dev/null differ diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb index 993cab0cee..22ee80f56d 100644 --- a/src/mainboard/google/glados/variants/cave/devicetree.cb +++ b/src/mainboard/google/glados/variants/cave/devicetree.cb @@ -70,20 +70,20 @@ chip soc/intel/skylake register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 4A | 24A | 24A | 24A | 24A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 4A | 24A | 24A | 24A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -110,19 +110,6 @@ chip soc/intel/skylake .voltage_limit = 1520, }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), - .voltage_limit = 1520, - }" - register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), diff --git a/src/mainboard/google/glados/variants/cave/variant.c b/src/mainboard/google/glados/variants/cave/variant.c index d63a298df7..d625f1700a 100644 --- a/src/mainboard/google/glados/variants/cave/variant.c +++ b/src/mainboard/google/glados/variants/cave/variant.c @@ -21,9 +21,11 @@ #include #include -void variant_memory_init_params( - MEMORY_INIT_UPD *const memory_params, const int spd_index) +void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index) { + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + /* DQ byte map */ const u8 dq_map[2][12] = { { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, @@ -41,18 +43,12 @@ void variant_memory_init_params( /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map[0], - sizeof(memory_params->DqByteMapCh0)); - memcpy(memory_params->DqByteMapCh1, dq_map[1], - sizeof(memory_params->DqByteMapCh1)); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], - sizeof(memory_params->DqsMapCpu2DramCh0)); - memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], - sizeof(memory_params->DqsMapCpu2DramCh1)); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0)); + memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1)); + memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0)); + memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1)); + memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget)); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/chell/data.vbt b/src/mainboard/google/glados/variants/chell/data.vbt deleted file mode 100644 index a654a5efd5..0000000000 Binary files a/src/mainboard/google/glados/variants/chell/data.vbt and /dev/null differ diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb index a3797571ff..89f1c08b75 100644 --- a/src/mainboard/google/glados/variants/chell/devicetree.cb +++ b/src/mainboard/google/glados/variants/chell/devicetree.cb @@ -70,20 +70,20 @@ chip soc/intel/skylake register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 4A | 24A | 24A | 24A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -93,7 +93,7 @@ chip soc/intel/skylake .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(7), + .icc_max = VR_CFG_AMP(4), .voltage_limit = 1520, }" @@ -106,20 +106,7 @@ chip soc/intel/skylake .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), - .voltage_limit = 1520, - }" - - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), + .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, }" @@ -132,7 +119,7 @@ chip soc/intel/skylake .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), + .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, }" @@ -145,7 +132,7 @@ chip soc/intel/skylake .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), + .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, }" diff --git a/src/mainboard/google/glados/variants/chell/variant.c b/src/mainboard/google/glados/variants/chell/variant.c index 3e8503fe9e..892dbeed38 100644 --- a/src/mainboard/google/glados/variants/chell/variant.c +++ b/src/mainboard/google/glados/variants/chell/variant.c @@ -21,15 +21,18 @@ #include #include -void variant_memory_init_params( - MEMORY_INIT_UPD *const memory_params, const int spd_index) +void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index) { + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + /* DQ byte map */ const u8 dq_map[2][12] = { { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 0, 3, 1, 2, 4, 5, 6, 7 }, @@ -41,18 +44,12 @@ void variant_memory_init_params( /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map[0], - sizeof(memory_params->DqByteMapCh0)); - memcpy(memory_params->DqByteMapCh1, dq_map[1], - sizeof(memory_params->DqByteMapCh1)); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], - sizeof(memory_params->DqsMapCpu2DramCh0)); - memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], - sizeof(memory_params->DqsMapCpu2DramCh1)); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0)); + memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1)); + memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0)); + memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1)); + memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget)); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb index 1d9e6cdf1f..20166253c9 100644 --- a/src/mainboard/google/glados/variants/glados/devicetree.cb +++ b/src/mainboard/google/glados/variants/glados/devicetree.cb @@ -70,20 +70,20 @@ chip soc/intel/skylake register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -110,19 +110,6 @@ chip soc/intel/skylake .voltage_limit = 1520, }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), - .voltage_limit = 1520, - }" - register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), diff --git a/src/mainboard/google/glados/variants/glados/variant.c b/src/mainboard/google/glados/variants/glados/variant.c index d63a298df7..d625f1700a 100644 --- a/src/mainboard/google/glados/variants/glados/variant.c +++ b/src/mainboard/google/glados/variants/glados/variant.c @@ -21,9 +21,11 @@ #include #include -void variant_memory_init_params( - MEMORY_INIT_UPD *const memory_params, const int spd_index) +void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index) { + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + /* DQ byte map */ const u8 dq_map[2][12] = { { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, @@ -41,18 +43,12 @@ void variant_memory_init_params( /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map[0], - sizeof(memory_params->DqByteMapCh0)); - memcpy(memory_params->DqByteMapCh1, dq_map[1], - sizeof(memory_params->DqByteMapCh1)); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], - sizeof(memory_params->DqsMapCpu2DramCh0)); - memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], - sizeof(memory_params->DqsMapCpu2DramCh1)); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0)); + memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1)); + memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0)); + memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1)); + memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget)); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb index b8871d196d..503cf5a58d 100644 --- a/src/mainboard/google/glados/variants/lars/devicetree.cb +++ b/src/mainboard/google/glados/variants/lars/devicetree.cb @@ -58,20 +58,20 @@ chip soc/intel/skylake register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -98,19 +98,6 @@ chip soc/intel/skylake .voltage_limit = 1520, }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), - .voltage_limit = 1520, - }" - register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c index 37860c3738..c24950d814 100644 --- a/src/mainboard/google/glados/variants/lars/variant.c +++ b/src/mainboard/google/glados/variants/lars/variant.c @@ -28,9 +28,11 @@ #define MEM_SINGLE_CHANB 0xb #define MEM_SINGLE_CHANC 0xc -void variant_memory_init_params( - MEMORY_INIT_UPD *const params, const int spd_index) +void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index) { + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + /* DQ byte map */ const u8 dq_map[2][12] = { { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, @@ -58,18 +60,12 @@ void variant_memory_init_params( if (spd_index == K4E6E304EB_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(params->DqByteMapCh0, dq_map[0], - sizeof(params->DqByteMapCh0)); - memcpy(params->DqByteMapCh1, dq_map[1], - sizeof(params->DqByteMapCh1)); - memcpy(params->DqsMapCpu2DramCh0, dqs_map[0], - sizeof(params->DqsMapCpu2DramCh0)); - memcpy(params->DqsMapCpu2DramCh1, dqs_map[1], - sizeof(params->DqsMapCpu2DramCh1)); - memcpy(params->RcompResistor, RcompResistor, - sizeof(params->RcompResistor)); - memcpy(params->RcompTarget, targeted_rcomp, - sizeof(params->RcompTarget)); + memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0)); + memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1)); + memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0)); + memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1)); + memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget)); } int is_dual_channel(const int spd_index) diff --git a/src/mainboard/google/glados/variants/sentry/data.vbt b/src/mainboard/google/glados/variants/sentry/data.vbt deleted file mode 100644 index 0aac82c3b1..0000000000 Binary files a/src/mainboard/google/glados/variants/sentry/data.vbt and /dev/null differ diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb index 7f52586e3d..4c6bbf817a 100644 --- a/src/mainboard/google/glados/variants/sentry/devicetree.cb +++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb @@ -60,20 +60,20 @@ chip soc/intel/skylake register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -100,19 +100,6 @@ chip soc/intel/skylake .voltage_limit = 1520, }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), - .voltage_limit = 1520, - }" - register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), diff --git a/src/mainboard/google/glados/variants/sentry/variant.c b/src/mainboard/google/glados/variants/sentry/variant.c index 101be2a0fb..b77e5edc7f 100644 --- a/src/mainboard/google/glados/variants/sentry/variant.c +++ b/src/mainboard/google/glados/variants/sentry/variant.c @@ -21,9 +21,11 @@ #define K4E6E304EE_MEM_ID 0x3 -void variant_memory_init_params( - MEMORY_INIT_UPD *const memory_params, const int spd_index) +void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index) { + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + /* DQ byte map */ const u8 dq_map[2][12] = { { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, @@ -51,16 +53,10 @@ void variant_memory_init_params( if (spd_index == K4E6E304EE_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(memory_params->DqByteMapCh0, dq_map[0], - sizeof(memory_params->DqByteMapCh0)); - memcpy(memory_params->DqByteMapCh1, dq_map[1], - sizeof(memory_params->DqByteMapCh1)); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], - sizeof(memory_params->DqsMapCpu2DramCh0)); - memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], - sizeof(memory_params->DqsMapCpu2DramCh1)); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, targeted_rcomp, - sizeof(memory_params->RcompTarget)); + memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0)); + memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1)); + memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0)); + memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1)); + memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget)); } diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index fbc4c15894..160194bcfb 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -30,3 +30,5 @@ config BOARD_GOOGLE_HELIOS bool "-> Helios" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 + select CHROMEOS_DSM_CALIB + select DRIVERS_I2C_RT1011 diff --git a/src/mainboard/google/hatch/chromeos-16MiB.fmd b/src/mainboard/google/hatch/chromeos-16MiB.fmd index eb92bb0a01..8880a4f9fe 100644 --- a/src/mainboard/google/hatch/chromeos-16MiB.fmd +++ b/src/mainboard/google/hatch/chromeos-16MiB.fmd @@ -35,8 +35,8 @@ FLASH@0xff000000 0x1000000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x30c000 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 } } } diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd index 393ac808b5..8368b0a44b 100644 --- a/src/mainboard/google/hatch/chromeos.fmd +++ b/src/mainboard/google/hatch/chromeos.fmd @@ -19,7 +19,7 @@ FLASH@0xfe000000 0x2000000 { RW_FWID_B@0x3dffc0 0x40 } RW_MISC@0x17c0000 0x40000 { - UNIFIED_MRC_CACHE@0x0 0x30000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x20000 } @@ -39,8 +39,8 @@ FLASH@0xfe000000 0x2000000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x30c000 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 } } } diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index e2959a788a..62478293f3 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include /* global NVS and variables */ - #include + #include /* CPU */ #include @@ -52,10 +52,10 @@ DefinitionBlock( #endif /* Chipset specific sleep states */ - #include + #include - /* Low power idle table */ - #include + /* Low power idle table */ + #include /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index 04e1bc10ea..e9f50625cd 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -22,13 +22,33 @@ #include void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + variant_devtree_update(); +} + +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ +} + +static void mainboard_init(struct device *dev) +{ + mainboard_ec_init(); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +static void mainboard_chip_init(void *chip_info) { const struct pad_config *base_table; const struct pad_config *override_table; size_t base_gpios; size_t override_gpios; - variant_devtree_update(); base_table = base_gpio_table(&base_gpios); override_table = override_gpio_table(&override_gpios); @@ -38,18 +58,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) override_gpios); } -void __weak variant_devtree_update(void) -{ - /* Override dev tree settings per board */ -} - -static void mainboard_enable(struct device *dev) -{ - mainboard_ec_init(); - - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; -} - struct chip_operations mainboard_ops = { + .init = mainboard_chip_init, .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/hatch/spd/Makefile.inc b/src/mainboard/google/hatch/spd/Makefile.inc index e35544bc7d..97a4dfdace 100644 --- a/src/mainboard/google/hatch/spd/Makefile.inc +++ b/src/mainboard/google/hatch/spd/Makefile.inc @@ -13,22 +13,20 @@ ## GNU General Public License for more details. ## +ifneq ($(SPD_SOURCES),) SPD_BIN = $(obj)/spd.bin -ifeq ($(SPD_SOURCES),) - SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) -else - SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) -endif +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) # Include spd ROM data $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := spd +endif diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 1ba9d3523d..4be3c34722 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -17,7 +17,6 @@ #include #include #include -#include static const struct pad_config ssd_sku_gpio_table[] = { /* A0 : NC */ diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl index 31f72b3f03..bb46fe9b1c 100644 --- a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl @@ -13,4 +13,133 @@ * GNU General Public License for more details. */ -#include +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_ACTIVE_AC0 87 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 39 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - CPU" +#define DPTF_TSR2_PASSIVE 60 +#define DPTF_TSR2_CRITICAL 75 +#define DPTF_TSR2_ACTIVE_AC0 51 +#define DPTF_TSR2_ACTIVE_AC1 48 +#define DPTF_TSR2_ACTIVE_AC2 45 +#define DPTF_TSR2_ACTIVE_AC3 42 +#define DPTF_TSR2_ACTIVE_AC4 39 +#define DPTF_TSR2_ACTIVE_AC5 36 +#define DPTF_TSR2_ACTIVE_AC6 33 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 80, 70, 60, 50, 40, 30, + 0, 0, 0 + }, +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on CPU (TSR2) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 64000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index 5ba8531ba3..51395f9f5c 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -1,12 +1,14 @@ chip soc/intel/cannonlake + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "51" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, [PchSerialIoIndexSPI0] = PchSerialIoPci, [PchSerialIoIndexSPI1] = PchSerialIoPci, [PchSerialIoIndexSPI2] = PchSerialIoDisabled, @@ -35,17 +37,14 @@ chip soc/intel/cannonlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 50, + .fall_time_ns = 15, }, .i2c[1] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 60, .fall_time_ns = 25, }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 150, - .fall_time_ns = 150, - }, .i2c[4] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 120, @@ -100,57 +99,18 @@ chip soc/intel/cannonlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "10" - register "generic.reset_off_delay_ms" = "1" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "12" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end - chip drivers/generic/gpio_keys - register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" - register "key.wake" = "GPE0_DW0_08" - register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" - register "key.dev_name" = ""EJCT"" - register "key.linux_code" = "SW_PEN_INSERTED" - register "key.linux_input_type" = "EV_SW" - register "key.label" = ""pen_eject"" - device generic 0 on end - end end # I2C #1 device pci 15.2 off end # I2C #2 - device pci 15.3 on - chip drivers/i2c/sx9310 - register "desc" = ""SAR Proximity Sensor"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)" - register "speed" = "I2C_SPEED_FAST" - register "uid" = "1" - register "reg_prox_ctrl0" = "0x10" - register "reg_prox_ctrl1" = "0x00" - register "reg_prox_ctrl2" = "0x84" - register "reg_prox_ctrl3" = "0x0e" - register "reg_prox_ctrl4" = "0x07" - register "reg_prox_ctrl5" = "0xc6" - register "reg_prox_ctrl6" = "0x20" - register "reg_prox_ctrl7" = "0x0d" - register "reg_prox_ctrl8" = "0x8d" - register "reg_prox_ctrl9" = "0x43" - register "reg_prox_ctrl10" = "0x1f" - register "reg_prox_ctrl11" = "0x00" - register "reg_prox_ctrl12" = "0x00" - register "reg_prox_ctrl13" = "0x00" - register "reg_prox_ctrl14" = "0x00" - register "reg_prox_ctrl15" = "0x00" - register "reg_prox_ctrl16" = "0x00" - register "reg_prox_ctrl17" = "0x00" - register "reg_prox_ctrl18" = "0x00" - register "reg_prox_ctrl19" = "0x00" - register "reg_sar_ctrl0" = "0x50" - register "reg_sar_ctrl1" = "0x8a" - register "reg_sar_ctrl2" = "0x3c" - device i2c 28 on end - end - end # I2C #3 + device pci 15.3 off end # I2C #3 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -166,16 +126,7 @@ chip soc/intel/cannonlake end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1e.3 on - chip drivers/spi/acpi - register "name" = ""CRFP"" - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "uid" = "1" - register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" - device spi 1 on end - end # FPMCU - end # GSPI #1 + device pci 1e.3 off end # GSPI #1 end end diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 7382209264..a2831e1bba 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -58,6 +58,8 @@ chip soc/intel/cannonlake register "PmTimerDisabled" = "1" + register "PchPmSlpS0Vm075VSupport" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 240bb5d23b..598600bda3 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -59,7 +59,7 @@ static const struct pad_config gpio_table[] = { /* A22 : FPMCU_PCH_BOOT0 */ PAD_CFG_GPO(GPP_A22, 0, DEEP), /* A23 : FPMCU_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_A23, NONE, PLTRST, LEVEL, INVERT), /* B0 : CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), @@ -443,3 +443,10 @@ const struct pad_config *__weak override_gpio_table(size_t *num) *num = 0; return NULL; } + +/* Weak implementation of early gpio */ +const struct pad_config *__weak variant_early_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/hatch/variants/dratini/Makefile.inc b/src/mainboard/google/hatch/variants/dratini/Makefile.inc index d82d7979e5..8b7e3d1014 100644 --- a/src/mainboard/google/hatch/variants/dratini/Makefile.inc +++ b/src/mainboard/google/hatch/variants/dratini/Makefile.inc @@ -23,3 +23,4 @@ SPD_SOURCES += 16G_3200 # 0b111 bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index 003b7d129e..30d56d78b8 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -31,6 +31,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_A18, NONE), /* A19 : NC */ PAD_NC(GPP_A19, NONE), + /* C12 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_C12, 0, DEEP), /* C15 : NC */ PAD_NC(GPP_C15, NONE), /* F1 : NC */ diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl index 31f72b3f03..0281913ee1 100644 --- a/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,4 +13,108 @@ * GNU General Public License for more details. */ -#include +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_ACTIVE_AC0 91 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 78 +#define DPTF_CPU_ACTIVE_AC3 71 +#define DPTF_CPU_ACTIVE_AC4 64 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor - Charger" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 85 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor - 5V" +#define DPTF_TSR1_PASSIVE 45 +#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 51 +#define DPTF_TSR1_ACTIVE_AC1 48 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 +#define DPTF_TSR1_ACTIVE_AC5 36 +#define DPTF_TSR1_ACTIVE_AC6 33 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 60, 50, 40, 30, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 100, 80, 70, 60, 50, 40, 30, + 0, 0, 0 + }, +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR0) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on CPU (TSR1) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, + +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 25000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/lenovo/z61t/smi.h b/src/mainboard/google/hatch/variants/dratini/include/variant/sku.h similarity index 65% rename from src/mainboard/lenovo/z61t/smi.h rename to src/mainboard/google/hatch/variants/dratini/include/variant/sku.h index f20314f743..e36d335c1f 100644 --- a/src/mainboard/lenovo/z61t/smi.h +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/sku.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle + * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,12 +13,13 @@ * GNU General Public License for more details. */ -#ifndef MAINBOARD_LENOVO_X60_SMI_H -#define MAINBOARD_LENOVO_X60_SMI_H +#ifndef __MAINBOARD_SKU_H__ +#define __MAINBOARD_SKU_H__ -#define SMI_DOCK_CONNECT 0x01 -#define SMI_DOCK_DISCONNECT 0x02 -#define SMI_BRIGHTNESS_UP 0x03 -#define SMI_BRIGHTNESS_DOWN 0x04 +enum { + SKU_21_DRAGONAIR = 21, /* TS + FPS + Stylus */ + SKU_22_DRAGONAIR = 22, /* TS + KB_BL + FPS + Stylus */ + SKU_23_DRAGONAIR = 23, /* TS + Stylus */ +}; -#endif +#endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 65649d1d45..28b18b8b7f 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -88,8 +88,9 @@ chip soc/intel/cannonlake register "reset_delay_ms" = "100" register "reset_off_delay_ms" = "5" register "has_power_resource" = "1" - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" - register "stop_off_delay_ms" = "5" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" device i2c 10 on end end chip drivers/i2c/hid @@ -97,24 +98,32 @@ chip soc/intel/cannonlake register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "10" - register "generic.reset_off_delay_ms" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_off_delay_ms" = "20" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end - chip drivers/generic/gpio_keys - register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" - register "key.wake" = "GPE0_DW0_08" - register "key.wakeup_event_action" = "EV_ACT_ASSERTED" - register "key.dev_name" = ""EJCT"" - register "key.linux_code" = "SW_PEN_INSERTED" - register "key.linux_input_type" = "EV_SW" - register "key.label" = ""pen_eject"" - device generic 0 on end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2513"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_delay_ms" = "130" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end end end # I2C #1 device pci 15.2 off end # I2C #2 @@ -140,7 +149,8 @@ chip soc/intel/cannonlake register "hid" = "ACPI_DT_NAMESPACE_HID" register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" device spi 1 on end end # FPMCU end # GSPI #1 diff --git a/src/mainboard/google/dragonegg/ramstage.c b/src/mainboard/google/hatch/variants/dratini/variant.c similarity index 61% rename from src/mainboard/google/dragonegg/ramstage.c rename to src/mainboard/google/hatch/variants/dratini/variant.c index 1719a0720b..3a00385d1d 100644 --- a/src/mainboard/google/dragonegg/ramstage.c +++ b/src/mainboard/google/hatch/variants/dratini/variant.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. + * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,14 +14,20 @@ */ #include -#include -#include +#include +#include -void mainboard_silicon_init_params(FSP_S_CONFIG *params) +const char *get_wifi_sar_cbfs_filename(void) { - size_t num; - const struct pad_config *gpio_table; + const char *filename = NULL; + uint32_t sku_id = get_board_sku(); - gpio_table = variant_gpio_table(&num); - gpio_configure_pads(gpio_table, num); + switch (sku_id) { + case SKU_21_DRAGONAIR: + case SKU_22_DRAGONAIR: + case SKU_23_DRAGONAIR: + filename = "wifi_sar-dragonair.hex"; + break; + } + return filename; } diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index df2cc381e9..bc6aa11cab 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -171,7 +171,8 @@ chip soc/intel/cannonlake register "hid" = "ACPI_DT_NAMESPACE_HID" register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" device spi 1 on end end # FPMCU end # GSPI #1 diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl index e3159c8d59..90943529b6 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl @@ -13,46 +13,37 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_PASSIVE 0 #define DPTF_CPU_CRITICAL 105 -#define DPTF_CPU_ACTIVE_AC0 87 -#define DPTF_CPU_ACTIVE_AC1 85 -#define DPTF_CPU_ACTIVE_AC2 83 -#define DPTF_CPU_ACTIVE_AC3 80 -#define DPTF_CPU_ACTIVE_AC4 75 #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "Battery Charger" -#define DPTF_TSR0_PASSIVE 65 -#define DPTF_TSR0_CRITICAL 75 -#define DPTF_TSR0_ACTIVE_AC0 50 -#define DPTF_TSR0_ACTIVE_AC1 47 -#define DPTF_TSR0_ACTIVE_AC2 45 -#define DPTF_TSR0_ACTIVE_AC3 42 -#define DPTF_TSR0_ACTIVE_AC4 40 -#define DPTF_TSR0_ACTIVE_AC5 38 +#define DPTF_TSR0_PASSIVE 50 +#define DPTF_TSR0_CRITICAL 80 #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "5V Regulator" -#define DPTF_TSR1_PASSIVE 45 -#define DPTF_TSR1_CRITICAL 65 -#define DPTF_TSR1_ACTIVE_AC0 50 -#define DPTF_TSR1_ACTIVE_AC1 47 -#define DPTF_TSR1_ACTIVE_AC2 45 -#define DPTF_TSR1_ACTIVE_AC3 42 -#define DPTF_TSR1_ACTIVE_AC4 40 -#define DPTF_TSR1_ACTIVE_AC5 38 +#define DPTF_TSR1_PASSIVE 0 +#define DPTF_TSR1_CRITICAL 70 +#define DPTF_TSR1_ACTIVE_AC0 43 +#define DPTF_TSR1_ACTIVE_AC1 40 +#define DPTF_TSR1_ACTIVE_AC2 38 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "Ambient" -#define DPTF_TSR2_PASSIVE 50 +#define DPTF_TSR2_PASSIVE 0 #define DPTF_TSR2_CRITICAL 65 -#define DPTF_TSR2_ACTIVE_AC0 50 -#define DPTF_TSR2_ACTIVE_AC1 47 -#define DPTF_TSR2_ACTIVE_AC2 45 -#define DPTF_TSR2_ACTIVE_AC3 42 -#define DPTF_TSR2_ACTIVE_AC4 40 -#define DPTF_TSR2_ACTIVE_AC5 38 + +#define DPTF_TSR3_SENSOR_ID 3 +#define DPTF_TSR3_SENSOR_NAME "CPU" +#define DPTF_TSR3_PASSIVE 85 +#define DPTF_TSR3_CRITICAL 100 +#define DPTF_TSR3_ACTIVE_AC0 0 +#define DPTF_TSR3_ACTIVE_AC1 0 +#define DPTF_TSR3_ACTIVE_AC2 0 +#define DPTF_TSR3_ACTIVE_AC3 0 +#define DPTF_TSR3_ACTIVE_AC4 0 +#define DPTF_TSR3_ACTIVE_AC5 0 #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL @@ -62,7 +53,6 @@ Name (CHPS, Package () { Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ }) /* DFPS: Fan Performance States */ @@ -93,35 +83,33 @@ Name (DART, Package () { * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, * AC7, AC8, AC9 */ - \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 100, 80, 60, 55, 40, 0, 0, + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 30, 0, + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 30, 0, + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 100, 80, 60, 0, 0, 0, 0, 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 30, 0, + \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 90, 69, 56, 46, 36, 30, 0, 0, 0, 0 } }) Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 60, 0, 0, 0, 0 }, - /* CPU Throttle Effect on TSR0 */ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, - /* Charger Throttle Effect on TSR1 */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on TSR2 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 }, + /* Charger Throttle Effect on TSR0 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, }) Name (MPPC, Package () @@ -129,8 +117,8 @@ Name (MPPC, Package () 0x2, /* Revision */ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 8000, /* PowerLimitMinimum */ - 13000, /* PowerLimitMaximum */ + 10000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ 28000, /* TimeWindowMinimum */ 28000, /* TimeWindowMaximum */ 200 /* StepSize */ diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 8ca878d43c..262ae8d607 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -1,5 +1,5 @@ chip soc/intel/cannonlake - register "tdp_pl1_override" = "13" + register "tdp_pl1_override" = "15" register "tdp_pl2_override" = "64" register "SerialIoDevMode" = "{ @@ -145,32 +145,36 @@ chip soc/intel/cannonlake register "property_list[0].integer" = "1" device i2c 1a on end end - chip drivers/i2c/generic - register "hid" = ""10EC1011"" - register "desc" = ""RT1011 Tweeter Left Speaker Amp"" + chip drivers/i2c/rt1011 + register "desc" = ""RT1011 Woofer Left Speaker Amp"" register "uid" = "0" - register "name" = ""TL"" + register "name" = ""RTWL"" + register "r0_calib_key" = ""dsm_calib_r0_0"" + register "temperature_calib_key" = ""dsm_calib_temp_0"" device i2c 38 on end end - chip drivers/i2c/generic - register "hid" = ""10EC1011"" - register "desc" = ""RT1011 Tweeter Right Speaker Amp"" + chip drivers/i2c/rt1011 + register "desc" = ""RT1011 Woofer Right Speaker Amp"" register "uid" = "1" - register "name" = ""TR"" + register "name" = ""RTWR"" + register "r0_calib_key" = ""dsm_calib_r0_1"" + register "temperature_calib_key" = ""dsm_calib_temp_0"" device i2c 39 on end end - chip drivers/i2c/generic - register "hid" = ""10EC1011"" - register "desc" = ""RT1011 Woofer Left Speaker Amp"" + chip drivers/i2c/rt1011 + register "desc" = ""RT1011 Tweeter Left Speaker Amp"" register "uid" = "2" - register "name" = ""WL"" + register "name" = ""RTTL"" + register "r0_calib_key" = ""dsm_calib_r0_2"" + register "temperature_calib_key" = ""dsm_calib_temp_0"" device i2c 3a on end end - chip drivers/i2c/generic - register "hid" = ""10EC1011"" - register "desc" = ""RT1011 Woofer Right Speaker Amp"" + chip drivers/i2c/rt1011 + register "desc" = ""RT1011 Tweeter Right Speaker Amp"" register "uid" = "3" - register "name" = ""WR"" + register "name" = ""RTTR"" + register "r0_calib_key" = ""dsm_calib_r0_3"" + register "temperature_calib_key" = ""dsm_calib_temp_0"" device i2c 3b on end end end #I2C #4 @@ -180,7 +184,8 @@ chip soc/intel/cannonlake register "hid" = "ACPI_DT_NAMESPACE_HID" register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" device spi 1 on end end # FPMCU end # GSPI #1 diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index 272cbfb6ea..9d33fa96d0 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -61,7 +61,7 @@ chip soc/intel/cannonlake # Refer to EDS-Vol2-14.3.8. # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x0F10" + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" # EMMC TX DATA Delay 2 # Refer to EDS-Vol2-14.3.9. @@ -69,7 +69,7 @@ chip soc/intel/cannonlake # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2F2D2D" + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" # EMMC RX CMD/DATA Delay 1 # Refer to EDS-Vol2-14.3.10. @@ -77,7 +77,7 @@ chip soc/intel/cannonlake # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C121936" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" # EMMC RX CMD/DATA Delay 2 # Refer to EDS-Vol2-14.3.12. @@ -88,13 +88,13 @@ chip soc/intel/cannonlake # 11: Reserved # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1182D" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" # EMMC Rx Strobe Delay # Refer to EDS-Vol2-14.3.11. # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1414" + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" device domain 0 on device pci 15.0 on diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 9654388087..7bf9a0cd5f 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -23,7 +23,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_A0, NONE), /* A6 : SERIRQ ==> NC */ PAD_NC(GPP_A6, NONE), - /* A10 : PEN_RESET_ODL */ + /* A10 : PEN_RESET_ODL for old revision devices */ PAD_CFG_GPO(GPP_A10, 1, DEEP), /* A16 : EMR_GARAGE_DET (notification) */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A16, NONE, PLTRST), @@ -31,8 +31,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_A17, NONE), /* A18 : ISH_GP0 ==> NC */ PAD_NC(GPP_A18, NONE), - /* A19 : ISH_GP1 ==> NC */ - PAD_NC(GPP_A19, NONE), + /* A19 : PEN_RESET_ODL */ + PAD_CFG_GPO(GPP_A19, 0, DEEP), /* A20 : ISH_GP2 ==> NC */ PAD_NC(GPP_A20, NONE), /* A22 : ISH_GP4 ==> NC */ diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 8c7bb1ff9a..55ac071be5 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -179,8 +179,24 @@ chip soc/intel/cannonlake register "enable_delay_ms" = "1" # 90 ns register "has_power_resource" = "1" register "disable_gpio_export_in_crs" = "1" + register "probed" = "1" device i2c 4b on end end + + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "100" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "20" + register "reset_off_delay_ms" = "2" + register "has_power_resource" = "1" + device i2c 10 on end + end end # I2C #1 device pci 15.2 on @@ -189,10 +205,8 @@ chip soc/intel/cannonlake register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C15)" - # TODO: We can't use GPP_A10 as reset_gpio due to its voltage level, - # so we need to reassign it or remove it. - #register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A10)" - #register "generic.reset_delay_ms" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A19)" + register "generic.reset_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x09 on end @@ -240,7 +254,8 @@ chip soc/intel/cannonlake register "hid" = "ACPI_DT_NAMESPACE_HID" register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" device spi 1 on end end # FPMCU end # GSPI #1 diff --git a/src/mainboard/google/jecht/acpi/platform.asl b/src/mainboard/google/jecht/acpi/platform.asl index 06de271998..fee0670b1d 100644 --- a/src/mainboard/google/jecht/acpi/platform.asl +++ b/src/mainboard/google/jecht/acpi/platform.asl @@ -14,44 +14,6 @@ * GNU General Public License for more details. */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index e216b132a9..fb8abe7e90 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -25,6 +25,7 @@ DefinitionBlock( ) { // Some generic macros + #include #include "acpi/platform.asl" // Thermal handler @@ -51,7 +52,7 @@ DefinitionBlock( #include // Chipset specific sleep states - #include + #include // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 4fc2ba0c93..4e32ab227b 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd index b746545488..d7d0a886d3 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd +++ b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd @@ -33,8 +33,8 @@ FLASH@0xFF000000 0x1000000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0x70000 - COREBOOT(CBFS)@0x71000 0x210000 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x27d000 } } } diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 542ee108a7..e6d604e5e7 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH - select FATAL_ASSERTS select SPI_FLASH_INCLUDE_ALL_DRIVERS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID diff --git a/src/mainboard/google/kukui/chromeos.fmd b/src/mainboard/google/kukui/chromeos.fmd index d183273549..2635854866 100644 --- a/src/mainboard/google/kukui/chromeos.fmd +++ b/src/mainboard/google/kukui/chromeos.fmd @@ -1,30 +1,45 @@ -FLASH@0x0 0x800000 { - WP_RO@0x0 0x200000 { - RO_SECTION@0x0 0x1f8000 { - BOOTBLOCK@0 32K - FMAP@0x8000 0x1000 - COREBOOT(CBFS)@0x9000 0x1ec000 +# Firmware Layout Description for Chrome OS. +# +# The size and address of every section must be aligned to at least 4K, except: +# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. +# +# 'FMAP' may be found by binary search so its starting address should be better +# aligned to larger values. +# +# For sections to be preserved on update, add (PRESERVE) to individual sections +# instead of a group section; otherwise the preserved data may be wrong if you +# resize or reorder sections inside a group. + +FLASH@0x0 8M { + WP_RO@0x0 4M { + RO_SECTION { + BOOTBLOCK 128K + FMAP 4K + COREBOOT(CBFS) GBB 0x2f00 RO_FRID 0x100 } - RO_VPD(PRESERVE)@0x1f8000 0x8000 + RO_VPD(PRESERVE) 32K # At least 16K. } - RW_SECTION_A@0x200000 0x7c000 { - VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS) 0x79f00 + RW_SECTION_A 1500K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) RW_FWID_A 0x100 } - RW_SHARED@0x27c000 0x1000 { - SHARED_DATA@0x0 0x1000 + RW_MISC 36K { + RW_VPD(PRESERVE) 16K # At least 8K. + RW_NVRAM(PRESERVE) 8K + RW_DDR_TRAINING(PRESERVE) 8K + RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. } - RW_NVRAM(PRESERVE)@0x27d000 0x2000 - # ELOG driver has hard-coded the size to 4k. - RW_ELOG(PRESERVE)@0x27f000 0x1000 - RW_SECTION_B@0x280000 0x7c000 { - VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS) 0x79f00 + RW_SECTION_B 1500K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) RW_FWID_B 0x100 } - RW_VPD(PRESERVE)@0x2fc000 0x4000 - RW_LEGACY(CBFS)@0x300000 0x100000 + RW_SHARED 36K { # Will be force updated on recovery. + SHARED_DATA 4K # 4K or less for netboot params. + RW_UNUSED + } + RW_LEGACY(CBFS) 1M # Minimal 1M. } diff --git a/src/mainboard/google/kukui/panel_ps8640.c b/src/mainboard/google/kukui/panel_ps8640.c index 83358d366a..6381228c09 100644 --- a/src/mainboard/google/kukui/panel_ps8640.c +++ b/src/mainboard/google/kukui/panel_ps8640.c @@ -19,7 +19,6 @@ #include #include #include -#include #include "panel.h" diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index a86690b6fb..2b7dd6a20c 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -14,6 +14,9 @@ */ #include +#include +#include +#include #include #include #include @@ -22,6 +25,42 @@ #include "early_init.h" +/* This must be defined in chromeos.fmd in same name and size. */ +#define CALIBRATION_REGION "RW_DDR_TRAINING" +#define CALIBRATION_REGION_SIZE 0x2000 + +_Static_assert(sizeof(struct dramc_param) <= CALIBRATION_REGION_SIZE, + "sizeof(struct dramc_param) exceeds " CALIBRATION_REGION); + +static bool read_calibration_data_from_flash(struct dramc_param *dparam) +{ + const size_t length = sizeof(*dparam); + size_t ret = fmap_read_area(CALIBRATION_REGION, dparam, length); + printk(BIOS_DEBUG, "%s: ret=%#lx, length=%#lx\n", + __func__, ret, length); + + return ret == length; +} + +static bool write_calibration_data_to_flash(const struct dramc_param *dparam) +{ + const size_t length = sizeof(*dparam); + size_t ret = fmap_overwrite_area(CALIBRATION_REGION, dparam, length); + printk(BIOS_DEBUG, "%s: ret=%#lx, length=%#lx\n", + __func__, ret, length); + + return ret == length; +} + +/* dramc_param is ~2K and too large to fit in stack. */ +static struct dramc_param dramc_parameter; + +static struct dramc_param_ops dparam_ops = { + .param = &dramc_parameter, + .read_from_flash = &read_calibration_data_from_flash, + .write_to_flash = &write_calibration_data_to_flash, +}; + void platform_romstage_main(void) { /* This will be done in verstage if CONFIG_VBOOT is enabled. */ @@ -34,6 +73,6 @@ void platform_romstage_main(void) mt_pll_raise_ca53_freq(1989 * MHz); pmic_init_scp_voltage(); rtc_boot(); - mt_mem_init(get_sdram_config()); + mt_mem_init(&dparam_ops); mtk_mmu_after_dram(); } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c index fab124038f..5471f0154f 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c @@ -16,6 +16,8 @@ #include struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .frequency = 1600, .wr_level = { [CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} }, [CHANNEL_B] = { {0x24, 0x20}, {0x25, 0x20} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c index d3c1496a6c..5743304bc9 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c @@ -16,6 +16,8 @@ #include struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .frequency = 1600, .wr_level = { [CHANNEL_A] = { {0x22, 0x1C}, {0x23, 0x1D} }, [CHANNEL_B] = { {0x26, 0x23}, {0x26, 0x23} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c index c21cd12315..de06818460 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c @@ -16,6 +16,8 @@ #include struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .frequency = 1600, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, [CHANNEL_B] = { {0x1E, 0x1F}, {0x1D, 0x1E} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c index 434984541c..fb83e6f418 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c @@ -16,6 +16,8 @@ #include struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .frequency = 1600, .wr_level = { [CHANNEL_A] = { {0x22, 0x21}, {0x20, 0x21} }, [CHANNEL_B] = { {0x23, 0x27}, {0x23, 0x27} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c index cab57ce853..415dbda827 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c @@ -16,6 +16,8 @@ #include struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .frequency = 1600, .wr_level = { [CHANNEL_A] = { {0x21, 0x24}, {0x22, 0x24} }, [CHANNEL_B] = { {0x24, 0x28}, {0x22, 0x27} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c index 2810ef50f7..bf3fe892c3 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c @@ -16,6 +16,8 @@ #include struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .frequency = 1600, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, [CHANNEL_B] = { {0x21, 0x28}, {0x21, 0x29} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c index 329cc76afe..e5b3dcc990 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c @@ -16,6 +16,8 @@ #include struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .frequency = 1600, .wr_level = { [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c index ccb591e06a..cb923f5551 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c @@ -16,6 +16,8 @@ #include struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .frequency = 1600, .wr_level = { [CHANNEL_A] = { {0x1F, 0x1C}, {0x1C, 0x1B} }, [CHANNEL_B] = { {0x27, 0x28}, {0x23, 0x28} } diff --git a/src/mainboard/google/link/acpi/mainboard.asl b/src/mainboard/google/link/acpi/mainboard.asl index 6a2d890802..79c45c8622 100644 --- a/src/mainboard/google/link/acpi/mainboard.asl +++ b/src/mainboard/google/link/acpi/mainboard.asl @@ -19,7 +19,6 @@ Scope (\_SB) { Device (TPAD) { - Name (_ADR, 0x0) Name (_UID, 1) // Report as a Sleep Button device so Linux will @@ -44,7 +43,6 @@ Scope (\_SB) { Device (TSCR) { - Name (_ADR, 0x0) Name (_UID, 2) // Report as a Sleep Button device so Linux will diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index a5370beddb..44a2bf5c1c 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl index ce4ba9195b..4c23e7dd0c 100644 --- a/src/mainboard/google/link/dsdt.asl +++ b/src/mainboard/google/link/dsdt.asl @@ -24,7 +24,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/platform.asl" @@ -55,5 +55,5 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 37d1a672cd..a91930bd7f 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -25,7 +25,6 @@ #include #include #include -#include #include "onboard.h" #include "ec.h" #include diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 8e8d94335c..d42572b632 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -34,9 +34,6 @@ void pch_enable_lpc(void) { - /* Set COM1/COM2 decode range */ - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \ GAMEL_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c index d2264591fd..893d2eace5 100644 --- a/src/mainboard/google/nyan/pmic.c +++ b/src/mainboard/google/nyan/pmic.c @@ -55,7 +55,7 @@ static struct as3722_init_reg init_list[] = { {AS3722_LDO11, 0x00, 1}, }; -static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay) +static void pmic_write_reg(unsigned int bus, uint8_t reg, uint8_t val, int do_delay) { if (i2c_writeb(bus, AS3722_I2C_ADDR, reg, val)) { printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", @@ -68,7 +68,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay) } } -static void pmic_slam_defaults(unsigned bus) +static void pmic_slam_defaults(unsigned int bus) { int i; for (i = 0; i < ARRAY_SIZE(init_list); i++) { @@ -77,7 +77,7 @@ static void pmic_slam_defaults(unsigned bus) } } -void pmic_init(unsigned bus) +void pmic_init(unsigned int bus) { /* * Don't need to set up VDD_CORE - already done - by OTP diff --git a/src/mainboard/google/nyan/pmic.h b/src/mainboard/google/nyan/pmic.h index 9843b72156..639725e431 100644 --- a/src/mainboard/google/nyan/pmic.h +++ b/src/mainboard/google/nyan/pmic.h @@ -39,6 +39,6 @@ enum { AS3722_LDO11, }; -void pmic_init(unsigned bus); +void pmic_init(unsigned int bus); #endif /* __MAINBOARD_GOOGLE_NYAN_PMIC_H__ */ diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c index 948d867750..f70e6dd49f 100644 --- a/src/mainboard/google/nyan_big/pmic.c +++ b/src/mainboard/google/nyan_big/pmic.c @@ -55,7 +55,7 @@ static struct as3722_init_reg init_list[] = { {AS3722_LDO11, 0x00, 1}, }; -static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay) +static void pmic_write_reg(unsigned int bus, uint8_t reg, uint8_t val, int do_delay) { if (i2c_writeb(bus, AS3722_I2C_ADDR, reg, val)) { printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", @@ -68,7 +68,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay) } } -static void pmic_slam_defaults(unsigned bus) +static void pmic_slam_defaults(unsigned int bus) { int i; @@ -78,7 +78,7 @@ static void pmic_slam_defaults(unsigned bus) } } -void pmic_init(unsigned bus) +void pmic_init(unsigned int bus) { /* * Don't need to set up VDD_CORE - already done - by OTP diff --git a/src/mainboard/google/nyan_big/pmic.h b/src/mainboard/google/nyan_big/pmic.h index 65ee264145..e4fbb8d56c 100644 --- a/src/mainboard/google/nyan_big/pmic.h +++ b/src/mainboard/google/nyan_big/pmic.h @@ -39,6 +39,6 @@ enum { AS3722_LDO11, }; -void pmic_init(unsigned bus); +void pmic_init(unsigned int bus); #endif /* __MAINBOARD_GOOGLE_NYAN_BIG_PMIC_H__ */ diff --git a/src/mainboard/google/nyan_blaze/pmic.c b/src/mainboard/google/nyan_blaze/pmic.c index 948d867750..f70e6dd49f 100644 --- a/src/mainboard/google/nyan_blaze/pmic.c +++ b/src/mainboard/google/nyan_blaze/pmic.c @@ -55,7 +55,7 @@ static struct as3722_init_reg init_list[] = { {AS3722_LDO11, 0x00, 1}, }; -static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay) +static void pmic_write_reg(unsigned int bus, uint8_t reg, uint8_t val, int do_delay) { if (i2c_writeb(bus, AS3722_I2C_ADDR, reg, val)) { printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", @@ -68,7 +68,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay) } } -static void pmic_slam_defaults(unsigned bus) +static void pmic_slam_defaults(unsigned int bus) { int i; @@ -78,7 +78,7 @@ static void pmic_slam_defaults(unsigned bus) } } -void pmic_init(unsigned bus) +void pmic_init(unsigned int bus) { /* * Don't need to set up VDD_CORE - already done - by OTP diff --git a/src/mainboard/google/nyan_blaze/pmic.h b/src/mainboard/google/nyan_blaze/pmic.h index a1213d9b2d..02b3e81a9c 100644 --- a/src/mainboard/google/nyan_blaze/pmic.h +++ b/src/mainboard/google/nyan_blaze/pmic.h @@ -39,6 +39,6 @@ enum { AS3722_LDO11, }; -void pmic_init(unsigned bus); +void pmic_init(unsigned int bus); #endif /* __MAINBOARD_GOOGLE_NYAN_BLAZE_PMIC_H__ */ diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 916632e27b..421826cdeb 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index c13d7f8ade..7b07c2ca24 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -60,6 +60,7 @@ config VARIANT_DIR default "bloog" if BOARD_GOOGLE_BLOOG default "octopus" if BOARD_GOOGLE_OCTOPUS default "garg" if BOARD_GOOGLE_GARG + default "dood" if BOARD_GOOGLE_DOOD config DEVICETREE string @@ -81,6 +82,7 @@ config MAINBOARD_PART_NUMBER default "Bloog" if BOARD_GOOGLE_BLOOG default "Octopus" if BOARD_GOOGLE_OCTOPUS default "Garg" if BOARD_GOOGLE_GARG + default "Dood" if BOARD_GOOGLE_DOOD config MAINBOARD_FAMILY string diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index b192134fb4..8a8d33981c 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -58,3 +58,9 @@ config BOARD_GOOGLE_GARG select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_DOOD + bool "-> Dood" + select BASEBOARD_OCTOPUS_LAPTOP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/octopus/chromeos.fmd b/src/mainboard/google/octopus/chromeos.fmd index fbdafaa3a2..332465ae19 100644 --- a/src/mainboard/google/octopus/chromeos.fmd +++ b/src/mainboard/google/octopus/chromeos.fmd @@ -7,8 +7,8 @@ FLASH 16M { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - COREBOOT(CBFS)@0x1000 0x1bb000 - GBB@0x1bc000 0x40000 + COREBOOT(CBFS)@0x1000 0x1f8000 + GBB@0x1f9000 0x3000 } } MISC_RW@0x400000 0x30000 { diff --git a/src/mainboard/google/octopus/dsdt.asl b/src/mainboard/google/octopus/dsdt.asl index b43494821a..2b6c33f667 100644 --- a/src/mainboard/google/octopus/dsdt.asl +++ b/src/mainboard/google/octopus/dsdt.asl @@ -45,7 +45,7 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/octopus/variants/bloog/variant.c b/src/mainboard/google/octopus/variants/bloog/variant.c index 6484080d41..18f44b955a 100644 --- a/src/mainboard/google/octopus/variants/bloog/variant.c +++ b/src/mainboard/google/octopus/variants/bloog/variant.c @@ -17,9 +17,25 @@ #include #include #include +#include #define SKU_UNKNOWN 0xFFFFFFFF +enum { + SKU_33_BLOOG = 33, /* no kb blit, USI Stylus */ + SKU_34_BLOOG = 34, /* kb blit, no USI Stylus */ + SKU_35_BLOOG = 35, /* kb blit, USI Stylus */ + SKU_36_BLOOG = 36, /* no kb blit, no USI Stylus */ + SKU_49_BLOOGUARD = 49, /* kb blit, no USI Stylus */ + SKU_50_BLOOGUARD = 50, /* kb blit, USI Stylus */ + SKU_51_BLOOGUARD = 51, /* no kb blit, no USI Stylus */ + SKU_52_BLOOGUARD = 52, /* no kb blit, USI Stylus */ + SKU_65_BLOOGLET = 65, /* TS, kb blit */ + SKU_66_BLOOGLET = 66, /* TS, no kb blit */ + SKU_67_BLOOGLET = 67, /* non-TS, kb blit */ + SKU_68_BLOOGLET = 68, /* non-TS, no kb blit */ +}; + const char *get_wifi_sar_cbfs_filename(void) { const char *filename = NULL; @@ -29,11 +45,28 @@ const char *get_wifi_sar_cbfs_filename(void) if (sku_id == SKU_UNKNOWN) return NULL; - if (sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36) + if (sku_id == SKU_33_BLOOG || sku_id == SKU_34_BLOOG || + sku_id == SKU_35_BLOOG || sku_id == SKU_36_BLOOG) filename = "wifi_sar-bloog.hex"; - if (sku_id == 49 || sku_id == 50 || sku_id == 51 || sku_id == 52) + if (sku_id == SKU_49_BLOOGUARD || sku_id == SKU_50_BLOOGUARD || + sku_id == SKU_51_BLOOGUARD || sku_id == SKU_52_BLOOGUARD) filename = "wifi_sar-blooguard.hex"; return filename; } + +const char *mainboard_vbt_filename(void) +{ + uint32_t sku_id; + + sku_id = get_board_sku(); + + if (sku_id == SKU_49_BLOOGUARD || sku_id == SKU_50_BLOOGUARD || + sku_id == SKU_51_BLOOGUARD || sku_id == SKU_52_BLOOGUARD || + sku_id == SKU_65_BLOOGLET || sku_id == SKU_66_BLOOGLET || + sku_id == SKU_67_BLOOGLET || sku_id == SKU_68_BLOOGLET) + return "vbt_blooguard.bin"; + + return "vbt.bin"; +} diff --git a/src/mainboard/google/octopus/variants/dood/Makefile.inc b/src/mainboard/google/octopus/variants/dood/Makefile.inc new file mode 100644 index 0000000000..9fb63f5f43 --- /dev/null +++ b/src/mainboard/google/octopus/variants/dood/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/dood/gpio.c b/src/mainboard/google/octopus/variants/dood/gpio.c new file mode 100644 index 0000000000..05a05f6565 --- /dev/null +++ b/src/mainboard/google/octopus/variants/dood/gpio.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 The coreboot project Authors. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +static const struct pad_config default_override_table[] = { + PAD_NC(GPIO_104, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_213, DN_20K), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(default_override_table); + + return default_override_table; +} diff --git a/src/mainboard/google/octopus/variants/dood/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/dood/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..1406d3488f --- /dev/null +++ b/src/mainboard/google/octopus/variants/dood/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 The coreboot project Authors. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/drivers/intel/fsp1_1/include/fsp/bootblock.h b/src/mainboard/google/octopus/variants/dood/include/variant/ec.h similarity index 80% rename from src/drivers/intel/fsp1_1/include/fsp/bootblock.h rename to src/mainboard/google/octopus/variants/dood/include/variant/ec.h index a962bdf0be..a8640cd186 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/bootblock.h +++ b/src/mainboard/google/octopus/variants/dood/include/variant/ec.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Intel Corp. + * Copyright 2019 The coreboot project Authors. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ -#ifndef FSP1_1_BOOTBLOCK_H -#define FSP1_1_BOOTBLOCK_H +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H -void bootblock_fsp_temp_ram_init(void); +#include #endif diff --git a/src/mainboard/google/octopus/variants/dood/include/variant/gpio.h b/src/mainboard/google/octopus/variants/dood/include/variant/gpio.h new file mode 100644 index 0000000000..d7e9ddb6fb --- /dev/null +++ b/src/mainboard/google/octopus/variants/dood/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 The coreboot project Authors. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb new file mode 100644 index 0000000000..6df9f5395e --- /dev/null +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -0,0 +1,152 @@ +chip soc/intel/apollolake + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0a0b" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c272828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181b1a" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10021" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0a0a" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | + #+-------------------+---------------------------+ + + register "tcc_offset" = "10" + + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 44, + .fall_time_ns = 90, + }, + }" + + device domain 0 on + device pci 16.0 off end # - I2C 0 + device pci 17.1 on + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end # - I2C 5 + device pci 17.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "wake" = "GPE0_DW3_27" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # - I2C 6 + device pci 17.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "50" + register "has_power_resource" = "1" + device i2c 39 on end + end + end # - I2C 7 + end + + # Disable compliance mode + register "DisableComplianceMode" = "1" +end diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index a1e02d2159..5924fa03a0 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -26,10 +26,6 @@ static const struct pad_config default_override_table[] = { PAD_NC(GPIO_67, UP_20K), PAD_NC(GPIO_117, UP_20K), - PAD_NC(GPIO_138, UP_20K), - PAD_NC(GPIO_139, UP_20K), - /* GPIO_140 -- PEN_RESET */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), PAD_NC(GPIO_143, UP_20K), PAD_NC(GPIO_144, UP_20K), PAD_NC(GPIO_145, UP_20K), diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index da4e701641..1d1a67ad33 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -63,6 +63,8 @@ chip soc/intel/apollolake }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 25, + .fall_time_ns = 52, }, .i2c[5] = { .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/sku.h b/src/mainboard/google/octopus/variants/meep/include/variant/sku.h index c12ba80302..c3a18c4452 100644 --- a/src/mainboard/google/octopus/variants/meep/include/variant/sku.h +++ b/src/mainboard/google/octopus/variants/meep/include/variant/sku.h @@ -29,6 +29,8 @@ enum { SKU_50_VORTININJA = 50, /* Stylus + no rear camera */ SKU_51_VORTININJA = 51, /* no Stylus + rear camera */ SKU_52_VORTININJA = 52, /* no Stylus + no rear camera */ + SKU_65_VORTICON = 65, /* no touchscreen */ + SKU_66_VORTICON = 66, /* with touchscreen */ }; diff --git a/src/mainboard/google/octopus/variants/meep/variant.c b/src/mainboard/google/octopus/variants/meep/variant.c index ed76a29298..20aaa0a1f4 100644 --- a/src/mainboard/google/octopus/variants/meep/variant.c +++ b/src/mainboard/google/octopus/variants/meep/variant.c @@ -53,6 +53,13 @@ const char *mainboard_vbt_filename(void) case SKU_35_DORP: case SKU_36_DORP: return "vbt_dorp_hdmi.bin"; + case SKU_49_VORTININJA: + case SKU_50_VORTININJA: + case SKU_51_VORTININJA: + case SKU_52_VORTININJA: + case SKU_65_VORTICON: + case SKU_66_VORTICON: + return "vbt_vortininja.bin"; default: return "vbt.bin"; } diff --git a/src/mainboard/google/parrot/acpi/mainboard.asl b/src/mainboard/google/parrot/acpi/mainboard.asl index 4906efcdb5..8fe68c5805 100644 --- a/src/mainboard/google/parrot/acpi/mainboard.asl +++ b/src/mainboard/google/parrot/acpi/mainboard.asl @@ -43,7 +43,6 @@ Scope (\_SB) { Device (TPAD) { - Name (_ADR, 0x0) Name (_UID, 1) // Report as a Sleep Button device so Linux will diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 4adcdb6b08..4587a127fd 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl index e866e21169..0465ceda26 100644 --- a/src/mainboard/google/parrot/dsdt.asl +++ b/src/mainboard/google/parrot/dsdt.asl @@ -24,7 +24,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/platform.asl" @@ -55,5 +55,5 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 5f6b09d7be..361215a1bd 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -20,7 +20,6 @@ #include #include #include -#include #include "onboard.h" #include "ec.h" #include diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index ac06fbc83e..210c7fc04c 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -28,9 +28,6 @@ void pch_enable_lpc(void) { - /* Parrot EC Decode Range Port60/64, Port62/66 */ - /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN); } void mainboard_rcba_config(void) diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 5883cdcae9..92d361dd4c 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -42,7 +42,7 @@ static u8 mainboard_smi_ec(void) #if CONFIG(ELOG_GSMI) if (!battery_critical_logged) elog_add_event_byte(ELOG_TYPE_EC_EVENT, - EC_EVENT_BATTERY_CRITICAL); + EC_HOST_EVENT_BATTERY_CRITICAL); battery_critical_logged = 1; #endif break; @@ -50,7 +50,8 @@ static u8 mainboard_smi_ec(void) printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); #if CONFIG(ELOG_GSMI) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED); + elog_add_event_byte(ELOG_TYPE_EC_EVENT, + EC_HOST_EVENT_LID_CLOSED); #endif /* Go to S5 */ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); @@ -71,7 +72,8 @@ void mainboard_smi_gpi(u32 gpi_sts) printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); #if CONFIG(ELOG_GSMI) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED); + elog_add_event_byte(ELOG_TYPE_EC_EVENT, + EC_HOST_EVENT_LID_CLOSED); #endif /* Go to S5 */ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index 8bd35bee95..f2b1e8ce8b 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -19,7 +19,6 @@ #include #include #include -#include #include void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index ecd2260511..234a433acb 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -465,9 +465,9 @@ static void mainboard_enable(struct device *dev) mmu_config_range((uintptr_t)_dma_coherent/MiB, REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF); - const unsigned epll_hz = 192000000; - const unsigned sample_rate = 48000; - const unsigned lr_frame_size = 256; + const unsigned int epll_hz = 192000000; + const unsigned int sample_rate = 48000; + const unsigned int lr_frame_size = 256; clock_epll_set_rate(epll_hz); clock_select_i2s_clk_source(); clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size); diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 07e3990b47..85dc9a5701 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -10,7 +10,7 @@ config BOARD_GOOGLE_BASEBOARD_POPPY select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_NAMI + select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_NAMI || BOARD_GOOGLE_NAUTILUS select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_KABYLAKE diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index 34862df3cb..7e0eb9ae08 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -55,7 +55,7 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c index b3e91e888e..5aa45d40a8 100644 --- a/src/mainboard/google/poppy/mainboard.c +++ b/src/mainboard/google/poppy/mainboard.c @@ -21,6 +21,8 @@ #include #include +#include + static void mainboard_init(struct device *dev) { mainboard_ec_init(); @@ -62,6 +64,18 @@ static void mainboard_enable(struct device *dev) dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } +static void mainboard_chip_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); + pads = variant_sku_gpio_table(&num); + gpio_configure_pads(pads, num); +} + struct chip_operations mainboard_ops = { + .init = mainboard_chip_init, .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/poppy/ramstage.c b/src/mainboard/google/poppy/ramstage.c index e39afecb9c..29a83df69b 100644 --- a/src/mainboard/google/poppy/ramstage.c +++ b/src/mainboard/google/poppy/ramstage.c @@ -16,17 +16,9 @@ #include #include -#include - void mainboard_silicon_init_params(FSP_SIL_UPD *params) { - const struct pad_config *pads; - size_t num; variant_devtree_update(); - pads = variant_gpio_table(&num); - gpio_configure_pads(pads, num); - pads = variant_sku_gpio_table(&num); - gpio_configure_pads(pads, num); } void __weak variant_devtree_update(void) diff --git a/src/mainboard/google/poppy/spd/Makefile.inc b/src/mainboard/google/poppy/spd/Makefile.inc index 444ac00b92..dd57835739 100644 --- a/src/mainboard/google/poppy/spd/Makefile.inc +++ b/src/mainboard/google/poppy/spd/Makefile.inc @@ -5,7 +5,7 @@ SEC_SPD_BIN = $(obj)/sec-spd.bin define gen_spd_bin for f in $2; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $1 endef diff --git a/src/mainboard/google/glados/variants/lars/data.vbt b/src/mainboard/google/poppy/variants/nautilus/data.vbt similarity index 75% rename from src/mainboard/google/glados/variants/lars/data.vbt rename to src/mainboard/google/poppy/variants/nautilus/data.vbt index 0aac82c3b1..95248052b1 100644 Binary files a/src/mainboard/google/glados/variants/lars/data.vbt and b/src/mainboard/google/poppy/variants/nautilus/data.vbt differ diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index a4ea3c329b..c62317a04b 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -196,7 +196,7 @@ static const struct pad_config gpio_table[] = { /* D16 : ISH_UART0_CTS# ==> RCAM_RST_L */ PAD_CFG_GPO(GPP_D16, 0, DEEP), /* D17 : DMIC_CLK1 ==> EC_PCH_ARCORE_INT_L */ - PAD_CFG_GPI_APIC_INVERT(GPP_D17, NONE, PLTRST), + PAD_CFG_GPI_APIC(GPP_D17, NONE, PLTRST), /* D18 : DMIC_DATA1 ==> TP131 */ PAD_CFG_NC(GPP_D18), /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */ diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 8ca9dfb592..2393830d13 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -48,7 +48,7 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include #include "acpi/mainboard.asl" } diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 30be5f79ca..64dc99f005 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -23,7 +23,6 @@ #endif #include #include -#include #include #include "ec.h" #include diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index 2b2f522661..29b816586c 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -45,7 +45,7 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd index ece0eda099..65a915a2c0 100644 --- a/src/mainboard/google/sarien/chromeos.fmd +++ b/src/mainboard/google/sarien/chromeos.fmd @@ -41,8 +41,8 @@ FLASH@0xfe000000 0x2000000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x300000 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3ec000 } } } diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 58e0704deb..9a5c787a25 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -29,7 +29,7 @@ DefinitionBlock( #include /* global NVS and variables */ - #include + #include /* CPU */ #include @@ -54,7 +54,7 @@ DefinitionBlock( #endif /* Chipset specific sleep states */ - #include + #include /* Low power idle table */ #include diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index 811afa1b16..d57c6fe08c 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include @@ -68,7 +67,7 @@ static const struct pad_config gpio_unused[] = { /* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), }; -void mainboard_silicon_init_params(FSP_S_CONFIG *params) +static void mainboard_init(void *chip_info) { const struct pad_config *gpio_table; size_t num_gpios; @@ -87,5 +86,6 @@ static void mainboard_enable(struct device *dev) } struct chip_operations mainboard_ops = { + .init = mainboard_init, .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 0f3023cace..4af8ca25ca 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -335,6 +335,14 @@ chip soc/intel/cannonlake register "probed" = "1" device i2c 2c on end end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Cirque Touchpad"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2a on end + end end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 diff --git a/src/mainboard/google/slippy/acpi/platform.asl b/src/mainboard/google/slippy/acpi/platform.asl index 10b0efb9ef..5b0d27657e 100644 --- a/src/mainboard/google/slippy/acpi/platform.asl +++ b/src/mainboard/google/slippy/acpi/platform.asl @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include +#include /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl index 8424c258ae..6c45ea95aa 100644 --- a/src/mainboard/google/slippy/dsdt.asl +++ b/src/mainboard/google/slippy/dsdt.asl @@ -64,5 +64,5 @@ DefinitionBlock( #include // Chipset specific sleep states - #include + #include } diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index cf025d1740..4c50ea65a6 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include "ec.h" diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index 9add211ccd..68e0f6ccd3 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -36,7 +36,7 @@ struct max77620_init_reg { u8 delay; }; -static void pmic_write_reg(unsigned bus, uint8_t chip, uint8_t reg, uint8_t val, +static void pmic_write_reg(unsigned int bus, uint8_t chip, uint8_t reg, uint8_t val, int delay) { if (i2c_writeb(bus, chip, reg, val)) { @@ -50,19 +50,19 @@ static void pmic_write_reg(unsigned bus, uint8_t chip, uint8_t reg, uint8_t val, } } -void pmic_write_reg_77620(unsigned bus, uint8_t reg, uint8_t val, +void pmic_write_reg_77620(unsigned int bus, uint8_t reg, uint8_t val, int delay) { pmic_write_reg(bus, MAX77620_I2C_ADDR, reg, val, delay); } -static inline void pmic_write_reg_77621(unsigned bus, uint8_t reg, uint8_t val, +static inline void pmic_write_reg_77621(unsigned int bus, uint8_t reg, uint8_t val, int delay) { pmic_write_reg(bus, MAX77621_CPU_I2C_ADDR, reg, val, delay); } -void pmic_init(unsigned bus) +void pmic_init(unsigned int bus) { /* MAX77620: Set SD0 to 1.0V - VDD_CORE */ pmic_write_reg_77620(bus, MAX77620_SD0_REG, 0x20, 1); diff --git a/src/mainboard/google/smaug/pmic.h b/src/mainboard/google/smaug/pmic.h index e01a556948..130f134d95 100644 --- a/src/mainboard/google/smaug/pmic.h +++ b/src/mainboard/google/smaug/pmic.h @@ -73,8 +73,8 @@ #define MAX77621_CONTROL1_REG 0x02 #define MAX77621_CONTROL2_REG 0x03 -void pmic_init(unsigned bus); -void pmic_write_reg_77620(unsigned bus, uint8_t reg, uint8_t val, +void pmic_init(unsigned int bus); +void pmic_write_reg_77620(unsigned int bus, uint8_t reg, uint8_t val, int delay); #endif /* __MAINBOARD_GOOGLE_FOSTER_PMIC_H__ */ diff --git a/src/mainboard/google/storm/cdp.c b/src/mainboard/google/storm/cdp.c index 3c27491c50..f143bf9171 100644 --- a/src/mainboard/google/storm/cdp.c +++ b/src/mainboard/google/storm/cdp.c @@ -21,7 +21,7 @@ #include #include -void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count) +void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count) { int i; diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 09144507b8..dc3f3abb45 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 1361a516de..580ca1606d 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -25,7 +25,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/platform.asl" @@ -55,5 +55,5 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index a54b80b633..660bb76361 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -76,7 +76,8 @@ void stout_ec_finalize_smm(void) printk(BIOS_ERR, " EC Fan Error\n"); critical_shutdown = 1; #if CONFIG(ELOG_GSMI) - elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_FAN_ERROR); + elog_add_event_word(EC_HOST_EVENT_BATTERY_CRITICAL, + EC_HOST_EVENT_THROTTLE_START); #endif } @@ -86,7 +87,8 @@ void stout_ec_finalize_smm(void) printk(BIOS_ERR, " EC Thermal Device Error\n"); critical_shutdown = 1; #if CONFIG(ELOG_GSMI) - elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_THERMAL); + elog_add_event_word(EC_HOST_EVENT_BATTERY_CRITICAL, + EC_HOST_EVENT_THERMAL); #endif } @@ -98,14 +100,15 @@ void stout_ec_finalize_smm(void) printk(BIOS_ERR, " EC Critical Battery Error\n"); critical_shutdown = 1; #if CONFIG(ELOG_GSMI) - elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY_CRITICAL); + elog_add_event_word(ELOG_TYPE_EC_EVENT, + EC_HOST_EVENT_BATTERY_CRITICAL); #endif } if ((ec_reg & 0x8F) == 0x8F) { printk(BIOS_ERR, " EC Read Battery Error\n"); #if CONFIG(ELOG_GSMI) - elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY); + elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_HOST_EVENT_BATTERY); #endif } diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index ac356027f5..782546a54d 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig new file mode 100644 index 0000000000..56b3a729c2 --- /dev/null +++ b/src/mainboard/google/trogdor/Kconfig @@ -0,0 +1,50 @@ + +config BOARD_GOOGLE_TROGDOR_COMMON # Umbrella option to be selected by variants + def_bool n + +if BOARD_GOOGLE_TROGDOR_COMMON + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select COMMON_CBFS_SPI_WRAPPER + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_RTC + select EC_GOOGLE_CHROMEEC_SPI + select RTC + select SOC_QUALCOMM_SC7180 + select SPI_FLASH + select SPI_FLASH_WINBOND + select MAINBOARD_HAS_CHROMEOS + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_VBNV_FLASH + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select VBOOT_MOCK_SECDATA + +config MAINBOARD_DIR + string + default google/trogdor + +config MAINBOARD_VENDOR + string + default "Google" + +config DRIVER_TPM_SPI_BUS + hex + default 0x5 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0xa + +########################################################## +#### Update below when adding a new derivative board. #### +########################################################## + +config MAINBOARD_PART_NUMBER + string + default "Trogdor" if BOARD_GOOGLE_TROGDOR + +endif # BOARD_GOOGLE_TROGDOR_COMMON diff --git a/src/mainboard/google/trogdor/Kconfig.name b/src/mainboard/google/trogdor/Kconfig.name new file mode 100644 index 0000000000..425c9bfa95 --- /dev/null +++ b/src/mainboard/google/trogdor/Kconfig.name @@ -0,0 +1,4 @@ + +config BOARD_GOOGLE_TROGDOR + bool "Trogdor" + select BOARD_GOOGLE_TROGDOR_COMMON diff --git a/src/mainboard/google/trogdor/Makefile.inc b/src/mainboard/google/trogdor/Makefile.inc new file mode 100644 index 0000000000..bda55be4fb --- /dev/null +++ b/src/mainboard/google/trogdor/Makefile.inc @@ -0,0 +1,38 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2018 Google LLC +## Copyright 2019 The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += memlayout.ld +bootblock-y += reset.c +bootblock-y += boardid.c +bootblock-y += chromeos.c +bootblock-y += bootblock.c + +verstage-y += memlayout.ld +verstage-y += reset.c +verstage-y += boardid.c +verstage-y += chromeos.c + +romstage-y += memlayout.ld +romstage-y += romstage.c +romstage-y += reset.c +romstage-y += boardid.c +romstage-y += chromeos.c + +ramstage-y += memlayout.ld +ramstage-y += mainboard.c +ramstage-y += reset.c +ramstage-y += chromeos.c +ramstage-y += boardid.c diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h new file mode 100644 index 0000000000..f024e13646 --- /dev/null +++ b/src/mainboard/google/trogdor/board.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ +#define _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ + +#include +#include + +#define GPIO_EC_IN_RW GPIO(118) +#define GPIO_AP_EC_INT GPIO(94) +#define GPIO_AP_SUSPEND GPIO(20) +#define GPIO_WP_STATE GPIO(42) +#define GPIO_H1_AP_INT GPIO(21) + +void setup_chromeos_gpios(void); + +#endif /* _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ */ diff --git a/src/mainboard/google/trogdor/board_info.txt b/src/mainboard/google/trogdor/board_info.txt new file mode 100644 index 0000000000..2d1742bfc6 --- /dev/null +++ b/src/mainboard/google/trogdor/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Trogdor Qualcomm sc7180 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/trogdor/boardid.c b/src/mainboard/google/trogdor/boardid.c new file mode 100644 index 0000000000..def3068d31 --- /dev/null +++ b/src/mainboard/google/trogdor/boardid.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * Copyright 2019 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +uint32_t board_id(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; + + const gpio_t pins[] = {[2] = GPIO(31), [1] = GPIO(93), [0] = GPIO(33)}; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + + return id; +} + +uint32_t ram_code(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; + + const gpio_t pins[] = {[1] = GPIO(91), [0] = GPIO(29)}; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + + return id; +} + +uint32_t sku_id(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; + + const gpio_t pins[] = {[1] = GPIO(90), [0] = GPIO(114)}; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + + return id; +} diff --git a/src/mainboard/google/trogdor/bootblock.c b/src/mainboard/google/trogdor/bootblock.c new file mode 100644 index 0000000000..c658093d07 --- /dev/null +++ b/src/mainboard/google/trogdor/bootblock.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "board.h" + +void bootblock_mainboard_init(void) +{ + setup_chromeos_gpios(); +} diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c new file mode 100644 index 0000000000..e84061352e --- /dev/null +++ b/src/mainboard/google/trogdor/chromeos.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "board.h" + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO_WP_STATE); +} + +void setup_chromeos_gpios(void) +{ + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_AP_EC_INT); + gpio_output(GPIO_AP_SUSPEND, 1); + gpio_input(GPIO_WP_STATE); + gpio_input_pullup(GPIO_H1_AP_INT); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {GPIO_EC_IN_RW.addr, ACTIVE_LOW, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), + "EC interrupt"}, + {GPIO_WP_STATE.addr, ACTIVE_LOW, !get_write_protect_state(), + "write protect"}, + {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), + "TPM interrupt"}, + }; + + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd new file mode 100644 index 0000000000..9af3d51cb8 --- /dev/null +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -0,0 +1,54 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License version 2 and +## only version 2 as published by the Free Software Foundation. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +FLASH@0x0 8M { + WP_RO 4M { + RO_SECTION 0x204000 { + BOOTBLOCK 96K + COREBOOT(CBFS) + FMAP@0x200000 0x1000 + GBB 0x2f00 + RO_FRID 0x100 + } + RO_VPD(PRESERVE) 16K + RO_DDR_TRAINING(PRESERVE) 8K + RO_LIMITS_CFG(PRESERVE) 4K + RO_FSG(PRESERVE) + } + + RW_VPD(PRESERVE) 32K + RW_NVRAM(PRESERVE) 16K + RW_DDR_TRAINING(PRESERVE) 8K + RW_LIMITS_CFG(PRESERVE) 4K + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA + } + + RW_SECTION_A 1280K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + + + RW_SECTION_B 1280K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + + RW_LEGACY(CBFS) +} diff --git a/src/superio/intel/i8900/Kconfig b/src/mainboard/google/trogdor/devicetree.cb similarity index 59% rename from src/superio/intel/i8900/Kconfig rename to src/mainboard/google/trogdor/devicetree.cb index ed37f7fe16..d64ade4fce 100644 --- a/src/superio/intel/i8900/Kconfig +++ b/src/mainboard/google/trogdor/devicetree.cb @@ -1,11 +1,11 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. ## ## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. +## it under the terms of the GNU General Public License version 2 and +## only version 2 as published by the Free Software Foundation. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -13,5 +13,6 @@ ## GNU General Public License for more details. ## -config SUPERIO_INTEL_I8900 - bool +chip soc/qualcomm/sc7180 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c new file mode 100644 index 0000000000..ce03ce1421 --- /dev/null +++ b/src/mainboard/google/trogdor/mainboard.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +static void mainboard_init(struct device *dev) +{ + +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/trogdor/memlayout.ld b/src/mainboard/google/trogdor/memlayout.ld new file mode 100644 index 0000000000..74790f5404 --- /dev/null +++ b/src/mainboard/google/trogdor/memlayout.ld @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/eve/ramstage.c b/src/mainboard/google/trogdor/reset.c similarity index 59% rename from src/mainboard/google/eve/ramstage.c rename to src/mainboard/google/trogdor/reset.c index be3676a1f2..558f63d79f 100644 --- a/src/mainboard/google/eve/ramstage.c +++ b/src/mainboard/google/trogdor/reset.c @@ -1,8 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2016 Intel Corporation + * Copyright 2018 Google LLC + * Copyright 2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,10 +14,12 @@ * GNU General Public License for more details. */ -#include -#include "gpio.h" +#include +#include -void mainboard_silicon_init_params(FSP_SIL_UPD *params) +/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage), + but this works well enough for our purposes. */ +void do_board_reset(void) { - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + google_chromeec_reboot(0, EC_REBOOT_COLD, 0); } diff --git a/src/mainboard/google/trogdor/romstage.c b/src/mainboard/google/trogdor/romstage.c new file mode 100644 index 0000000000..718538728c --- /dev/null +++ b/src/mainboard/google/trogdor/romstage.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +void platform_romstage_main(void) +{ + /* QCLib: DDR init & train */ + qclib_load_and_run(); +} diff --git a/src/mainboard/hp/2570p/dsdt.asl b/src/mainboard/hp/2570p/dsdt.asl index 756516efe2..5730ea083e 100644 --- a/src/mainboard/hp/2570p/dsdt.asl +++ b/src/mainboard/hp/2570p/dsdt.asl @@ -29,10 +29,10 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c index 6401909dd5..6ffc3409a5 100644 --- a/src/mainboard/hp/2570p/romstage.c +++ b/src/mainboard/hp/2570p/romstage.c @@ -22,12 +22,6 @@ void pch_enable_lpc(void) { - /* - * CNF2 and CNF1 for Super I/O - * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC - */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/2760p/dsdt.asl b/src/mainboard/hp/2760p/dsdt.asl index 756516efe2..5730ea083e 100644 --- a/src/mainboard/hp/2760p/dsdt.asl +++ b/src/mainboard/hp/2760p/dsdt.asl @@ -29,10 +29,10 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c index ba6f9566cf..b448f79259 100644 --- a/src/mainboard/hp/2760p/romstage.c +++ b/src/mainboard/hp/2760p/romstage.c @@ -21,12 +21,6 @@ void pch_enable_lpc(void) { - /* - * CNF2 and CNF1 for Super I/O - * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC - */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/8460p/dsdt.asl b/src/mainboard/hp/8460p/dsdt.asl index 756516efe2..5730ea083e 100644 --- a/src/mainboard/hp/8460p/dsdt.asl +++ b/src/mainboard/hp/8460p/dsdt.asl @@ -29,10 +29,10 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c index f30c3a8d27..72a62c9eb3 100644 --- a/src/mainboard/hp/8460p/romstage.c +++ b/src/mainboard/hp/8460p/romstage.c @@ -25,15 +25,6 @@ void pch_enable_lpc(void) { - /* - * CNF2 and CNF1 for Super I/O - * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC - * Enable parallel port and serial port - */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - LPT_LPC_EN | COMA_LPC_EN); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/8470p/dsdt.asl b/src/mainboard/hp/8470p/dsdt.asl index 756516efe2..5730ea083e 100644 --- a/src/mainboard/hp/8470p/dsdt.asl +++ b/src/mainboard/hp/8470p/dsdt.asl @@ -29,10 +29,10 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/romstage.c index b1375e815b..83f382d0a4 100644 --- a/src/mainboard/hp/8470p/romstage.c +++ b/src/mainboard/hp/8470p/romstage.c @@ -24,15 +24,6 @@ void pch_enable_lpc(void) { - /* - * CNF2 and CNF1 for Super I/O - * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC - * Enable parallel port and serial port - */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - LPT_LPC_EN | COMA_LPC_EN); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/8770w/dsdt.asl b/src/mainboard/hp/8770w/dsdt.asl index 756516efe2..5730ea083e 100644 --- a/src/mainboard/hp/8770w/dsdt.asl +++ b/src/mainboard/hp/8770w/dsdt.asl @@ -29,10 +29,10 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c index 8956b08b7b..2bd9162beb 100644 --- a/src/mainboard/hp/8770w/romstage.c +++ b/src/mainboard/hp/8770w/romstage.c @@ -25,15 +25,6 @@ void pch_enable_lpc(void) { - /* - * CNF2 and CNF1 for Super I/O - * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC - * Enable parallel port and serial port - */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - LPT_LPC_EN | COMA_LPC_EN); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c index c87749e2d4..75d026e00a 100644 --- a/src/mainboard/hp/abm/mptable.c +++ b/src/mainboard/hp/abm/mptable.c @@ -39,7 +39,7 @@ u8 intr_data[0x54] = { 0x10,0x11,0x12,0x13 }; -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; mc->mpc_entry_count++; diff --git a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl index ef67ee7477..3f249e35a5 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl @@ -29,10 +29,10 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c index 3c388776c3..258eac74b2 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c @@ -29,16 +29,6 @@ void pch_enable_lpc(void) { - /* - * Enable SuperIO, TPM, Keyboard, LPT, COMA - * (COMB can be equip on expansion header) - */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN |CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | - COMB_LPC_EN | COMA_LPC_EN); - - /* COMA: 3F8h, COMB: 2F8h */ - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c index 16908cf704..b70b0a3e24 100644 --- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c +++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c @@ -18,13 +18,13 @@ #define SCH4307_CONFIG_PORT 0x162e static inline void shc4307_enter_ext_func_mode(pnp_devfn_t dev) { - unsigned port = dev >> 8; + unsigned int port = dev >> 8; outb(0x55, port); } static inline void shc4307_exit_ext_func_mode(pnp_devfn_t dev) { - unsigned port = dev >> 8; + unsigned int port = dev >> 8; outb(0xaa, port); } diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c index e217aa7138..0d8ee8c28b 100644 --- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c +++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c @@ -33,7 +33,7 @@ struct mb_sysconf_t mb_sysconf; void get_bus_conf(void) { - unsigned apicid_base; + unsigned int apicid_base; struct device *dev; int i; diff --git a/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h b/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h index 8b0e580057..b2a11e33f2 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h +++ b/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h @@ -29,9 +29,9 @@ struct mb_sysconf_t { unsigned char bus_bcm5785_0; unsigned char bus_bcm5785_1; unsigned char bus_bcm5785_1_1; - unsigned apicid_bcm5785[3]; + unsigned int apicid_bcm5785[3]; - unsigned sbdn2; + unsigned int sbdn2; }; #endif diff --git a/src/mainboard/hp/folio_9470m/dsdt.asl b/src/mainboard/hp/folio_9470m/dsdt.asl index 756516efe2..5730ea083e 100644 --- a/src/mainboard/hp/folio_9470m/dsdt.asl +++ b/src/mainboard/hp/folio_9470m/dsdt.asl @@ -29,10 +29,10 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/romstage.c index 8ff7813cd9..061a06877c 100644 --- a/src/mainboard/hp/folio_9470m/romstage.c +++ b/src/mainboard/hp/folio_9470m/romstage.c @@ -23,13 +23,6 @@ void pch_enable_lpc(void) { - /* - * CNF2 and CNF1 for Super I/O - * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC - */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index 08de04e4ca..0d44397be5 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -39,7 +39,7 @@ u8 intr_data[0x54] = { 0x10,0x11,0x12,0x13 }; -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; mc->mpc_entry_count++; diff --git a/src/mainboard/hp/revolve_810_g1/dsdt.asl b/src/mainboard/hp/revolve_810_g1/dsdt.asl index 756516efe2..5730ea083e 100644 --- a/src/mainboard/hp/revolve_810_g1/dsdt.asl +++ b/src/mainboard/hp/revolve_810_g1/dsdt.asl @@ -29,10 +29,10 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c index 5f8df63f5c..5c83a91511 100644 --- a/src/mainboard/hp/revolve_810_g1/romstage.c +++ b/src/mainboard/hp/revolve_810_g1/romstage.c @@ -26,13 +26,6 @@ void pch_enable_lpc(void) { - /* - * CNF2 and CNF1 for Super I/O - * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC - */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); } void mainboard_rcba_config(void) diff --git a/src/mainboard/hp/z220_sff_workstation/dsdt.asl b/src/mainboard/hp/z220_sff_workstation/dsdt.asl index ef67ee7477..3f249e35a5 100644 --- a/src/mainboard/hp/z220_sff_workstation/dsdt.asl +++ b/src/mainboard/hp/z220_sff_workstation/dsdt.asl @@ -29,10 +29,10 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/hp/z220_sff_workstation/romstage.c b/src/mainboard/hp/z220_sff_workstation/romstage.c index 9883879bae..6c139ed34d 100644 --- a/src/mainboard/hp/z220_sff_workstation/romstage.c +++ b/src/mainboard/hp/z220_sff_workstation/romstage.c @@ -17,10 +17,8 @@ */ #include -#include #include #include -#include #include #include #include @@ -31,16 +29,6 @@ void pch_enable_lpc(void) { - /* - * Enable SuperIO, TPM, Keyboard, LPT, COMA - * (COMB can be equip on expansion header) - */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | - COMB_LPC_EN | COMA_LPC_EN); - - /* COMA: 3F8h, COMB: 2F8h */ - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); } void mainboard_rcba_config(void) diff --git a/src/mainboard/ibase/mb899/dsdt.asl b/src/mainboard/ibase/mb899/dsdt.asl index cc56d89aa5..31b67a73d5 100644 --- a/src/mainboard/ibase/mb899/dsdt.asl +++ b/src/mainboard/ibase/mb899/dsdt.asl @@ -47,5 +47,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 82dbba5dc5..f1ecc1f040 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -149,12 +149,12 @@ static void early_ich7_init(void) uint32_t reg32; // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); // usb transient disconnect reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); @@ -169,31 +169,7 @@ static void early_ich7_init(void) reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c index 7fb45f91f2..aa88cc76ed 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.c +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -15,10 +15,10 @@ */ #include -#include #include #include #include +#include #include "superio_hwm.h" @@ -33,17 +33,6 @@ #define HWM_BASE 0x290 -static void hwm_write(u8 reg, u8 value) -{ - outb(reg, HWM_BASE + 0x05); - outb(value, HWM_BASE + 0x06); -} - -static void hwm_bank(u8 bank) -{ - hwm_write(0x4e, bank); -} - struct fan_speed { u8 fan_in; u16 fan_speed; @@ -90,19 +79,19 @@ void hwm_setup(void) //sysfan_temperature = FAN_TEMPERATURE_30DEGC; //get_option(&sysfan_temperature, "sysfan_temperature"); - // hwm_write(0x31, 0x20); // AVCC high limit - // hwm_write(0x34, 0x06); // VIN2 low limit + // pnp_write_hwm5_index(HWM_BASE, 0x31, 0x20); // AVCC high limit + // pnp_write_hwm5_index(HWM_BASE, 0x34, 0x06); // VIN2 low limit - hwm_bank(0); - hwm_write(0x59, 0x20); // Diode Selection - hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + pnp_write_hwm5_index(HWM_BASE, 0x4e, 0); + pnp_write_hwm5_index(HWM_BASE, 0x59, 0x20); // Diode Selection + pnp_write_hwm5_index(HWM_BASE, 0x5d, 0x0f); // All Sensors Diode, not Thermistor - hwm_bank(4); - hwm_write(0x54, 0xf1); // SYSTIN temperature offset - hwm_write(0x55, 0x19); // CPUTIN temperature offset - hwm_write(0x56, 0xfc); // AUXTIN temperature offset + pnp_write_hwm5_index(HWM_BASE, 0x4e, 4); + pnp_write_hwm5_index(HWM_BASE, 0x54, 0xf1); // SYSTIN temperature offset + pnp_write_hwm5_index(HWM_BASE, 0x55, 0x19); // CPUTIN temperature offset + pnp_write_hwm5_index(HWM_BASE, 0x56, 0xfc); // AUXTIN temperature offset - hwm_bank(0x80); // Default + pnp_write_hwm5_index(HWM_BASE, 0x4e, 0x80); // Default u8 fan_config = 0; // 00 FANOUT is Manual Mode @@ -117,41 +106,43 @@ void hwm_setup(void) case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; } // This register must be written first - hwm_write(0x04, fan_config); + pnp_write_hwm5_index(HWM_BASE, 0x04, fan_config); switch (cpufan_control) { - case FAN_CRUISE_CONTROL_SPEED: + case FAN_CRUISE_CONTROL_SPEED: /* CPUFANIN target speed */ printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", fan_speeds[cpufan_speed].fan_speed); - hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + pnp_write_hwm5_index(HWM_BASE, 0x06, fan_speeds[cpufan_speed].fan_in); break; - case FAN_CRUISE_CONTROL_THERMAL: + case FAN_CRUISE_CONTROL_THERMAL: /* CPUFANIN target temperature */ printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", temperatures[cpufan_temperature].deg_celsius, temperatures[cpufan_temperature].deg_fahrenheit); - hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + pnp_write_hwm5_index(HWM_BASE, 0x06, + temperatures[cpufan_temperature].deg_celsius); break; } switch (sysfan_control) { - case FAN_CRUISE_CONTROL_SPEED: + case FAN_CRUISE_CONTROL_SPEED: /* SYSFANIN target speed */ printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", fan_speeds[sysfan_speed].fan_speed); - hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + pnp_write_hwm5_index(HWM_BASE, 0x05, fan_speeds[sysfan_speed].fan_in); break; - case FAN_CRUISE_CONTROL_THERMAL: + case FAN_CRUISE_CONTROL_THERMAL: /* SYSFANIN target temperature */ printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", temperatures[sysfan_temperature].deg_celsius, temperatures[sysfan_temperature].deg_fahrenheit); - hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + pnp_write_hwm5_index(HWM_BASE, + 0x05, temperatures[sysfan_temperature].deg_celsius); break; } - hwm_write(0x0e, 0x02); // Fan Output Step Down Time - hwm_write(0x0f, 0x02); // Fan Output Step Up Time + pnp_write_hwm5_index(HWM_BASE, 0x0e, 0x02); // Fan Output Step Down Time + pnp_write_hwm5_index(HWM_BASE, 0x0f, 0x02); // Fan Output Step Up Time - hwm_write(0x47, 0xaf); // FAN divisor register - hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + pnp_write_hwm5_index(HWM_BASE, 0x47, 0xaf); // FAN divisor register + pnp_write_hwm5_index(HWM_BASE, 0x4b, 0x84); // AUXFANIN speed divisor - hwm_write(0x40, 0x01); // Init, but no SMI# + pnp_write_hwm5_index(HWM_BASE, 0x40, 0x01); // Init, but no SMI# } diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi/cpstate.asl b/src/mainboard/iei/kino-780am2-fam10/acpi/cpstate.asl index 206dd686f5..acaa5bae32 100644 --- a/src/mainboard/iei/kino-780am2-fam10/acpi/cpstate.asl +++ b/src/mainboard/iei/kino-780am2-fam10/acpi/cpstate.asl @@ -22,17 +22,25 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl index 6bb7ff46b1..ffbe3ac974 100644 --- a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl +++ b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl @@ -58,39 +58,24 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - CPU0, /* name space name */ - 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "acpi/cpstate.asl" } - - Processor( - CPU1, /* name space name */ - 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "acpi/cpstate.asl" } - - Processor( - CPU2, /* name space name */ - 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "acpi/cpstate.asl" } - - Processor( - CPU3, /* name space name */ - 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl index 2e3fa7ac44..9dd8879706 100644 --- a/src/mainboard/intel/apollolake_rvp/dsdt.asl +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -33,6 +33,6 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/intel/baskingridge/acpi/platform.asl b/src/mainboard/intel/baskingridge/acpi/platform.asl index 4d610d5a6b..bb2d6f9e86 100644 --- a/src/mainboard/intel/baskingridge/acpi/platform.asl +++ b/src/mainboard/intel/baskingridge/acpi/platform.asl @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include +#include /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 2d5919c06e..74eb788595 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl index c713330f38..28d743e598 100644 --- a/src/mainboard/intel/baskingridge/dsdt.asl +++ b/src/mainboard/intel/baskingridge/dsdt.asl @@ -52,5 +52,5 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index e0fa7eb714..37af13f8da 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/intel/bayleybay_fsp/dsdt.asl b/src/mainboard/intel/bayleybay_fsp/dsdt.asl index 3719154bdd..bea6af7973 100644 --- a/src/mainboard/intel/bayleybay_fsp/dsdt.asl +++ b/src/mainboard/intel/bayleybay_fsp/dsdt.asl @@ -48,7 +48,7 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include #include "acpi/mainboard.asl" } diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c index 2ffb137469..f6ba0355ee 100644 --- a/src/mainboard/intel/bayleybay_fsp/mainboard.c +++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c @@ -20,7 +20,6 @@ #if CONFIG(VGA_ROM_RUN) #include #endif -#include /* * mainboard_enable is executed as first thing after enumerate_buses(). diff --git a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c index e497bdbdc9..29f98f46c0 100644 --- a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c +++ b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c @@ -20,7 +20,6 @@ #if CONFIG(VGA_ROM_RUN) #include #endif -#include /* * mainboard_enable is executed as first thing after enumerate_buses(). diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index c719d2388f..9a519c0b39 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -29,7 +29,7 @@ DefinitionBlock( #include // global NVS and variables - #include + #include Scope (\_SB) { Device (PCI0) @@ -45,6 +45,6 @@ DefinitionBlock( #endif // Chipset specific sleep states - #include + #include } diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 70d0bd6ded..1d7216aecc 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -29,7 +29,7 @@ DefinitionBlock( #include // global NVS and variables - #include + #include Scope (\_SB) { Device (PCI0) @@ -45,6 +45,6 @@ DefinitionBlock( #endif // Chipset specific sleep states - #include + #include } diff --git a/src/mainboard/intel/d510mo/acpi/platform.asl b/src/mainboard/intel/d510mo/acpi/platform.asl deleted file mode 100644 index 6c92a4ed47..0000000000 --- a/src/mainboard/intel/d510mo/acpi/platform.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Method(_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store(Arg0, PICM) -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) /* SMI Function */ - Store (0, TRP0) /* Generate trap */ - Return (SMIF) /* Return value of SMI handler */ -} diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl index 8dc11942a0..e07ecc2801 100644 --- a/src/mainboard/intel/d510mo/dsdt.asl +++ b/src/mainboard/intel/d510mo/dsdt.asl @@ -24,7 +24,7 @@ DefinitionBlock( 0x20090419 // OEM revision ) { - #include "acpi/platform.asl" + #include #include #include @@ -38,5 +38,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/intel/d945gclf/dsdt.asl b/src/mainboard/intel/d945gclf/dsdt.asl index 95ed8d913d..afc53861bb 100644 --- a/src/mainboard/intel/d945gclf/dsdt.asl +++ b/src/mainboard/intel/d945gclf/dsdt.asl @@ -50,5 +50,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index bad2b6d538..f0ae18823e 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -69,12 +69,12 @@ static void early_ich7_init(void) uint32_t reg32; // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); // usb transient disconnect reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); @@ -89,31 +89,7 @@ static void early_ich7_init(void) reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); - reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) diff --git a/src/mainboard/intel/dcp847ske/dsdt.asl b/src/mainboard/intel/dcp847ske/dsdt.asl index 60f4c74241..39e7008759 100644 --- a/src/mainboard/intel/dcp847ske/dsdt.asl +++ b/src/mainboard/intel/dcp847ske/dsdt.asl @@ -27,10 +27,10 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 705ace9bc6..984629574c 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -27,18 +27,8 @@ #include "superio.h" #include "thermal.h" -#if CONFIG(DISABLE_UART_ON_TESTPADS) -#define DEBUG_UART_EN 0 -#else -#define DEBUG_UART_EN COMA_LPC_EN -#endif - void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, - CNF2_LPC_EN | DEBUG_UART_EN); - /* Decode SuperIO 0x0a00 */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01); } void mainboard_rcba_config(void) diff --git a/src/mainboard/intel/dcp847ske/superio.h b/src/mainboard/intel/dcp847ske/superio.h index 56938e7026..6f74d3e72c 100644 --- a/src/mainboard/intel/dcp847ske/superio.h +++ b/src/mainboard/intel/dcp847ske/superio.h @@ -18,6 +18,7 @@ #define DCP847SKE_SUPERIO_H #include +#include #define NUVOTON_PORT 0x4e #define HWM_PORT 0x0a30 @@ -44,11 +45,6 @@ #define SUPERIO_WRITE_INITVAL(val) SUPERIO_WRITE((val) >> 8, (val) & 0xff) -#define HWM_WRITE(reg, data) do { \ - outb((reg), HWM_PORT + 5); \ - outb((data), HWM_PORT + 6); \ -} while (0) - -#define HWM_WRITE_INITVAL(val) HWM_WRITE((val) >> 8, (val) & 0xff) +#define HWM_WRITE_INITVAL(val) pnp_write_hwm5_index(HWM_PORT, (val) >> 8, (val) & 0xff) #endif /* DCP847SKE_SUPERIO_H */ diff --git a/src/mainboard/intel/dg41wv/Kconfig b/src/mainboard/intel/dg41wv/Kconfig index 373f6fa0c8..74c7d5270c 100644 --- a/src/mainboard/intel/dg41wv/Kconfig +++ b/src/mainboard/intel/dg41wv/Kconfig @@ -25,9 +25,6 @@ config BOARD_SPECIFIC_OPTIONS select SUPERIO_WINBOND_W83627DHG select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_L1_SUB_STATE select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME diff --git a/src/mainboard/intel/dg41wv/acpi/platform.asl b/src/mainboard/intel/dg41wv/acpi/platform.asl deleted file mode 100644 index 6c92a4ed47..0000000000 --- a/src/mainboard/intel/dg41wv/acpi/platform.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Method(_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store(Arg0, PICM) -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) /* SMI Function */ - Store (0, TRP0) /* Generate trap */ - Return (SMIF) /* Return value of SMI handler */ -} diff --git a/src/mainboard/intel/dg41wv/dsdt.asl b/src/mainboard/intel/dg41wv/dsdt.asl index 002dfcaeb6..31e7c10d3e 100644 --- a/src/mainboard/intel/dg41wv/dsdt.asl +++ b/src/mainboard/intel/dg41wv/dsdt.asl @@ -25,7 +25,7 @@ DefinitionBlock( ) { // global NVS and variables - #include "acpi/platform.asl" + #include #include Scope (\_SB) { @@ -38,5 +38,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 74f86221eb..81d50670e9 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -32,7 +32,6 @@ static void mb_lpc_setup(void) { - u32 reg32; /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); @@ -55,10 +54,7 @@ static void mb_lpc_setup(void) RCBA8(0x31ff) = 0x03; RCBA8(0x31ff); - reg32 = RCBA32(GCS); - reg32 |= (1 << 5); - RCBA32(GCS) = reg32; - RCBA32(CG) = 0x00000001; + ich7_setup_cir(); } static void ich7_enable_lpc(void) diff --git a/src/mainboard/intel/dg43gt/acpi/platform.asl b/src/mainboard/intel/dg43gt/acpi/platform.asl deleted file mode 100644 index 6c92a4ed47..0000000000 --- a/src/mainboard/intel/dg43gt/acpi/platform.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Method(_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store(Arg0, PICM) -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) /* SMI Function */ - Store (0, TRP0) /* Generate trap */ - Return (SMIF) /* Return value of SMI handler */ -} diff --git a/src/mainboard/intel/dg43gt/dsdt.asl b/src/mainboard/intel/dg43gt/dsdt.asl index 911dceeaf3..f36d179534 100644 --- a/src/mainboard/intel/dg43gt/dsdt.asl +++ b/src/mainboard/intel/dg43gt/dsdt.asl @@ -25,7 +25,7 @@ DefinitionBlock( ) { // global NVS and variables - #include "acpi/platform.asl" + #include #include Scope (\_SB) { @@ -38,5 +38,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 4fb512a694..470688fc98 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl index 45968fbfc3..74268ef60a 100644 --- a/src/mainboard/intel/emeraldlake2/dsdt.asl +++ b/src/mainboard/intel/emeraldlake2/dsdt.asl @@ -24,7 +24,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/platform.asl" @@ -53,5 +53,5 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 5a64e07d99..210588c93c 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index ee3cec1ebf..d56576e2e5 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -32,9 +32,6 @@ void pch_enable_lpc(void) { pci_devfn_t dev = PCH_LPC_DEV; - /* Set COM1/COM2 decode range */ - pci_write_config16(dev, LPC_IO_DEC, 0x0010); - /* Enable SuperIO + PS/2 Keyboard/Mouse */ u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN; pci_write_config16(dev, LPC_EN, lpc_config); diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 7e1742d0f9..37f88dd8f0 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_QUARK select MAINBOARD_HAS_I2C_TPM_ATMEL select MAINBOARD_HAS_TPM2 - select PLATFORM_USES_FSP2_0 select UDK_2015_BINDING @@ -103,7 +102,6 @@ config FSP_DEBUG_ALL Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA also turn on FSP 2.0 debug support for ESRAM_LAYOUT, FSP_CALLS_AND_STATUS, FSP_HEADER, POSTCAR_CONSOLE and VERIFY_HOBS - or FSP 1.1 DISPLAY_FSP_ENTRY_POINTS config VBOOT_WITH_CRYPTO_SHIELD bool "Verified boot using the Crypto Shield board" diff --git a/src/mainboard/intel/galileo/acpi_tables.c b/src/mainboard/intel/galileo/acpi_tables.c index 78b05abb89..bba8cedf30 100644 --- a/src/mainboard/intel/galileo/acpi_tables.c +++ b/src/mainboard/intel/galileo/acpi_tables.c @@ -26,7 +26,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 5; + header->revision = ACPI_FADT_REV_ACPI_5_0; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/mainboard/intel/glkrvp/dsdt.asl b/src/mainboard/intel/glkrvp/dsdt.asl index 759d669f8a..d7711be75d 100644 --- a/src/mainboard/intel/glkrvp/dsdt.asl +++ b/src/mainboard/intel/glkrvp/dsdt.asl @@ -45,7 +45,7 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/intel/harcuvar/acpi/platform.asl b/src/mainboard/intel/harcuvar/acpi/platform.asl index ea66a9f974..8d8229ab43 100644 --- a/src/mainboard/intel/harcuvar/acpi/platform.asl +++ b/src/mainboard/intel/harcuvar/acpi/platform.asl @@ -16,44 +16,6 @@ * */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/intel/harcuvar/dsdt.asl b/src/mainboard/intel/harcuvar/dsdt.asl index 9bc42cf4de..c7e7f7c91b 100644 --- a/src/mainboard/intel/harcuvar/dsdt.asl +++ b/src/mainboard/intel/harcuvar/dsdt.asl @@ -27,6 +27,7 @@ DefinitionBlock( ) { // Some generic macros + #include #include "acpi/platform.asl" #include "acpi/mainboard.asl" @@ -50,5 +51,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index ad469faaa7..152f038fc6 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include // global NVS and variables - #include + #include // CPU #include @@ -60,7 +60,7 @@ DefinitionBlock( #endif // Chipset specific sleep states - #include + #include // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index 8a165518b7..059bcd54c3 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -57,7 +57,7 @@ DefinitionBlock( #endif // Chipset specific sleep states - #include + #include // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 63961513b9..d7706d16a0 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -20,19 +20,6 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select SOC_INTEL_SKYLAKE -choice - prompt "FSP driver" - default KUNIMITSU_USES_FSP1_1 - -config KUNIMITSU_USES_FSP1_1 - bool "FSP driver 1.1" - -config KUNIMITSU_USES_FSP2_0 - bool "FSP driver 2.0" - select MAINBOARD_USES_FSP2_0 - -endchoice - config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index 933074b4c5..9a667d6a36 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -29,7 +29,3 @@ ramstage-y += mainboard.c ramstage-y += ramstage.c smm-y += smihandler.c - -ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) -romstage-srcs := $(subst $(MAINBOARDDIR)/romstage.c,$(MAINBOARDDIR)/romstage_fsp20.c,$(romstage-srcs)) -endif diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index f2c9f43ec1..670a474865 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -60,82 +60,70 @@ chip soc/intel/skylake register "PmConfigSlpAMinAssert" = "0x03" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x10, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x1C, \ - .voltage_limit = 0x5F0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, }" register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x88, \ - .voltage_limit = 0x5F0 \ - }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x88, \ - .voltage_limit = 0x5F0, \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x8C ,\ - .voltage_limit = 0x5F0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, }" register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x8C, \ - .voltage_limit = 0x5F0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, }" # Enable Root port 1 and 5. diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index af5f99d815..6dab56ea77 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -49,7 +49,7 @@ DefinitionBlock( #include // Chipset specific sleep states - #include + #include // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index 0312ad1987..e2b065c1cc 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -1,9 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,21 +13,26 @@ * GNU General Public License for more details. */ +#include #include -#include #include "gpio.h" +#include +#include #include "spd/spd.h" -void mainboard_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) +void mainboard_memory_init_params(FSPM_UPD *mupd) { - spd_memory_init_params(memory_params); - mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0, - &memory_params->DqByteMapCh1); - mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0, - &memory_params->DqsMapCpu2DramCh1); - mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); - mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); - memory_params->MemorySpdDataLen = SPD_LEN; - memory_params->DqPinsInterleaved = FALSE; + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); + if (mainboard_has_dual_channel_mem()) + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + mem_cfg->MemorySpdDataLen = SPD_LEN; } diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c deleted file mode 100644 index 2a4474e15f..0000000000 --- a/src/mainboard/intel/kunimitsu/romstage_fsp20.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "gpio.h" -#include -#include -#include "spd/spd.h" - -void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - FSP_M_CONFIG *mem_cfg; - mem_cfg = &mupd->FspmConfig; - - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, - &mem_cfg->DqByteMapCh1); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, - &mem_cfg->DqsMapCpu2DramCh1); - mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); - mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); - - mem_cfg->DqPinsInterleaved = 0; - mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); - if (mainboard_has_dual_channel_mem()) - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; - mem_cfg->MemorySpdDataLen = SPD_LEN; -} diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc index 9856368e7a..814d04df4b 100644 --- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc @@ -14,7 +14,6 @@ ## GNU General Public License for more details. ## -romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += spd.c romstage-y += spd_util.c SPD_BIN = $(obj)/spd.bin @@ -43,7 +42,7 @@ SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f). $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/intel/kunimitsu/spd/spd.c b/src/mainboard/intel/kunimitsu/spd/spd.c deleted file mode 100644 index db5e24e927..0000000000 --- a/src/mainboard/intel/kunimitsu/spd/spd.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include "spd.h" - -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, - "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", - banks, ranks, rows, cols, capmb); - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} - -/* Fill SPD pointers for on-board memory */ -void spd_memory_init_params(MEMORY_INIT_UPD *memory_params) -{ - uintptr_t spd_data; - spd_data = mainboard_get_spd_data(); - - /* Make sure a valid SPD was found */ - if (*(uint8_t *)spd_data == 0) - die("Invalid SPD data."); - - memory_params->MemorySpdPtr00 = spd_data; - if (mainboard_has_dual_channel_mem()) - memory_params->MemorySpdPtr10 = spd_data; - - mainboard_print_spd_info((uint8_t *)spd_data); -} diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index 8bc7336470..c6e47f084f 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -54,7 +54,6 @@ static inline int get_spd_index(void) { }; return (gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios))); } -void spd_memory_init_params(MEMORY_INIT_UPD *memory_params); void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1); void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig index 69bfde764f..e89d892631 100644 --- a/src/mainboard/intel/leafhill/Kconfig +++ b/src/mainboard/intel/leafhill/Kconfig @@ -53,7 +53,6 @@ config HAVE_IFD_BIN config ADD_FSP_BINARIES bool "Add FSP blobs" - depends on PLATFORM_USES_FSP2_0 default n config FSP_M_FILE diff --git a/src/mainboard/intel/leafhill/dsdt.asl b/src/mainboard/intel/leafhill/dsdt.asl index 48b24b9190..6fccf4917c 100644 --- a/src/mainboard/intel/leafhill/dsdt.asl +++ b/src/mainboard/intel/leafhill/dsdt.asl @@ -39,5 +39,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/intel/littleplains/acpi/platform.asl b/src/mainboard/intel/littleplains/acpi/platform.asl index 6ba95ce465..059cd740ff 100644 --- a/src/mainboard/intel/littleplains/acpi/platform.asl +++ b/src/mainboard/intel/littleplains/acpi/platform.asl @@ -14,44 +14,6 @@ * GNU General Public License for more details. */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _WAK method is called on system wakeup */ Method(_WAK,1) diff --git a/src/mainboard/intel/littleplains/dsdt.asl b/src/mainboard/intel/littleplains/dsdt.asl index 310ad04741..4aad8a8b15 100644 --- a/src/mainboard/intel/littleplains/dsdt.asl +++ b/src/mainboard/intel/littleplains/dsdt.asl @@ -31,6 +31,7 @@ DefinitionBlock( #include // Some generic macros + #include #include "acpi/platform.asl" // global NVS and variables @@ -49,5 +50,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/intel/minnow3/Kconfig b/src/mainboard/intel/minnow3/Kconfig index a787a2d571..2dea6b40cc 100644 --- a/src/mainboard/intel/minnow3/Kconfig +++ b/src/mainboard/intel/minnow3/Kconfig @@ -49,7 +49,6 @@ config HAVE_IFD_BIN config ADD_FSP_BINARIES bool "Add FSP blobs" - depends on PLATFORM_USES_FSP2_0 default n config FSP_M_FILE diff --git a/src/mainboard/intel/minnow3/dsdt.asl b/src/mainboard/intel/minnow3/dsdt.asl index 48b24b9190..6fccf4917c 100644 --- a/src/mainboard/intel/minnow3/dsdt.asl +++ b/src/mainboard/intel/minnow3/dsdt.asl @@ -39,5 +39,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/intel/minnowmax/dsdt.asl b/src/mainboard/intel/minnowmax/dsdt.asl index 3719154bdd..bea6af7973 100644 --- a/src/mainboard/intel/minnowmax/dsdt.asl +++ b/src/mainboard/intel/minnowmax/dsdt.asl @@ -48,7 +48,7 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include #include "acpi/mainboard.asl" } diff --git a/src/mainboard/intel/mohonpeak/acpi/platform.asl b/src/mainboard/intel/mohonpeak/acpi/platform.asl index 6ba95ce465..059cd740ff 100644 --- a/src/mainboard/intel/mohonpeak/acpi/platform.asl +++ b/src/mainboard/intel/mohonpeak/acpi/platform.asl @@ -14,44 +14,6 @@ * GNU General Public License for more details. */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _WAK method is called on system wakeup */ Method(_WAK,1) diff --git a/src/mainboard/intel/mohonpeak/dsdt.asl b/src/mainboard/intel/mohonpeak/dsdt.asl index 310ad04741..4aad8a8b15 100644 --- a/src/mainboard/intel/mohonpeak/dsdt.asl +++ b/src/mainboard/intel/mohonpeak/dsdt.asl @@ -31,6 +31,7 @@ DefinitionBlock( #include // Some generic macros + #include #include "acpi/platform.asl" // global NVS and variables @@ -49,5 +50,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 934c15affd..315104e846 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -24,14 +24,12 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select INTEL_LPSS_UART_FOR_CONSOLE select SKYLAKE_SOC_PCH_H select SOC_INTEL_SKYLAKE select SUPERIO_NUVOTON_NCT6776 select SUPERIO_NUVOTON_NCT6776_COM_A select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION - select USE_INTEL_FSP_MP_INIT config IRQ_SLOT_COUNT int diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 3322bf8e42..7d7b58bd34 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -61,82 +61,75 @@ chip soc/intel/skylake register "serirq_mode" = "SERIRQ_CONTINUOUS" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x10, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x1C, \ - .voltage_limit = 0x5F0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, }" register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x88, \ - .voltage_limit = 0x5F0 \ - }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x88, \ - .voltage_limit = 0x5F0, \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x8C ,\ - .voltage_limit = 0x5F0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, }" register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x8C, \ - .voltage_limit = 0x5F0 \ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, }" # Enable x1 slot diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl index ac929a6bc4..86ea299aa9 100644 --- a/src/mainboard/intel/saddlebrook/dsdt.asl +++ b/src/mainboard/intel/saddlebrook/dsdt.asl @@ -43,7 +43,7 @@ DefinitionBlock( } // Chipset specific sleep states - #include + #include // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/saddlebrook/ramstage.c b/src/mainboard/intel/saddlebrook/ramstage.c index 42477e6ef3..ed37681822 100644 --- a/src/mainboard/intel/saddlebrook/ramstage.c +++ b/src/mainboard/intel/saddlebrook/ramstage.c @@ -16,7 +16,7 @@ #include #include "gpio.h" -void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +void mainboard_silicon_init_params(FSP_SIL_UPD *params) { /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 46c2cdd6e0..8e280de638 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -17,7 +17,6 @@ #include #include -#include #include #include #include @@ -25,10 +24,10 @@ #include -void mainboard_memory_init_params( - struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) +void mainboard_memory_init_params(FSPM_UPD *mupd) { + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + struct spd_block blk = { .addr_map = { 0x50, 0x52, }, }; @@ -37,26 +36,22 @@ void mainboard_memory_init_params( dump_spd_info(&blk); printk(BIOS_SPEW, "spd block length: 0x%08x\n", blk.len); - memory_params->MemorySpdPtr00 = (UINT32) blk.spd_array[0]; - memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[1]; - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", - memory_params->MemorySpdPtr00); - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", - memory_params->MemorySpdPtr10); + mem_cfg->MemorySpdPtr00 = (UINT32) blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (UINT32) blk.spd_array[1]; + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", mem_cfg->MemorySpdPtr00); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", mem_cfg->MemorySpdPtr10); /* * Configure the DQ/DQS settings if required. In general the settings * should be set in the FSP flash image and should not need to be * changed. */ - mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0, - &memory_params->DqByteMapCh1); - mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0, - &memory_params->DqsMapCpu2DramCh1); - mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); - mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); /* update spd length*/ - memory_params->MemorySpdDataLen = blk.len; - memory_params->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->DqPinsInterleaved = TRUE; } diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl index 5052ba265c..e89b88797f 100644 --- a/src/mainboard/intel/strago/dsdt.asl +++ b/src/mainboard/intel/strago/dsdt.asl @@ -58,7 +58,7 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include #include "acpi/mainboard.asl" } diff --git a/src/mainboard/intel/wtm2/acpi/platform.asl b/src/mainboard/intel/wtm2/acpi/platform.asl index 270464e6bd..b510fc13b2 100644 --- a/src/mainboard/intel/wtm2/acpi/platform.asl +++ b/src/mainboard/intel/wtm2/acpi/platform.asl @@ -14,44 +14,6 @@ * GNU General Public License for more details. */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index 42fd7eab95..d3febf511e 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -26,6 +26,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + #include // Some generic macros #include "acpi/platform.asl" @@ -53,7 +54,7 @@ DefinitionBlock( #include // Chipset specific sleep states - #include + #include // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c index a7c65365b8..7d9096c804 100644 --- a/src/mainboard/intel/wtm2/fadt.c +++ b/src/mainboard/intel/wtm2/fadt.c @@ -24,7 +24,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 5; + header->revision = ACPI_FADT_REV_ACPI_5_0; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index 0e9217daec..ce16815327 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -20,7 +20,6 @@ #include #include #include -#include #include void mainboard_suspend_resume(void) diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index f4e336694d..9edc170a21 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -16,7 +16,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/jetway/pa78vm5/acpi/cpstate.asl b/src/mainboard/jetway/pa78vm5/acpi/cpstate.asl index 206dd686f5..acaa5bae32 100644 --- a/src/mainboard/jetway/pa78vm5/acpi/cpstate.asl +++ b/src/mainboard/jetway/pa78vm5/acpi/cpstate.asl @@ -22,17 +22,25 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/jetway/pa78vm5/dsdt.asl b/src/mainboard/jetway/pa78vm5/dsdt.asl index 4da6035532..89120c7b02 100644 --- a/src/mainboard/jetway/pa78vm5/dsdt.asl +++ b/src/mainboard/jetway/pa78vm5/dsdt.asl @@ -58,39 +58,24 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - CPU0, /* name space name */ - 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "acpi/cpstate.asl" } - - Processor( - CPU1, /* name space name */ - 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "acpi/cpstate.asl" } - - Processor( - CPU2, /* name space name */ - 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "acpi/cpstate.asl" } - - Processor( - CPU3, /* name space name */ - 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/kontron/986lcd-m/dsdt.asl b/src/mainboard/kontron/986lcd-m/dsdt.asl index c412c4e2ff..d4ffd7ba4c 100644 --- a/src/mainboard/kontron/986lcd-m/dsdt.asl +++ b/src/mainboard/kontron/986lcd-m/dsdt.asl @@ -46,5 +46,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index 85b704e3dd..b3e84278a3 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -20,23 +20,12 @@ #include #include #include -#include +#include /* Hardware Monitor */ static u16 hwm_base = 0xa00; -static void hwm_write(u8 reg, u8 value) -{ - outb(reg, hwm_base + 0x05); - outb(value, hwm_base + 0x06); -} - -static void hwm_bank(u8 bank) -{ - hwm_write(0x4e, bank); -} - #define FAN_CRUISE_CONTROL_DISABLED 0 #define FAN_CRUISE_CONTROL_SPEED 1 #define FAN_CRUISE_CONTROL_THERMAL 2 @@ -86,16 +75,16 @@ static void hwm_setup(void) sysfan_speed = FAN_SPEED_5625; get_option(&sysfan_speed, "sysfan_speed"); - hwm_bank(0); - hwm_write(0x59, 0x20); /* Diode Selection */ - hwm_write(0x5d, 0x0f); /* All Sensors Diode, not Thermistor */ + pnp_write_hwm5_index(hwm_base, 0x4e, 0); + pnp_write_hwm5_index(hwm_base, 0x59, 0x20); /* Diode Selection */ + pnp_write_hwm5_index(hwm_base, 0x5d, 0x0f); /* All Sensors Diode, not Thermistor */ - hwm_bank(4); - hwm_write(0x54, 0xf1); /* SYSTIN temperature offset */ - hwm_write(0x55, 0x19); /* CPUTIN temperature offset */ - hwm_write(0x56, 0xfc); /* AUXTIN temperature offset */ + pnp_write_hwm5_index(hwm_base, 0x4e, 4); + pnp_write_hwm5_index(hwm_base, 0x54, 0xf1); /* SYSTIN temperature offset */ + pnp_write_hwm5_index(hwm_base, 0x55, 0x19); /* CPUTIN temperature offset */ + pnp_write_hwm5_index(hwm_base, 0x56, 0xfc); /* AUXTIN temperature offset */ - hwm_bank(0x80); /* Default */ + pnp_write_hwm5_index(hwm_base, 0x4e, 0x80); /* Default */ u8 fan_config = 0; /* 00 FANOUT is Manual Mode */ @@ -110,43 +99,45 @@ static void hwm_setup(void) case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; } /* This register must be written first */ - hwm_write(0x04, fan_config); + pnp_write_hwm5_index(hwm_base, 0x04, fan_config); switch (cpufan_control) { - case FAN_CRUISE_CONTROL_SPEED: + case FAN_CRUISE_CONTROL_SPEED: /* CPUFANIN target speed */ printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", fan_speeds[cpufan_speed].fan_speed); - hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); /* CPUFANIN target speed */ + pnp_write_hwm5_index(hwm_base, 0x06, fan_speeds[cpufan_speed].fan_in); break; - case FAN_CRUISE_CONTROL_THERMAL: + case FAN_CRUISE_CONTROL_THERMAL: /* CPUFANIN target temperature */ printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", temperatures[cpufan_temperature].deg_celsius, temperatures[cpufan_temperature].deg_fahrenheit); - hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); /* CPUFANIN target temperature */ + pnp_write_hwm5_index(hwm_base, 0x06, + temperatures[cpufan_temperature].deg_celsius); break; } switch (sysfan_control) { - case FAN_CRUISE_CONTROL_SPEED: + case FAN_CRUISE_CONTROL_SPEED: /* SYSFANIN target speed */ printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", fan_speeds[sysfan_speed].fan_speed); - hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); /* SYSFANIN target speed */ + pnp_write_hwm5_index(hwm_base, 0x05, fan_speeds[sysfan_speed].fan_in); break; - case FAN_CRUISE_CONTROL_THERMAL: + case FAN_CRUISE_CONTROL_THERMAL: /* SYSFANIN target temperature */ printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", temperatures[sysfan_temperature].deg_celsius, temperatures[sysfan_temperature].deg_fahrenheit); - hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); /* SYSFANIN target temperature */ + pnp_write_hwm5_index(hwm_base, 0x05, + temperatures[sysfan_temperature].deg_celsius); break; } - hwm_write(0x0e, 0x02); /* Fan Output Step Down Time */ - hwm_write(0x0f, 0x02); /* Fan Output Step Up Time */ + pnp_write_hwm5_index(hwm_base, 0x0e, 0x02); /* Fan Output Step Down Time */ + pnp_write_hwm5_index(hwm_base, 0x0f, 0x02); /* Fan Output Step Up Time */ - hwm_write(0x47, 0xaf); /* FAN divisor register */ - hwm_write(0x4b, 0x84); /* AUXFANIN speed divisor */ + pnp_write_hwm5_index(hwm_base, 0x47, 0xaf); /* FAN divisor register */ + pnp_write_hwm5_index(hwm_base, 0x4b, 0x84); /* AUXFANIN speed divisor */ - hwm_write(0x40, 0x01); /* Init, but no SMI# */ + pnp_write_hwm5_index(hwm_base, 0x40, 0x01); /* Init, but no SMI# */ } /* mainboard_enable is executed as first thing after */ diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index cee7c2a603..189406225c 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include @@ -193,12 +192,12 @@ static void early_ich7_init(void) uint32_t reg32; /* program secondary mlt XXX byte? */ - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); /* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); /* usb transient disconnect */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); @@ -213,31 +212,7 @@ static void early_ich7_init(void) reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - /* next step only on ich7m b0 and later: */ - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) @@ -246,11 +221,6 @@ void mainboard_romstage_entry(void) enable_lapic(); - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0); - ich7_enable_lpc(); early_superio_config_w83627thg(); diff --git a/src/mainboard/kontron/ktqm77/dsdt.asl b/src/mainboard/kontron/ktqm77/dsdt.asl index f0dd7eee2c..2d6ce7953b 100644 --- a/src/mainboard/kontron/ktqm77/dsdt.asl +++ b/src/mainboard/kontron/ktqm77/dsdt.asl @@ -24,7 +24,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/platform.asl" @@ -52,5 +52,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 675cb05003..50a7b6be08 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -24,7 +24,6 @@ #endif #include #include -#include #include #if CONFIG(VGA_ROM_RUN) @@ -166,7 +165,7 @@ static void mainboard_enable(struct device *dev) mainboard_interrupt_handlers(0x15, &int15_handler); #endif - unsigned disable = 0; + unsigned int disable = 0; if ((get_option(&disable, "ethernet1") == CB_SUCCESS) && disable) { struct device *nic = pcidev_on_root(0x1c, 2); if (nic) { diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c index 08de04e4ca..0d44397be5 100644 --- a/src/mainboard/lenovo/g505s/mptable.c +++ b/src/mainboard/lenovo/g505s/mptable.c @@ -39,7 +39,7 @@ u8 intr_data[0x54] = { 0x10,0x11,0x12,0x13 }; -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; mc->mpc_entry_count++; diff --git a/src/mainboard/lenovo/l520/dsdt.asl b/src/mainboard/lenovo/l520/dsdt.asl index ecd8f27bd3..8b2c3e6005 100644 --- a/src/mainboard/lenovo/l520/dsdt.asl +++ b/src/mainboard/lenovo/l520/dsdt.asl @@ -30,10 +30,10 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c index 426ac4e6fa..82f63776d9 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/romstage.c @@ -24,11 +24,6 @@ void pch_enable_lpc(void) { - /* EC Decode Range Port60/64, Port62/66 */ - /* Enable EC, PS/2 Keyboard/Mouse, LPT */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - LPT_LPC_EN); } void mainboard_rcba_config(void) diff --git a/src/mainboard/lenovo/s230u/dsdt.asl b/src/mainboard/lenovo/s230u/dsdt.asl index cc9b7aab09..01bb91f376 100644 --- a/src/mainboard/lenovo/s230u/dsdt.asl +++ b/src/mainboard/lenovo/s230u/dsdt.asl @@ -30,9 +30,9 @@ DefinitionBlock( #include "acpi/platform.asl" #include "acpi/gpe.asl" #include - #include + #include #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index dd8fc17268..754c49aa4f 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -29,7 +29,6 @@ void pch_enable_lpc(void) { - pci_write_config16(PCH_LPC_DEV, LPC_EN, MC_LPC_EN | KBC_LPC_EN); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); /* Memory map KB9012 EC registers */ diff --git a/src/mainboard/lenovo/s230u/smihandler.c b/src/mainboard/lenovo/s230u/smihandler.c index 3c4df31f08..668fe697dd 100644 --- a/src/mainboard/lenovo/s230u/smihandler.c +++ b/src/mainboard/lenovo/s230u/smihandler.c @@ -32,23 +32,6 @@ /* FIXME: check this */ #define GPE_EC_WAKE 13 -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); -} - -int mainboard_io_trap_handler(int smif) -{ - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - - return 0; -} - enum sleep_states { S0 = 0, S1 = 1, diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 2caf1d3b65..8d286c442b 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -28,6 +28,24 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_USES_IFD_GBE_REGION if !BOARD_LENOVO_R500 select INTEL_GMA_HAVE_VBT +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x82 + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + config MAINBOARD_DIR string default lenovo/t400 diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc index d0ee1537f4..b3ca78d2de 100644 --- a/src/mainboard/lenovo/t400/Makefile.inc +++ b/src/mainboard/lenovo/t400/Makefile.inc @@ -13,7 +13,8 @@ ## GNU General Public License for more details. ## -romstage-y += dock.c +bootblock-y += bootblock.c +bootblock-y += dock.c subdirs-y += variants/$(VARIANT_DIR)/ diff --git a/src/mainboard/lenovo/t400/bootblock.c b/src/mainboard/lenovo/t400/bootblock.c new file mode 100644 index 0000000000..c9f3cf6b5b --- /dev/null +++ b/src/mainboard/lenovo/t400/bootblock.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "dock.h" + +static int dock_err; + +void bootblock_mainboard_early_init(void) +{ + /* Minimal setup to detect dock */ + dock_err = pc87382_early(); + if (dock_err == 0) + dock_connect(); +} + +void bootblock_mainboard_init(void) +{ + /* Console is not yet initialized in bootblock_mainboard_early_init, + so we print the dock information here */ + if (dock_err) + printk(BIOS_ERR, "DOCK: Failed to init pc87382\n"); + else + dock_info(); +} diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 62072dce8f..9ab29b4ed1 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -88,6 +88,9 @@ entries # RAM initialization internal data 1024 128 r 0 read_training_results +# VBOOT +1152 128 r 0 vbnv + # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index b4c2ea89b1..9561dfa93f 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -75,6 +75,9 @@ chip northbridge/intel/gm45 # Maybe we should set less for Mini PCIe. register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" + register "gen3_dec" = "0x001c1681" device pci 19.0 on end # LAN device pci 1a.0 on # UHCI diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl index 6aafec69c4..eb9c2adf53 100644 --- a/src/mainboard/lenovo/t400/dsdt.asl +++ b/src/mainboard/lenovo/t400/dsdt.asl @@ -53,7 +53,7 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include /* Hybrid graphics support code */ #include "acpi/graphics.asl" diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 1b763188e8..4b0a4c7352 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -14,15 +14,10 @@ * GNU General Public License for more details. */ -#include #include -#include #include #include #include -#include "dock.h" - -#define LPC_DEV PCI_DEV(0, 0x1f, 0) static void hybrid_graphics_init(sysinfo_t *sysinfo) { @@ -34,30 +29,6 @@ static void hybrid_graphics_init(sysinfo_t *sysinfo) sysinfo->enable_peg = peg; } -static int dock_err; - -void mb_setup_lpc(void) -{ - /* Set up SuperIO LPC forwards */ - - /* Configure serial IRQs.*/ - pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0); - /* Map COMa on 0x3f8, COMb on 0x2f8. */ - pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); - pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3f0f); - pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x7c1601); - pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xc15e1); - pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681); -} - -void mb_setup_superio(void) -{ - /* Minimal setup to detect dock */ - dock_err = pc87382_early(); - if (dock_err == 0) - dock_connect(); -} - void get_mb_spd_addrmap(u8 *spd_addrmap) { spd_addrmap[0] = 0x50; @@ -66,13 +37,6 @@ void get_mb_spd_addrmap(u8 *spd_addrmap) void mb_pre_raminit_setup(sysinfo_t *sysinfo) { - /* Console is not yet initialized in mb_setup_superio, so we print - the dock information here */ - if (dock_err) - printk(BIOS_ERR, "DOCK: Failed to init pc87382\n"); - else - dock_info(); - if (CONFIG(BOARD_LENOVO_R500)) { int use_integrated = get_gpio(21); printk(BIOS_DEBUG, "R500 variant found with an %s GPU\n", diff --git a/src/mainboard/lenovo/t400/vboot-rwa.fmd b/src/mainboard/lenovo/t400/vboot-rwa.fmd new file mode 100644 index 0000000000..4af3fcd2d6 --- /dev/null +++ b/src/mainboard/lenovo/t400/vboot-rwa.fmd @@ -0,0 +1,26 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x600000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x5f5000 + SI_GBE@0x5f6000 0x2000 + SI_PD@0x5f8000 0x8000 + } + SI_BIOS@0x600000 0x200000 { + RW_SECTION_A 0x100000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + RW_VPD(PRESERVE) 0x1000 + CONSOLE 0x10000 + SMMSTORE(PRESERVE) 0x40000 + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig new file mode 100644 index 0000000000..329d08de26 --- /dev/null +++ b/src/mainboard/lenovo/t410/Kconfig @@ -0,0 +1,69 @@ +if BOARD_LENOVO_T410 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_LAPTOP + select NORTHBRIDGE_INTEL_NEHALEM + select SOUTHBRIDGE_INTEL_IBEXPEAK + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select NO_UART_ON_SUPERIO + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select INTEL_INT15 + select HAVE_ACPI_RESUME + select DRIVERS_LENOVO_WACOM + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select DRIVERS_LENOVO_HYBRID_GRAPHICS + select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION + select H8_HAS_BAT_TRESHOLDS_IMPL + select MAINBOARD_HAS_LIBGFXINIT + +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + +config MAINBOARD_DIR + string + default lenovo/t410 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad T410" + +config USBDEBUG_HCD_INDEX + int + default 2 + +config MAX_CPUS + int + default 8 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config DRAM_RESET_GATE_GPIO + int + default 10 + +endif diff --git a/src/mainboard/lenovo/t410/Kconfig.name b/src/mainboard/lenovo/t410/Kconfig.name new file mode 100644 index 0000000000..d79cf3910a --- /dev/null +++ b/src/mainboard/lenovo/t410/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_T410 + bool "ThinkPad T410" diff --git a/src/mainboard/lenovo/z61t/Makefile.inc b/src/mainboard/lenovo/t410/Makefile.inc similarity index 81% rename from src/mainboard/lenovo/z61t/Makefile.inc rename to src/mainboard/lenovo/t410/Makefile.inc index f646af8fd5..518d91a2b6 100644 --- a/src/mainboard/lenovo/z61t/Makefile.inc +++ b/src/mainboard/lenovo/t410/Makefile.inc @@ -13,6 +13,12 @@ ## GNU General Public License for more details. ## +bootblock-y += early_init.c + smm-y += dock.c +smm-y += smihandler.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + romstage-y += dock.c +ramstage-y += dock.c romstage-y += gpio.c diff --git a/src/mainboard/lenovo/z61t/acpi/dock.asl b/src/mainboard/lenovo/t410/acpi/dock.asl similarity index 59% rename from src/mainboard/lenovo/z61t/acpi/dock.asl rename to src/mainboard/lenovo/t410/acpi/dock.asl index 5085b29fb3..2bba82141c 100644 --- a/src/mainboard/lenovo/z61t/acpi/dock.asl +++ b/src/mainboard/lenovo/t410/acpi/dock.asl @@ -14,17 +14,8 @@ * GNU General Public License for more details. */ -#include "smi.h" - Scope (\_SB) { - OperationRegion (DLPC, SystemIO, 0x164c, 1) - Field(DLPC, ByteAcc, NoLock, Preserve) - { - , 3, - DSTA, 1, - } - Device(DOCK) { Name(_HID, "ACPI0003") @@ -34,60 +25,48 @@ Scope (\_SB) Method(_DCK, 1, NotSerialized) { if (Arg0) { - Sleep(250) /* connect dock */ - TRAP(SMI_DOCK_CONNECT) + Store (1, \GP28) + Store (1, \_SB.PCI0.LPCB.EC.DKR1) + Store (1, \_SB.PCI0.LPCB.EC.DKR2) + Store (1, \_SB.PCI0.LPCB.EC.DKR3) } else { /* disconnect dock */ - TRAP(SMI_DOCK_DISCONNECT) + Store (0, \GP28) + Store (0, \_SB.PCI0.LPCB.EC.DKR1) + Store (0, \_SB.PCI0.LPCB.EC.DKR2) + Store (0, \_SB.PCI0.LPCB.EC.DKR3) } - - Xor(Arg0, DSTA, Local0) + Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0) Return (Local0) } Method(_STA, 0, NotSerialized) { - Return (DSTA) + Return (\_SB.PCI0.LPCB.EC.DKR1) } } } Scope(\_SB.PCI0.LPCB.EC) { - OperationRegion(PMH7, SystemIO, 0x15e0, 0x10) - Field(PMH7, ByteAcc, NoLock, Preserve) - { - Offset(0x0c), - PIDX, 8, - Offset(0x0e), - PDAT, 8, - } - - IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) - { - Offset (0x61), - DPWR, 1, - } - Method(_Q18, 0, NotSerialized) { - Notify(\_SB.DOCK, 3) + Notify(\_SB.DOCK, 3) + } + + Method(_Q45, 0, NotSerialized) + { + Notify(\_SB.DOCK, 3) + } + + Method(_Q58, 0, NotSerialized) + { + Notify(\_SB.DOCK, 0) } Method(_Q37, 0, NotSerialized) { - if (DPWR) { - Notify(\_SB.DOCK, 0) - } else { - Notify(\_SB.DOCK, 3) - } - } - - Method(_Q50, 0, NotSerialized) - { - if (\_SB.DOCK._STA()) { - Notify(\_SB.DOCK, 1) - } + Notify(\_SB.DOCK, 0) } } diff --git a/src/mainboard/lenovo/z61t/acpi/ec.asl b/src/mainboard/lenovo/t410/acpi/ec.asl similarity index 86% rename from src/mainboard/lenovo/z61t/acpi/ec.asl rename to src/mainboard/lenovo/t410/acpi/ec.asl index fe7115aa77..c00121bab5 100644 --- a/src/mainboard/lenovo/z61t/acpi/ec.asl +++ b/src/mainboard/lenovo/t410/acpi/ec.asl @@ -15,3 +15,6 @@ */ #include + +#define H8_BAT_THRESHOLDS_BIT7 +#include diff --git a/src/mainboard/lenovo/z61t/acpi/gpe.asl b/src/mainboard/lenovo/t410/acpi/gpe.asl similarity index 97% rename from src/mainboard/lenovo/z61t/acpi/gpe.asl rename to src/mainboard/lenovo/t410/acpi/gpe.asl index 3cc25b2d85..5c900ca3a9 100644 --- a/src/mainboard/lenovo/z61t/acpi/gpe.asl +++ b/src/mainboard/lenovo/t410/acpi/gpe.asl @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include "smi.h" Scope (\_GPE) { Method(_L18, 0, NotSerialized) diff --git a/src/mainboard/lenovo/z61t/acpi/platform.asl b/src/mainboard/lenovo/t410/acpi/platform.asl similarity index 51% rename from src/mainboard/lenovo/z61t/acpi/platform.asl rename to src/mainboard/lenovo/t410/acpi/platform.asl index f9e991b984..c2cb94c242 100644 --- a/src/mainboard/lenovo/z61t/acpi/platform.asl +++ b/src/mainboard/lenovo/t410/acpi/platform.asl @@ -32,53 +32,21 @@ Method(_WAK,1) /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - // CPU specific part - - // Notify PCI Express slots in case a card - // was inserted while a sleep state was active. - - // Are we going to S3? - If (LEqual(Arg0, 3)) { - // .. - } - - // Are we going to S4? - If (LEqual(Arg0, 4)) { - // .. - } - - // TODO: Windows XP SP2 P-State restore - + /* Not implemented. */ Return(Package(){0,0}) } -/* System Bus */ - -Scope(\_SB) +Method(UCMS, 1, Serialized) { - /* This method is placed on the top level, so we can make sure it's the - * first executed _INI method. - */ - Method(_INI, 0) + Switch(ToInteger(Arg0)) { - /* The DTS data in NVS is probably not up to date. - * Update temperature values and make sure AP thermal - * interrupts can happen - */ - - // TRAP(71) // TODO - - \GOS() - - /* And the OS workarounds start right after we know what we're - * running: Windows XP SP1 needs to have C-State coordination - * enabled in SMM. - */ - If (LAnd(LEqual(OSYS, 2001), MPEN)) { - // TRAP(61) // TODO + Case (0x0c) /* Turn on ThinkLight */ + { + \_SB.PCI0.LPCB.EC.LGHT(1) + } + Case (0x0d) /* Turn off ThinkLight */ + { + \_SB.PCI0.LPCB.EC.LGHT(0) } - - /* SMM power state and C4-on-C3 settings need to be updated */ - // TRAP(43) // TODO } } diff --git a/src/mainboard/lenovo/t410/acpi/superio.asl b/src/mainboard/lenovo/t410/acpi/superio.asl new file mode 100644 index 0000000000..f2b35ba9c1 --- /dev/null +++ b/src/mainboard/lenovo/t410/acpi/superio.asl @@ -0,0 +1 @@ +#include diff --git a/src/mainboard/lenovo/z61t/acpi_tables.c b/src/mainboard/lenovo/t410/acpi_tables.c similarity index 75% rename from src/mainboard/lenovo/z61t/acpi_tables.c rename to src/mainboard/lenovo/t410/acpi_tables.c index bd10a0e3fb..2a8d9350e9 100644 --- a/src/mainboard/lenovo/z61t/acpi_tables.c +++ b/src/mainboard/lenovo/t410/acpi_tables.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -14,21 +15,14 @@ * GNU General Public License for more details. */ -#include -#include +#include #include "thermal.h" -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; -} - void acpi_create_gnvs(global_nvs_t *gnvs) { - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; - acpi_update_thermal_table(gnvs); + /* the lid is open by default. */ + gnvs->lids = 1; } diff --git a/src/mainboard/lenovo/t410/board_info.txt b/src/mainboard/lenovo/t410/board_info.txt new file mode 100644 index 0000000000..f27808b855 --- /dev/null +++ b/src/mainboard/lenovo/t410/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-8 / WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2010 diff --git a/src/mainboard/lenovo/z61t/cmos.default b/src/mainboard/lenovo/t410/cmos.default similarity index 64% rename from src/mainboard/lenovo/z61t/cmos.default rename to src/mainboard/lenovo/t410/cmos.default index af865f16da..5fbc86f742 100644 --- a/src/mainboard/lenovo/z61t/cmos.default +++ b/src/mainboard/lenovo/t410/cmos.default @@ -1,18 +1,17 @@ boot_option=Fallback debug_level=Debug +power_on_after_fail=Disable nmi=Enable -boot_devices='' -boot_default=0x41 -cmos_defaults_loaded=Yes -lpt=Enable -touchpad=Enable -volume=0x3 first_battery=Primary bluetooth=Enable -wlan=Enable wwan=Enable +wlan=Enable +touchpad=Enable trackpoint=Enable +fn_ctrl_swap=Disable sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable -gfx_uma_size=8M +sata_mode=AHCI +hybrid_graphics_mode=Integrated Only +usb_always_on=Disable diff --git a/src/mainboard/lenovo/z61t/cmos.layout b/src/mainboard/lenovo/t410/cmos.layout similarity index 52% rename from src/mainboard/lenovo/z61t/cmos.layout rename to src/mainboard/lenovo/t410/cmos.layout index 75ad42760c..5c7defa839 100644 --- a/src/mainboard/lenovo/z61t/cmos.layout +++ b/src/mainboard/lenovo/t410/cmos.layout @@ -1,18 +1,18 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2007-2008 coresystems GmbH -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2013 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## # ----------------------------------------------------------------- entries @@ -44,56 +44,47 @@ entries # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? +#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console +#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused +#399 1 r 0 unused #400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi -#409 2 e 7 power_on_after_fail +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 power_management_beeps +420 1 e 1 low_battery_beep +421 1 e 9 sata_mode +422 2 e 11 usb_always_on +#423 1 r 1 unused # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +424 3 e 10 gfx_uma_size +#427 5 r 0 unused +432 2 e 12 hybrid_graphics_mode -# coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt -#938 7 r 0 unused - -# coreboot config options: cpu -#945 3 r 0 unused - -# coreboot config options: ec -948 1 e 1 touchpad -949 1 e 1 bluetooth -950 1 e 1 wwan -951 1 e 1 wlan -952 8 h 0 volume -960 1 e 9 first_battery -961 1 e 1 trackpoint -#962 1 r 0 unused -963 1 e 1 sticky_fn -964 1 e 1 power_management_beeps -965 1 e 1 low_battery_beep +# VBOOT +448 128 r 0 vbnv # coreboot config options: check sums 984 16 h 0 check_sum #1000 24 r 0 amd_reserved -# RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 - # ----------------------------------------------------------------- enumerations @@ -117,19 +108,23 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep -8 0 No -8 1 Yes -9 0 Secondary -9 1 Primary -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 32M +10 1 48M +10 2 64M +10 3 128M +10 5 96M +10 6 160M +11 0 Disable +11 1 AC and battery +11 2 AC only +12 0 Integrated Only +12 1 Discrete Only # ----------------------------------------------------------------- checksums -checksum 392 983 984 +checksum 392 447 984 diff --git a/src/mainboard/lenovo/t410/data.vbt b/src/mainboard/lenovo/t410/data.vbt new file mode 100644 index 0000000000..908234e9aa Binary files /dev/null and b/src/mainboard/lenovo/t410/data.vbt differ diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb new file mode 100644 index 0000000000..808e05759e --- /dev/null +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -0,0 +1,198 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/nehalem + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable Panel as LVDS and configure power delays + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "1" + register "gpu_panel_power_up_delay" = "1" + register "gpu_panel_power_down_delay" = "600" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_cpu_backlight" = "0x58d" + register "gpu_pch_backlight" = "0x061a061a" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.link_frequency_270_mhz" = "1" + + device cpu_cluster 0 on + chip cpu/intel/model_2065x + device lapic 0 on end + end + end + + register "pci_mmio_size" = "2048" + + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x17aa 0x2193 + end + device pci 01.0 on end # PEG + device pci 02.0 on # VGA controller + subsystemid 0x17aa 0x215a + end + chip southbridge/intel/ibexpeak + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi1_routing" = "2" + register "gpi13_routing" = "2" + + # 0:HDD Bay 1:ODD Bay 4:eSATA Combo Connector + register "sata_port_map" = "0x13" + + register "gpe0_en" = "0x20022046" + register "alt_gp_smi_en" = "0x0000" + register "gen1_dec" = "0x7c1601" # EC + register "gen2_dec" = "0x0c15e1" # PMH7 + register "gen3_dec" = "0x1c1681" # EC ? + register "gen4_dec" = "0x040069" # ? + + register "c2_latency" = "1" + register "docking_supported" = "1" + + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + + device pci 16.0 off end # MEI + device pci 16.2 on # IDE/SATA + subsystemid 0x17aa 0x2161 + end + + device pci 19.0 on # Ethernet + subsystemid 0x17aa 0x2153 + end + + device pci 1a.0 on # USB2 EHCI + subsystemid 0x17aa 0x2163 + end + + device pci 1b.0 on # Audio Controller + subsystemid 0x17aa 0x215e + end + + device pci 1c.0 on end # PCIe Port #1 (wlan) + device pci 1c.1 off end # PCIe Port #2 (wwan) + device pci 1c.2 off end # PCIe Port #3 (wusb) + device pci 1c.3 on end # PCIe Port #4 (ExpressCard) + device pci 1c.4 on + subsystemid 0x17aa 0x2133 + chip drivers/ricoh/rce822 + register "sdwppol" = "1" + register "disable_mask" = "0x87" + device pci 00.0 on + subsystemid 0x17aa 0x2134 + end + end + end # PCIe Port #5 (Ricoh SD & FW) + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 Intel Gigabit Ethernet PHY (not PCIe) + + device pci 1d.0 on # USB2 EHCI + subsystemid 0x17aa 0x2163 + end + device pci 1f.0 on # PCI-LPC bridge + subsystemid 0x17aa 0x2166 + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/lenovo/pmh7 + device pnp ff.1 on end # dummy + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + end + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + register "config0" = "0xa6" + register "config1" = "0x05" + register "config2" = "0xa0" + register "config3" = "0xe0" + + register "beepmask0" = "0xfe" + register "beepmask1" = "0x96" + register "has_power_management_beeps" = "1" + + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xf4" + register "event5_enable" = "0x3c" + register "event6_enable" = "0x87" + register "event7_enable" = "0x89" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventa_enable" = "0x83" + register "eventb_enable" = "0x00" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x2d" + end + chip drivers/lenovo/hybrid_graphics + device pnp ff.f on end # dummy + + register "detect_gpio" = "21" + + register "has_panel_hybrid_gpio" = "1" + register "panel_hybrid_gpio" = "52" + register "panel_integrated_lvl" = "1" + + register "has_backlight_gpio" = "1" + register "backlight_gpio" = "50" + register "backlight_integrated_lvl" = "0" + + register "has_dgpu_power_gpio" = "1" + register "dgpu_power_gpio" = "49" + register "dgpu_power_off_lvl" = "0" + + register "has_thinker1" = "1" + end + end + device pci 1f.2 on # IDE/SATA + subsystemid 0x17aa 0x2168 + end + device pci 1f.3 on # SMBUS + subsystemid 0x17aa 0x2167 + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end + device pci 1f.6 on # Thermal Subsystem + subsystemid 0x17aa 0x2190 + end + end + end +end diff --git a/src/mainboard/lenovo/x200/dock.c b/src/mainboard/lenovo/t410/dock.c similarity index 63% rename from src/mainboard/lenovo/x200/dock.c rename to src/mainboard/lenovo/t410/dock.c index d5f774bb48..317fb0513c 100644 --- a/src/mainboard/lenovo/x200/dock.c +++ b/src/mainboard/lenovo/t410/dock.c @@ -15,22 +15,14 @@ * GNU General Public License for more details. */ -#define __SIMPLE_DEVICE__ - #include -#include -#include #include -#include -#include +#include "dock.h" +#include #include #include -#include "dock.h" - -#define LPC_DEV PCI_DEV(0, 0x1f, 0) - -void h8_mainboard_init_dock (void) +void h8_mainboard_init_dock(void) { if (dock_present()) { printk(BIOS_DEBUG, "dock is connected\n"); @@ -41,22 +33,23 @@ void h8_mainboard_init_dock (void) void dock_connect(void) { - u16 gpiobase = pci_read_config16(LPC_DEV, D31F0_GPIO_BASE) & 0xfffc; + /* UNTESTED */ ec_set_bit(0x02, 0); - outl(inl(gpiobase + 0x0c) | (1 << 28), gpiobase + 0x0c); + ec_set_bit(0x1a, 0); + ec_set_bit(0xfe, 4); } void dock_disconnect(void) { - u16 gpiobase = pci_read_config16(LPC_DEV, D31F0_GPIO_BASE) & 0xfffc; + /* UNTESTED */ ec_clr_bit(0x02, 0); - outl(inl(gpiobase + 0x0c) & ~(1 << 28), gpiobase + 0x0c); + ec_clr_bit(0x1a, 0); + ec_clr_bit(0xfe, 4); } int dock_present(void) { - u16 gpiobase = pci_read_config16(LPC_DEV, D31F0_GPIO_BASE) & 0xfffc; - u8 st = inb(gpiobase + 0x0c); + const int gpio_num_array[] = {3, 4, 5, -1}; - return ((st >> 2) & 7) != 7; + return get_gpios(gpio_num_array) != 7; } diff --git a/src/mainboard/lenovo/x201/smi.h b/src/mainboard/lenovo/t410/dock.h similarity index 80% rename from src/mainboard/lenovo/x201/smi.h rename to src/mainboard/lenovo/t410/dock.h index 4e99db9520..4cd8c857a8 100644 --- a/src/mainboard/lenovo/x201/smi.h +++ b/src/mainboard/lenovo/t410/dock.h @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ -#ifndef MAINBOARD_LENOVO_X60_SMI_H -#define MAINBOARD_LENOVO_X60_SMI_H - -#define SMI_DOCK_CONNECT 0x01 -#define SMI_DOCK_DISCONNECT 0x02 +#ifndef THINKPAD_X201_DOCK_H +#define THINKPAD_X201_DOCK_H +void dock_connect(void); +void dock_disconnect(void); +int dock_present(void); #endif diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl new file mode 100644 index 0000000000..9d0204e5cc --- /dev/null +++ b/src/mainboard/lenovo/t410/dsdt.asl @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define THINKPAD_EC_GPE 17 +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20130325 /* OEM revision */ +) +{ + #include + + /* Some generic macros */ + #include "acpi/platform.asl" + + /* global NVS and variables */ + #include + + /* General Purpose Events */ + #include "acpi/gpe.asl" + + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + + #include + } + Device (UNCR) + { + Name (_BBN, 0xFF) + Name (RID, 0x00) + Name (_HID, EisaId ("PNP0A03")) + Name (_CRS, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* Granularity */ + 0x00FF, /* Range Minimum */ + 0x00FF, /* Range Maximum */ + 0x0000, /* Translation Offset */ + 0x0001, /* Length */ + ,, ) + }) + Device (SAD) + { + Name (_ADR, 0x01) + Name (RID, 0x00) + OperationRegion (SADC, PCI_Config, 0x00, 0x0100) + Field (SADC, DWordAcc, NoLock, Preserve) + { + Offset (0x40), + PAM0, 8, + PAM1, 8, + PAM2, 8, + PAM3, 8, + PAM4, 8, + PAM5, 8, + PAM6, 8 + } + } + } + } + + /* Chipset specific sleep states */ + #include + + /* Dock support code */ + #include "acpi/dock.asl" +} diff --git a/src/soc/intel/braswell/acpi/sleepstates.asl b/src/mainboard/lenovo/t410/early_init.c similarity index 69% rename from src/soc/intel/braswell/acpi/sleepstates.asl rename to src/mainboard/lenovo/t410/early_init.c index d37f9cc803..ba222f60d3 100644 --- a/src/soc/intel/braswell/acpi/sleepstates.asl +++ b/src/mainboard/lenovo/t410/early_init.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2019 Patrick Rudolph * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -14,7 +14,11 @@ * GNU General Public License for more details. */ -Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -Name(\_S3, Package(){0x5,0x5,0x0,0x0}) -Name(\_S4, Package(){0x6,0x6,0x0,0x0}) -Name(\_S5, Package(){0x7,0x7,0x0,0x0}) +#include +#include + +void bootblock_mainboard_early_init(void) +{ + /* Enable USB Power. We need to do it early for usbdebug to work. */ + ec_set_bit(0x3b, 4); +} diff --git a/src/mainboard/lenovo/t410/gma-mainboard.ads b/src/mainboard/lenovo/t410/gma-mainboard.ads new file mode 100644 index 0000000000..9c2a3cb369 --- /dev/null +++ b/src/mainboard/lenovo/t410/gma-mainboard.ads @@ -0,0 +1,30 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, -- DP++ connector on the dock + HDMI2, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t410/gpio.c b/src/mainboard/lenovo/t410/gpio.c new file mode 100644 index 0000000000..2eeeca5469 --- /dev/null +++ b/src/mainboard/lenovo/t410/gpio.c @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, /* DOCK0 */ + .gpio4 = GPIO_MODE_GPIO, /* DOCK1 */ + .gpio5 = GPIO_MODE_GPIO, /* DOCK2 */ + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, /* -SC_DTCT */ + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, /* -1394_DTCT */ + .gpio17 = GPIO_MODE_GPIO, /* DGFX_PWRGD */ + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio18 = GPIO_NO_BLINK, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_NATIVE, + .gpio34 = GPIO_MODE_NATIVE, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_GPIO, /* PLANARID0 */ + .gpio37 = GPIO_MODE_GPIO, /* PLANARID1 */ + .gpio38 = GPIO_MODE_GPIO, /* PLANARID2 */ + .gpio39 = GPIO_MODE_GPIO, /* PLANARID3 */ + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_GPIO, /* -MDC_KILL */ + .gpio42 = GPIO_MODE_GPIO, /* SMB_3B_EN */ + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, /* -BDC_PRESENCE */ + .gpio49 = GPIO_MODE_GPIO, /* GFX_PWR_EN_D */ + .gpio50 = GPIO_MODE_GPIO, /* BKLT_CTRL_SEL */ + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_GPIO, /* DISCRETE_ENABLE */ + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, /* DDC_MUX_SEL */ + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, /* -DEBUGCARD */ + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_NATIVE, + .gpio69 = GPIO_MODE_NATIVE, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .reset = &pch_gpio_set1_reset, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; diff --git a/src/mainboard/lenovo/t410/hda_verb.c b/src/mainboard/lenovo/t410/hda_verb.c new file mode 100644 index 0000000000..752e5da67b --- /dev/null +++ b/src/mainboard/lenovo/t410/hda_verb.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License, + * or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */ + 0x17AA214C, /* Subsystem ID */ + 0x0000000B, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(0x0, 0x17AA214C), + AZALIA_PIN_CFG(0x0, 0x19, 0x042110F0), + AZALIA_PIN_CFG(0x0, 0x1A, 0x61A190F0), + AZALIA_PIN_CFG(0x0, 0x1B, 0x04A110F0), + AZALIA_PIN_CFG(0x0, 0x1C, 0x612140F0), + AZALIA_PIN_CFG(0x0, 0x1D, 0x40F001F0), + AZALIA_PIN_CFG(0x0, 0x1E, 0x40F001F0), + AZALIA_PIN_CFG(0x0, 0x1F, 0x901701F0), + AZALIA_PIN_CFG(0x0, 0x20, 0x40F001F0), + AZALIA_PIN_CFG(0x0, 0x22, 0x40F001F0), + AZALIA_PIN_CFG(0x0, 0x23, 0x90A601F0), + + 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ + 0x17AA21B5, /* Subsystem ID */ + 0x00000004, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(0x3, 0x17AA21B5), + AZALIA_PIN_CFG(0x3, 0x04, 0x18560010), + AZALIA_PIN_CFG(0x3, 0x05, 0x18560020), + AZALIA_PIN_CFG(0x3, 0x06, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t410/mainboard.c b/src/mainboard/lenovo/t410/mainboard.c new file mode 100644 index 0000000000..23b68fabc2 --- /dev/null +++ b/src/mainboard/lenovo/t410/mainboard.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_LFP, 2); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/t410/romstage.c b/src/mainboard/lenovo/t410/romstage.c new file mode 100644 index 0000000000..7c796de8ee --- /dev/null +++ b/src/mainboard/lenovo/t410/romstage.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* Enabled, Current table lookup index, OC map */ + { 1, IF1_557, 0 }, + { 1, IF1_55F, 1 }, + { 1, IF1_74B, 3 }, + { 1, IF1_14B, 3 }, + { 1, IF1_14B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_55F, 4 }, + { 1, IF1_55F, 5 }, + { 1, IF1_74B, 7 }, + { 1, IF1_74B, 7 }, + { 1, IF1_557, 7 }, + { 1, IF1_55F, 7 }, +}; + +static void hybrid_graphics_init(void) +{ + bool peg, igd; + u32 reg32; + + early_hybrid_graphics(&igd, &peg); + + /* Hide disabled devices */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN); + reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); + + if (peg) + reg32 |= DEVEN_PEG10; + + if (igd) + reg32 |= DEVEN_IGD; + else + /* Disable IGD VGA decode, no GTT or GFX stolen */ + pci_write_config16(PCI_DEV(0, 0, 0), D0F0_GGC, 2); + + pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, reg32); +} + +void mainboard_pre_raminit(void) +{ + hybrid_graphics_init(); +} + +void mainboard_get_spd_map(u8 *spd_addrmap) +{ + spd_addrmap[0] = 0x50; + spd_addrmap[2] = 0x52; +} diff --git a/src/mainboard/lenovo/t410/smihandler.c b/src/mainboard/lenovo/t410/smihandler.c new file mode 100644 index 0000000000..91cb0ce2d6 --- /dev/null +++ b/src/mainboard/lenovo/t410/smihandler.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dock.h" + +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); + + switch (event) { + case 0x18: + /* Fn-F9 key */ + case 0x27: + /* Power loss */ + case 0x50: + /* Undock Key */ + ec_clr_bit(0x03, 2); + dock_disconnect(); + break; + case 0x37: + case 0x58: + /* Dock Event */ + ec_clr_bit(0x03, 2); + mdelay(250); + dock_connect(); + ec_set_bit(0x03, 2); + /* set dock LED to indicate status */ + ec_write(0x0c, 0x09); + ec_write(0x0c, 0x88); + break; + default: + break; + } +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route H8SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route H8SCI# to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +} diff --git a/src/mainboard/lenovo/z61t/thermal.h b/src/mainboard/lenovo/t410/thermal.h similarity index 80% rename from src/mainboard/lenovo/z61t/thermal.h rename to src/mainboard/lenovo/t410/thermal.h index 72953fd2c2..d8c94805b8 100644 --- a/src/mainboard/lenovo/z61t/thermal.h +++ b/src/mainboard/lenovo/t410/thermal.h @@ -1,11 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko * Copyright (C) 2016 Patrick Rudolph - * Copyright (C) 2017 James Ye * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t410/vboot-rwa.fmd b/src/mainboard/lenovo/t410/vboot-rwa.fmd new file mode 100644 index 0000000000..8f50d33fbb --- /dev/null +++ b/src/mainboard/lenovo/t410/vboot-rwa.fmd @@ -0,0 +1,31 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_SECTION_A 0x180000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE) 0x40000 + + WP_RO { + RO_VPD(PRESERVE) 0x1000 + RO_SECTION 0x11e000 { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl index 1cb4add847..a6a57e256e 100644 --- a/src/mainboard/lenovo/t420/dsdt.asl +++ b/src/mainboard/lenovo/t420/dsdt.asl @@ -31,7 +31,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/platform.asl" @@ -52,5 +52,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index ebf5aed0f1..e7851f3edb 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -51,11 +51,6 @@ static void hybrid_graphics_init(void) void pch_enable_lpc(void) { - /* EC Decode Range Port60/64, Port62/66 */ - /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl index 1cb4add847..a6a57e256e 100644 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ b/src/mainboard/lenovo/t420s/dsdt.asl @@ -31,7 +31,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/platform.asl" @@ -52,5 +52,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index 49de58d8d1..72cbcad245 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -51,11 +51,6 @@ static void hybrid_graphics_init(void) void pch_enable_lpc(void) { - /* EC Decode Range Port60/64, Port62/66 */ - /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl index 48e00767d1..55781d6b5f 100644 --- a/src/mainboard/lenovo/t430/dsdt.asl +++ b/src/mainboard/lenovo/t430/dsdt.asl @@ -34,10 +34,10 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c index 1f4b90d7f9..3caa443fe9 100644 --- a/src/mainboard/lenovo/t430/romstage.c +++ b/src/mainboard/lenovo/t430/romstage.c @@ -51,10 +51,6 @@ static void hybrid_graphics_init(void) void pch_enable_lpc(void) { - /* EC Decode Range Port60/64, Port62/66 */ - /* Enable TPM, EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | MC_LPC_EN | KBC_LPC_EN); } void mainboard_rcba_config(void) diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl index 1cb4add847..a6a57e256e 100644 --- a/src/mainboard/lenovo/t430s/dsdt.asl +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -31,7 +31,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/platform.asl" @@ -52,5 +52,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index e590bb6c67..34793d1301 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -21,11 +21,6 @@ void pch_enable_lpc(void) { - /* EC Decode Range Port60/64, Port62/66 */ - /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc b/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc index 4b9ef55007..72657b4c23 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc +++ b/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc @@ -22,7 +22,7 @@ SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/ $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/lenovo/t440p/Kconfig b/src/mainboard/lenovo/t440p/Kconfig new file mode 100644 index 0000000000..bf821f3d0c --- /dev/null +++ b/src/mainboard/lenovo/t440p/Kconfig @@ -0,0 +1,54 @@ +if BOARD_LENOVO_THINKPAD_T440P + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_12288 + select CPU_INTEL_HASWELL + select EC_LENOVO_H8 + select H8_HAS_PRIMARY_FN_KEYS + select EC_LENOVO_PMH7 + select NO_UART_ON_SUPERIO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + select MAINBOARD_USES_IFD_GBE_REGION + +config MAINBOARD_DIR + string + default lenovo/t440p + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad T440p" + +config VGA_BIOS_FILE + string + default "pci8086,0416.rom" + +config VGA_BIOS_ID + string + default "8086,0416" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config DRIVER_LENOVO_SERIALS + bool + default n + +endif diff --git a/src/mainboard/lenovo/t440p/Kconfig.name b/src/mainboard/lenovo/t440p/Kconfig.name new file mode 100644 index 0000000000..e90299d930 --- /dev/null +++ b/src/mainboard/lenovo/t440p/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKPAD_T440P + bool "ThinkPad T440p" diff --git a/src/mainboard/lenovo/t440p/Makefile.inc b/src/mainboard/lenovo/t440p/Makefile.inc new file mode 100644 index 0000000000..fa6e7af202 --- /dev/null +++ b/src/mainboard/lenovo/t440p/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +smm-y += smihandler.c diff --git a/src/soc/intel/icelake/acpi/sleepstates.asl b/src/mainboard/lenovo/t440p/acpi/ec.asl similarity index 58% rename from src/soc/intel/icelake/acpi/sleepstates.asl rename to src/mainboard/lenovo/t440p/acpi/ec.asl index 13cc3582aa..3ff0ff7cbc 100644 --- a/src/soc/intel/icelake/acpi/sleepstates.asl +++ b/src/mainboard/lenovo/t440p/acpi/ec.asl @@ -1,12 +1,11 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2019 Iru Cai * - * - * This program is free software; you can redistribute it and/or modify + * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or + * the Free Software Foundation, either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -15,6 +14,4 @@ * GNU General Public License for more details. */ -Name (\_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) -Name (\_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) -Name (\_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) +#include diff --git a/src/soc/intel/cannonlake/acpi/sleepstates.asl b/src/mainboard/lenovo/t440p/acpi/platform.asl similarity index 54% rename from src/soc/intel/cannonlake/acpi/sleepstates.asl rename to src/mainboard/lenovo/t440p/acpi/platform.asl index 2a351b6c99..db142f0e5b 100644 --- a/src/soc/intel/cannonlake/acpi/sleepstates.asl +++ b/src/mainboard/lenovo/t440p/acpi/platform.asl @@ -1,12 +1,11 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. + * Copyright (C) 2019 Iru Cai * - * - * This program is free software; you can redistribute it and/or modify + * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or + * the Free Software Foundation, either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -15,7 +14,15 @@ * GNU General Public License for more details. */ -Name (\_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) -Name (\_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) -Name (\_S4, Package () { 0x6, 0x6, 0x0, 0x0 }) -Name (\_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.RADI(0) +} diff --git a/src/superio/winbond/wpcd376i/chip.h b/src/mainboard/lenovo/t440p/acpi/superio.asl similarity index 55% rename from src/superio/winbond/wpcd376i/chip.h rename to src/mainboard/lenovo/t440p/acpi/superio.asl index c16743d483..3139e35be5 100644 --- a/src/superio/winbond/wpcd376i/chip.h +++ b/src/mainboard/lenovo/t440p/acpi/superio.asl @@ -1,12 +1,11 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2019 Iru Cai * - * This program is free software; you can redistribute it and/or modify + * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or + * the Free Software Foundation, either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -15,9 +14,4 @@ * GNU General Public License for more details. */ -#ifndef SUPERIO_WINBOND_WPCD376I_CHIP_H -#define SUPERIO_WINBOND_WPCD376I_CHIP_H - -struct superio_winbond_wpcd376i_config { -}; -#endif +#include diff --git a/src/mainboard/lenovo/z61t/acpi/video.asl b/src/mainboard/lenovo/t440p/acpi_tables.c similarity index 55% rename from src/mainboard/lenovo/z61t/acpi/video.asl rename to src/mainboard/lenovo/t440p/acpi_tables.c index 6db3a44c9e..6012708b28 100644 --- a/src/mainboard/lenovo/z61t/acpi/video.asl +++ b/src/mainboard/lenovo/t440p/acpi_tables.c @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2011 Sven Schnelle + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -14,19 +15,21 @@ * GNU General Public License for more details. */ -#include "smi.h" +#include -Scope (\) +void acpi_create_gnvs(global_nvs_t *gnvs) { - Method(BRTD, 0, NotSerialized) - { - Trap(SMI_BRIGHTNESS_DOWN) - \_SB.PCI0.GFX0.DECB() - } + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; - Method(BRTU, 0, NotSerialized) - { - Trap(SMI_BRIGHTNESS_UP) - \_SB.PCI0.GFX0.INCB() - } + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* the lid is open by default */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; } diff --git a/src/mainboard/lenovo/t440p/board_info.txt b/src/mainboard/lenovo/t440p/board_info.txt new file mode 100644 index 0000000000..46461fe7da --- /dev/null +++ b/src/mainboard/lenovo/t440p/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://pcsupport.lenovo.com/us/zh/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t440p +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2013 diff --git a/src/mainboard/lenovo/t440p/cmos.default b/src/mainboard/lenovo/t440p/cmos.default new file mode 100644 index 0000000000..b104ae145c --- /dev/null +++ b/src/mainboard/lenovo/t440p/cmos.default @@ -0,0 +1,13 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +volume=0x3 +first_battery=Primary +wlan=Enable +fn_ctrl_swap=Disable +f1_to_f12_as_primary=Enable +sticky_fn=Disable +trackpoint=Enable +backlight=Both +usb_always_on=Disable diff --git a/src/mainboard/lenovo/t440p/cmos.layout b/src/mainboard/lenovo/t440p/cmos.layout new file mode 100644 index 0000000000..8c5fb0b14b --- /dev/null +++ b/src/mainboard/lenovo/t440p/cmos.layout @@ -0,0 +1,120 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 13 usb_always_on +422 2 e 10 backlight +424 1 e 1 f1_to_f12_as_primary + +# coreboot config options: northbridge +#435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused +440 8 h 0 volume + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +#12 0 Integrated Only +#12 1 Discrete Only +#12 2 Dual Graphics +13 0 Disable +13 1 AC and battery +13 2 AC only + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/lenovo/t440p/data.vbt b/src/mainboard/lenovo/t440p/data.vbt new file mode 100644 index 0000000000..1b2cd87507 Binary files /dev/null and b/src/mainboard/lenovo/t440p/data.vbt differ diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb new file mode 100644 index 0000000000..7e5e616d03 --- /dev/null +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -0,0 +1,113 @@ +chip northbridge/intel/haswell + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.ndid" = "3" + register "gpu_cpu_backlight" = "0x12ba12ba" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight" = "0x12ba12ba" + device cpu_cluster 0x0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x17aa 0x220e inherit + + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + device pci 03.0 on end # Mini-HD audio Audio controller + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" + register "gen4_dec" = "0x000c06a1" + register "gpi13_routing" = "2" + register "gpi1_routing" = "2" + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8a" + register "pirqd_routing" = "0x89" + register "pirqe_routing" = "0x86" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x8b" + register "pirqh_routing" = "0x87" + register "sata_ahci" = "1" + # 0(HDD), 1(M.2), 5(ODD) + register "sata_port_map" = "0x23" + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1, Realtek Card Reader + device pci 1c.1 on # PCIe Port #2, WLAN + smbios_slot_desc "0x14" "1" "M.2 2230" "8" + end + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge PCI-LPC bridge + chip ec/lenovo/pmh7 + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + device pnp ff.1 on # dummy + end + end + chip ec/lenovo/h8 + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "config0" = "0xa6" + register "config1" = "0x0d" + register "config2" = "0xa8" + register "config3" = "0xc4" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xd0" + register "event5_enable" = "0x3c" + register "event7_enable" = "0x01" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x9d" + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl new file mode 100644 index 0000000000..69cd4160e6 --- /dev/null +++ b/src/mainboard/lenovo/t440p/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define THINKPAD_EC_GPE 17 + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + } +} diff --git a/src/mainboard/lenovo/t440p/gma-mainboard.ads b/src/mainboard/lenovo/t440p/gma-mainboard.ads new file mode 100644 index 0000000000..d36cb82e3c --- /dev/null +++ b/src/mainboard/lenovo/t440p/gma-mainboard.ads @@ -0,0 +1,30 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- MiniDP + DP2, -- dock, DP2-1 (DP/HDMI) and DP2-2 (DP/DVI) + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t440p/gpio.c b/src/mainboard/lenovo/t440p/gpio.c new file mode 100644 index 0000000000..cdb707ac1a --- /dev/null +++ b/src/mainboard/lenovo/t440p/gpio.c @@ -0,0 +1,224 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/t440p/hda_verb.c b/src/mainboard/lenovo/t440p/hda_verb.c new file mode 100644 index 0000000000..9527312340 --- /dev/null +++ b/src/mainboard/lenovo/t440p/hda_verb.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ + 0x17aa220e, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x17aa220e), + AZALIA_PIN_CFG(0x0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0x0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x15, 0x0321101f), + AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1a, 0x03a11020), + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x40738105), + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t440p/mainboard.c b/src/mainboard/lenovo/t440p/mainboard.c new file mode 100644 index 0000000000..dcfd5038fd --- /dev/null +++ b/src/mainboard/lenovo/t440p/mainboard.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +void h8_mainboard_init_dock(void) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c new file mode 100644 index 0000000000..c8c630bfde --- /dev/null +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +static const struct rcba_config_instruction rcba_config[] = { + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_config_superio(void) +{ +} + +void mainboard_romstage_entry(void) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 0, /* mobile */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0, 0xa2, 0 }, + .ec_present = 1, + .gbe_enable = 1, + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */ + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* USB2 charge */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK }, + { 0x0080, 1, 2, USB_PORT_BACK_PANEL }, /* USB2 */ + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, /* WWAN */ + { 0x0040, 1, 5, USB_PORT_INTERNAL }, /* WLAN */ + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, /* webcam */ + { 0x0080, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + { 1, 0 }, + { 1, 0 }, + { 1, USB_OC_PIN_SKIP }, + { 1, USB_OC_PIN_SKIP }, + { 1, 1 }, + { 1, 1 }, /* WWAN */ + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = rcba_config, + }; + + romstage_common(&romstage_params); +} diff --git a/src/mainboard/lenovo/t440p/smihandler.c b/src/mainboard/lenovo/t440p/smihandler.c new file mode 100644 index 0000000000..9f5044a3d5 --- /dev/null +++ b/src/mainboard/lenovo/t440p/smihandler.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +/* lynxpoint doesn't have gpi_route_interrupt, so add it */ +#define GPI_DISABLE 0x00 +#define GPI_IS_SMI 0x01 +#define GPI_IS_SCI 0x02 +#define GPI_IS_NMI 0x03 + +static void gpi_route_interrupt(u8 gpi, u8 mode) +{ + u32 gpi_rout; + + gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + gpi_rout &= ~(3 << (2 * gpi)); + gpi_rout |= ((mode & 3) << (2 * gpi)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, + * enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +} diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index 1cb4add847..a6a57e256e 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -31,7 +31,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/platform.asl" @@ -52,5 +52,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 5c23b8e06f..75e331e6d4 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -53,11 +53,6 @@ static void hybrid_graphics_init(void) void pch_enable_lpc(void) { - /* EC Decode Range Port60/64, Port62/66 */ - /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index 1cb4add847..a6a57e256e 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -31,7 +31,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/platform.asl" @@ -52,5 +52,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 67cf97c486..cb17a27dda 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -53,11 +53,6 @@ static void hybrid_graphics_init(void) void pch_enable_lpc(void) { - /* EC Decode Range Port60/64, Port62/66 */ - /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index e4e87c93ef..bc8fa293b2 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_T60 +if BOARD_LENOVO_T60 || BOARD_LENOVO_Z61T || BOARD_LENOVO_R60 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -28,12 +28,23 @@ config MAINBOARD_DIR string default lenovo/t60 +config VARIANT_DIR + string + default "t60" if BOARD_LENOVO_T60 || BOARD_LENOVO_R60 + default "z61t" if BOARD_LENOVO_Z61T + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + config MAINBOARD_PART_NUMBER string - default "ThinkPad T60" + default "ThinkPad T60" if BOARD_LENOVO_T60 + default "ThinkPad Z61t" if BOARD_LENOVO_Z61T + default "ThinkPad R60" if BOARD_LENOVO_R60 config MAX_CPUS int default 2 -endif +endif # BOARD_LENOVO_T60 || BOARD_LENOVO_Z61T || BOARD_LENOVO_R60 diff --git a/src/mainboard/lenovo/t60/Kconfig.name b/src/mainboard/lenovo/t60/Kconfig.name index f02fc3defe..454ac52db5 100644 --- a/src/mainboard/lenovo/t60/Kconfig.name +++ b/src/mainboard/lenovo/t60/Kconfig.name @@ -1,2 +1,8 @@ config BOARD_LENOVO_T60 bool "ThinkPad T60 / T60p" + +config BOARD_LENOVO_Z61T + bool "ThinkPad Z61t" + +config BOARD_LENOVO_R60 + bool "ThinkPad R60" diff --git a/src/mainboard/lenovo/t60/acpi/gpe.asl b/src/mainboard/lenovo/t60/acpi/gpe.asl index 3cc25b2d85..5c900ca3a9 100644 --- a/src/mainboard/lenovo/t60/acpi/gpe.asl +++ b/src/mainboard/lenovo/t60/acpi/gpe.asl @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include "smi.h" Scope (\_GPE) { Method(_L18, 0, NotSerialized) diff --git a/src/mainboard/lenovo/t60/board_info.txt b/src/mainboard/lenovo/t60/board_info.txt index 59ec88c323..3b7137ab3a 100644 --- a/src/mainboard/lenovo/t60/board_info.txt +++ b/src/mainboard/lenovo/t60/board_info.txt @@ -1,4 +1,5 @@ -Board name: T60/T60p +Vendor name: Lenovo +Board name: ThinkPad R60/T60/T60p/Z61t baseboard Category: laptop ROM package: SOIC-8 ROM protocol: SPI diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 28e0574188..70900eae2c 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -116,7 +116,6 @@ chip northbridge/intel/i945 end register "scr" = "0x0844d070" register "mrr" = "0x01d01002" - end end device pci 1e.2 off end # AC'97 Audio @@ -138,7 +137,6 @@ chip northbridge/intel/i945 io 0x66 = 0x1604 end - register "config0" = "0xa6" register "config1" = "0x05" register "config2" = "0xa0" @@ -160,10 +158,6 @@ chip northbridge/intel/i945 register "eventb_enable" = "0xff" register "eventc_enable" = "0x3c" register "eventd_enable" = "0xff" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "7" - register "bdc_gpio_lvl" = "0" end chip superio/nsc/pc87382 device pnp 164e.2 on # IR @@ -210,21 +204,12 @@ chip northbridge/intel/i945 end end end - device pci 1f.1 on # IDE - subsystemid 0x17aa 0x200c - end device pci 1f.2 on # SATA subsystemid 0x17aa 0x200d end device pci 1f.3 on # SMBUS subsystemid 0x17aa 0x200f chip drivers/i2c/ck505 - register "mask" = "{ 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff }" - register "regs" = "{ 0x2e, 0xf7, 0x3c, - 0x20, 0x01, 0x00, 0x1b, 0x01, - 0x54, 0xff, 0xff, 0x07 }" device i2c 69 on end end # eeprom, 8 virtual devices, same chip diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index 8f8c47dae6..12923215d4 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -59,7 +59,7 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include // Dock support code #include "acpi/dock.asl" diff --git a/src/mainboard/lenovo/t60/gpio.c b/src/mainboard/lenovo/t60/gpio.c index f220b2be0c..2ddeb0436f 100644 --- a/src/mainboard/lenovo/t60/gpio.c +++ b/src/mainboard/lenovo/t60/gpio.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 Arthur Heymans + * Copyright (C) 2019 Maciej Matuszczyk * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,21 +17,24 @@ #include static const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio1 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, /* DASP_BAY# */ .gpio6 = GPIO_MODE_GPIO, /* LEGACYIO# */ .gpio7 = GPIO_MODE_GPIO, /* BDC_PRESENCE# */ .gpio8 = GPIO_MODE_GPIO, /* H8_WAKE# */ - .gpio9 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, /* Pulled Up */ .gpio10 = GPIO_MODE_GPIO, /* MDI_DETECT */ .gpio12 = GPIO_MODE_GPIO, /* H8SCI# */ - .gpio13 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, /* Pulled Up */ .gpio14 = GPIO_MODE_GPIO, /* CPUSB# */ .gpio15 = GPIO_MODE_GPIO, /* CPPE# */ - .gpio19 = GPIO_MODE_GPIO, - .gpio22 = GPIO_MODE_GPIO, - .gpio24 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, /* GBE_RS# */ +#if CONFIG(BOARD_LENOVO_R60) + .gpio21 = GPIO_MODE_GPIO, /* LCD_PRESENCE# */ +#endif + .gpio22 = GPIO_MODE_GPIO, /* FWH_WP# */ + .gpio24 = GPIO_MODE_GPIO, /* Pulled Down */ .gpio25 = GPIO_MODE_GPIO, /* MDC_KILL# */ - .gpio26 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, /* Pulled Down */ .gpio27 = GPIO_MODE_GPIO, /* EXC_PWR_CTRL */ .gpio28 = GPIO_MODE_GPIO, /* EXC_AUX_CTRL */ }; @@ -47,7 +51,12 @@ static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio14 = GPIO_DIR_INPUT, .gpio15 = GPIO_DIR_INPUT, .gpio19 = GPIO_DIR_OUTPUT, +#if CONFIG(BOARD_LENOVO_R60) + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, +#else .gpio22 = GPIO_DIR_INPUT, +#endif .gpio24 = GPIO_DIR_OUTPUT, .gpio25 = GPIO_DIR_OUTPUT, .gpio26 = GPIO_DIR_OUTPUT, @@ -77,14 +86,20 @@ static const struct pch_gpio_set1 pch_gpio_set1_blink = { }; static const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio36 = GPIO_MODE_GPIO, /*PLANARID0 */ - .gpio37 = GPIO_MODE_GPIO, /*PLANARID1 */ - .gpio38 = GPIO_MODE_GPIO, /*PLANARID2 */ - .gpio39 = GPIO_MODE_GPIO, /*PLANARID3 */ - .gpio48 = GPIO_MODE_GPIO, +#if CONFIG(BOARD_LENOVO_R60) + .gpio34 = GPIO_MODE_GPIO, /* SMB_3B_EN */ +#endif + .gpio36 = GPIO_MODE_GPIO, /* PLANARID0 */ + .gpio37 = GPIO_MODE_GPIO, /* PLANARID1 */ + .gpio38 = GPIO_MODE_GPIO, /* PLANARID2 */ + .gpio39 = GPIO_MODE_GPIO, /* PLANARID3 */ + .gpio48 = GPIO_MODE_GPIO, /* FWH_TBL# */ }; static const struct pch_gpio_set2 pch_gpio_set2_direction = { +#if CONFIG(BOARD_LENOVO_R60) + .gpio34 = GPIO_DIR_INPUT, +#endif .gpio36 = GPIO_DIR_INPUT, .gpio37 = GPIO_DIR_INPUT, .gpio38 = GPIO_DIR_INPUT, diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 9e832208b5..756ebc8eeb 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -109,12 +109,12 @@ static void early_ich7_init(void) uint32_t reg32; // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); // usb transient disconnect reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); @@ -129,31 +129,7 @@ static void early_ich7_init(void) reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index 51ced894be..3e97ed4a73 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -28,13 +28,6 @@ #define LVTMA_BL_MOD_LEVEL 0x7af9 /* ATI Radeon backlight level */ -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); - /* Enable 0x1600/0x1600 register pair */ - ec_set_bit(0x00, 0x05); -} - static void mainboard_smi_brightness_down(void) { u8 *bar; @@ -59,13 +52,6 @@ static void mainboard_smi_brightness_up(void) int mainboard_io_trap_handler(int smif) { - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - switch (smif) { case SMI_DOCK_CONNECT: /* If there's an legacy I/O module present, we're not diff --git a/src/mainboard/lenovo/t60/variants/t60/board_info.txt b/src/mainboard/lenovo/t60/variants/t60/board_info.txt new file mode 100644 index 0000000000..d7c759c56a --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/t60/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Lenovo +Board name: ThinkPad R60/T60/T60p +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2006 diff --git a/src/mainboard/lenovo/t60/data.vbt b/src/mainboard/lenovo/t60/variants/t60/data.vbt similarity index 100% rename from src/mainboard/lenovo/t60/data.vbt rename to src/mainboard/lenovo/t60/variants/t60/data.vbt diff --git a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb new file mode 100644 index 0000000000..eee3a4d575 --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb @@ -0,0 +1,69 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i945 + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x17aa 0x2015 + end + device pci 01.0 on # PCI-e + device pci 00.0 on # VGA + subsystemid 0x17aa 0x20a4 + end + end + chip southbridge/intel/i82801gx + device pci 1c.0 on # Ethernet + subsystemid 0x17aa 0x2001 + end + device pci 1c.1 on end # WLAN + device pci 1c.2 on end # PCIe port 3 + device pci 1c.3 on end # PCIe port 4 + device pci 1e.0 on # PCI Bridge + chip southbridge/ti/pci1x2x + device pci 00.0 on + subsystemid 0x17aa 0x2012 + end + end + end + device pci 1f.0 on # PCI-LPC bridge + chip ec/lenovo/h8 + register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "7" + register "bdc_gpio_lvl" = "0" + end + chip superio/nsc/pc87384 + device pnp 2e.2 off # Serial Port / IR + irq 0x70 = 4 + end + end + end + device pci 1f.1 on # IDE + subsystemid 0x17aa 0x200c + end + device pci 1f.3 on # SMBUS + chip drivers/i2c/ck505 + register "mask" = "{ 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }" + register "regs" = "{ 0x2e, 0xf7, 0x3c, + 0x20, 0x01, 0x00, 0x1b, 0x01, + 0x54, 0xff, 0xff, 0x07 }" + end + end + end + end +end diff --git a/src/mainboard/lenovo/z61t/board_info.txt b/src/mainboard/lenovo/t60/variants/z61t/board_info.txt similarity index 70% rename from src/mainboard/lenovo/z61t/board_info.txt rename to src/mainboard/lenovo/t60/variants/z61t/board_info.txt index 310e10086c..c7c5643849 100644 --- a/src/mainboard/lenovo/z61t/board_info.txt +++ b/src/mainboard/lenovo/t60/variants/z61t/board_info.txt @@ -1,4 +1,5 @@ -Board name: Z61t +Vendor name: Lenovo +Board name: ThinkPad Z61t Category: laptop ROM package: SOIC-8 ROM protocol: SPI diff --git a/src/mainboard/lenovo/z61t/data.vbt b/src/mainboard/lenovo/t60/variants/z61t/data.vbt similarity index 100% rename from src/mainboard/lenovo/z61t/data.vbt rename to src/mainboard/lenovo/t60/variants/z61t/data.vbt diff --git a/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb new file mode 100644 index 0000000000..d29df3b488 --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb @@ -0,0 +1,64 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i945 + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x17aa 0x2017 + end + device pci 01.0 on # PEG + device pci 00.0 on end # VGA + end + chip southbridge/intel/i82801gx + device pci 1c.0 on # PCI Express Port 1 + subsystemid 0x17aa 0x2011 + end + device pci 1c.1 on # PCI Express Port 2 + subsystemid 0x17aa 0x2011 + end + device pci 1c.2 on # PCI Express Port 3 + subsystemid 0x17aa 0x2011 + end + device pci 1c.3 on # PCI Express Port 4 + subsystemid 0x17aa 0x2011 + end + device pci 1e.0 on # PCI Bridge + chip southbridge/ti/pci1x2x + device pci 00.0 on + subsystemid 0x17aa 0x2013 + end + end + end + device pci 1f.0 on # PCI-LPC bridge + chip superio/nsc/pc87384 + device pnp 2e.2 off # Serial Port / IR + irq 0x70 = 3 + end + end + end + device pci 1f.3 on # SMBUS + chip drivers/i2c/ck505 + register "mask" = "{ 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff }" + # vendor clockgen setup + register "regs" = "{ 0x6d, 0xff, 0xff, + 0x20, 0x41, 0x7f, 0x18, 0x00 }" + end + end + end + end +end diff --git a/src/mainboard/lenovo/thinkcentre_a58/Kconfig b/src/mainboard/lenovo/thinkcentre_a58/Kconfig index fc1c6a7934..6d8b3dcd39 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/Kconfig +++ b/src/mainboard/lenovo/thinkcentre_a58/Kconfig @@ -25,9 +25,6 @@ config BOARD_SPECIFIC_OPTIONS select SUPERIO_SMSC_SMSCSUPERIO select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_L1_SUB_STATE select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi/platform.asl b/src/mainboard/lenovo/thinkcentre_a58/acpi/platform.asl deleted file mode 100644 index 6c92a4ed47..0000000000 --- a/src/mainboard/lenovo/thinkcentre_a58/acpi/platform.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Method(_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store(Arg0, PICM) -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) /* SMI Function */ - Store (0, TRP0) /* Generate trap */ - Return (SMIF) /* Return value of SMI handler */ -} diff --git a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl index 002dfcaeb6..31e7c10d3e 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl +++ b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl @@ -25,7 +25,7 @@ DefinitionBlock( ) { // global NVS and variables - #include "acpi/platform.asl" + #include #include Scope (\_SB) { @@ -38,5 +38,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index e4abab5770..cb84ce07f5 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -30,7 +30,6 @@ static void mb_lpc_setup(void) { - u32 reg32; /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); @@ -41,10 +40,7 @@ static void mb_lpc_setup(void) RCBA8(0x31ff) = 0x03; RCBA8(0x31ff); - reg32 = RCBA32(GCS); - reg32 |= (1 << 5); - RCBA32(GCS) = reg32; - RCBA32(CG) = 0x00000001; + ich7_setup_cir(); } static void ich7_enable_lpc(void) diff --git a/src/mainboard/lenovo/x131e/dsdt.asl b/src/mainboard/lenovo/x131e/dsdt.asl index 3e5ede5a22..95eb2db254 100644 --- a/src/mainboard/lenovo/x131e/dsdt.asl +++ b/src/mainboard/lenovo/x131e/dsdt.asl @@ -35,13 +35,13 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include // global NVS and variables #include // Chipset specific sleep states - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c index 5fc5df6b85..2a6ee2733b 100644 --- a/src/mainboard/lenovo/x131e/romstage.c +++ b/src/mainboard/lenovo/x131e/romstage.c @@ -22,10 +22,6 @@ void pch_enable_lpc(void) { - /* EC Decode Range Port60/64, Port62/66 */ - /* Enable TPM, EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); } void mainboard_rcba_config(void) diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index 8c9bd5ad64..3acc87d33c 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -31,7 +31,7 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/platform.asl" @@ -52,5 +52,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index f666671dd6..b779c4eff5 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -30,11 +30,6 @@ void pch_enable_lpc(void) { - /* EC Decode Range Port60/64, Port62/66 */ - /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc index f5c233add0..235fc102d1 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc @@ -24,7 +24,7 @@ SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f)) $(SPD_BIN): $(SPD_DEPS) for f in $+; \ do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 7b905bcfff..5e88c21c2f 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_X200 +if BOARD_LENOVO_X200 || BOARD_LENOVO_X301 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -24,13 +24,41 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x82 + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + config MAINBOARD_DIR string default lenovo/x200 +config VARIANT_DIR + string + default "x200" if BOARD_LENOVO_X200 + default "x301" if BOARD_LENOVO_X301 + config MAINBOARD_PART_NUMBER string - default "ThinkPad X200" + default "ThinkPad X200" if BOARD_LENOVO_X200 + default "ThinkPad X301" if BOARD_LENOVO_X301 + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config USBDEBUG_HCD_INDEX int @@ -44,4 +72,4 @@ config CBFS_SIZE hex default 0x200000 -endif # BOARD_LENOVO_X200 +endif # BOARD_LENOVO_X200 || BOARD_LENOVO_X301 diff --git a/src/mainboard/lenovo/x200/Kconfig.name b/src/mainboard/lenovo/x200/Kconfig.name index 8e1dd430b1..54c79616e4 100644 --- a/src/mainboard/lenovo/x200/Kconfig.name +++ b/src/mainboard/lenovo/x200/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_LENOVO_X200 - bool "ThinkPad X200 / X200t" + bool "ThinkPad X200 / X200s / X200t" + +config BOARD_LENOVO_X301 + bool "ThinkPad X301" diff --git a/src/mainboard/lenovo/x200/Makefile.inc b/src/mainboard/lenovo/x200/Makefile.inc index ffd7cf22d1..f6c2c0c074 100644 --- a/src/mainboard/lenovo/x200/Makefile.inc +++ b/src/mainboard/lenovo/x200/Makefile.inc @@ -13,10 +13,10 @@ ## GNU General Public License for more details. ## -ramstage-y += dock.c +ramstage-y += variants/$(VARIANT_DIR)/dock.c ramstage-y += cstates.c ramstage-y += blc.c -romstage-y += gpio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x200/blc.c b/src/mainboard/lenovo/x200/blc.c index 6c5779a0b2..0856060e86 100644 --- a/src/mainboard/lenovo/x200/blc.c +++ b/src/mainboard/lenovo/x200/blc.c @@ -23,6 +23,7 @@ static const struct blc_pwm_t blc_entries[] = { /* corrected to 320MHz CDClk, vendor set 753; works fine at both: */ {"LTD121EQ3B", 447}, {"LTD121EWVB", 165}, + {"LTD133EQ1B", 264}, /* Found on an X301 */ {"B121EW03 V6 ", 165}, /* datasheets: between 100 and 20k, typical 200 */ /* TESTED: works best at 400 */ diff --git a/src/mainboard/lenovo/x200/board_info.txt b/src/mainboard/lenovo/x200/board_info.txt index c9cc0036d1..91d5bd8af0 100644 --- a/src/mainboard/lenovo/x200/board_info.txt +++ b/src/mainboard/lenovo/x200/board_info.txt @@ -1,5 +1,6 @@ Category: laptop -ROM package: SOIC-16 or SOIC-8 +Board name: Thinkpad X200/X200T/X200S/X301 +ROM package: SOIC-16 or SOIC-8 or WSON8 ROM protocol: SPI ROM socketed: n Flashrom support: n diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index 4a381462b6..ebae12d452 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -86,6 +86,10 @@ entries # RAM initialization internal data 1024 128 r 0 read_training_results +# VBOOT +1152 128 r 0 vbnv + + # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 2ed4308cfa..3c4e094f35 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -73,12 +73,9 @@ chip northbridge/intel/gm45 # Set thermal throttling to 75%. register "throttle_duty" = "THTL_75_0" - # Enable PCIe ports 1,2,4 as slots (Mini * PCIe). - register "pcie_slot_implemented" = "0xb" - # Set power limits to 10 * 10^0 watts. - # Maybe we should set less for Mini PCIe. - register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }" - register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" + register "gen3_dec" = "0x001c1681" device pci 19.0 on end # LAN device pci 1a.0 on # UHCI @@ -111,10 +108,7 @@ chip northbridge/intel/gm45 device pci 1c.2 on subsystemid 0x17aa 0x20f3 # UWB end # PCIe Port #3 - device pci 1c.3 on - subsystemid 0x17aa 0x20f3 # Expresscard - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #4 + device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 device pci 1d.0 on # UHCI @@ -151,7 +145,6 @@ chip northbridge/intel/gm45 device pnp ff.1 on # dummy end register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" end chip ec/lenovo/h8 @@ -189,22 +182,6 @@ chip northbridge/intel/gm45 register "bdc_gpio_num" = "7" register "bdc_gpio_lvl" = "0" end - - chip superio/nsc/pc87382 - device pnp 164e.3 on # Digitizer - io 0x60 = 0x200 - irq 0x29 = 0xb0 - irq 0x70 = 0x5 - irq 0xf0 = 0x82 - end - # IR, not connected - device pnp 164e.2 off end - # GPIO, not connected - device pnp 164e.7 off end - # DLPC, not connected - device pnp 164e.19 off end - end - end device pci 1f.2 on # SATA/IDE 1 subsystemid 0x17aa 0x20f8 diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl index 8a11ec1954..e300234e87 100644 --- a/src/mainboard/lenovo/x200/dsdt.asl +++ b/src/mainboard/lenovo/x200/dsdt.asl @@ -52,7 +52,7 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include /* Dock support code */ #include "acpi/dock.asl" diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 4382bc084d..41be94f357 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -14,25 +14,9 @@ * GNU General Public License for more details. */ -#include #include -#include #include -#define LPC_DEV PCI_DEV(0, 0x1f, 0) - -void mb_setup_lpc(void) -{ - /* Configure serial IRQs.*/ - pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0); - /* Map COMa on 0x3f8, COMb on 0x2f8. */ - pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); - pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3f0f); - pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x7c1601); - pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xc15e1); - pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681); -} - void get_mb_spd_addrmap(u8 *spd_addrmap) { spd_addrmap[0] = 0x50; diff --git a/src/mainboard/lenovo/x200/variants/x200/board_info.txt b/src/mainboard/lenovo/x200/variants/x200/board_info.txt new file mode 100644 index 0000000000..c9cc0036d1 --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x200/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-16 or SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2008 diff --git a/src/mainboard/lenovo/x200/variants/x200/dock.c b/src/mainboard/lenovo/x200/variants/x200/dock.c new file mode 100644 index 0000000000..bdd65a564a --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x200/dock.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "../../dock.h" + +void h8_mainboard_init_dock(void) +{ + if (dock_present()) { + printk(BIOS_DEBUG, "dock is connected\n"); + dock_connect(); + } else + printk(BIOS_DEBUG, "dock is not connected\n"); +} + +void dock_connect(void) +{ + ec_set_bit(0x02, 0); + set_gpio(28, GPIO_LEVEL_HIGH); +} + +void dock_disconnect(void) +{ + ec_clr_bit(0x02, 0); + set_gpio(28, GPIO_LEVEL_LOW); +} + +int dock_present(void) +{ + const int dock_id_gpio[] = { 2, 3, 4, -1}; + + return get_gpios(dock_id_gpio) != 7; +} diff --git a/src/mainboard/lenovo/x200/gpio.c b/src/mainboard/lenovo/x200/variants/x200/gpio.c similarity index 100% rename from src/mainboard/lenovo/x200/gpio.c rename to src/mainboard/lenovo/x200/variants/x200/gpio.c diff --git a/src/mainboard/lenovo/x200/variants/x200/overridetree.cb b/src/mainboard/lenovo/x200/variants/x200/overridetree.cb new file mode 100644 index 0000000000..dd08f1f515 --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x200/overridetree.cb @@ -0,0 +1,38 @@ +chip northbridge/intel/gm45 + device domain 0 on + chip southbridge/intel/i82801ix + # Enable PCIe ports 1,2,3,4 as slots (Mini * PCIe). + register "pcie_slot_implemented" = "0xf" + # Set power limits to 10 * 10^0 watts. + # Maybe we should set less for Mini PCIe. + register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 10, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }" + # Enable hotplug on PCIe port 4 (Express Card) + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + + device pci 1c.3 on + subsystemid 0x17aa 0x20f3 # Expresscard + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" + end # PCIe Port #4 + + device pci 1f.0 on # LPC bridge + chip ec/lenovo/pmh7 + register "dock_event_enable" = "0x01" + end + chip superio/nsc/pc87382 + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 + end + # IR, not connected + device pnp 164e.2 off end + # GPIO, not connected + device pnp 164e.7 off end + # DLPC, not connected + device pnp 164e.19 off end + end + end + end + end +end diff --git a/src/mainboard/lenovo/x200/variants/x301/board_info.txt b/src/mainboard/lenovo/x200/variants/x301/board_info.txt new file mode 100644 index 0000000000..6ee5df0c6c --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x301/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2008 diff --git a/src/soc/intel/apollolake/acpi/lpc.asl b/src/mainboard/lenovo/x200/variants/x301/dock.c similarity index 73% rename from src/soc/intel/apollolake/acpi/lpc.asl rename to src/mainboard/lenovo/x200/variants/x301/dock.c index 749daf78b1..f8a2dc4260 100644 --- a/src/soc/intel/apollolake/acpi/lpc.asl +++ b/src/mainboard/lenovo/x200/variants/x301/dock.c @@ -1,8 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. + * Copyright (C) 2011 Sven Schnelle + * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -15,9 +15,8 @@ * GNU General Public License for more details. */ -/* Intel LPC Bus Device - 0:1f.0 */ +#include -Device (LPCB) +void h8_mainboard_init_dock(void) { - Name (_ADR, 0x001f0000) } diff --git a/src/mainboard/lenovo/x200/variants/x301/gpio.c b/src/mainboard/lenovo/x200/variants/x301/gpio.c new file mode 100644 index 0000000000..10ad18a855 --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x301/gpio.c @@ -0,0 +1,160 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio9 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/lenovo/x200/variants/x301/overridetree.cb b/src/mainboard/lenovo/x200/variants/x301/overridetree.cb new file mode 100644 index 0000000000..03cb4dfe9a --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x301/overridetree.cb @@ -0,0 +1,13 @@ +chip northbridge/intel/gm45 + device domain 0 on + chip southbridge/intel/i82801ix + # Enable PCIe ports 1,2,3 as slots (Mini * PCIe). + register "pcie_slot_implemented" = "0x7" + # Set power limits to 10 * 10^0 watts. + # Maybe we should set less for Mini PCIe. + register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 } }" + # x301 has no Express Card slot. + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + end + end +end diff --git a/src/mainboard/lenovo/x200/vboot-rwa.fmd b/src/mainboard/lenovo/x200/vboot-rwa.fmd new file mode 100644 index 0000000000..4af3fcd2d6 --- /dev/null +++ b/src/mainboard/lenovo/x200/vboot-rwa.fmd @@ -0,0 +1,26 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x600000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x5f5000 + SI_GBE@0x5f6000 0x2000 + SI_PD@0x5f8000 0x8000 + } + SI_BIOS@0x600000 0x200000 { + RW_SECTION_A 0x100000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + RW_VPD(PRESERVE) 0x1000 + CONSOLE 0x10000 + SMMSTORE(PRESERVE) 0x40000 + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 905d81d682..e40c0d3e41 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -23,6 +23,25 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_USES_IFD_GBE_REGION select H8_HAS_BAT_TRESHOLDS_IMPL +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + config MAINBOARD_DIR string default lenovo/x201 diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc index f97235612e..548beff15d 100644 --- a/src/mainboard/lenovo/x201/Makefile.inc +++ b/src/mainboard/lenovo/x201/Makefile.inc @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ## +bootblock-y += early_init.c + smm-y += dock.c smm-y += smihandler.c romstage-y += dock.c diff --git a/src/mainboard/lenovo/x201/acpi/dock.asl b/src/mainboard/lenovo/x201/acpi/dock.asl index db3e9fef4f..2bba82141c 100644 --- a/src/mainboard/lenovo/x201/acpi/dock.asl +++ b/src/mainboard/lenovo/x201/acpi/dock.asl @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include "smi.h" - Scope (\_SB) { Device(DOCK) diff --git a/src/mainboard/lenovo/x201/acpi/gpe.asl b/src/mainboard/lenovo/x201/acpi/gpe.asl index 3cc25b2d85..5c900ca3a9 100644 --- a/src/mainboard/lenovo/x201/acpi/gpe.asl +++ b/src/mainboard/lenovo/x201/acpi/gpe.asl @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include "smi.h" Scope (\_GPE) { Method(_L18, 0, NotSerialized) diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index 7d7013bcd3..bcd6de67c8 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -14,40 +14,6 @@ * GNU General Public License for more details. */ -/* These come from the dynamically created CPU SSDT */ -External(PDC0) -External(PDC1) - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, /* APM command */ - APMS, 8 /* APM status */ -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) /* SMI Function */ - Store (0, TRP0) /* Generate trap */ - Return (SMIF) /* Return value of SMI handler */ -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ @@ -63,6 +29,10 @@ Method(_PTS,1) Method(_WAK,1) { + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 0cda679814..990db6df06 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -78,6 +78,9 @@ entries #427 5 r 0 unused 432 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # coreboot config options: check sums 984 16 h 0 check_sum #1000 24 r 0 amd_reserved diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index bf74d710bb..3ababc9e9c 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -48,6 +48,7 @@ chip northbridge/intel/nehalem device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2193 end + device pci 01.0 off end # PEG device pci 02.0 on # VGA controller subsystemid 0x17aa 0x215a end @@ -73,9 +74,10 @@ chip northbridge/intel/nehalem register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - device pci 16.2 on # IDE/SATA - subsystemid 0x17aa 0x2161 - end + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R, only management boot + device pci 16.3 off end # Management Engine KT device pci 19.0 on # Ethernet subsystemid 0x17aa 0x2153 @@ -91,14 +93,19 @@ chip northbridge/intel/nehalem device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 (wwan) + device pci 1c.2 off end device pci 1c.3 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 (Expresscard) device pci 1c.4 on end # PCIe Port #5 (wlan) + device pci 1c.5 off end + device pci 1c.6 off end + device pci 1c.7 off end device pci 1d.0 on # USB2 EHCI subsystemid 0x17aa 0x2163 end + device pci 1e.0 on end # PCI 2 PCI bridge device pci 1f.0 on # PCI-LPC bridge subsystemid 0x17aa 0x2166 chip superio/nsc/pc87382 @@ -178,6 +185,9 @@ chip northbridge/intel/nehalem device i2c 5f on end end end + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 on end end end end diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c index 04050f2d35..652a144104 100644 --- a/src/mainboard/lenovo/x201/dock.c +++ b/src/mainboard/lenovo/x201/dock.c @@ -15,18 +15,14 @@ * GNU General Public License for more details. */ -#define __SIMPLE_DEVICE__ #include -#include -#include #include -#include #include "dock.h" -#include +#include #include #include -void h8_mainboard_init_dock (void) +void h8_mainboard_init_dock(void) { if (dock_present()) { printk(BIOS_DEBUG, "dock is connected\n"); @@ -37,30 +33,25 @@ void h8_mainboard_init_dock (void) void dock_connect(void) { - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; - ec_set_bit(0x02, 0); ec_set_bit(0x1a, 0); ec_set_bit(0xfe, 4); - outl(inl(gpiobase + 0x0c) | (1 << 28), gpiobase + 0x0c); + set_gpio(28, GPIO_LEVEL_HIGH); } void dock_disconnect(void) { - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; - ec_clr_bit(0x02, 0); ec_clr_bit(0x1a, 0); ec_clr_bit(0xfe, 4); - outl(inl(gpiobase + 0x0c) & ~(1 << 28), gpiobase + 0x0c); + set_gpio(28, GPIO_LEVEL_LOW); } int dock_present(void) { - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; - u8 st = inb(gpiobase + 0x0c); + const int dock_id_gpio[] = { 3, 4, 5, -1}; - return ((st >> 3) & 7) != 7; + return get_gpios(dock_id_gpio) != 7; } diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index 461892bf7e..9d0204e5cc 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -30,6 +30,8 @@ DefinitionBlock( 0x20130325 /* OEM revision */ ) { + #include + /* Some generic macros */ #include "acpi/platform.asl" @@ -52,7 +54,6 @@ DefinitionBlock( Device (UNCR) { Name (_BBN, 0xFF) - Name (_ADR, 0x00) Name (RID, 0x00) Name (_HID, EisaId ("PNP0A03")) Name (_CRS, ResourceTemplate () @@ -86,7 +87,7 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include /* Dock support code */ #include "acpi/dock.asl" diff --git a/src/southbridge/intel/fsp_rangeley/acpi/sleepstates.asl b/src/mainboard/lenovo/x201/early_init.c similarity index 64% rename from src/southbridge/intel/fsp_rangeley/acpi/sleepstates.asl rename to src/mainboard/lenovo/x201/early_init.c index cd391fb76a..7383381ce9 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/sleepstates.asl +++ b/src/mainboard/lenovo/x201/early_init.c @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle + * Copyright (C) 2013 Vladimir Serbinenko * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -14,13 +16,11 @@ * GNU General Public License for more details. */ -Name(\_S0, Package(){0x0,0x0,0x0,0x0}) +#include +#include -/* - * S1 and S3 sleep states are not supported - * Name(\_S1, Package(){0x1,0x1,0x0,0x0}) - * Name(\_S3, Package(){0x5,0x5,0x0,0x0}) - */ - -Name(\_S4, Package(){0x6,0x6,0x0,0x0}) -Name(\_S5, Package(){0x7,0x7,0x0,0x0}) +void bootblock_mainboard_early_init(void) +{ + /* Enable USB Power. We need to do it early for usbdebug to work. */ + ec_set_bit(0x3b, 4); +} diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 56c439bb58..c021db185c 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -16,9 +16,7 @@ * GNU General Public License for more details. */ -#include #include -#include #include #include #include diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 3a06a8cd93..99875ed65a 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -19,141 +19,28 @@ #include #include #include -#include -#include -#include -#include -#include #include -#include -#include -#include "dock.h" #include -#include #include -#include -#include - -static void pch_enable_lpc(void) -{ - /* EC Decode Range Port60/64, Port62/66 */ - /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN | GAMEL_LPC_EN); - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - - pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0); - pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8); - - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); - - pci_write_config32(PCH_LPC_DEV, ETR3, - pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); -} - -static void rcba_config(void) -{ - southbridge_configure_default_intmap(); - - static const u32 rcba_dump3[] = { - /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, - /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, - /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000, - /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000, - /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000, - /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b, - /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000, - /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, - /* 3410 */ 0x00000c61, 0x00000000, 0x16e41fe1, 0xbf4f001f, - /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, - /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000, - /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b, - /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b, - /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f, - /* 3530 */ 0x20000557, 0x2000055f, 0x00000000, 0x00000000, - /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3560 */ 0x00000001, 0x000026a3, 0x00040002, 0x01000052, - /* 3570 */ 0x02000772, 0x16000f8f, 0x1800ff4f, 0x0001d630, - /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35a0 */ 0xfc000201, 0x3c000201, 0x00000000, 0x00000000, - /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001, - /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000, - /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3650 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3660 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3670 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3680 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3690 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 36a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 36b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 36c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 36d0 */ 0x00000000, 0x089c0018, 0x00000000, 0x00000000, - /* 36e0 */ 0x11111111, 0x00000000, 0x00000000, 0x00000000, - /* 36f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3700 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3710 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3720 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000, - }; - unsigned i; - for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3310) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3310); - } -} - -static inline void write_acpi32(u32 addr, u32 val) -{ - outl(val, DEFAULT_PMBASE | addr); -} - -static inline void write_acpi16(u32 addr, u16 val) -{ - outw(val, DEFAULT_PMBASE | addr); -} - -static inline u32 read_acpi32(u32 addr) -{ - return inl(DEFAULT_PMBASE | addr); -} +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* Enabled, Current table lookup index, OC map */ + { 1, IF1_557, 0 }, + { 1, IF1_55F, 1 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_557, 3 }, + { 1, IF1_14B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 4 }, + { 1, IF1_74B, 5 }, + { 1, IF1_55F, 7 }, + { 1, IF1_55F, 7 }, + { 1, IF1_557, 7 }, + { 1, IF1_55F, 7 }, +}; static void set_fsb_frequency(void) { @@ -166,98 +53,18 @@ static void set_fsb_frequency(void) smbus_block_write(0x69, 0, 5, block); } -void mainboard_romstage_entry(void) +void mainboard_pre_raminit(void) { - u32 reg32; - int s3resume = 0; - const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 }; - enable_lapic(); - - nehalem_early_initialization(NEHALEM_MOBILE); - - pch_enable_lpc(); - - /* Enable USB Power. We need to do it early for usbdebug to work. */ - ec_set_bit(0x3b, 4); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - console_init(); - - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - printk(BIOS_DEBUG, "a2: %02x\n", reg8); - if (!(reg8 & 0x20)) { - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); - } else { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - } else { - printk(BIOS_DEBUG, - "Resume from S3 detected, but disabled.\n"); - } - } - } - - /* Enable SMBUS. */ - enable_smbus(); - outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20, DEFAULT_GPIOBASE | 0x3a); outb(0x50, 0x15ec); outb(inb(0x15ee) & 0x70, 0x15ee); - write_acpi16(0x2, 0x0); - write_acpi32(0x28, 0x0); - write_acpi32(0x2c, 0x0); - if (!s3resume) { - read_acpi32(0x4); - read_acpi32(0x20); - read_acpi32(0x34); - write_acpi16(0x0, 0x900); - write_acpi32(0x20, 0xffff7ffe); - write_acpi32(0x34, 0x56974); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2); - } - - early_thermal_init(); - - timestamp_add_now(TS_BEFORE_INITRAM); - - chipset_init(s3resume); - set_fsb_frequency(); - - raminit(s3resume, spd_addrmap); - - timestamp_add_now(TS_AFTER_INITRAM); - - intel_early_me_status(); - - if (s3resume) { - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } - - romstage_handoff_init(s3resume); +} + +void mainboard_get_spd_map(u8 *spd_addrmap) +{ + spd_addrmap[0] = 0x50; + spd_addrmap[2] = 0x51; } diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index e80782acf6..4ba10b47cd 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -24,52 +24,10 @@ #include #include #include "dock.h" -#include "smi.h" #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); - /* Enable 0x1600/0x1600 register pair */ - ec_set_bit(0x00, 0x05); -} - -int mainboard_io_trap_handler(int smif) -{ - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - - switch (smif) { - case SMI_DOCK_CONNECT: - ec_clr_bit(0x03, 2); - udelay(250000); - dock_connect(); - ec_set_bit(0x03, 2); - /* set dock LED to indicate status */ - ec_write(0x0c, 0x09); - ec_write(0x0c, 0x88); - break; - - case SMI_DOCK_DISCONNECT: - ec_clr_bit(0x03, 2); - dock_disconnect(); - break; - - default: - return 0; - } - - /* On success, the IO Trap Handler returns 1 - * On failure, the IO Trap Handler returns a value != 1 */ - return 1; -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); @@ -88,12 +46,19 @@ static void mainboard_smi_handle_ec_sci(void) /* Power loss */ case 0x50: /* Undock Key */ - mainboard_io_trap_handler(SMI_DOCK_DISCONNECT); + ec_clr_bit(0x03, 2); + dock_disconnect(); break; case 0x37: case 0x58: /* Dock Event */ - mainboard_io_trap_handler(SMI_DOCK_CONNECT); + ec_clr_bit(0x03, 2); + udelay(250000); + dock_connect(); + ec_set_bit(0x03, 2); + /* set dock LED to indicate status */ + ec_write(0x0c, 0x09); + ec_write(0x0c, 0x88); break; default: break; diff --git a/src/mainboard/lenovo/x201/vboot-rwa.fmd b/src/mainboard/lenovo/x201/vboot-rwa.fmd new file mode 100644 index 0000000000..0d1aa5df13 --- /dev/null +++ b/src/mainboard/lenovo/x201/vboot-rwa.fmd @@ -0,0 +1,30 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_SECTION_A 0x180000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE) 0x40000 + WP_RO { + RO_VPD(PRESERVE) 0x1000 + RO_SECTION { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index 1cb4add847..a6a57e256e 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -31,7 +31,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/platform.asl" @@ -52,5 +52,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 9ecb8a3e1e..af92f9ba8e 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -29,11 +29,6 @@ void pch_enable_lpc(void) { - /* EC Decode Range Port60/64, Port62/66 */ - /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index 1cb4add847..a6a57e256e 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -31,7 +31,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/platform.asl" @@ -52,5 +52,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 10cddebda3..60016a4f07 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -26,11 +26,6 @@ void pch_enable_lpc(void) { - /* EC Decode Range Port60/64, Port62/66 */ - /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/x60/acpi/gpe.asl b/src/mainboard/lenovo/x60/acpi/gpe.asl index 3cc25b2d85..5c900ca3a9 100644 --- a/src/mainboard/lenovo/x60/acpi/gpe.asl +++ b/src/mainboard/lenovo/x60/acpi/gpe.asl @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include "smi.h" Scope (\_GPE) { Method(_L18, 0, NotSerialized) diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 2bba47ceec..00430bb62a 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -53,7 +53,7 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include // Dock support code #include "acpi/dock.asl" diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 5a8ab942bc..34d8d7a435 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -109,12 +109,12 @@ static void early_ich7_init(void) uint32_t reg32; // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); // usb transient disconnect reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); @@ -129,31 +129,7 @@ static void early_ich7_init(void) reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index 18e5046289..0a2c7e2e6b 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -29,13 +29,6 @@ #define GPE_EC_SCI 12 -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); - /* Enable 0x1600/0x1600 register pair */ - ec_set_bit(0x00, 0x05); -} - static void mainboard_smi_save_cmos(void) { u8 val; @@ -55,13 +48,6 @@ static void mainboard_smi_save_cmos(void) int mainboard_io_trap_handler(int smif) { - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - switch (smif) { case SMI_DOCK_CONNECT: ec_clr_bit(0x03, 2); diff --git a/src/mainboard/lenovo/z61t/Kconfig b/src/mainboard/lenovo/z61t/Kconfig deleted file mode 100644 index de48d95050..0000000000 --- a/src/mainboard/lenovo/z61t/Kconfig +++ /dev/null @@ -1,39 +0,0 @@ -if BOARD_LENOVO_Z61T - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_M - select NORTHBRIDGE_INTEL_I945 - select NORTHBRIDGE_INTEL_SUBTYPE_I945GM - select SOUTHBRIDGE_INTEL_I82801GX - select SUPERIO_NSC_PC87382 - select SUPERIO_NSC_PC87384 - select SOUTHBRIDGE_TI_PCI1X2X - select EC_LENOVO_PMH7 - select EC_LENOVO_H8 - select DRIVERS_I2C_CK505 - select HAVE_OPTION_TABLE - select INTEL_INT15 - select HAVE_MP_TABLE - select BOARD_ROMSIZE_KB_2048 - select HAVE_ACPI_TABLES - select HAVE_ACPI_RESUME - select H8_DOCK_EARLY_INIT - select HAVE_CMOS_DEFAULT - select I945_LVDS - select INTEL_GMA_HAVE_VBT - -config MAINBOARD_DIR - string - default lenovo/z61t - -config MAINBOARD_PART_NUMBER - string - default "ThinkPad Z61t" - -config MAX_CPUS - int - default 2 - -endif diff --git a/src/mainboard/lenovo/z61t/Kconfig.name b/src/mainboard/lenovo/z61t/Kconfig.name deleted file mode 100644 index a2328575ee..0000000000 --- a/src/mainboard/lenovo/z61t/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LENOVO_Z61T - bool "ThinkPad Z61t" diff --git a/src/mainboard/lenovo/z61t/acpi/ich7_pci_irqs.asl b/src/mainboard/lenovo/z61t/acpi/ich7_pci_irqs.asl deleted file mode 100644 index 4c7c3a3757..0000000000 --- a/src/mainboard/lenovo/z61t/acpi/ich7_pci_irqs.asl +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * 0:1e.0 PCI bridge of the ICH7 - */ - -If (PICM) { - Return (Package() { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x16 }, - Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 } - }) - } Else { - Return (Package() { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 }, - Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 } - }) -} diff --git a/src/mainboard/lenovo/z61t/acpi/mainboard.asl b/src/mainboard/lenovo/z61t/acpi/mainboard.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/lenovo/z61t/acpi/superio.asl b/src/mainboard/lenovo/z61t/acpi/superio.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/lenovo/z61t/devicetree.cb b/src/mainboard/lenovo/z61t/devicetree.cb deleted file mode 100644 index d35c62b09c..0000000000 --- a/src/mainboard/lenovo/z61t/devicetree.cb +++ /dev/null @@ -1,241 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2011 Sven Schnelle -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/intel/i945 - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - - register "gpu_hotplug" = "0x00000220" - register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "pwm_freq" = "275" - register "gpu_panel_power_up_delay" = "250" - register "gpu_panel_power_backlight_on_delay" = "2380" - register "gpu_panel_power_down_delay" = "250" - register "gpu_panel_power_backlight_off_delay" = "2380" - register "gpu_panel_power_cycle_delay" = "2" - - device cpu_cluster 0 on - chip cpu/intel/socket_m - device lapic 0 on end - end - end - - register "pci_mmio_size" = "768" - - device domain 0 on - device pci 00.0 on # Host bridge - subsystemid 0x17aa 0x2017 - end - - device pci 01.0 on # PEG - device pci 00.0 on end # VGA - end - - device pci 02.0 on # GMA Graphics controller - subsystemid 0x17aa 0x201a - end - device pci 02.1 on # display controller - subsystemid 0x17aa 0x201a - end - - chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi13_routing" = "2" - register "gpi12_routing" = "2" - register "gpi8_routing" = "2" - - register "sata_ports_implemented" = "0x01" - - register "gpe0_en" = "0x11000006" - register "alt_gp_smi_en" = "0x1000" - - register "c4onc3_enable" = "1" - register "c3_latency" = "0x23" - register "docking_supported" = "1" - register "p_cnt_throttling_supported" = "1" - - device pci 1b.0 on # Audio Controller - subsystemid 0x17aa 0x2010 - end - device pci 1c.0 on # PCI Express Port 1 - subsystemid 0x17aa 0x2011 - end - device pci 1c.1 on # PCI Express Port 2 - subsystemid 0x17aa 0x2011 - end - device pci 1c.2 on # PCI Express Port 3 - subsystemid 0x17aa 0x2011 - end - device pci 1c.3 on # PCI Express Port 4 - subsystemid 0x17aa 0x2011 - end - device pci 1c.4 off end # PCIe port 5 - device pci 1c.5 off end # PCIe port 6 - - device pci 1d.0 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.1 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.2 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.3 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.7 on # USB2 EHCI - subsystemid 0x17aa 0x200b - end - device pci 1e.0 on # PCI Bridge - chip southbridge/ti/pci1x2x - device pci 00.0 on - subsystemid 0x17aa 0x2013 - end - register "scr" = "0x0844d070" - register "mrr" = "0x01d01002" - - end - end - device pci 1e.2 off end # AC'97 Audio - device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # PCI-LPC bridge - subsystemid 0x17aa 0x2009 - chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end - - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa6" - register "config1" = "0x05" - register "config2" = "0xa0" - register "config3" = "0x01" - - register "beepmask0" = "0xfe" - register "beepmask1" = "0x96" - register "has_power_management_beeps" = "1" - - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xf4" - register "event5_enable" = "0x3f" - register "event6_enable" = "0x80" - register "event7_enable" = "0x01" - register "event8_enable" = "0x01" - register "event9_enable" = "0xff" - register "eventa_enable" = "0xff" - register "eventb_enable" = "0xff" - register "eventc_enable" = "0x3c" - register "eventd_enable" = "0xff" - - end - chip superio/nsc/pc87382 - device pnp 164e.2 on # IR - io 0x60 = 0x2f8 - end - - device pnp 164e.3 off # Serial Port - io 0x60 = 0x3f8 - end - - device pnp 164e.7 on # GPIO - io 0x60 = 0x1680 - end - - device pnp 164e.19 on # DLPC - io 0x60 = 0x164c - end - end - - chip superio/nsc/pc87384 - device pnp 2e.0 off #FDC - end - - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x3bc - irq 0x70 = 7 - end - - device pnp 2e.2 off # Serial Port / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - - device pnp 2e.3 on # Serial Port - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - - device pnp 2e.7 on # GPIO - io 0x60 = 0x1620 - end - - device pnp 2e.a off # WDT - end - end - end - device pci 1f.2 on # SATA - subsystemid 0x17aa 0x200d - end - device pci 1f.3 on # SMBUS - subsystemid 0x17aa 0x200f - chip drivers/i2c/ck505 - register "mask" = "{ 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff }" - # vendor clockgen setup - register "regs" = "{ 0x6d, 0xff, 0xff, - 0x20, 0x41, 0x7f, 0x18, 0x00 }" - device i2c 69 on end - end - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end - end - end -end diff --git a/src/mainboard/lenovo/z61t/dock.c b/src/mainboard/lenovo/z61t/dock.c deleted file mode 100644 index 05dd65ef3e..0000000000 --- a/src/mainboard/lenovo/z61t/dock.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "dock.h" -#include -#include "ec/acpi/ec.h" -#include "ec/lenovo/pmh7/pmh7.h" -#include - -#define DLPC_CONTROL 0x164c - -static void dlpc_write_register(int reg, int value) -{ - outb(reg, 0x164e); - outb(value, 0x164f); -} - -static u8 dlpc_read_register(int reg) -{ - outb(reg, 0x164e); - return inb(0x164f); -} - -static void dock_write_register(int reg, int value) -{ - outb(reg, 0x2e); - outb(value, 0x2f); -} - -static u8 dock_read_register(int reg) -{ - outb(reg, 0x2e); - return inb(0x2f); -} - -static void dlpc_gpio_set_mode(int port, int mode) -{ - dlpc_write_register(0xf0, port); - dlpc_write_register(0xf1, mode); -} - -static void dock_gpio_set_mode(int port, int mode, int irq) -{ - dock_write_register(0xf0, port); - dock_write_register(0xf1, mode); - dock_write_register(0xf2, irq); -} - -static void dlpc_gpio_init(void) -{ - /* Select GPIO module */ - dlpc_write_register(0x07, 0x07); - /* GPIO Base Address 0x1680 */ - dlpc_write_register(0x60, 0x16); - dlpc_write_register(0x61, 0x80); - - /* Activate GPIO */ - dlpc_write_register(0x30, 0x01); - - dlpc_gpio_set_mode(0x00, 3); - dlpc_gpio_set_mode(0x01, 3); - dlpc_gpio_set_mode(0x02, 0); - dlpc_gpio_set_mode(0x03, 3); - dlpc_gpio_set_mode(0x04, 4); - dlpc_gpio_set_mode(0x20, 4); - dlpc_gpio_set_mode(0x21, 4); - dlpc_gpio_set_mode(0x23, 4); -} - -int dlpc_init(void) -{ - int timeout = 1000; - - /* Enable 14.318MHz CLK on CLKIN */ - dlpc_write_register(0x29, 0xa0); - while(!(dlpc_read_register(0x29) & 0x10) && timeout--) - udelay(1000); - - if (!timeout) - return 1; - - /* Select DLPC module */ - dlpc_write_register(0x07, 0x19); - /* DLPC Base Address */ - dlpc_write_register(0x60, (DLPC_CONTROL >> 8) & 0xff); - dlpc_write_register(0x61, DLPC_CONTROL & 0xff); - /* Activate DLPC */ - dlpc_write_register(0x30, 0x01); - - /* Reset docking state */ - outb(0x00, DLPC_CONTROL); - - dlpc_gpio_init(); - return 0; -} - -static int dock_superio_init(void) -{ - int timeout = 1000; - /* startup 14.318MHz Clock */ - dock_write_register(0x29, 0xa0); - /* wait until clock is settled */ - while(!(dock_read_register(0x29) & 0x10) && timeout--) - udelay(1000); - - if (!timeout) - return 1; - - /* set GPIO pins to Serial/Parallel Port - * functions - */ - dock_write_register(0x22, 0xa9); - - /* enable serial port */ - dock_write_register(0x07, PC87384_SP1); - dock_write_register(0x30, 0x01); - - dock_write_register(0x07, PC87384_GPIO); - dock_write_register(0x60, 0x16); - dock_write_register(0x61, 0x20); - /* enable GPIO */ - dock_write_register(0x30, 0x01); - - dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); - - dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); - - dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); - - dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); - - dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); - - dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); - - dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); - - dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); - - - /* no GPIO events enabled for PORT0 */ - outb(0x00, 0x1622); - /* clear GPIO events on PORT0 */ - outb(0xff, 0x1623); - outb(0xff, 0x1624); - /* no GPIO events enabled for PORT1 */ - outb(0x00, 0x1626); - - /* clear GPIO events on PORT1*/ - outb(0xff, 0x1627); - outb(0x1F, 0x1628); - outb(0xfd, 0x1620); - return 0; -} - -int dock_connect(void) -{ - int timeout = 1000; - - outb(0x07, DLPC_CONTROL); - - timeout = 1000; - - while(!(inb(DLPC_CONTROL) & 8) && timeout--) - udelay(1000); - - if (!timeout) { - /* docking failed, disable DLPC switch */ - outb(0x00, DLPC_CONTROL); - dlpc_write_register(0x30, 0x00); - return 1; - } - - /* Assert D_PLTRST# */ - outb(0xfe, 0x1680); - udelay(1000); - /* Deassert D_PLTRST# */ - outb(0xff, 0x1680); - udelay(10000); - - return dock_superio_init(); -} - -void dock_disconnect(void) -{ - /* disconnect LPC bus */ - outb(0x00, DLPC_CONTROL); - /* Assert PLTRST and DLPCPD */ - outb(0xfc, 0x1680); -} - -int dock_present(void) -{ - return pmh7_register_read(0x61) & 1; -} - -int legacy_io_present(void) -{ - return !(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40); -} - -void legacy_io_init(void) -{ - /* Enable Power for Ultrabay slot */ - pmh7_ultrabay_power_enable(1); - udelay(100000); - dock_superio_init(); -} diff --git a/src/mainboard/lenovo/z61t/dock.h b/src/mainboard/lenovo/z61t/dock.h deleted file mode 100644 index 6a9efc2ef9..0000000000 --- a/src/mainboard/lenovo/z61t/dock.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef THINKPAD_X60_DOCK_H -#define THINKPAD_X60_DOCK_H - -int dock_connect(void); -void dock_disconnect(void); -int dock_present(void); -int dlpc_init(void); - -int legacy_io_present(void); -void legacy_io_init(void); -#endif diff --git a/src/mainboard/lenovo/z61t/dsdt.asl b/src/mainboard/lenovo/z61t/dsdt.asl deleted file mode 100644 index 8f8c47dae6..0000000000 --- a/src/mainboard/lenovo/z61t/dsdt.asl +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define THINKPAD_EC_GPE 28 -#define BRIGHTNESS_UP \BRTU -#define BRIGHTNESS_DOWN \BRTD -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20090419 // OEM revision -) -{ - // Some generic macros - #include "acpi/platform.asl" - - // global NVS and variables - #include - #include - - // General Purpose Events - #include "acpi/gpe.asl" - - // mainboard specific devices - #include "acpi/mainboard.asl" - - Scope (\) - { - // backlight control, display switching, lid - #include "acpi/video.asl" - } - - #include - - Scope (\_SB) { - Device (PCI0) - { - #include - #include - } - } - - /* Chipset specific sleep states */ - #include - - // Dock support code - #include "acpi/dock.asl" -} diff --git a/src/mainboard/lenovo/z61t/gpio.c b/src/mainboard/lenovo/z61t/gpio.c deleted file mode 100644 index f220b2be0c..0000000000 --- a/src/mainboard/lenovo/z61t/gpio.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Arthur Heymans - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -static const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio1 = GPIO_MODE_GPIO, - .gpio6 = GPIO_MODE_GPIO, /* LEGACYIO# */ - .gpio7 = GPIO_MODE_GPIO, /* BDC_PRESENCE# */ - .gpio8 = GPIO_MODE_GPIO, /* H8_WAKE# */ - .gpio9 = GPIO_MODE_GPIO, - .gpio10 = GPIO_MODE_GPIO, /* MDI_DETECT */ - .gpio12 = GPIO_MODE_GPIO, /* H8SCI# */ - .gpio13 = GPIO_MODE_GPIO, - .gpio14 = GPIO_MODE_GPIO, /* CPUSB# */ - .gpio15 = GPIO_MODE_GPIO, /* CPPE# */ - .gpio19 = GPIO_MODE_GPIO, - .gpio22 = GPIO_MODE_GPIO, - .gpio24 = GPIO_MODE_GPIO, - .gpio25 = GPIO_MODE_GPIO, /* MDC_KILL# */ - .gpio26 = GPIO_MODE_GPIO, - .gpio27 = GPIO_MODE_GPIO, /* EXC_PWR_CTRL */ - .gpio28 = GPIO_MODE_GPIO, /* EXC_AUX_CTRL */ -}; - -static const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio1 = GPIO_DIR_INPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio19 = GPIO_DIR_OUTPUT, - .gpio22 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_OUTPUT, - .gpio25 = GPIO_DIR_OUTPUT, - .gpio26 = GPIO_DIR_OUTPUT, - .gpio27 = GPIO_DIR_OUTPUT, - .gpio28 = GPIO_DIR_OUTPUT, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio19 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_HIGH, - .gpio25 = GPIO_LEVEL_HIGH, - .gpio26 = GPIO_LEVEL_LOW, - .gpio27 = GPIO_LEVEL_HIGH, - .gpio28 = GPIO_LEVEL_HIGH, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio1 = GPIO_INVERT, - .gpio6 = GPIO_INVERT, - .gpio7 = GPIO_INVERT, - .gpio8 = GPIO_INVERT, - .gpio12 = GPIO_INVERT, - .gpio13 = GPIO_INVERT, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_blink = { -}; - -static const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio36 = GPIO_MODE_GPIO, /*PLANARID0 */ - .gpio37 = GPIO_MODE_GPIO, /*PLANARID1 */ - .gpio38 = GPIO_MODE_GPIO, /*PLANARID2 */ - .gpio39 = GPIO_MODE_GPIO, /*PLANARID3 */ - .gpio48 = GPIO_MODE_GPIO, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_INPUT, - .gpio38 = GPIO_DIR_INPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio48 = GPIO_DIR_OUTPUT, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio48 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .blink = &pch_gpio_set1_blink, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, -}; diff --git a/src/mainboard/lenovo/z61t/hda_verb.c b/src/mainboard/lenovo/z61t/hda_verb.c deleted file mode 100644 index 73eecf6671..0000000000 --- a/src/mainboard/lenovo/z61t/hda_verb.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * 2012 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -const u32 cim_verb_data[] = { - 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ - 0x17aa2025, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ - - AZALIA_SUBVENDOR(0x0, 0x17aa2025), - - AZALIA_PIN_CFG(0, 0x05, 0xc3014110), - AZALIA_PIN_CFG(0, 0x06, 0x4221401f), - AZALIA_PIN_CFG(0, 0x07, 0x591311f0), - AZALIA_PIN_CFG(0, 0x08, 0xc3a15020), - AZALIA_PIN_CFG(0, 0x09, 0x41813021), - AZALIA_PIN_CFG(0, 0x0a, 0x014470f0), - AZALIA_PIN_CFG(0, 0x16, 0x59f311f0), - AZALIA_PIN_CFG(0, 0x17, 0x59931122), - AZALIA_PIN_CFG(0, 0x18, 0x41a19023), - AZALIA_PIN_CFG(0, 0x19, 0x9933e12e) -}; -const u32 pc_beep_verbs[0] = {}; -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/z61t/mainboard.c b/src/mainboard/lenovo/z61t/mainboard.c deleted file mode 100644 index 5f599465a1..0000000000 --- a/src/mainboard/lenovo/z61t/mainboard.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define PANEL INT15_5F35_CL_DISPLAY_DEFAULT - -static acpi_cstate_t cst_entries[] = { - { 1, 1, 1000, { 0x7f, 1, 2, 0, 1, 0 } }, - { 2, 1, 500, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 0 } }, - { 3, 17, 250, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 0 } }, -}; - -int get_cst_entries(acpi_cstate_t **entries) -{ - *entries = cst_entries; - return ARRAY_SIZE(cst_entries); -} - -static void mainboard_init(struct device *dev) -{ - struct southbridge_intel_i82801gx_config *config; - struct device *idedev; - - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, - GMA_INT15_PANEL_FIT_DEFAULT, - PANEL, 3); - - /* If we're resuming from suspend, blink suspend LED */ - if (acpi_is_wakeup_s3()) - ec_write(0x0c, 0xc7); - - idedev = pcidev_on_root(0x1f, 1); - - if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) { - /* legacy I/O connected */ - pmh7_ultrabay_power_enable(1); - ec_write(0x0c, 0x84); - } else if (idedev && idedev->chip_info && - h8_ultrabay_device_present()) { - config = idedev->chip_info; - config->ide_enable_primary = 1; - pmh7_ultrabay_power_enable(1); - ec_write(0x0c, 0x84); - } else { - pmh7_ultrabay_power_enable(0); - ec_write(0x0c, 0x04); - } - - /* set dock status led */ - ec_write(0x0c, 0x08); - ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = mainboard_init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/lenovo/z61t/mptable.c b/src/mainboard/lenovo/z61t/mptable.c deleted file mode 100644 index 165b725ac6..0000000000 --- a/src/mainboard/lenovo/z61t/mptable.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int isa_bus; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &isa_bus); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR); - - /* Legacy Interrupts */ - mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); - - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, 0x02, 0x10); /* PCIe root 0.01.0 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, 0x02, 0x11); /* HD Audio 0:1b.0 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, 0x02, 0x14); /* PCIe 0:1c.0 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, 0x02, 0x10); /* USB 0:1d.0 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, 0x02, 0x11); /* USB 0:1d.1 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, 0x02, 0x13); /* USB 0:1d.3 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, 0x02, 0x17); /* LPC 0:1f.0 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ - smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ - smp_write_pci_intsrc(mc, mp_INT, 0x06, 0x00, 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */ - - mptable_lintsrc(mc, isa_bus); - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c deleted file mode 100644 index 7f12091ced..0000000000 --- a/src/mainboard/lenovo/z61t/romstage.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "dock.h" - -static void ich7_enable_lpc(void) -{ - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN - | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN - | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); - - /* range 0x1600 - 0x167f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601); - - /* range 0x15e0 - 0x15ef */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1); - - /* range 0x1680 - 0x169f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681); -} - -static void early_superio_config(void) -{ - int timeout = 100000; - pnp_devfn_t dev = PNP_DEV(0x2e, 3); - - pnp_write_config(dev, 0x29, 0xa0); - - while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) - udelay(1000); - - /* Enable COM1 */ - pnp_set_logical_device(dev); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_enable(dev, 1); -} - -static void rcba_config(void) -{ - /* Set up virtual channel 0 */ - RCBA32(V0CTL) = 0x80000001; - - /* Device 1f interrupt pin register */ - RCBA32(D31IP) = 0x00001230; - RCBA32(D29IP) = 0x40004321; - - /* PCIe Interrupts */ - RCBA32(D28IP) = 0x00004321; - /* HD Audio Interrupt */ - RCBA32(D27IP) = 0x00000002; - - /* dev irq route register */ - RCBA16(D31IR) = 0x1007; - RCBA16(D30IR) = 0x0076; - RCBA16(D29IR) = 0x3210; - RCBA16(D28IR) = 0x7654; - RCBA16(D27IR) = 0x0010; - - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - - /* Disable unused devices */ - RCBA32(FD) |= FD_INTLAN; - - /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - RCBA64(IOTR0) = 0x000200010000fe01ULL; - - /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ - RCBA64(IOTR3) = 0x000200f0000c0801ULL; -} - -static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} - -void mainboard_romstage_entry(void) -{ - int s3resume = 0; - int dock_err; - const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; - - enable_lapic(); - - ich7_enable_lpc(); - - /* We want early GPIO setup, to be able to detect legacy I/O module */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - /* Enable GPIOs */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */, 0x10); - setup_pch_gpios(&mainboard_gpio_map); - - dock_err = dlpc_init(); - - /* We prefer Legacy I/O module over docking */ - if (legacy_io_present()) { - legacy_io_init(); - early_superio_config(); - } else if (!dock_err && dock_present()) { - dock_connect(); - early_superio_config(); - } - - /* Setup the console */ - console_init(); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - system_reset(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - - if (CONFIG(DEBUG_RAM_SETUP)) - dump_spd_registers(); - - sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); -} diff --git a/src/mainboard/lenovo/z61t/smihandler.c b/src/mainboard/lenovo/z61t/smihandler.c deleted file mode 100644 index eacbd5e077..0000000000 --- a/src/mainboard/lenovo/z61t/smihandler.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "dock.h" -#include "smi.h" - -#define GPE_EC_SCI 12 - -#define LVTMA_BL_MOD_LEVEL 0x7af9 /* ATI Radeon backlight level */ - -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); - /* Enable 0x1600/0x1600 register pair */ - ec_set_bit(0x00, 0x05); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 *bar; - if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { - printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, - *(bar+LVTMA_BL_MOD_LEVEL)); - *(bar+LVTMA_BL_MOD_LEVEL) &= 0xf0; - if (*(bar+LVTMA_BL_MOD_LEVEL) > 0x10) - *(bar+LVTMA_BL_MOD_LEVEL) -= 0x10; - } -} - -static void mainboard_smi_brightness_up(void) -{ - u8 *bar; - if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { - printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, - *(bar+LVTMA_BL_MOD_LEVEL)); - *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f; - if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0) - *(bar+LVTMA_BL_MOD_LEVEL) += 0x10; - } -} - -int mainboard_io_trap_handler(int smif) -{ - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - - switch (smif) { - case SMI_DOCK_CONNECT: - /* If there's an legacy I/O module present, we're not - * allowed to connect the Docking LPC Bus, as both Super I/O - * chips are using 0x2e as base address. - */ - if (legacy_io_present()) - break; - - if (!dock_connect()) { - /* set dock LED to indicate status */ - ec_write(0x0c, 0x08); - ec_write(0x0c, 0x89); - } else { - /* blink dock LED to indicate failure */ - ec_write(0x0c, 0xc8); - ec_write(0x0c, 0x09); - } - break; - - case SMI_DOCK_DISCONNECT: - dock_disconnect(); - ec_write(0x0c, 0x09); - ec_write(0x0c, 0x08); - break; - - case SMI_BRIGHTNESS_UP: - mainboard_smi_brightness_up(); - break; - - case SMI_BRIGHTNESS_DOWN: - mainboard_smi_brightness_down(); - break; - - default: - return 0; - } - - /* On success, the IO Trap Handler returns 1 - * On failure, the IO Trap Handler returns a value != 1 */ - return 1; -} - -static void mainboard_smi_handle_ec_sci(void) -{ - u8 status = inb(EC_SC); - u8 event; - - if (!(status & EC_SCI_EVT)) - return; - - event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - /* brightness up */ - case 0x14: - mainboard_smi_brightness_up(); - break; - /* brightness down */ - case 0x15: - mainboard_smi_brightness_down(); - break; - /* Fn-F9 Key */ - case 0x18: - /* power loss */ - case 0x27: - /* undock event */ - case 0x50: - mainboard_io_trap_handler(SMI_DOCK_DISCONNECT); - break; - /* dock event */ - case 0x37: - mainboard_io_trap_handler(SMI_DOCK_CONNECT); - break; - default: - break; - } -} - -void mainboard_smi_gpi(u32 gpi) -{ - if (gpi & (1 << GPE_EC_SCI)) - mainboard_smi_handle_ec_sci(); -} - -int mainboard_smi_apmc(u8 data) -{ - switch (data) { - case APM_CNT_ACPI_ENABLE: - /* use 0x1600/0x1604 to prevent races with userspace */ - ec_set_ports(0x1604, 0x1600); - /* route H8SCI to SCI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); - break; - case APM_CNT_ACPI_DISABLE: - /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't - provide a EC query function */ - ec_set_ports(0x66, 0x62); - /* route H8SCI# to SMI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); - break; - default: - break; - } - return 0; -} diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 67f71cbfe7..07b50713c7 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -58,34 +58,21 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ - 0, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (C000) { + Name (_HID, "ACPI0007") + Name (_UID, 0) } - - Processor( - C001, /* name space name */ - 1, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (C001) { + Name (_HID, "ACPI0007") + Name (_UID, 1) } - Processor( - C002, /* name space name */ - 2, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (C002) { + Name (_HID, "ACPI0007") + Name (_UID, 2) } - Processor( - C003, /* name space name */ - 3, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (C003) { + Name (_HID, "ACPI0007") + Name (_UID, 3) } } /* End _PR scope */ diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index df49001676..347f1a1a02 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -58,34 +58,21 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ - 0, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (C000) { + Name (_HID, "ACPI0007") + Name (_UID, 0) } - - Processor( - C001, /* name space name */ - 1, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (C001) { + Name (_HID, "ACPI0007") + Name (_UID, 1) } - Processor( - C002, /* name space name */ - 2, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (C002) { + Name (_HID, "ACPI0007") + Name (_UID, 2) } - Processor( - C003, /* name space name */ - 3, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (C003) { + Name (_HID, "ACPI0007") + Name (_UID, 3) } } /* End _PR scope */ diff --git a/src/mainboard/msi/ms7707/dsdt.asl b/src/mainboard/msi/ms7707/dsdt.asl index 88085399b9..1aa87fe332 100644 --- a/src/mainboard/msi/ms7707/dsdt.asl +++ b/src/mainboard/msi/ms7707/dsdt.asl @@ -27,10 +27,10 @@ DefinitionBlock( /* Some generic macros */ #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Device (\_SB.PCI0) { diff --git a/src/mainboard/msi/ms7707/romstage.c b/src/mainboard/msi/ms7707/romstage.c index 30bb545328..a797f5099c 100644 --- a/src/mainboard/msi/ms7707/romstage.c +++ b/src/mainboard/msi/ms7707/romstage.c @@ -18,16 +18,10 @@ #include #include #include -#include #include void pch_enable_lpc(void) { - /* IO Decode Ranges Register */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); - /* LPC IF Enables Register (CNF2_LPC_EN|KBC_LPC_EN) */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400); - u16 reg16; reg16 = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xa4); reg16 |= (1 << 13); // WOL Enable Override (WOL_EN_OVRD) diff --git a/src/mainboard/msi/ms7721/acpi/cpstate.asl b/src/mainboard/msi/ms7721/acpi/cpstate.asl index 69de2d86a3..3cbc0ad60b 100644 --- a/src/mainboard/msi/ms7721/acpi/cpstate.asl +++ b/src/mainboard/msi/ms7721/acpi/cpstate.asl @@ -22,17 +22,25 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/msi/ms7721/mptable.c b/src/mainboard/msi/ms7721/mptable.c index 0811fd2e1c..8bfe4d535a 100644 --- a/src/mainboard/msi/ms7721/mptable.c +++ b/src/mainboard/msi/ms7721/mptable.c @@ -39,7 +39,7 @@ u8 intr_data[0x54] = { 0x10,0x11,0x12,0x13 }; -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; mc->mpc_entry_count++; diff --git a/src/mainboard/msi/ms9652_fam10/acpi_tables.c b/src/mainboard/msi/ms9652_fam10/acpi_tables.c index c81798587f..9f230df518 100644 --- a/src/mainboard/msi/ms9652_fam10/acpi_tables.c +++ b/src/mainboard/msi/ms9652_fam10/acpi_tables.c @@ -34,7 +34,7 @@ unsigned long acpi_fill_madt(unsigned long current) //extern unsigned char bus_mcp55[8]; //extern unsigned apicid_mcp55; - unsigned sbdn; + unsigned int sbdn; struct resource *res; struct device *dev; diff --git a/src/mainboard/msi/ms9652_fam10/dsdt.asl b/src/mainboard/msi/ms9652_fam10/dsdt.asl index f555c4d1ff..2115f4cc44 100644 --- a/src/mainboard/msi/ms9652_fam10/dsdt.asl +++ b/src/mainboard/msi/ms9652_fam10/dsdt.asl @@ -36,7 +36,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, OEM_ID, ACPI_TABLE_CREATOR, 1) Device (PCI0) { Name (_HID, EisaId ("PNP0A03")) - Name (_ADR, 0x00) Name (_UID, 0x00) Name (_BBN, 0x00) diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c index 74b14b42c8..d13a8130ed 100644 --- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c +++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c @@ -32,7 +32,7 @@ struct mb_sysconf_t mb_sysconf; void get_bus_conf(void) { - unsigned apicid_base; + unsigned int apicid_base; struct mb_sysconf_t *m; struct device *dev; diff --git a/src/mainboard/msi/ms9652_fam10/irq_tables.c b/src/mainboard/msi/ms9652_fam10/irq_tables.c index e33ceecbaa..69327dcafa 100644 --- a/src/mainboard/msi/ms9652_fam10/irq_tables.c +++ b/src/mainboard/msi/ms9652_fam10/irq_tables.c @@ -49,10 +49,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; - unsigned slot_num; + unsigned int slot_num; uint8_t *v; struct mb_sysconf_t *m; - unsigned sbdn; + unsigned int sbdn; uint8_t sum = 0; int i; @@ -96,8 +96,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) for (i = 1; i < sysconf.hc_possible_num; i++) { if (!(sysconf.pci1234[i] & 0x1)) continue; - unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; - unsigned devn = sysconf.hcdn[i] & 0xff; + unsigned int busn = (sysconf.pci1234[i] >> 12) & 0xff; + unsigned int devn = sysconf.hcdn[i] & 0xff; write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); diff --git a/src/mainboard/msi/ms9652_fam10/mb_sysconf.h b/src/mainboard/msi/ms9652_fam10/mb_sysconf.h index ddd6cfe38f..1a287c6a8a 100644 --- a/src/mainboard/msi/ms9652_fam10/mb_sysconf.h +++ b/src/mainboard/msi/ms9652_fam10/mb_sysconf.h @@ -20,7 +20,7 @@ struct mb_sysconf_t { unsigned char bus_mcp55[8]; //1 - unsigned apicid_mcp55; + unsigned int apicid_mcp55; }; #endif diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c index 13b5d92125..6ae3de18f0 100644 --- a/src/mainboard/msi/ms9652_fam10/mptable.c +++ b/src/mainboard/msi/ms9652_fam10/mptable.c @@ -26,7 +26,7 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; struct mb_sysconf_t *m; - unsigned sbdn; + unsigned int sbdn; int i, j, bus_isa; diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 2fc6fb42f0..4658d75427 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -52,7 +52,7 @@ inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -unsigned get_sbdn(unsigned bus) +unsigned int get_sbdn(unsigned int bus) { pci_devfn_t dev; diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig index ad4e9c7208..7d85bbba70 100644 --- a/src/mainboard/ocp/monolake/Kconfig +++ b/src/mainboard/ocp/monolake/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select IPMI_KCS + select VPD config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/ocp/monolake/ipmi.c b/src/mainboard/ocp/monolake/ipmi.c index 37aacc842e..3f178dc2cc 100644 --- a/src/mainboard/ocp/monolake/ipmi.c +++ b/src/mainboard/ocp/monolake/ipmi.c @@ -17,8 +17,6 @@ #include #include "ipmi.h" -#define BMC_KCS_BASE 0xca2 - int is_ipmi_clear_cmos_set(ipmi_oem_rsp_t *rsp) { int ret; diff --git a/src/mainboard/ocp/monolake/ipmi.h b/src/mainboard/ocp/monolake/ipmi.h index 5863eb5082..04649111c2 100644 --- a/src/mainboard/ocp/monolake/ipmi.h +++ b/src/mainboard/ocp/monolake/ipmi.h @@ -23,7 +23,7 @@ #define GET_CMOS_BIT(x) ((x) & (1 << 1)) #define GET_VALID_BIT(x) ((x) & (1 << 7)) #define CLEAR_CMOS_AND_VALID_BIT(x) ((x) &= 0x7d) - +#define BMC_KCS_BASE 0xca2 typedef struct { u8 BootMode; /* Bit 1:CMOS clear, bit 7:valid bit. */ u8 Boot0000; diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index 010e064c35..dffd19f0f0 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -19,7 +19,46 @@ #include #include #include +#include +#include +#include #include "ipmi.h" +/* VPD variable for enabling/disabling FRB2 timer. */ +#define FRB2_TIMER "FRB2_TIMER" +/* VPD variable for setting FRB2 timer countdown value. */ +#define FRB2_COUNTDOWN "FRB2_COUNTDOWN" +#define VPD_LEN 10 +/* Default countdown is 15 minutes. */ +#define DEFAULT_COUNTDOWN 9000 + +static void init_frb2_wdt(void) +{ + + char val[VPD_LEN]; + /* Enable FRB2 timer by default. */ + u8 enable = 1; + uint16_t countdown; + + if (vpd_get_bool(FRB2_TIMER, VPD_RW, &enable)) { + if (!enable) { + printk(BIOS_DEBUG, "Disable FRB2 timer\n"); + ipmi_stop_bmc_wdt(BMC_KCS_BASE); + } + } + if (enable) { + if (vpd_gets(FRB2_COUNTDOWN, val, VPD_LEN, VPD_RW)) { + countdown = (uint16_t)atol(val); + printk(BIOS_DEBUG, "FRB2 timer countdown set to: %d\n", + countdown); + } else { + printk(BIOS_DEBUG, "FRB2 timer use default value: %d\n", + DEFAULT_COUNTDOWN); + countdown = DEFAULT_COUNTDOWN; + } + ipmi_init_and_start_bmc_wdt(BMC_KCS_BASE, countdown, + TIMEOUT_HARD_RESET); + } +} /* * mainboard_enable is executed as first thing after enumerate_buses(). @@ -29,6 +68,7 @@ static void mainboard_enable(struct device *dev) { ipmi_oem_rsp_t rsp; + init_frb2_wdt(); if (is_ipmi_clear_cmos_set(&rsp)) { /* TODO: Should also try to restore CMOS to cmos.default * if USE_OPTION_TABLE is set */ diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index 8625868428..ef41b7720e 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2019 Wiwynn Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,10 +25,168 @@ #include #include #include +#include + /* Define the strings for UPD variables that could be customized */ #define FSP_VAR_HYPERTHREADING "HyperThreading" +static const struct gpio_config gpio_tables[] = { + /* PU_BMBUSY_N */ + {0, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* SKU_BDE_ID1 */ + {1, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_BDXDE_ERR0_LVT3_N */ + {2, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_BDXDE_ERR1_LVT3_N */ + {3, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_CPU2PCH_THROT_LVT3 */ + {4, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_BDXDE_CATERR_LVT3_N */ + {5, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* SKU_BDE_ID2 */ + {6, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* REV_BDE_ID0 */ + {7, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* RQ_BMC_PCH_NMI_NOA1_CLK */ + {8, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_USB_OC_5_N */ + {9, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_USB_OC_6_N */ + {10, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PU_SMBALERT_N */ + {11, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* RQ_IBMC_PCH_SMI_LPC_N */ + {12, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {13, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_LVC3_RISER1_ID4_N_PU */ + {14, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PD_P1V2_VDDQ_SEL_N */ + {15, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_CPU_THROTTLE_N */ + {16, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + /* SKU_BDE_ID0 */ + {17, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_SRC1CLKRQB */ + {18, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* RST_PCIE_PCH_N */ + {19, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* SMI_BMC_N_R */ + {20, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* M_SATA0GP */ + {21, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* SGPIO_SATA_CLOCK_R */ + {22, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* TP */ + {23, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FAST_THROTTLE_N_R */ + {24, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* BMC_READY_N */ + {25, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* TP */ + {26, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_CPLD */ + {27, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_BDXDE_ME_DRIVE_N */ + {28, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* H_BDXDE_PROCHOT_DISABLE */ + {29, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + /* SUSPWRDNACK */ + {30, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* SMB_INA230_ALRT_N */ + {31, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* TP */ + {32, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PD_DMI_RX_TERMINATION */ + {33, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + /* NC */ + {34, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NMI_BDE_R */ + {35, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* FM_BIOS_ADV_FUNCTIONS */ + {36, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_ADR_TRIGGER_N */ + {37, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* SGPIO_SATA_LOAD_R */ + {38, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* SGPIO_SATA_DATAOUT0_R */ + {39, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* FM_USB_OC_1_N */ + {40, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_USB_OC_2_N */ + {41, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_USB_OC_3_N */ + {42, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_USB_OC_4_N */ + {43, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* TP */ + {44, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* TP */ + {45, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_BIOS_POST_CMPLT_N */ + {46, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + /* NC */ + {47, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PU_SGPIO_SATA_DATAOUT1 */ + {48, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_XDP_PCH_OBSDATA */ + {49, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PU_GSXCLK */ + {50, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PU_GSXDOUT */ + {51, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PD_CPUSV */ + {52, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PD_GSXDIN */ + {53, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PU_GSXSREST_N */ + {54, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PU_BIOS_RCVR_BOOT_J2 */ + {55, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {56, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PU_ME_RCVR_N */ + {57, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* SMB_SML1_3V3SB_CLK */ + {58, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* FM_USB_OC_0_N */ + {59, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* SMB_SML0_3V3SB_ALERT */ + {60, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* SLP_SUS_STAT_N */ + {61, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* CLK_CPLD_SUSCLK_R */ + {62, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* NC */ + {63, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {64, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {65, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {66, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {67, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* REV_BDE_ID1 */ + {68, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* TPM_PRSNT_N */ + {69, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {70, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {71, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PU_BATLOW_N */ + {72, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {73, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PCHHOT_CPU_N */ + {74, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* SMB_SML1_3V3SB_DAT */ + {75, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {0xff, GPIO_LIST_END, 0, 0, 0, 0}, +}; + /** * /brief mainboard call for setup that needs to be done before fsp init * @@ -59,6 +218,9 @@ void late_mainboard_romstage_entry(void) // IPMI through BIC pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, 0x0c0ca1); + + // Initialize GPIOs + init_gpios(gpio_tables); } /* diff --git a/src/mainboard/opencellular/rotundu/dsdt.asl b/src/mainboard/opencellular/rotundu/dsdt.asl index 3719154bdd..bea6af7973 100644 --- a/src/mainboard/opencellular/rotundu/dsdt.asl +++ b/src/mainboard/opencellular/rotundu/dsdt.asl @@ -48,7 +48,7 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include #include "acpi/mainboard.asl" } diff --git a/src/mainboard/packardbell/ms2290/acpi/platform.asl b/src/mainboard/packardbell/ms2290/acpi/platform.asl index 9812d14bac..2371eab70f 100644 --- a/src/mainboard/packardbell/ms2290/acpi/platform.asl +++ b/src/mainboard/packardbell/ms2290/acpi/platform.asl @@ -14,40 +14,6 @@ * GNU General Public License for more details. */ -/* These come from the dynamically created CPU SSDT */ -External(PDC0) -External(PDC1) - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, /* APM command */ - APMS, 8 /* APM status */ -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) /* SMI Function */ - Store (0, TRP0) /* Generate trap */ - Return (SMIF) /* Return value of SMI handler */ -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index bb4e854e59..bf1c171222 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -48,6 +48,7 @@ chip northbridge/intel/nehalem device pci 00.0 on # Host bridge subsystemid 0x1025 0x0379 end + device pci 01.0 off end # PEG device pci 02.0 on # VGA controller subsystemid 0x1025 0x0379 end @@ -65,6 +66,13 @@ chip northbridge/intel/nehalem register "alt_gp_smi_en" = "0x0000" register "gen1_dec" = "0x040069" + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R, only management boot + device pci 16.3 off end # Management Engine KT + + device pci 19.0 off end # Ethernet + device pci 1a.0 on # USB2 EHCI subsystemid 0x1025 0x0379 end @@ -74,11 +82,18 @@ chip northbridge/intel/nehalem end device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 off end + device pci 1c.3 off end + device pci 1c.4 off end + device pci 1c.5 off end + device pci 1c.6 off end + device pci 1c.7 off end device pci 1d.0 on # USB2 EHCI subsystemid 0x1025 0x0379 end + device pci 1e.0 on end # PCI 2 PCI bridge device pci 1f.0 on # PCI-LPC bridge subsystemid 0x1025 0x0379 end @@ -88,6 +103,9 @@ chip northbridge/intel/nehalem device pci 1f.3 on # SMBUS subsystemid 0x1025 0x0379 end + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 off end end end end diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl index 92994c0601..72b7d4c78a 100644 --- a/src/mainboard/packardbell/ms2290/dsdt.asl +++ b/src/mainboard/packardbell/ms2290/dsdt.asl @@ -24,6 +24,8 @@ DefinitionBlock( 0x20140108 /* OEM revision */ ) { + #include + /* Some generic macros */ #include "acpi/platform.asl" @@ -46,7 +48,6 @@ DefinitionBlock( Device (UNCR) { Name (_BBN, 0xFF) - Name (_ADR, 0x00) Name (RID, 0x00) Name (_HID, EisaId ("PNP0A03")) Name (_CRS, ResourceTemplate () @@ -80,5 +81,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 809ccea597..f64e9e34c8 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -16,7 +16,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 5a4a9f1e71..4d94329b60 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -17,233 +17,36 @@ */ #include -#include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include #include #include -#include -#include +/* Seems copied from Lenovo Thinkpad x201, might be wrong */ +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* Enabled, Current table lookup index, OC map */ + { 1, IF1_557, 0 }, + { 1, IF1_55F, 1 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_557, 3 }, + { 1, IF1_14B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 4 }, + { 1, IF1_74B, 5 }, + { 1, IF1_55F, 7 }, + { 1, IF1_55F, 7 }, + { 1, IF1_557, 7 }, + { 1, IF1_55F, 7 }, +}; -static void pch_enable_lpc(void) +void mainboard_pre_raminit(void) { - /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x00040001); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - - pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0); - pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8); - - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); - - pci_write_config32(PCH_LPC_DEV, ETR3, - pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); } -static void rcba_config(void) +void mainboard_get_spd_map(u8 *spd_addrmap) { - southbridge_configure_default_intmap(); - - static const u32 rcba_dump3[] = { - /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, - /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, - /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000, - /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000, - /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000, - /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b, - /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000, - /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, - /* 3410 */ 0x00000c61, 0x00000000, 0x16fc1fe1, 0xbf4f001f, - /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, - /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000, - /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b, - /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b, - /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f, - /* 3530 */ 0x20000557, 0x2000055f, 0x00000000, 0x00000000, - /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3560 */ 0x00000001, 0x000026a3, 0x00040002, 0x01000052, - /* 3570 */ 0x02000772, 0x16000f8f, 0x1800ff4f, 0x0001d630, - /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35a0 */ 0xfc000201, 0x3c000201, 0x00000000, 0x00000000, - /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001, - /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000, - /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3650 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3660 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3670 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3680 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3690 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 36a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 36b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 36c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 36d0 */ 0x00000000, 0x089c0018, 0x00000000, 0x00000000, - /* 36e0 */ 0x11111111, 0x00000000, 0x00000000, 0x00000000, - /* 36f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3700 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3710 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3720 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000, - }; - unsigned i; - - for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3310) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3310); - } -} - -static inline void write_acpi32(u32 addr, u32 val) -{ - outl(val, DEFAULT_PMBASE | addr); -} - -static inline void write_acpi16(u32 addr, u16 val) -{ - outw(val, DEFAULT_PMBASE | addr); -} - -static inline u32 read_acpi32(u32 addr) -{ - return inl(DEFAULT_PMBASE | addr); -} - -// unused func - used for RE -#if 0 -static inline u16 read_acpi16(u32 addr) -{ - return inw(DEFAULT_PMBASE | addr); -} -#endif - -void mainboard_romstage_entry(void) -{ - u32 reg32; - int s3resume = 0; - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - - /* SERR pin is confused on reset. Clear NMI. */ - outb(4, 0x61); - outb(0, 0x61); - - enable_lapic(); - - nehalem_early_initialization(NEHALEM_MOBILE); - - pch_enable_lpc(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - console_init(); - - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - printk(BIOS_DEBUG, "a2: %02x\n", reg8); - if (!(reg8 & 0x20)) { - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); - } else { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - } else { - printk(BIOS_DEBUG, - "Resume from S3 detected, but disabled.\n"); - } - } - } - - /* Enable SMBUS. */ - enable_smbus(); - - write_acpi16(0x2, 0x0); - write_acpi32(0x28, 0x0); - write_acpi32(0x2c, 0x0); - if (!s3resume) { - read_acpi32(0x4); - read_acpi32(0x20); - read_acpi32(0x34); - write_acpi16(0x0, 0x900); - write_acpi32(0x20, 0xffff7ffe); - write_acpi32(0x34, 0x56974); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2); - } - - early_thermal_init(); - - timestamp_add_now(TS_BEFORE_INITRAM); - - chipset_init(s3resume); - raminit(s3resume, spd_addrmap); - - timestamp_add_now(TS_AFTER_INITRAM); - - intel_early_me_status(); - - if (s3resume) { - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } - - romstage_handoff_init(s3resume); + spd_addrmap[0] = 0x50; + spd_addrmap[2] = 0x52; } diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index dfc66f98cf..bc5067be1e 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -22,31 +22,6 @@ #include #include -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); -} - -int mainboard_io_trap_handler(int smif) -{ - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - - switch (smif) { - - default: - return 0; - } - - /* On success, the IO Trap Handler returns 1 - * On failure, the IO Trap Handler returns a value != 1 */ - return 1; -} - void mainboard_smi_gpi(u32 gpi_sts) { } diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig index b366418c16..3ab20f0b77 100644 --- a/src/mainboard/portwell/m107/Kconfig +++ b/src/mainboard/portwell/m107/Kconfig @@ -41,6 +41,12 @@ config ONBOARD_MEM_MICRON bool "Micron" help Micron MT41K512M16HA memory + +config ONBOARD_MEM_KINGSTON + bool "Kingston" + help + Kingston B5116ECMDXGGB memory + endchoice config MAINBOARD_DIR @@ -73,14 +79,6 @@ config FSP_LOC hex default 0xfff9c000 -config BOOTBLOCK_LOC - hex - default 0xFFFF0000 - -config BOOTBLOCK_SIZE - hex - default 0x10000 - config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n @@ -93,8 +91,4 @@ config C_ENV_BOOTBLOCK_SIZE hex "C Bootblock Size" default 0x4000 -config DRIVERS_INTEL_WIFI - bool - default n - endif # BOARD_PORTWELL_M107 diff --git a/src/mainboard/portwell/m107/Makefile.inc b/src/mainboard/portwell/m107/Makefile.inc index cca992e20c..7d4725efe4 100644 --- a/src/mainboard/portwell/m107/Makefile.inc +++ b/src/mainboard/portwell/m107/Makefile.inc @@ -25,3 +25,4 @@ ramstage-y += w25q64.c # Order of names in SPD_SOURCES is important! SPD_SOURCES = SAMSUNG_K4B8G1646D-MYKO SPD_SOURCES += MICRON_MT41K512M16HA-125A +SPD_SOURCES += KINGSTON_B5116ECMDXGGB diff --git a/src/mainboard/portwell/m107/acpi/superio.asl b/src/mainboard/portwell/m107/acpi/superio.asl index 0258e28216..e411f721dc 100644 --- a/src/mainboard/portwell/m107/acpi/superio.asl +++ b/src/mainboard/portwell/m107/acpi/superio.asl @@ -21,7 +21,6 @@ Device (COM1) { Name (_HID, EISAID ("PNP0501")) Name (_UID, 1) - Name (_ADR, 0) Method (_STA, 0, NotSerialized) { diff --git a/src/mainboard/portwell/m107/fadt.c b/src/mainboard/portwell/m107/fadt.c index 7814106a4c..82986f63b1 100644 --- a/src/mainboard/portwell/m107/fadt.c +++ b/src/mainboard/portwell/m107/fadt.c @@ -25,7 +25,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 3; + header->revision = ACPI_FADT_REV_ACPI_2_0; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/mainboard/portwell/m107/romstage.c b/src/mainboard/portwell/m107/romstage.c index 0fe76864ec..1307717b55 100644 --- a/src/mainboard/portwell/m107/romstage.c +++ b/src/mainboard/portwell/m107/romstage.c @@ -33,6 +33,9 @@ void mainboard_memory_init_params(struct romstage_params *params, if (CONFIG(ONBOARD_MEM_MICRON)) spd_index = 1; + else if (CONFIG(ONBOARD_MEM_KINGSTON)) + spd_index = 2; + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) die("spd.bin not found\n"); diff --git a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex new file mode 100644 index 0000000000..c018620d3b --- /dev/null +++ b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -0,0 +1,258 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Facebook, Inc. +# Copyright (C) 2019 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# +# 8 Gb DDR3 (1600 MHz 11-11-11) Kingston B5116ECMDXGGB +# +# SINGLE DIE +# + +# 64Mx16x8 ( 8 bank, 16 Rows, 10 Col, 2 KB page size ) +# 6-7-8-9-10-11 +# DDR3L-1600 +# tCk 1.25ns +# tRCD 13.75ns +# tRP 13.75ns +# tRAS 35ns +# tRC 48.75ns +# CL-tRCD-tRP 11-11-11 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 3 = 384 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +23 + +# 1 SPD Revision +# 0x10 = Revision 1.0 +10 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0c = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SODIMM +# bits[6:4]: 0 = Not hybrid +# bits[7]: 0 = Not hybrid +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bits[7]: reserverd +05 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 4 = 16 Row Address Bits +# bits[7:6]: 0 = reserved +21 + +# 6 Module Nominal Voltage +# bits[0]: 0 = 1.5V operable +# bits[1]: 1 = 1.35V operable +# bits[2]: 0 = NOT 1.25V operable +# bits[7:3]: reserved +02 + +# 7 Module Organization +# bits[2:0]: 010b = 16 bits SDRAM device +# bits[5:3]: 000b = 1 ranks +# bits[7:6]: reserved +02 + +# 8 Module Memory Bus width +# bits[2:0]: 3 = 64 bits pirmary bus width +# bits[4:3]: 0 = 0 bits bus witdth extension +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) dividend / divisor +# bits[3:0]: 1 = Divisor +# bits[7:4]: 1 = Dividend +11 + +# 10 Medium Timebase (MTB) dividend +# bits[7:0]: 0 = 1 (timebase 0.125ns) +01 + +# 11 Medium Timebase (MTB) divisor +# bits[7:0]: 8 (timebase 0.125ns) +08 + +# 12 SDRAM Minimum cycle time (tCKmin) +# 0xA tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +0A + +# 13 Reserved +00 + +# 14 CAS Latencies supported, Least Significate Byte +# Support 6,7,8,9,10,11 +FC + +# 15 CAS Latencies supported, Most Significate Byte +# No supporting CL 12-18 +00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x69 tAA = 13.125ns (offset = 00) DDR3-1600K downbin +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 tWR = 15 ns +78 + +# 18 Minimum RAS to CAS Delay Time (tRCDmin) +# 0x69 tRCD = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x3C tRRD = 7.5ns DDR3-1600, 2KB +3C + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x69 tRP = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 21 Upper Nibble for tRAS and tRC +# 3:0 : 1 higher tRAS = 35ns +# 7:0 : 1 higher tRC = 48.125ns +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant byte +# lower 0x118 : tRAS = 35ns DDR3-1600 +18 + +# 23 Minimum Active to Precharge Delay Time (tRCmin), Most Significant byte +# lower 0x181 : tRC = 48.125ns (offset 00) DDR3-1600K downbin +81 + +# 24 Minimum Refresh Recovery Delay time (tRFCmin), Least Significant byte +# lower 0xAF0 : tRFC = 350ns 8 Gb +F0 + +# 25 Minimum Refresh Recovery Delay time (tRFCmin), Most Significant byte +# higher 0xAF0 : tRFC = 350ns 8 Gb +0A + +# 26 tWTRmin +# 0x3C : tWTR = 7.5 ns (DDR3) +3C + +# 27 tRTPmin +# 0x3C : tRTP = 7.5 ns (DDR3) +3C + +# 28 Upper Nibble for tFAW +# Bit [3:0] : 1 = higher 0x140 tFAW = 40ns +01 + +# 29 tFAWmin Lower +# lower 0x140 : tFAW = 40ns +40 + +# 30 SDRAM Optional Features +# byte [0] : 1 = RZQ/6 is support +# byte [1] : 1 = RZQ/7 is supported +# byte [7] : 1 = DLL-Off Mode support +83 + +# 31 Thermal options +# byte [0] : 1 = 0 - 95C +# byte [2] : 0 = Auto Self Refresh (ASR) is not supported +# byte [7] : 0 = Partial Array Self Refres (PASR) is not supported +01 + +# 32 Module Thermal support +# byte [0] : 0 = Thermal sensor accuracy undefined +# byte [7] : 0 = No thermal sensor +00 + +# 33 SDRAM device type +# byte [1:0] : 00b = Signal Loading not specified +# byte [6:4] : 000b = Die count not specified +# byte [7] : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine tCKmin +# 0x00 tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +00 + +# 35 Fine tAAmin +# 0x00 tAA = 13.125ns (tAAmin offset = 00) DDR3-1600K downbin +00 + +# 36 Fine tRCDmin +# 0x00 tRCD = 13.125ns DDR3-1600K downbin +00 + +# 37 Fine tRPmin +# 0x00 tRP = 13.125ns (offset 00) DDR3-1600K downbin +00 + +# 38 Fine tRCmin +# 0x00 tRC = 48.125ns (offset 00) DDR3-1600K downbin +00 + +# 39-59 reserved, general section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60-116 Module specific section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 + +# 117-118 Module Manufacturer +01 98 + +# 119 Module Manufacturing Location +00 + +# 120-121 Module Manufacturing Date +13 0A + +# 122-125 Module Serial number +00 00 00 00 + +# 126-127 SPD CRC +00 00 + +# 128-145 Module Part number +66 53 49 49 54 69 67 77 68 88 71 71 66 00 00 00 +00 00 + +# 145-146 Module revision code +00 00 + +# 148-149 DRAM Manufacturer ID code +01 98 + +# 150-175 Manufacturer Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 + +# 176-255 Open for Customer Use + +# 176 - 255 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index 7f7519c73e..339d7012f7 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -6,8 +6,8 @@ config BOARD_PURISM_BASEBOARD_LIBREM_BDW select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT select SOC_INTEL_BROADWELL - select NO_POST # This platform does not have any way to see POST codes if BOARD_PURISM_BASEBOARD_LIBREM_BDW @@ -73,5 +73,8 @@ config VGA_BIOS_ID default "8086,1616" if BOARD_PURISM_LIBREM13_V1 default "8086,162b" if BOARD_PURISM_LIBREM15_V2 +# This platform has limited means to display POST codes +config NO_POST + default y endif diff --git a/src/mainboard/purism/librem_bdw/Makefile.inc b/src/mainboard/purism/librem_bdw/Makefile.inc index 16ce37a95f..13c0af4c8d 100644 --- a/src/mainboard/purism/librem_bdw/Makefile.inc +++ b/src/mainboard/purism/librem_bdw/Makefile.inc @@ -16,3 +16,5 @@ romstage-y += gpio.c romstage-y += variants/$(VARIANT_DIR)/pei_data.c ramstage-y += variants/$(VARIANT_DIR)/pei_data.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index bd49349cde..3cd4ef99ae 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -41,7 +41,7 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include /* Mainboard specific */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/purism/librem_bdw/gma-mainboard.ads b/src/mainboard/purism/librem_bdw/gma-mainboard.ads new file mode 100644 index 0000000000..1aba615128 --- /dev/null +++ b/src/mainboard/purism/librem_bdw/gma-mainboard.ads @@ -0,0 +1,28 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Internal, + HDMI1, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c index 0e1ad885b0..72b3fe25cd 100644 --- a/src/mainboard/purism/librem_bdw/romstage.c +++ b/src/mainboard/purism/librem_bdw/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb index e713cd2f56..98b5163b5f 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb @@ -6,9 +6,8 @@ chip soc/intel/broadwell # Enable DDI1 Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000200" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb index 3e83d3fb1a..32c3ed166f 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb @@ -6,9 +6,8 @@ chip soc/intel/broadwell # Enable DDI1 Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000200" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index ecde9e4774..a58ca0b718 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -7,10 +7,9 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL select INTEL_LPSS_UART_FOR_CONSOLE select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_SKYLAKE - select MAINBOARD_USES_FSP2_0 select SPD_READ_BY_WORD + select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM - select NO_POST # This platform does not have any way to see POST codes if BOARD_PURISM_BASEBOARD_LIBREM_SKL @@ -68,4 +67,8 @@ config CBFS_SIZE hex default 0xe00000 +# This platform has limited means to display POST codes +config NO_POST + default y + endif diff --git a/src/mainboard/purism/librem_skl/Makefile.inc b/src/mainboard/purism/librem_skl/Makefile.inc index 35f0f6cbde..ad4fd525dc 100644 --- a/src/mainboard/purism/librem_skl/Makefile.inc +++ b/src/mainboard/purism/librem_skl/Makefile.inc @@ -15,3 +15,5 @@ ramstage-y += ramstage.c ramstage-y += hda_verb.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/purism/librem_skl/dsdt.asl b/src/mainboard/purism/librem_skl/dsdt.asl index 1bf202ea47..1cd0531368 100644 --- a/src/mainboard/purism/librem_skl/dsdt.asl +++ b/src/mainboard/purism/librem_skl/dsdt.asl @@ -44,7 +44,7 @@ DefinitionBlock( } // Chipset specific sleep states - #include + #include // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/purism/librem_skl/gma-mainboard.ads b/src/mainboard/purism/librem_skl/gma-mainboard.ads new file mode 100644 index 0000000000..1aba615128 --- /dev/null +++ b/src/mainboard/purism/librem_skl/gma-mainboard.ads @@ -0,0 +1,28 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Internal, + HDMI1, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 944a2dddb5..deac4105f1 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -1,5 +1,13 @@ chip soc/intel/skylake + register "gpu_pp_up_delay_ms" = "200" + register "gpu_pp_down_delay_ms" = " 50" + register "gpu_pp_cycle_delay_ms" = "500" + register "gpu_pp_backlight_on_delay_ms" = " 1" + register "gpu_pp_backlight_off_delay_ms" = "200" + + register "gpu_pch_backlight_pwm_hz" = "200" + # Enable deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index 4ac06107a0..fd301cd9b3 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -1,5 +1,13 @@ chip soc/intel/skylake + register "gpu_pp_up_delay_ms" = "200" + register "gpu_pp_down_delay_ms" = " 50" + register "gpu_pp_cycle_delay_ms" = "500" + register "gpu_pp_backlight_on_delay_ms" = " 1" + register "gpu_pp_backlight_off_delay_ms" = "200" + + register "gpu_pch_backlight_pwm_hz" = "200" + # Enable deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" diff --git a/src/mainboard/razer/blade_stealth_kbl/Kconfig b/src/mainboard/razer/blade_stealth_kbl/Kconfig index 986a4df7bf..903d7baa4c 100644 --- a/src/mainboard/razer/blade_stealth_kbl/Kconfig +++ b/src/mainboard/razer/blade_stealth_kbl/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS select SUPERIO_ITE_IT8528E select SOC_INTEL_KABYLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select MAINBOARD_USES_FSP2_0 select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LIBGFXINIT @@ -17,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select ADD_FSP_BINARIES select FSP_USE_REPO - select NO_POST # For now no way to choose the correct the available RAM config BOARD_RAZER_BLADE_STEALTH_KBL_16GB @@ -52,4 +50,7 @@ config BOARD_SPECIFIC_OPTIONS int default 4 +config NO_POST + default y + endif diff --git a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl index e110067901..0112654950 100644 --- a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl +++ b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl @@ -43,7 +43,7 @@ DefinitionBlock( } // Chipset specific sleep states - #include + #include #include "acpi/mainboard.asl" } diff --git a/src/mainboard/razer/blade_stealth_kbl/romstage.c b/src/mainboard/razer/blade_stealth_kbl/romstage.c index 893d28a2ab..89903ab7c4 100644 --- a/src/mainboard/razer/blade_stealth_kbl/romstage.c +++ b/src/mainboard/razer/blade_stealth_kbl/romstage.c @@ -16,11 +16,9 @@ * GNU General Public License for more details. */ -#include #include #include #include -#include #include "spd/spd.h" #include #include diff --git a/src/mainboard/roda/rk886ex/dsdt.asl b/src/mainboard/roda/rk886ex/dsdt.asl index d33287445d..f9a2abed37 100644 --- a/src/mainboard/roda/rk886ex/dsdt.asl +++ b/src/mainboard/roda/rk886ex/dsdt.asl @@ -51,5 +51,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 93b24a0a47..19a0e4a5a1 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -70,13 +69,6 @@ static void pnp_exit_ext_func_mode(pnp_devfn_t dev) outb(0xaa, port); } -static void pnp_write_register(pnp_devfn_t dev, int reg, int val) -{ - unsigned int port = dev >> 8; - outb(reg, port); - outb(val, port+1); -} - static void early_superio_config(void) { pnp_devfn_t dev; @@ -84,30 +76,30 @@ static void early_superio_config(void) dev = PNP_DEV(0x2e, 0x00); pnp_enter_ext_func_mode(dev); - pnp_write_register(dev, 0x01, 0x94); /* Extended Parport modes */ - pnp_write_register(dev, 0x02, 0x88); /* UART power on */ - pnp_write_register(dev, 0x03, 0x72); /* Floppy */ - pnp_write_register(dev, 0x04, 0x01); /* EPP + SPP */ - pnp_write_register(dev, 0x14, 0x03); /* Floppy */ - pnp_write_register(dev, 0x20, (0x3f0 >> 2)); /* Floppy */ - pnp_write_register(dev, 0x23, (0x378 >> 2)); /* PP base */ - pnp_write_register(dev, 0x24, (0x3f8 >> 2)); /* UART1 base */ - pnp_write_register(dev, 0x25, (0x2f8 >> 2)); /* UART2 base */ - pnp_write_register(dev, 0x26, (2 << 4) | 0); /* FDC + PP DMA */ - pnp_write_register(dev, 0x27, (6 << 4) | 7); /* FDC + PP DMA */ - pnp_write_register(dev, 0x28, (4 << 4) | 3); /* UART1,2 IRQ */ + pnp_write_config(dev, 0x01, 0x94); /* Extended Parport modes */ + pnp_write_config(dev, 0x02, 0x88); /* UART power on */ + pnp_write_config(dev, 0x03, 0x72); /* Floppy */ + pnp_write_config(dev, 0x04, 0x01); /* EPP + SPP */ + pnp_write_config(dev, 0x14, 0x03); /* Floppy */ + pnp_write_config(dev, 0x20, (0x3f0 >> 2)); /* Floppy */ + pnp_write_config(dev, 0x23, (0x378 >> 2)); /* PP base */ + pnp_write_config(dev, 0x24, (0x3f8 >> 2)); /* UART1 base */ + pnp_write_config(dev, 0x25, (0x2f8 >> 2)); /* UART2 base */ + pnp_write_config(dev, 0x26, (2 << 4) | 0); /* FDC + PP DMA */ + pnp_write_config(dev, 0x27, (6 << 4) | 7); /* FDC + PP DMA */ + pnp_write_config(dev, 0x28, (4 << 4) | 3); /* UART1,2 IRQ */ /* These are the SMI status registers in the SIO: */ - pnp_write_register(dev, 0x30, (0x600 >> 4)); /* Runtime Register Block Base */ + pnp_write_config(dev, 0x30, (0x600 >> 4)); /* Runtime Register Block Base */ - pnp_write_register(dev, 0x31, 0x00); /* GPIO1 DIR */ - pnp_write_register(dev, 0x32, 0x00); /* GPIO1 POL */ - pnp_write_register(dev, 0x33, 0x40); /* GPIO2 DIR */ - pnp_write_register(dev, 0x34, 0x00); /* GPIO2 POL */ - pnp_write_register(dev, 0x35, 0xff); /* GPIO3 DIR */ - pnp_write_register(dev, 0x36, 0x00); /* GPIO3 POL */ - pnp_write_register(dev, 0x37, 0xe0); /* GPIO4 DIR */ - pnp_write_register(dev, 0x38, 0x00); /* GPIO4 POL */ - pnp_write_register(dev, 0x39, 0x80); /* GPIO4 POL */ + pnp_write_config(dev, 0x31, 0x00); /* GPIO1 DIR */ + pnp_write_config(dev, 0x32, 0x00); /* GPIO1 POL */ + pnp_write_config(dev, 0x33, 0x40); /* GPIO2 DIR */ + pnp_write_config(dev, 0x34, 0x00); /* GPIO2 POL */ + pnp_write_config(dev, 0x35, 0xff); /* GPIO3 DIR */ + pnp_write_config(dev, 0x36, 0x00); /* GPIO3 POL */ + pnp_write_config(dev, 0x37, 0xe0); /* GPIO4 DIR */ + pnp_write_config(dev, 0x38, 0x00); /* GPIO4 POL */ + pnp_write_config(dev, 0x39, 0x80); /* GPIO4 POL */ pnp_exit_ext_func_mode(dev); } @@ -149,12 +141,12 @@ static void early_ich7_init(void) uint32_t reg32; /* program secondary mlt XXX byte? */ - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); /* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); /* usb transient disconnect */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); @@ -169,31 +161,7 @@ static void early_ich7_init(void) reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - /* next step only on ich7m b0 and later: */ - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } static void init_artec_dongle(void) @@ -209,11 +177,6 @@ void mainboard_romstage_entry(void) enable_lapic(); - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0); - ich7_enable_lpc(); early_superio_config(); diff --git a/src/mainboard/roda/rk9/Makefile.inc b/src/mainboard/roda/rk9/Makefile.inc index 7ff15887ca..1140e11d0f 100644 --- a/src/mainboard/roda/rk9/Makefile.inc +++ b/src/mainboard/roda/rk9/Makefile.inc @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ## +bootblock-y += bootblock.c + romstage-y = gpio.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += ti_pci7xx1.c diff --git a/src/mainboard/roda/rk9/bootblock.c b/src/mainboard/roda/rk9/bootblock.c new file mode 100644 index 0000000000..454c3a0418 --- /dev/null +++ b/src/mainboard/roda/rk9/bootblock.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* Original settings: + idx 30 31 32 33 34 35 36 37 38 39 + val 60 00 00 40 00 ff 00 e0 00 80 + def 00 00 00 00 00 00 00 00 00 80 + + Values: + GP1 GP2 GP3 GP4 + fd 17 88 14 + */ + const pnp_devfn_t sio = PNP_DEV(0x2e, 0); + + /* Enter super-io's configuration state. */ + pnp_enter_conf_state(sio); + + /* Set lpc47n227's runtime register block's base address. */ + pnp_write_config(sio, 0x30, 0x600 >> 4); + + /* Set GP23 to alternate function. */ + pnp_write_config(sio, 0x33, 0x40); + + /* Set GP30 - GP37 to output mode: COM control */ + pnp_write_config(sio, 0x35, 0xff); + + /* Set GP45 - GP47 to output mode. */ + pnp_write_config(sio, 0x37, 0xe0); + + /* Set nIO_PME to open drain. */ + pnp_write_config(sio, 0x39, 0x80); + + /* Exit configuration state. */ + pnp_exit_conf_state(sio); + + /* Set GPIO output values: */ + outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */ + outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */ + + lpc47n227_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index 4300171207..ddb2ad72a9 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -67,6 +67,8 @@ chip northbridge/intel/gm45 # Maybe we should set less for Mini PCIe. register "pcie_power_limits" = "{ { 10, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 } }" + register "gen1_dec" = "0x000c0601" + device pci 19.0 off end # LAN device pci 1a.0 on # UHCI ioapic_irq 2 INTA 0x10 diff --git a/src/mainboard/roda/rk9/dsdt.asl b/src/mainboard/roda/rk9/dsdt.asl index f930a14aa1..e8fb13d22f 100644 --- a/src/mainboard/roda/rk9/dsdt.asl +++ b/src/mainboard/roda/rk9/dsdt.asl @@ -53,5 +53,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 497828b58a..48ca6b6b7d 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -14,72 +14,7 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include -#include #include -#include - -#define LPC_DEV PCI_DEV(0, 0x1f, 0) -#define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1) - -void mb_setup_lpc(void) -{ - /* Set up SuperIO LPC forwards */ - - /* Configure serial IRQs.*/ - pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0); - /* Map COMa on 0x3f8, COMb on 0x2f8. */ - pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); - /* Enable COMa, COMb, Kbd, SuperIO at 0x2e, MCs at 0x4e and 0x62/66. */ - pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3c03); -} - -void mb_setup_superio(void) -{ - /* Original settings: - idx 30 31 32 33 34 35 36 37 38 39 - val 60 00 00 40 00 ff 00 e0 00 80 - def 00 00 00 00 00 00 00 00 00 80 - - Values: - GP1 GP2 GP3 GP4 - fd 17 88 14 - */ - const pnp_devfn_t sio = PNP_DEV(0x2e, 0); - - /* Enter super-io's configuration state. */ - pnp_enter_conf_state(sio); - - /* Set lpc47n227's runtime register block's base address. */ - pnp_write_config(sio, 0x30, 0x600 >> 4); - - /* Set GP23 to alternate function. */ - pnp_write_config(sio, 0x33, 0x40); - - /* Set GP30 - GP37 to output mode: COM control */ - pnp_write_config(sio, 0x35, 0xff); - - /* Set GP45 - GP47 to output mode. */ - pnp_write_config(sio, 0x37, 0xe0); - - /* Set nIO_PME to open drain. */ - pnp_write_config(sio, 0x39, 0x80); - - /* Exit configuration state. */ - pnp_exit_conf_state(sio); - - /* Enable decoding of 0x600-0x60f through lpc. */ - pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x000c0601); - - /* Set GPIO output values: */ - outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */ - outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */ - - lpc47n227_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} void get_mb_spd_addrmap(u8 *spd_addrmap) { diff --git a/src/mainboard/roda/rk9/ti_pci7xx1.c b/src/mainboard/roda/rk9/ti_pci7xx1.c index 9f8e53ee2e..4154cc86bd 100644 --- a/src/mainboard/roda/rk9/ti_pci7xx1.c +++ b/src/mainboard/roda/rk9/ti_pci7xx1.c @@ -25,7 +25,7 @@ static void pci7xx1_enable(struct device *const dev) { printk(BIOS_DEBUG, "%s: TI PCI7xx1 media controller\n", __func__); if (PCI_FUNC(dev->path.pci.devfn) == 0) { - const unsigned slot = PCI_SLOT(dev->path.pci.devfn); + const unsigned int slot = PCI_SLOT(dev->path.pci.devfn); int fn; diff --git a/src/mainboard/roda/rv11/dsdt.asl b/src/mainboard/roda/rv11/dsdt.asl index 859b4cd157..67f88d0803 100644 --- a/src/mainboard/roda/rv11/dsdt.asl +++ b/src/mainboard/roda/rv11/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock( 0x20141018 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/platform.asl" @@ -50,5 +50,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/roda/rv11/variants/rv11/include/acpi/superio.asl b/src/mainboard/roda/rv11/variants/rv11/include/acpi/superio.asl index d1b2193a20..9de6da0a8e 100644 --- a/src/mainboard/roda/rv11/variants/rv11/include/acpi/superio.asl +++ b/src/mainboard/roda/rv11/variants/rv11/include/acpi/superio.asl @@ -1 +1 @@ -/* no super i/o */ +/* no Super I/O */ diff --git a/src/mainboard/roda/rv11/variants/rv11/romstage.c b/src/mainboard/roda/rv11/variants/rv11/romstage.c index 685e94237f..4491370cbf 100644 --- a/src/mainboard/roda/rv11/variants/rv11/romstage.c +++ b/src/mainboard/roda/rv11/variants/rv11/romstage.c @@ -23,10 +23,6 @@ void pch_enable_lpc(void) { - /* Enable KBC on 0x60/0x64 (KBC), - EC on 0x62/0x66 (MC) */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - KBC_LPC_EN | MC_LPC_EN); } void mainboard_config_superio(void) diff --git a/src/mainboard/roda/rv11/variants/rw11/romstage.c b/src/mainboard/roda/rv11/variants/rw11/romstage.c index 97d9d2b099..f355578b6e 100644 --- a/src/mainboard/roda/rv11/variants/rw11/romstage.c +++ b/src/mainboard/roda/rv11/variants/rw11/romstage.c @@ -27,14 +27,6 @@ void pch_enable_lpc(void) { - /* COMA on 0x3f8, COMB on 0x2f8 */ - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - /* Enable KBC on 0x60/0x64 (KBC), - EC on 0x62/0x66 (MC), - SIO on 0x2e/0x2f (CNF1) */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMB_LPC_EN | COMA_LPC_EN); } void mainboard_config_superio(void) diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 9e02d9a901..c70ee1d22e 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl index c007432581..7dd85b5cd6 100644 --- a/src/mainboard/samsung/lumpy/dsdt.asl +++ b/src/mainboard/samsung/lumpy/dsdt.asl @@ -24,7 +24,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/platform.asl" @@ -56,5 +56,5 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index f793963fd4..c64a51b7cb 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include "ec.h" #include "onboard.h" diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index f316b2256f..2cce8ad9fc 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl index 969ef66701..db8bfd45d2 100644 --- a/src/mainboard/samsung/stumpy/dsdt.asl +++ b/src/mainboard/samsung/stumpy/dsdt.asl @@ -24,7 +24,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // Some generic macros #include "acpi/platform.asl" @@ -53,5 +53,5 @@ DefinitionBlock( #include /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl index 60ba44b6aa..fee7e9356f 100644 --- a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -30,10 +30,10 @@ DefinitionBlock( // Some generic macros #include "acpi/platform.asl" #include - #include + #include /* global NVS and variables. */ #include - #include + #include Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c index c7d8f0f724..ff5bb701a8 100644 --- a/src/mainboard/sapphire/pureplatinumh61/romstage.c +++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c @@ -23,8 +23,6 @@ void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); } diff --git a/src/mainboard/scaleway/tagada/acpi/platform.asl b/src/mainboard/scaleway/tagada/acpi/platform.asl index ea66a9f974..8d8229ab43 100644 --- a/src/mainboard/scaleway/tagada/acpi/platform.asl +++ b/src/mainboard/scaleway/tagada/acpi/platform.asl @@ -16,44 +16,6 @@ * */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/scaleway/tagada/dsdt.asl b/src/mainboard/scaleway/tagada/dsdt.asl index 9bc42cf4de..c7e7f7c91b 100644 --- a/src/mainboard/scaleway/tagada/dsdt.asl +++ b/src/mainboard/scaleway/tagada/dsdt.asl @@ -27,6 +27,7 @@ DefinitionBlock( ) { // Some generic macros + #include #include "acpi/platform.asl" #include "acpi/mainboard.asl" @@ -50,5 +51,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/siemens/mc_apl1/dsdt.asl b/src/mainboard/siemens/mc_apl1/dsdt.asl index 9ce3ef8bc1..449bcf878f 100644 --- a/src/mainboard/siemens/mc_apl1/dsdt.asl +++ b/src/mainboard/siemens/mc_apl1/dsdt.asl @@ -42,5 +42,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd index 8c6dda8496..36772d6686 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd @@ -1,14 +1,14 @@ FLASH 16M { SI_DESC@0x0 0x1000 - IFWI@0x1000 0x2ff000 - FMAP@0x300000 0x800 - COREBOOT(CBFS)@0x300800 0xb9d800 - UNIFIED_MRC_CACHE@0xe9e000 0x21000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - RW_VAR_MRC_CACHE@0x20000 0x1000 + IFWI 0x2ff000 + FMAP 0x800 + COREBOOT(CBFS) 0xb9d800 + UNIFIED_MRC_CACHE 0x21000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + RW_VAR_MRC_CACHE 0x1000 } - BIOS_UNUSABLE@0xebf000 0x40000 - DEVICE_EXTENSION@0xeff000 0x100000 - UNUSED_HOLE@0xfff000 0x1000 + BIOS_UNUSABLE 0x40000 + DEVICE_EXTENSION 0x100000 + UNUSED_HOLE 0x1000 } diff --git a/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd index d1cbfcf7f7..8af2e9ab3f 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd @@ -1,30 +1,30 @@ FLASH 16M { WP_RO@0x0 0xe93000 { - SI_DESC@0x0 0x1000 - IFWI@0x1000 0x2ff000 - RO_VPD@0x300000 0x4000 - RO_SECTION@0x304000 0xb8f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - COREBOOT(CBFS)@0x1000 0xb4e000 - GBB@0xb4f000 0x40000 + SI_DESC 0x1000 + IFWI 0x2ff000 + RO_VPD 0x4000 + RO_SECTION 0xb8f000 { + FMAP 0x800 + RO_FRID 0x40 + RO_FRID_PAD 0x7c0 + COREBOOT(CBFS) 0xb4e000 + GBB 0x40000 } } - MISC_RW@0xe93000 0x2c000 { - UNIFIED_MRC_CACHE@0x0 0x21000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - RW_VAR_MRC_CACHE@0x20000 0x1000 + MISC_RW 0x2c000 { + UNIFIED_MRC_CACHE 0x21000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + RW_VAR_MRC_CACHE 0x1000 } - RW_SHARED@0x21000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 + RW_SHARED 0x4000 { + SHARED_DATA 0x2000 + VBLOCK_DEV 0x2000 } - RW_VPD@0x25000 0x2000 - RW_NVRAM@0x27000 0x5000 + RW_VPD 0x2000 + RW_NVRAM 0x5000 } - BIOS_UNUSABLE@0xebf000 0x40000 - DEVICE_EXTENSION@0xeff000 0x100000 - UNUSED_HOLE@0xfff000 0x1000 + BIOS_UNUSABLE 0x40000 + DEVICE_EXTENSION 0x100000 + UNUSED_HOLE 0x1000 } diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c index e0fec7c786..7401c74a01 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c @@ -363,7 +363,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1), /* SVID0_CLK */ }; -const struct pad_config *__weak variant_gpio_table(size_t *num) +const struct pad_config *variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; @@ -406,8 +406,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1), /* LPC_FRAME_N */ }; -const struct pad_config *__weak -variant_early_gpio_table(size_t *num) +const struct pad_config *variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c index f6578cb866..3edf14f8c2 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c @@ -363,7 +363,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1), /* SVID0_CLK */ }; -const struct pad_config *__weak variant_gpio_table(size_t *num) +const struct pad_config *variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; @@ -409,8 +409,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(PMIC_STDBY, 0, DEEP), }; -const struct pad_config *__weak -variant_early_gpio_table(size_t *num) +const struct pad_config *variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c index 5cef53ce2a..4f9c8406c6 100644 --- a/src/mainboard/siemens/mc_bdx1/mainboard.c +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -27,7 +27,6 @@ #include #endif #include -#include #include #include #include diff --git a/src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd b/src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd index cb7ef391e1..44502f607c 100644 --- a/src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd +++ b/src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd @@ -1,9 +1,9 @@ FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x300000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x2ff000 + SI_ALL 0x300000 { + SI_DESC 0x1000 + SI_ME 0x2ff000 } - SI_BIOS@0x300000 0xd00000 { + SI_BIOS 0xd00000 { RW_MRC_CACHE 0x10000 RW_SHARED 0x4000 { SHARED_DATA 0x2000 diff --git a/src/mainboard/siemens/mc_tcu3/dsdt.asl b/src/mainboard/siemens/mc_tcu3/dsdt.asl index 3719154bdd..bea6af7973 100644 --- a/src/mainboard/siemens/mc_tcu3/dsdt.asl +++ b/src/mainboard/siemens/mc_tcu3/dsdt.asl @@ -48,7 +48,7 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include #include "acpi/mainboard.asl" } diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index 9e12aa588f..955193fec2 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -21,7 +21,6 @@ #if CONFIG(VGA_ROM_RUN) #include #endif -#include #include #include #include "lcd_panel.h" @@ -69,10 +68,16 @@ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6]) * This is the earliest point to add customization. */ static void mainboard_enable(struct device *dev) +{ + +} + +static void mainboard_final(void *chip_info) { setup_lcd_panel(); } struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, + .final = mainboard_final, }; diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c index 414baeb089..56f51f9647 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.c +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Siemens AG + * Copyright (C) 2014-2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ #include #include #include - +#include #include "soc/i2c.h" #include "ptn3460.h" @@ -34,6 +34,7 @@ int ptn3460_init(char *hwi_block) uint8_t disp_con = 0, color_depth = 0; uint8_t edid_data[0x80]; uint8_t hwid[4], tcu31_hwid[4] = {7, 9, 2, 0}; + uint8_t i; if (!hwi_block || hwilib_find_blocks(hwi_block) != CB_SUCCESS) { printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", @@ -41,10 +42,6 @@ int ptn3460_init(char *hwi_block) return 1; } - status = i2c_init(PTN_I2C_CONTROLLER); - if (status) - return (PTN_BUS_ERROR | status); - /* Get all needed information from hwinfo block */ if (hwilib_get_field(Edid, edid_data, 0x80) != sizeof(edid_data)) { printk(BIOS_ERR, "LCD: No EDID data available in %s\n", @@ -69,8 +66,8 @@ int ptn3460_init(char *hwi_block) /* Select this table to be emulated */ ptn_select_edid(6); /* Read PTN configuration data */ - status = i2c_read(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF, - (u8*)&cfg, PTN_CONFIG_LEN); + status = i2c_read_bytes(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF, (u8 *) &cfg, + sizeof(struct ptn_3460_config)); if (status) return (PTN_BUS_ERROR | status); @@ -81,7 +78,6 @@ int ptn3460_init(char *hwi_block) cfg.lvds_interface_ctrl1 |= 0x0b; /* Turn on dual LVDS lane and clock */ if (color_depth == PF_COLOR_DEPTH_6BIT) cfg.lvds_interface_ctrl1 |= 0x20; /* Use 18 bits per pixel */ - cfg.lvds_interface_ctrl2 = 0x03; /* no clock spreading, 300 mV LVDS swing */ /* Swap LVDS even and odd lanes for HW-ID 7.9.2.0 only. */ if (hwilib_get_field(HWID, hwid, sizeof(hwid)) == sizeof(hwid) && @@ -89,20 +85,22 @@ int ptn3460_init(char *hwi_block) cfg.lvds_interface_ctrl3 = 0x01; /* swap LVDS even and odd */ } else cfg.lvds_interface_ctrl3 = 0x00; /* no LVDS signal swap */ - cfg.t2_delay = 1; /* Delay T2 (VDD to LVDS active) by 16 ms */ - cfg.t3_timing = 10; /* 500 ms from LVDS to backlight active */ - cfg.t12_timing = 20; /* 1 second re-power delay */ - cfg.t4_timing = 3; /* 150 ms backlight off to LVDS inactive */ - cfg.t5_delay = 1; /* Delay T5 (LVDS to VDD inactive) by 16 ms */ - cfg.backlight_ctrl = 0; /* Enable backlight control */ + cfg.t2_delay = 1; /* Delay T2 (VDD to LVDS active) by 16 ms */ + cfg.t3_timing = 10; /* 500 ms from LVDS to backlight active */ + cfg.t12_timing = 20; /* 1 second re-power delay */ + cfg.t4_timing = 3; /* 150 ms backlight off to LVDS inactive */ + cfg.t5_delay = 1; /* Delay T5 (LVDS to VDD inactive) by 16 ms */ + cfg.backlight_ctrl = 0; /* Enable backlight control */ /* Write back configuration data to PTN3460 */ - status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF, - (u8*)&cfg, PTN_CONFIG_LEN); - if (status) - return (PTN_BUS_ERROR | status); - else - return PTN_NO_ERROR; + for (i = 0; i < sizeof(struct ptn_3460_config); i++) { + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + i, + *(((uint8_t *) &cfg) + i)); + if (status) + return (PTN_BUS_ERROR | status); + } + + return PTN_NO_ERROR; } /** \brief This functions reads one desired EDID data structure from PTN3460 @@ -117,14 +115,13 @@ int ptn3460_read_edid(u8 edid_num, u8 *data) if (edid_num > PTN_MAX_EDID_NUM) return PTN_INVALID_EDID; /* First enable access to the desired EDID table */ - status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, - &edid_num, 1); + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, edid_num); if (status) return (PTN_BUS_ERROR | status); /* Now we can simply read back EDID-data */ - status = i2c_read(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_EDID_OFF, - data, PTN_EDID_LEN); + status = i2c_read_bytes(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_EDID_OFF, data, + PTN_EDID_LEN); if (status) return (PTN_BUS_ERROR | status); else @@ -139,22 +136,24 @@ int ptn3460_read_edid(u8 edid_num, u8 *data) int ptn3460_write_edid(u8 edid_num, u8 *data) { int status; + int i; if (edid_num > PTN_MAX_EDID_NUM) return PTN_INVALID_EDID; + /* First enable access to the desired EDID table */ - status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, - &edid_num, 1); + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, edid_num); if (status) return (PTN_BUS_ERROR | status); /* Now we can simply write EDID-data to ptn3460 */ - status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_EDID_OFF, - data, PTN_EDID_LEN); - if (status) - return (PTN_BUS_ERROR | status); - else - return PTN_NO_ERROR; + for (i = 0; i < PTN_EDID_LEN; i++) { + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_EDID_OFF + i, + data[i]); + if (status) + return (PTN_BUS_ERROR | status); + } + return PTN_NO_ERROR; } /** \brief This functions selects one of 7 EDID-tables inside PTN3460 @@ -171,8 +170,7 @@ int ptn_select_edid (u8 edid_num) return PTN_INVALID_EDID; /* Enable emulation of the desired EDID table */ val = (edid_num << 1) | 1; - status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 4, - &val, 1); + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 4, val); if (status) return (PTN_BUS_ERROR | status); else @@ -188,14 +186,19 @@ int ptn_select_edid (u8 edid_num) */ int ptn3460_flash_config(void) { - int status; + int status, i; struct ptn_3460_flash flash; flash.cmd = 0x01; /* perform erase and flash cycle */ flash.magic = 0x7845; /* Magic number to protect flash operation */ flash.trigger = 0x56; /* This value starts flash operation */ - status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_FLASH_CFG_OFF, - (u8*)&flash, PTN_FLASH_CFG_LEN); + + for (i = 0; i < sizeof(struct ptn_3460_flash); i++) { + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_FLASH_CFG_OFF+i, + *(((uint8_t *) &flash) + i)); + if (status) + return (PTN_BUS_ERROR | status); + } if (status) { return (PTN_BUS_ERROR | status); } else { diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c index 6279d9c060..0bb16d36b2 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c @@ -33,7 +33,7 @@ struct mb_sysconf_t mb_sysconf; void get_bus_conf(void) { - unsigned apicid_base; + unsigned int apicid_base; struct mb_sysconf_t *m; struct device *dev; diff --git a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c b/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c index e33ceecbaa..69327dcafa 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c +++ b/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c @@ -49,10 +49,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; - unsigned slot_num; + unsigned int slot_num; uint8_t *v; struct mb_sysconf_t *m; - unsigned sbdn; + unsigned int sbdn; uint8_t sum = 0; int i; @@ -96,8 +96,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) for (i = 1; i < sysconf.hc_possible_num; i++) { if (!(sysconf.pci1234[i] & 0x1)) continue; - unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; - unsigned devn = sysconf.hcdn[i] & 0xff; + unsigned int busn = (sysconf.pci1234[i] >> 12) & 0xff; + unsigned int devn = sysconf.hcdn[i] & 0xff; write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); diff --git a/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h index ddd6cfe38f..1a287c6a8a 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h +++ b/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h @@ -20,7 +20,7 @@ struct mb_sysconf_t { unsigned char bus_mcp55[8]; //1 - unsigned apicid_mcp55; + unsigned int apicid_mcp55; }; #endif diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c index d41551db27..cdb2980867 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c +++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c @@ -26,7 +26,7 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; struct mb_sysconf_t *m; - unsigned sbdn; + unsigned int sbdn; int i, j, bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 2750129859..6f6ac712c7 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -55,7 +55,7 @@ inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -unsigned get_sbdn(unsigned bus) +unsigned int get_sbdn(unsigned int bus) { pci_devfn_t dev; diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c index f32312d6dc..56ea43c7fe 100644 --- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c @@ -30,12 +30,12 @@ // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables struct mb_sysconf_t mb_sysconf; -unsigned sbdn3; +unsigned int sbdn3; void get_bus_conf(void) { - unsigned apicid_base; + unsigned int apicid_base; struct mb_sysconf_t *m; struct device *dev; diff --git a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c index 5248567739..b77e86209b 100644 --- a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c +++ b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c @@ -49,10 +49,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; - unsigned slot_num; + unsigned int slot_num; uint8_t *v; struct mb_sysconf_t *m; - unsigned sbdn; + unsigned int sbdn; uint8_t sum = 0; int i; @@ -96,8 +96,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) for (i = 1; i < sysconf.hc_possible_num; i++) { if (!(sysconf.pci1234[i] & 0x1)) continue; - unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; - unsigned devn = sysconf.hcdn[i] & 0xff; + unsigned int busn = (sysconf.pci1234[i] >> 12) & 0xff; + unsigned int devn = sysconf.hcdn[i] & 0xff; write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0); diff --git a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h index de45310c62..f93f9e8380 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h +++ b/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h @@ -20,13 +20,13 @@ struct mb_sysconf_t { unsigned char bus_mcp55[8]; //1 - unsigned apicid_mcp55; + unsigned int apicid_mcp55; unsigned char bus_8132_0; //7 unsigned char bus_8132_1; //8 unsigned char bus_8132_2; //9 - unsigned apicid_8132_1; - unsigned apicid_8132_2; + unsigned int apicid_8132_1; + unsigned int apicid_8132_2; }; #endif diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c index 8c884c4d65..7e6237f1f6 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mptable.c +++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c @@ -22,13 +22,13 @@ #include #include "mb_sysconf.h" -extern unsigned sbdn3; +extern unsigned int sbdn3; static void *smp_write_config_table(void *v) { struct mp_config_table *mc; struct mb_sysconf_t *m; - unsigned sbdn; + unsigned int sbdn; int i, j, bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 56d9f35ef2..7c489ca8dd 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -63,7 +63,7 @@ inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -unsigned get_sbdn(unsigned bus) +unsigned int get_sbdn(unsigned int bus) { pci_devfn_t dev; diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi/cpstate.asl b/src/mainboard/supermicro/h8scm_fam10/acpi/cpstate.asl index 206dd686f5..acaa5bae32 100644 --- a/src/mainboard/supermicro/h8scm_fam10/acpi/cpstate.asl +++ b/src/mainboard/supermicro/h8scm_fam10/acpi/cpstate.asl @@ -22,17 +22,25 @@ #include DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { + Scope (\_PR) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "cpstate.asl" } - Processor(CPU1,1,0x0,0x0) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "cpstate.asl" } - Processor(CPU2,2,0x0,0x0) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "cpstate.asl" } - Processor(CPU3,3,0x0,0x0) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "cpstate.asl" } } diff --git a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl index 84378458eb..4dfa9995b9 100644 --- a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl +++ b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl @@ -58,57 +58,34 @@ DefinitionBlock ( * */ Scope (\_PR) { /* define processor scope */ - Processor( - CPU0, /* name space name */ - 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) #include "acpi/cpstate.asl" } - - Processor( - CPU1, /* name space name */ - 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) #include "acpi/cpstate.asl" } - - Processor( - CPU2, /* name space name */ - 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) #include "acpi/cpstate.asl" } - - Processor( - CPU3, /* name space name */ - 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) #include "acpi/cpstate.asl" } - - Processor( - CPU4, /* name space name */ - 4, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU4) { + Name (_HID, "ACPI0007") + Name (_UID, 4) #include "acpi/cpstate.asl" } - - Processor( - CPU5, /* name space name */ - 5, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ - ) { + Device (CPU5) { + Name (_HID, "ACPI0007") + Name (_UID, 5) #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm-f/dsdt.asl index 3a587b65e3..57e9a864f5 100644 --- a/src/mainboard/supermicro/x10slm-f/dsdt.asl +++ b/src/mainboard/supermicro/x10slm-f/dsdt.asl @@ -19,9 +19,9 @@ DefinitionBlock("dsdt.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 0x20181220) { #include "acpi/platform.asl" - #include + #include #include - #include + #include #include Device (\_SB.PCI0) diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 541b23d5b5..a3ed8af972 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -12,6 +12,8 @@ config BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES select SUPERIO_ASPEED_AST2400 select GENERATE_SMBIOS_TABLES select IPMI_KCS + select MAINBOARD_NO_FSP_GOP + select SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND if BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES @@ -22,6 +24,7 @@ config MAINBOARD_FAMILY config MAINBOARD_PART_NUMBER string default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_TF + default "X11SSM-F" if BOARD_SUPERMICRO_X11SSM_F config MAINBOARD_DIR string @@ -30,6 +33,7 @@ config MAINBOARD_DIR config VARIANT_DIR string default "x11ssh-tf" if BOARD_SUPERMICRO_X11SSH_TF + default "x11ssm-f" if BOARD_SUPERMICRO_X11SSM_F config OVERRIDE_DEVICETREE string diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name index ec01b135f8..7b2eaaffcb 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name @@ -1,3 +1,7 @@ config BOARD_SUPERMICRO_X11SSH_TF bool "X11SSH-TF" select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES + +config BOARD_SUPERMICRO_X11SSM_F + bool "X11SSM-F" + select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc index a6d789e11c..cab662a4bf 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc +++ b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc @@ -18,5 +18,7 @@ bootblock-y += bootblock.c ramstage-y += ramstage.c +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c index 27653f5ae0..75afd2ead1 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c +++ b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c @@ -32,13 +32,7 @@ static void early_config_gpio(void) static void early_config_superio(void) { const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); - if (CONFIG(CONSOLE_SERIAL)) { - aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); - /* The serial output is garbeled before this timeout. - * FIXME: Find out why and remove delay. - */ - mdelay(1000); - } + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); } void bootblock_mainboard_early_init(void) diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index a5ff0c5df0..1b9dc271b6 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -17,8 +17,8 @@ chip soc/intel/skylake register "Device4Enable" = "1" register "SaGv" = "SaGv_Disabled" - # Disable SGX - register "sgx_enable" = "0" # SGX is broken in coreboot + # Enable SGX + register "sgx_enable" = "1" register "PrmrrSize" = "128 * MiB" register "pirqa_routing" = "PCH_IRQ11" @@ -59,46 +59,41 @@ chip soc/intel/skylake # superspeed_inter-chip_supplement (SSIC) disabled register "SsicPortEnable" = "0" - # USB configuration - # USB2/3 - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" - - # ? - register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" - - # USB4/5 - register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" - - # USB0/1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" - - # USB9/10 (USB3.0) - register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" - register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" - - # USB6/7 (USB3.0) - register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" - register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" - - # USB8 (USB3.0) - register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" - - # IPMI USB HUB - register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + # USB + register "usb2_ports" = "{ + [0] = USB2_PORT_EMPTY, + [1] = USB2_PORT_EMPTY, + [2] = USB2_PORT_EMPTY, + [3] = USB2_PORT_EMPTY, + [4] = USB2_PORT_EMPTY, + [5] = USB2_PORT_EMPTY, + [6] = USB2_PORT_EMPTY, + [7] = USB2_PORT_EMPTY, + [8] = USB2_PORT_EMPTY, + [9] = USB2_PORT_EMPTY, + [10] = USB2_PORT_EMPTY, + [11] = USB2_PORT_EMPTY, + [12] = USB2_PORT_EMPTY, + [13] = USB2_PORT_EMPTY, + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_EMPTY, + [1] = USB3_PORT_EMPTY, + [2] = USB3_PORT_EMPTY, + [3] = USB3_PORT_EMPTY, + [4] = USB3_PORT_EMPTY, + [5] = USB3_PORT_EMPTY, + [6] = USB3_PORT_EMPTY, + [7] = USB3_PORT_EMPTY, + [8] = USB3_PORT_EMPTY, + [9] = USB3_PORT_EMPTY, + }" # LPC register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + register "s0ix_enable" = "1" register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" diff --git a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl index ac929a6bc4..86ea299aa9 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl +++ b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl @@ -43,7 +43,7 @@ DefinitionBlock( } // Chipset specific sleep states - #include + #include // Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h b/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h new file mode 100644 index 0000000000..a2047d4cdf --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _BASEBOARD_X11_LGA1151_SERIES_H +#define _BASEBOARD_X11_LGA1151_SERIES_H + +#include + +void variant_mainboard_init(struct device *dev); + +#endif /* _BASEBOARD_X11_LGA1151_SERIES_H */ diff --git a/src/soc/intel/skylake/acpi/sleepstates.asl b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c similarity index 51% rename from src/soc/intel/skylake/acpi/sleepstates.asl rename to src/mainboard/supermicro/x11-lga1151-series/mainboard.c index 905a3e2e50..750c8561a6 100644 --- a/src/soc/intel/skylake/acpi/sleepstates.asl +++ b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c @@ -2,8 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,7 +15,27 @@ * GNU General Public License for more details. */ -Name (\_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) -Name (\_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) -Name (\_S4, Package () { 0x6, 0x6, 0x0, 0x0 }) -Name (\_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) +#include +#include + +__weak void variant_mainboard_init(struct device *dev) +{ +} + +static void mainboard_init(struct device *dev) +{ + /* do common init */ + // placeholder for common mainboard initialization + + /* do variant init */ + variant_mainboard_init(dev); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 09aa8b558c..3e587dc817 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -33,6 +33,42 @@ chip soc/intel/skylake # FIXME: find out why FSP crashes without this register "PchHdaVcType" = "Vc1" + # USB configuration + # USB2/3 + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + + # ? + register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" + + # USB4/5 + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" + + # USB0/1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + + # USB9/10 (USB3.0) + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" + + # USB6/7 (USB3.0) + register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" + + # USB8 (USB3.0) + register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" + + # IPMI USB HUB + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + device domain 0 on device pci 01.0 on end # unused device pci 01.1 on # PCIE Slot (JPCIE1) diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/Makefile.inc new file mode 100644 index 0000000000..f3c87b2318 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += mainboard.c diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/board_info.txt b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/board_info.txt new file mode 100644 index 0000000000..a914412ad9 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Vendor name: Supermicro +Board name: X11SSM-F +Board URL: https://www.supermicro.com/en/products/motherboard/X11SSM-F +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h new file mode 100644 index 0000000000..6a25128c5a --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h @@ -0,0 +1,269 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_X11SSM_F_H +#define _GPIO_X11SSM_F_H + +#include +#include + +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + _PAD_CFG_STRUCT(GPP_A0, 0x44000700, 0x00000010), /* RCIN# */ + _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */ + _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */ + _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */ + _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */ + _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */ + _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */ + _PAD_CFG_STRUCT(GPP_A7, 0x44000700, 0x00000010), /* PIRQA# */ + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */ + _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */ + _PAD_CFG_STRUCT(GPP_A11, 0x44000700, 0x00000010), /* PME# */ + _PAD_CFG_STRUCT(GPP_A12, 0x84000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000010), /* SUSWARN#/SUSPWRDNACK */ + _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000010), /* SUS_STAT# */ + _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x00000010), /* SUS_ACK# */ + _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000010), /* CLKOUT_48 */ + _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000010), /* GPIO */ + /* reserved */ + //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffffff), /* ISH_GP1 */ + _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_B */ + _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000010), /* SLP_S0# */ + _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000010), /* PLTRST# */ + _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000010), /* SPKR */ + _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000010), /* PCHHOT# */ + + /* GPIO Group GPP_C */ + /* reserved */ + //_PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x00000010), /* SMBCLK */ + //_PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x00000010), /* SMBDATA */ + _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000010), /* GPIO */ + /* reserved */ + //_PAD_CFG_STRUCT(GPP_C3, 0x44000700, 0x00000010), /* SML0CLK */ + //_PAD_CFG_STRUCT(GPP_C4, 0x44000700, 0x00000010), /* SML0DATA */ + _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000010), /* GPIO */ + /* reserved */ + //_PAD_CFG_STRUCT(GPP_C6, 0x44000700, 0x00000010), /* SML1CLK */ + //_PAD_CFG_STRUCT(GPP_C7, 0x44000700, 0x00000010), /* SML1DATA */ + _PAD_CFG_STRUCT(GPP_C8, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C10, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C22, 0x42040100, 0x00003010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_D */ + _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D2, 0x42020100, 0x00003000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D22, 0x04000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_E */ + _PAD_CFG_STRUCT(GPP_E0, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E6, 0x82020100, 0x00003000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000010), /* SATA_LED# */ + _PAD_CFG_STRUCT(GPP_E9, 0x44000700, 0x00000010), /* USB_OC0# */ + _PAD_CFG_STRUCT(GPP_E10, 0x44000700, 0x00000010), /* USB_OC1# */ + _PAD_CFG_STRUCT(GPP_E11, 0x44000700, 0x00000010), /* USB_OC2# */ + _PAD_CFG_STRUCT(GPP_E12, 0x44000700, 0x00000010), /* USB_OC3# */ + + /* GPIO Group GPP_F */ + _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F5, 0x80100100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F9, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000010), /* SATA_SCLOCK */ + _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000010), /* SATA_SLOAD */ + _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000010), /* SATA_SDATAOUT1 */ + _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000010), /* SATA_SDATAOUT2 */ + _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x00000010), /* USB_OC4# */ + _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x00000010), /* USB_OC5# */ + _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_G */ + _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G2, 0x44000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G14, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000010), /* NMI# */ + _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000010), /* SMI# */ + _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_H */ + _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H1, 0x84000101, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H3, 0x44000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H4, 0x84000101, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H10, 0x44000700, 0x00000010), /* SML2CLK */ + _PAD_CFG_STRUCT(GPP_H11, 0x44000700, 0x00000010), /* SML2DATA */ + _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H13, 0x44000700, 0x00000010), /* SML3CLK */ + _PAD_CFG_STRUCT(GPP_H14, 0x44000700, 0x00000010), /* SML3DATA */ + _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H16, 0x44000700, 0x00000010), /* SML4CLK */ + _PAD_CFG_STRUCT(GPP_H17, 0x44000700, 0x00000010), /* SML4DATA */ + _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000010), /* GPIO */ + + /* GPIO Group GPP_I */ + _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000010), /* DDPB_HPD0 */ + _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000010), /* DDPC_HPD1 */ + _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000010), /* DDPD_HPD2 */ + _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000010), /* DDPE_HPD3 */ + _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000010), /* DDPB_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000010), /* DDPB_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000010), /* DDPC_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000010), /* DDPC_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000010), /* DDPD_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000010), /* DDPD_CTRLDATA */ + + /* GPIO Group GPD */ + _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD2, 0x04000700, 0x00000010), /* LAN_WAKE# */ + _PAD_CFG_STRUCT(GPD3, 0x04000700, 0x00000010), /* PWRBTN# */ + _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000010), /* SLP_S3# */ + _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000010), /* SLP_S4# */ + _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000010), /* SLP_A# */ + _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000010), /* SUSCLK */ + _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000010), /* GPIO */ +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* GPIO Group GPP_A */ + /* LPC */ + _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */ + _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */ + _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */ + _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */ + _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */ + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */ + _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */ + + /* Serial interrupt */ + _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */ +}; + +#endif /* _GPIO_X11SSM_F_H */ diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c new file mode 100644 index 0000000000..7cf8883dd6 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +void variant_mainboard_init(struct device *dev) +{ + /* TODO: + * Find out why the polarities from gpio.h gets overwritten by FSP. + * This sets irq polarity to the same values as vendor + * but I do not know if this is really needed.... + */ + itss_set_irq_polarity(33, 0); + itss_set_irq_polarity(34, 0); + + // TODO: NMI; is this needed? vendor sets it + pcr_write32(0xae, 0x01e4, 0x00000004); + pcr_write32(0xae, 0x01e8, 0x00000040); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb new file mode 100644 index 0000000000..ea90e0b0ba --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -0,0 +1,124 @@ +chip soc/intel/skylake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_G" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + register "gen3_dec" = "0x000c03e1" # UART3 + register "gen4_dec" = "0x000c02e1" # UART4 + + # PCIe configuration + register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4 + register "PcieRpEnable[4]" = "1" # Enable PCH PCIe Port 5 / PCH SLOT5 + register "PcieRpEnable[8]" = "1" # Enable PCH PCIe Port 9 / GbE 1 + register "PcieRpEnable[9]" = "1" # Enable PCH PCIe Port 10 / GbE 2 + register "PcieRpEnable[10]" = "1" # Enable PCH PCIe Port 11 / Aspeed 2400 VGA + + # USB configuration + # USB0/1 + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + + # USB2/3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" + + # USB4/5 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + + # USB6/7 (USB3.0) + register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)" + + # USB8/9 (USB3.0) + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" + register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + + # USB10 (USB3.0) + register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC5)" + + # IPMI USB HUB + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" + + device domain 0 on + device pci 01.0 on # CPU PCIe Port (x16) / PCIe Slot 6 (JPCIE6) + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" + end + device pci 01.1 on # CPU PCIe Port (x8) / PCIe Slot 7 (JPCIE7) + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X" + end + device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4) + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" + end + device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5) + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" + end + device pci 1d.0 on # PCH PCIe Port 9 + device pci 00.0 on end # GbE 1 + end + device pci 1d.1 on # PCH PCIe Port 10 + device pci 00.1 on end # GbE 2 + end + device pci 1d.2 on # PCH PCIe Port 11 + device pci 00.0 on # Aspeed PCI Bridge + device pci 00.0 on end # Aspeed 2400 VGA + end + end + device pci 1f.0 on # LPC Interface + chip drivers/ipmi + # On cold boot it takes a while for the BMC to start the IPMI service + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 on end # IPMI KCS + end + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 / COM1 (ext) + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 / COM2 (int) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 + irq 0x70 = 0xb + end + device pnp 2e.5 off end # KBC + device pnp 2e.7 on end # GPIO + device pnp 2e.b on # SUART3 + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.c on # SUART4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.d on end # iLPC2AHB + device pnp 2e.e on # Mailbox + io 0x60 = 0xa40 + irq 0x70 = 0x00 + end + end + end + end + end + end +end diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c index f589ef6c8d..7155813394 100644 --- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c +++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c @@ -32,7 +32,7 @@ struct mb_sysconf_t mb_sysconf; void get_bus_conf(void) { - unsigned apicid_base; + unsigned int apicid_base; struct mb_sysconf_t *m; struct device *dev; diff --git a/src/mainboard/tyan/s2912_fam10/irq_tables.c b/src/mainboard/tyan/s2912_fam10/irq_tables.c index e33ceecbaa..69327dcafa 100644 --- a/src/mainboard/tyan/s2912_fam10/irq_tables.c +++ b/src/mainboard/tyan/s2912_fam10/irq_tables.c @@ -49,10 +49,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; - unsigned slot_num; + unsigned int slot_num; uint8_t *v; struct mb_sysconf_t *m; - unsigned sbdn; + unsigned int sbdn; uint8_t sum = 0; int i; @@ -96,8 +96,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) for (i = 1; i < sysconf.hc_possible_num; i++) { if (!(sysconf.pci1234[i] & 0x1)) continue; - unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; - unsigned devn = sysconf.hcdn[i] & 0xff; + unsigned int busn = (sysconf.pci1234[i] >> 12) & 0xff; + unsigned int devn = sysconf.hcdn[i] & 0xff; write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); diff --git a/src/mainboard/tyan/s2912_fam10/mb_sysconf.h b/src/mainboard/tyan/s2912_fam10/mb_sysconf.h index ddd6cfe38f..1a287c6a8a 100644 --- a/src/mainboard/tyan/s2912_fam10/mb_sysconf.h +++ b/src/mainboard/tyan/s2912_fam10/mb_sysconf.h @@ -20,7 +20,7 @@ struct mb_sysconf_t { unsigned char bus_mcp55[8]; //1 - unsigned apicid_mcp55; + unsigned int apicid_mcp55; }; #endif diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c index 1781a6627d..5563aef2cf 100644 --- a/src/mainboard/tyan/s2912_fam10/mptable.c +++ b/src/mainboard/tyan/s2912_fam10/mptable.c @@ -26,7 +26,7 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; struct mb_sysconf_t *m; - unsigned sbdn; + unsigned int sbdn; int i, j, bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index f44346bbb6..c546a3309f 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -62,7 +62,7 @@ inline int spd_read_byte(unsigned int device, unsigned int address) #include #include "southbridge/nvidia/mcp55/early_setup_car.c" -unsigned get_sbdn(unsigned bus) +unsigned int get_sbdn(unsigned int bus) { pci_devfn_t dev; diff --git a/src/mainboard/up/squared/dsdt.asl b/src/mainboard/up/squared/dsdt.asl index 48b24b9190..6fccf4917c 100644 --- a/src/mainboard/up/squared/dsdt.asl +++ b/src/mainboard/up/squared/dsdt.asl @@ -39,5 +39,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/up/squared/ramstage.c b/src/mainboard/up/squared/ramstage.c index be70ea995a..637b8d87c9 100644 --- a/src/mainboard/up/squared/ramstage.c +++ b/src/mainboard/up/squared/ramstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index c6457a3998..01aedab94d 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -645,7 +645,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G mem_hole.node_id = i; break; //only one hole } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 928d9d2e8a..a05125593b 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -661,7 +661,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G mem_hole.node_id = i; break; //only one hole } diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index 3f2b138533..dc0f6840e2 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -50,11 +50,11 @@ void enumerate_ht_chain(void) * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ - unsigned next_unitid, last_unitid = 0; + unsigned int next_unitid, last_unitid = 0; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 // let't record the device of last ht device, So we can set the // Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE - unsigned real_last_unitid = 0; + unsigned int real_last_unitid = 0; u8 real_last_pos = 0; int ht_dev_num = 0; // except host_bridge u8 end_used = 0; @@ -96,8 +96,8 @@ void enumerate_ht_chain(void) pci_io_write_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS, flags); flags = pci_io_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); if ((flags >> 13) == 0) { - unsigned count; - unsigned ctrl, ctrl_off; + unsigned int count; + unsigned int ctrl, ctrl_off; pci_devfn_t devx; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 79f43db387..df1d947cdb 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -62,7 +62,7 @@ static struct device *__f0_dev[FX_DEVS]; struct device *__f1_dev[FX_DEVS]; static struct device *__f2_dev[FX_DEVS]; static struct device *__f4_dev[FX_DEVS]; -static unsigned fx_devs = 0; +static unsigned int fx_devs = 0; struct device *get_node_pci(u32 nodeid, u32 fn) { @@ -94,14 +94,14 @@ static void get_fx_devs(void) } } -static u32 f1_read_config32(unsigned reg) +static u32 f1_read_config32(unsigned int reg) { if (fx_devs == 0) get_fx_devs(); return pci_read_config32(__f1_dev[0], reg); } -static void f1_write_config32(unsigned reg, u32 value) +static void f1_write_config32(unsigned int reg, u32 value) { int i; if (fx_devs == 0) @@ -118,7 +118,7 @@ static void f1_write_config32(unsigned reg, u32 value) u32 amdfam10_nodeid(struct device *dev) { #if NODE_NUMS == 64 - unsigned busn; + unsigned int busn; busn = dev->bus->secondary; if (busn != CONFIG_CBB) { return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; @@ -361,11 +361,11 @@ static void amdfam10_scan_chains(struct device *dev) } -static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, - unsigned goal_link) +static int reg_useable(unsigned int reg, struct device *goal_dev, unsigned int goal_nodeid, + unsigned int goal_link) { struct resource *res; - unsigned nodeid, link = 0; + unsigned int nodeid, link = 0; int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { @@ -389,7 +389,7 @@ static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_node return result; } -static struct resource *amdfam10_find_iopair(struct device *dev, unsigned nodeid, unsigned link) +static struct resource *amdfam10_find_iopair(struct device *dev, unsigned int nodeid, unsigned int link) { struct resource *resource; u32 free_reg, reg; @@ -514,7 +514,7 @@ static void amdfam10_set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; - unsigned reg, link_num; + unsigned int reg, link_num; char buf[50]; /* Make certain the resource has actually been set */ @@ -564,7 +564,7 @@ static void amdfam10_set_resource(struct device *dev, struct resource *resource, * but it is too difficult to deal with the resource allocation magic. */ -static void amdfam10_create_vga_resource(struct device *dev, unsigned nodeid) +static void amdfam10_create_vga_resource(struct device *dev, unsigned int nodeid) { struct bus *link; struct resource *res; @@ -607,7 +607,7 @@ static void amdfam10_create_vga_resource(struct device *dev, unsigned nodeid) static void amdfam10_set_resources(struct device *dev) { - unsigned nodeid; + unsigned int nodeid; struct bus *bus; struct resource *res; @@ -685,7 +685,7 @@ struct chip_operations northbridge_amd_amdfam10_ops = { static void amdfam10_domain_read_resources(struct device *dev) { - unsigned reg; + unsigned int reg; uint8_t nvram; uint8_t enable_cc6; @@ -697,7 +697,7 @@ static void amdfam10_domain_read_resources(struct device *dev) limit = f1_read_config32(reg + 0x04); /* Is this register allocated? */ if ((base & 3) != 0) { - unsigned nodeid, reg_link; + unsigned int nodeid, reg_link; struct device *reg_dev; if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); @@ -817,7 +817,7 @@ static u32 my_find_pci_tolm(struct bus *bus, u32 tolm) #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { - unsigned hole_startk; + unsigned int hole_startk; int node_id; }; @@ -857,7 +857,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G mem_hole.node_id = i; break; //only one hole } @@ -949,7 +949,7 @@ static void amdfam10_domain_set_resources(struct device *dev) /* split the region to accommodate pci memory space */ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { - unsigned pre_sizek; + unsigned int pre_sizek; pre_sizek = mmio_basek - basek; if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); @@ -1325,7 +1325,7 @@ static void sysconf_init(struct device *dev) // first node sysconf.segbit = 0; sysconf.ht_c_num = 0; - unsigned ht_c_index; + unsigned int ht_c_index; for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { sysconf.ht_c_conf_bus[ht_c_index] = 0; @@ -1386,12 +1386,12 @@ static void cpu_bus_scan(struct device *dev) int nvram = 0; int i,j; int nodes; - unsigned nb_cfg_54; - unsigned siblings; + unsigned int nb_cfg_54; + unsigned int siblings; int cores_found; int disable_siblings; uint8_t disable_cu_siblings = 0; - unsigned ApicIdCoreIdSize; + unsigned int ApicIdCoreIdSize; nb_cfg_54 = 0; ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf); @@ -1485,7 +1485,7 @@ static void cpu_bus_scan(struct device *dev) for (i = 0; i < nodes; i++) { struct device *cdb_dev; - unsigned busn, devn; + unsigned int busn, devn; struct bus *pbus; uint8_t fam15h = 0; diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c index b36d4b4fe9..883f634c74 100644 --- a/src/northbridge/amd/amdht/comlib.c +++ b/src/northbridge/amd/amdht/comlib.c @@ -17,7 +17,6 @@ #include #include -#include #include #include diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index d8cbc36ff8..2b821b7c9e 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -26,6 +26,6 @@ void set_bios_reset(void); void distinguish_cpu_resets(unsigned int nodeid); unsigned int get_sblk(void); -unsigned int get_sbbusn(unsigned sblk); +unsigned int get_sbbusn(unsigned int sblk); #endif /* AMDK8_H */ diff --git a/src/northbridge/amd/amdmct/mct/mct.h b/src/northbridge/amd/amdmct/mct/mct.h index d13c42cdb5..598ab37e76 100644 --- a/src/northbridge/amd/amdmct/mct/mct.h +++ b/src/northbridge/amd/amdmct/mct/mct.h @@ -508,12 +508,12 @@ void K8FInterleaveBanks(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT void mctInitWithWritetoCS(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); void mctGet_PS_Cfg(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void Get_ChannelPS_Cfg0(unsigned MAAdimms, unsigned Speed, unsigned MAAload, unsigned DATAAload, - unsigned *AddrTmgCTL, unsigned *ODC_CTL); -void Get_ChannelPS_Cfg1(unsigned MAAdimms, unsigned Speed, unsigned MAAload, - unsigned *AddrTmgCTL, unsigned *ODC_CTL, unsigned *val); -void Get_ChannelPS_Cfg2(unsigned MAAdimms, unsigned Speed, unsigned MAAload, - unsigned *AddrTmgCTL, unsigned *ODC_CTL, unsigned *val); +void Get_ChannelPS_Cfg0(unsigned int MAAdimms, unsigned int Speed, unsigned int MAAload, unsigned int DATAAload, + unsigned int *AddrTmgCTL, unsigned int *ODC_CTL); +void Get_ChannelPS_Cfg1(unsigned int MAAdimms, unsigned int Speed, unsigned int MAAload, + unsigned int *AddrTmgCTL, unsigned int *ODC_CTL, unsigned int *val); +void Get_ChannelPS_Cfg2(unsigned int MAAdimms, unsigned int Speed, unsigned int MAAload, + unsigned int *AddrTmgCTL, unsigned int *ODC_CTL, unsigned int *val); u8 MCTDefRet(void); @@ -532,7 +532,7 @@ void K8FCPUMemTyping(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTsta void K8FCPUMemTyping_clear(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void K8FWaitMemClrDelay(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -unsigned K8FCalcFinalDQSRcvValue(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, unsigned LeftRcvEn, unsigned RightRcvEn, unsigned *valid); +unsigned int K8FCalcFinalDQSRcvValue(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, unsigned int LeftRcvEn, unsigned int RightRcvEn, unsigned int *valid); void K8FGetDeltaTSCPart1(struct DCTStatStruc *pDCTstat); void K8FGetDeltaTSCPart2(struct DCTStatStruc *pDCTstat); diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 518c6e2ab9..40d3e0577c 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -314,7 +314,7 @@ static void read_resources(struct device *dev) static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; - unsigned reg, link_num; + unsigned int reg, link_num; char buf[50]; /* Make certain the resource has actually been set */ @@ -658,7 +658,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G + mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G mem_hole.node_id = i; break; //only one hole } diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index c67e5ff2ee..533b651427 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -47,13 +47,13 @@ typedef struct dram_base_mask { u32 mask; //[47:27] at [28:8] and enable at bit 0 } dram_base_mask_t; -static unsigned node_nums; -static unsigned sblink; +static unsigned int node_nums; +static unsigned int sblink; static struct device *__f0_dev[MAX_NODE_NUMS]; static struct device *__f1_dev[MAX_NODE_NUMS]; static struct device *__f2_dev[MAX_NODE_NUMS]; static struct device *__f4_dev[MAX_NODE_NUMS]; -static unsigned fx_devs = 0; +static unsigned int fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { @@ -122,14 +122,14 @@ static void get_fx_devs(void) printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); } -static u32 f1_read_config32(unsigned reg) +static u32 f1_read_config32(unsigned int reg) { if (fx_devs == 0) get_fx_devs(); return pci_read_config32(__f1_dev[0], reg); } -static void f1_write_config32(unsigned reg, u32 value) +static void f1_write_config32(unsigned int reg, u32 value) { int i; if (fx_devs == 0) @@ -167,11 +167,11 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, - unsigned goal_link) +static int reg_useable(unsigned int reg, struct device *goal_dev, unsigned int goal_nodeid, + unsigned int goal_link) { struct resource *res; - unsigned nodeid, link = 0; + unsigned int nodeid, link = 0; int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { @@ -196,7 +196,7 @@ static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_node return result; } -static struct resource *amdfam15_find_iopair(struct device *dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device *dev, unsigned int nodeid, unsigned int link) { struct resource *resource; u32 free_reg, reg; @@ -301,7 +301,7 @@ static void read_resources(struct device *dev) static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; - unsigned reg, link_num; + unsigned int reg, link_num; char buf[50]; /* Make certain the resource has actually been set */ @@ -347,7 +347,7 @@ static void set_resource(struct device *dev, struct resource *resource, u32 node * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(struct device *dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned int nodeid) { struct bus *link; @@ -377,7 +377,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid) static void set_resources(struct device *dev) { - unsigned nodeid; + unsigned int nodeid; struct bus *bus; struct resource *res; @@ -658,7 +658,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G mem_hole.node_id = i; break; //only one hole } @@ -791,8 +791,8 @@ static void cpu_bus_scan(struct device *dev) int i,j; int coreid_bits; int core_max = 0; - unsigned ApicIdCoreIdSize; - unsigned core_nums; + unsigned int ApicIdCoreIdSize; + unsigned int core_nums; int siblings = 0; unsigned int family; u32 modules = 0; @@ -830,7 +830,7 @@ static void cpu_bus_scan(struct device *dev) cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { struct device *cdb_dev; - unsigned devn; + unsigned int devn; struct bus *pbus; devn = DEV_CDB + i; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index ba17c614e5..27e14f5df5 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -882,7 +882,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G mem_hole.node_id = i; break; //only one hole } diff --git a/src/northbridge/intel/e7505/Makefile.inc b/src/northbridge/intel/e7505/Makefile.inc index 4eda3d1049..9b68e13b9b 100644 --- a/src/northbridge/intel/e7505/Makefile.inc +++ b/src/northbridge/intel/e7505/Makefile.inc @@ -6,5 +6,4 @@ ramstage-y += memmap.c romstage-y += raminit.c romstage-y += memmap.c -postcar-y += memmap.c endif diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index 11af6e334f..009db80215 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -17,12 +17,11 @@ #include #include #include -#include #include #include #include "e7505.h" -void *cbmem_top(void) +void *cbmem_top_chipset(void) { pci_devfn_t mch = PCI_DEV(0, 0, 0); uintptr_t tolm; diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 8a336e6f0a..ba07b3e69b 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -434,7 +434,7 @@ static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) * @param dimm_socket_address SMBus address of DIMM socket to interrogate. * @return log2(number of bits) for each side of the DIMM. */ -static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address) +static struct dimm_size spd_get_dimm_size(unsigned int dimm_socket_address) { int value; @@ -757,7 +757,7 @@ DIMM-independent configuration functions: * (0..MAX_DIMM_SOCKETS_PER_CHANNEL). * @return New multiple of 64 MB total DRAM in the system. */ -static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index) +static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned int dimm_index) { int i; diff --git a/src/northbridge/intel/fsp_rangeley/Makefile.inc b/src/northbridge/intel/fsp_rangeley/Makefile.inc index a167c2369e..f02e3c4aec 100644 --- a/src/northbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/northbridge/intel/fsp_rangeley/Makefile.inc @@ -18,7 +18,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY),y) subdirs-y += fsp ramstage-y += northbridge.c -ramstage-y += memmap.c ramstage-y += acpi.c ramstage-y += port_access.c diff --git a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl b/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl index cb0d2a43ce..4e9bc324c6 100644 --- a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl +++ b/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl @@ -17,7 +17,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) // This is in the SSDT and can be accessed by the DSDT diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index 43e71f4d3d..9acce5b8b9 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -52,7 +52,7 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) DEVTREE_CONST config_t *config; printk(BIOS_DEBUG, "Configure Default UPD Data\n"); - dev = pcidev_path_on_root(SOC_DEV_FUNC); + dev = pcidev_path_on_root(SOC_DEVFN_SOC); config = dev->chip_info; /* Set SPD addresses */ @@ -103,30 +103,30 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) continue; switch (dev->path.pci.devfn) { - case GBE1_DEV_FUNC: - case GBE2_DEV_FUNC: - case GBE3_DEV_FUNC: - case GBE4_DEV_FUNC: + case SOC_DEVFN_GBE1: + case SOC_DEVFN_GBE2: + case SOC_DEVFN_GBE3: + case SOC_DEVFN_GBE4: UpdData->PcdEnableLan |= dev->enabled; printk(BIOS_DEBUG, "PcdEnableLan %d\n", UpdData->PcdEnableLan); break; - case SATA2_DEV_FUNC: + case SOC_DEVFN_SATA2: UpdData->PcdEnableSata2 = dev->enabled; printk(BIOS_DEBUG, "PcdEnableSata2 %d\n", UpdData->PcdEnableSata2); break; - case SATA3_DEV_FUNC: + case SOC_DEVFN_SATA3: UpdData->PcdEnableSata3 = dev->enabled; printk(BIOS_DEBUG, "PcdEnableSata3 %d\n", UpdData->PcdEnableSata3); break; - case IQAT_DEV_FUNC: + case SOC_DEVFN_IQAT: UpdData->PcdEnableIQAT |= dev->enabled; printk(BIOS_DEBUG, "PcdEnableIQAT %d\n", UpdData->PcdEnableIQAT); break; - case USB2_DEV_FUNC: + case SOC_DEVFN_USB2: UpdData->PcdEnableUsb20 = dev->enabled; printk(BIOS_DEBUG, "PcdEnableUsb20 %d\n", UpdData->PcdEnableUsb20); diff --git a/src/northbridge/intel/fsp_rangeley/memmap.c b/src/northbridge/intel/fsp_rangeley/memmap.c index da9ed71a67..275ddd3ac1 100644 --- a/src/northbridge/intel/fsp_rangeley/memmap.c +++ b/src/northbridge/intel/fsp_rangeley/memmap.c @@ -36,7 +36,7 @@ static uintptr_t smm_region_start(void) return tom; } -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE); } diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index 8375fbf38c..fd5fa05a39 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -52,7 +52,6 @@ #define P_UNIT 4 #ifndef __ASSEMBLER__ -static inline void barrier(void) { asm("" ::: "memory"); } #define PCI_DEVICE_ID_RG_MIN 0x1F00 #define PCI_DEVICE_ID_RG_MAX 0x1F0F diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 3042741370..4877fa9d6b 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -26,15 +26,16 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_GMA_ACPI select INTEL_GMA_SSC_ALTERNATE_REF select PARALLEL_MP + select C_ENVIRONMENT_BOOTBLOCK + +config VBOOT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE config CBFS_SIZE hex default 0x100000 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/gm45/bootblock.c" - config VGA_BIOS_ID string default "8086,2a42" diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index 3742cfcf7c..20fdbbe32c 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_GM45),y) +bootblock-y += bootblock.c + romstage-y += early_init.c romstage-y += early_reset.c romstage-y += raminit.c diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index 4678e1ff95..a3f9e9071f 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -16,6 +16,7 @@ #include "hostbridge.asl" #include "../gm45.h" +#include /* PCI Device Resource Consumption */ Device (PDRC) @@ -36,7 +37,7 @@ Device (PDRC) //}) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl index afa7a61404..22e2fdac5e 100644 --- a/src/northbridge/intel/gm45/acpi/hostbridge.asl +++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl @@ -19,7 +19,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Device (MCHC) diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index c076c5506b..d3aeb030f1 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -11,13 +11,14 @@ * GNU General Public License for more details. */ +#include #include /* Just re-define these instead of including gm45.h. It blows up romcc. */ #define D0F0_PCIEXBAR_LO 0x60 #define D0F0_PCIEXBAR_HI 0x64 -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg; diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 430afe4077..5c28f533a9 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -435,7 +435,6 @@ u32 decode_tseg_size(u8 esmramc); void init_iommu(void); /* romstage mainboard hookups */ -void mb_setup_lpc(void); void mb_setup_superio(void); /* optional */ void get_mb_spd_addrmap(u8 spd_addrmap[4]); void mb_pre_raminit_setup(sysinfo_t *); /* optional */ diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index a2de7f0fb0..1e6da69878 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -205,7 +205,7 @@ static void gma_func0_init(struct device *dev) /* Post VBIOS init */ gma_pm_init_post_vbios(dev, edid_lvds.ascii_string); - if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { + if (CONFIG(MAINBOARD_USE_LIBGFXINIT) && !acpi_is_wakeup_s3()) { int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; if (vga_disable) { printk(BIOS_INFO, diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 7479a7834a..d34820eb3d 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -117,7 +117,7 @@ static size_t northbridge_get_tseg_size(void) * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +void *cbmem_top_chipset(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); return (void *) top_of_ram; diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 384d98a54e..e652090238 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 7a30b761c5..a2c7643fb0 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -175,7 +175,7 @@ void get_gmch_info(sysinfo_t *sysinfo) printk(BIOS_SPEW, "GMCH supports DDR3 with %d MT or less\n", sysinfo->max_ddr3_mt); } - const unsigned max_fsb = (capid >> 28) & 0x3; + const unsigned int max_fsb = (capid >> 28) & 0x3; switch (max_fsb) { case 1: sysinfo->max_fsb_mhz = 1067; diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index 3f5dbca8fc..8b1e29287d 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -22,7 +22,7 @@ typedef struct { u32 addr[RANKS_PER_CHANNEL]; - unsigned count; + unsigned int count; } address_bunch_t; /* Read Training. */ diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index c853a3a1f4..a146734158 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -62,12 +62,6 @@ void mainboard_romstage_entry(void) i82801ix_early_init(); setup_pch_gpios(&mainboard_gpio_map); - mb_setup_lpc(); - - mb_setup_superio(); - - console_init(); - reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) { diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 0f0d38339e..45ebff29f1 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -16,6 +16,7 @@ #include "../haswell.h" #include "hostbridge.asl" +#include /* PCI Device Resource Consumption */ Device (PDRC) @@ -24,7 +25,7 @@ Device (PDRC) Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 1ebdf289de..19d788ce26 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -18,7 +18,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Device (MCHC) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index ca446e25a7..2081a396a1 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -205,7 +205,7 @@ static inline void gtt_write_regs(const struct gt_reg *gt) #define GTT_RETRY 1000 int gtt_poll(u32 reg, u32 mask, u32 value) { - unsigned try = GTT_RETRY; + unsigned int try = GTT_RETRY; u32 data; while (try--) { diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index bd89609601..fce94166a7 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -202,7 +202,6 @@ #define DMIDRCCFG 0xeb4 /* 32bit */ #ifndef __ASSEMBLER__ -static inline void barrier(void) { asm("" ::: "memory"); } void intel_northbridge_haswell_finalize_smm(void); diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index b1eb770f90..74d9292c14 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -17,7 +17,6 @@ #define __SIMPLE_DEVICE__ #include -#include #include #include #include @@ -35,7 +34,7 @@ static uintptr_t smm_region_start(void) return tom & ~((1 << 20) - 1); } -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return (void *)smm_region_start(); } diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc index 2c503c63c1..355d9b2524 100644 --- a/src/northbridge/intel/i440bx/Makefile.inc +++ b/src/northbridge/intel/i440bx/Makefile.inc @@ -17,12 +17,9 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y) ramstage-y += northbridge.c -ramstage-y += memmap.c romstage-y += raminit.c romstage-$(CONFIG_DEBUG_RAM_SETUP) += debug.c romstage-y += memmap.c -postcar-y += memmap.c - endif diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c index 9518618825..7df639b6bd 100644 --- a/src/northbridge/intel/i440bx/debug.c +++ b/src/northbridge/intel/i440bx/debug.c @@ -21,7 +21,7 @@ void dump_spd_registers(void) int i; printk(BIOS_DEBUG, "\n"); for (i = 0; i < DIMM_SOCKETS; i++) { - unsigned device; + unsigned int device; device = DIMM0 + i; if (device) { int j; @@ -45,7 +45,7 @@ void dump_spd_registers(void) } } -void dump_pci_device(unsigned dev) +void dump_pci_device(unsigned int dev) { int i; printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7); diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index 6c540a512a..d260af6f32 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -18,13 +18,12 @@ #include #include #include -#include #include #include #include #include "i440bx.h" -void *cbmem_top(void) +void *cbmem_top_chipset(void) { /* Base of TSEG is top of usable DRAM */ /* diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index 4711359181..448f8d69be 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -31,7 +31,7 @@ void sdram_initialize(void); /* Debug */ #if CONFIG(DEBUG_RAM_SETUP) void dump_spd_registers(void); -void dump_pci_device(unsigned dev); +void dump_pci_device(unsigned int dev); #else #define dump_spd_registers() #endif diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl index 83187730e4..db493eabac 100644 --- a/src/northbridge/intel/i945/acpi/hostbridge.asl +++ b/src/northbridge/intel/i945/acpi/hostbridge.asl @@ -19,7 +19,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Device (MCHC) diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 7a9715c967..50fabdc5de 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -16,6 +16,7 @@ #include "hostbridge.asl" #include "../i945.h" +#include /* Operating System Capabilities Method */ Method (_OSC, 4) @@ -51,7 +52,7 @@ Device (PDRC) //}) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d6d37d9083..ee10fdccb6 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -549,14 +550,9 @@ static void i945_setup_pci_express_x16(void) * PCI bus 0x0a and check whether we find a device on 0:a.0 */ - /* First we reset the secondary bus */ - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); - /* Read back and clear reset bit. */ - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; /* SRESET */ - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + /* Force PCIRST# */ + pci_s_assert_secondary_reset(p2peg); + pci_s_deassert_secondary_reset(p2peg); reg16 = pci_read_config16(p2peg, SLOTSTS); printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); @@ -565,10 +561,7 @@ static void i945_setup_pci_express_x16(void) reg16 |= (1 << 4) | (1 << 0); pci_write_config16(p2peg, SLOTSTS, reg16); - pci_write_config8(p2peg, PCI_SECONDARY_BUS, 0x00); - pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, 0x00); - pci_write_config8(p2peg, PCI_SECONDARY_BUS, tmp_secondary); - pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, tmp_secondary); + pci_s_bridge_set_secondary(p2peg, tmp_secondary); reg32 = pci_read_config32(p2peg, 0x224); reg32 &= ~(1 << 8); @@ -614,11 +607,9 @@ static void i945_setup_pci_express_x16(void) reg32 |= 1; pci_write_config32(p2peg, PEGSTS, reg32); - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); - reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + /* Force PCIRST# */ + pci_s_assert_secondary_reset(p2peg); + pci_s_deassert_secondary_reset(p2peg); printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; @@ -774,17 +765,14 @@ disable_pciexpress_x16_link: MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + /* Toggle PCIRST# */ + pci_s_assert_secondary_reset(p2peg); reg32 = pci_read_config32(p2peg, 0x224); reg32 |= (1 << 8); pci_write_config32(p2peg, 0x224, reg32); - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + pci_s_deassert_secondary_reset(p2peg); printk(BIOS_DEBUG, "Wait for link to enter detect state... "); timeout = 0x7fffff; diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index d19748eaf9..4dd5379469 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -83,8 +83,6 @@ /* Device 0:1.0 PCI configuration space (PCI Express) */ #define PCISTS1 0x06 /* 16bit */ -#define SBUSN1 0x19 /* 8bit */ -#define SUBUSN1 0x1a /* 8bit */ #define SSTS1 0x1e /* 16bit */ #define PEG_CAP 0xa2 /* 16bit */ #define DSTS 0xaa /* 16bit */ @@ -363,8 +361,6 @@ #define DMIDRCCFG 0xeb4 /* 32bit */ -static inline void barrier(void) { asm("" ::: "memory"); } - int i945_silicon_revision(void); void i945_early_initialization(void); void i945_late_initialization(int s3resume); diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 8207d06a55..000ac7e682 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -71,7 +71,7 @@ static size_t northbridge_get_tseg_size(void) * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +void *cbmem_top_chipset(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); return (void *) top_of_ram; diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 3adf6987bf..7b56841336 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -21,12 +21,16 @@ config NORTHBRIDGE_INTEL_NEHALEM select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP + select C_ENVIRONMENT_BOOTBLOCK if NORTHBRIDGE_INTEL_NEHALEM config VBOOT select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_STARTS_IN_ROMSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + # CPU is reset without platform/TPM during romstage + select TPM_STARTUP_IGNORE_POSTINIT config MMCONF_BUS_NUMBER int @@ -48,9 +52,12 @@ config DCACHE_RAM_SIZE hex default 0x10000 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/nehalem/bootblock.c" +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. config MRC_CACHE_SIZE hex diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index ebb7b8be03..225f0ce812 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y) +bootblock-y += bootblock.c + ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += smi.c @@ -26,7 +28,7 @@ romstage-y += memmap.c romstage-y += raminit.c romstage-y += raminit_tables.c romstage-y += early_init.c -romstage-y += ../../../arch/x86/walkcbfs.S +romstage-y += romstage.c smm-y += finalize.c diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/nehalem/acpi/hostbridge.asl index 337a9bcfa7..2b26096be6 100644 --- a/src/northbridge/intel/nehalem/acpi/hostbridge.asl +++ b/src/northbridge/intel/nehalem/acpi/hostbridge.asl @@ -18,7 +18,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Device (MCHC) diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/nehalem/acpi/nehalem.asl index df8aad7c62..404801ec3f 100644 --- a/src/northbridge/intel/nehalem/acpi/nehalem.asl +++ b/src/northbridge/intel/nehalem/acpi/nehalem.asl @@ -16,6 +16,7 @@ #include "../nehalem.h" #include "hostbridge.asl" +#include /* PCI Device Resource Consumption */ Device (PDRC) @@ -24,7 +25,7 @@ Device (PDRC) Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/nehalem/bootblock.c index f96ff56a56..46cdef0c47 100644 --- a/src/northbridge/intel/nehalem/bootblock.c +++ b/src/northbridge/intel/nehalem/bootblock.c @@ -12,8 +12,9 @@ */ #include +#include -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0); diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 087d37e5aa..d717e48821 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include @@ -36,225 +35,6 @@ #include "chip.h" #include "nehalem.h" -struct gt_powermeter { - u16 reg; - u32 value; -}; - -static const struct gt_powermeter snb_pm_gt1[] = { - {0xa200, 0xcc000000}, - {0xa204, 0x07000040}, - {0xa208, 0x0000fe00}, - {0xa20c, 0x00000000}, - {0xa210, 0x17000000}, - {0xa214, 0x00000021}, - {0xa218, 0x0817fe19}, - {0xa21c, 0x00000000}, - {0xa220, 0x00000000}, - {0xa224, 0xcc000000}, - {0xa228, 0x07000040}, - {0xa22c, 0x0000fe00}, - {0xa230, 0x00000000}, - {0xa234, 0x17000000}, - {0xa238, 0x00000021}, - {0xa23c, 0x0817fe19}, - {0xa240, 0x00000000}, - {0xa244, 0x00000000}, - {0xa248, 0x8000421e}, - {0} -}; - -static const struct gt_powermeter snb_pm_gt2[] = { - {0xa200, 0x330000a6}, - {0xa204, 0x402d0031}, - {0xa208, 0x00165f83}, - {0xa20c, 0xf1000000}, - {0xa210, 0x00000000}, - {0xa214, 0x00160016}, - {0xa218, 0x002a002b}, - {0xa21c, 0x00000000}, - {0xa220, 0x00000000}, - {0xa224, 0x330000a6}, - {0xa228, 0x402d0031}, - {0xa22c, 0x00165f83}, - {0xa230, 0xf1000000}, - {0xa234, 0x00000000}, - {0xa238, 0x00160016}, - {0xa23c, 0x002a002b}, - {0xa240, 0x00000000}, - {0xa244, 0x00000000}, - {0xa248, 0x8000421e}, - {0} -}; - -static const struct gt_powermeter ivb_pm_gt1[] = { - {0xa800, 0x00000000}, - {0xa804, 0x00021c00}, - {0xa808, 0x00000403}, - {0xa80c, 0x02001700}, - {0xa810, 0x05000200}, - {0xa814, 0x00000000}, - {0xa818, 0x00690500}, - {0xa81c, 0x0000007f}, - {0xa820, 0x01002501}, - {0xa824, 0x00000300}, - {0xa828, 0x01000331}, - {0xa82c, 0x0000000c}, - {0xa830, 0x00010016}, - {0xa834, 0x01100101}, - {0xa838, 0x00010103}, - {0xa83c, 0x00041300}, - {0xa840, 0x00000b30}, - {0xa844, 0x00000000}, - {0xa848, 0x7f000000}, - {0xa84c, 0x05000008}, - {0xa850, 0x00000001}, - {0xa854, 0x00000004}, - {0xa858, 0x00000007}, - {0xa85c, 0x00000000}, - {0xa860, 0x00010000}, - {0xa248, 0x0000221e}, - {0xa900, 0x00000000}, - {0xa904, 0x00001c00}, - {0xa908, 0x00000000}, - {0xa90c, 0x06000000}, - {0xa910, 0x09000200}, - {0xa914, 0x00000000}, - {0xa918, 0x00590000}, - {0xa91c, 0x00000000}, - {0xa920, 0x04002501}, - {0xa924, 0x00000100}, - {0xa928, 0x03000410}, - {0xa92c, 0x00000000}, - {0xa930, 0x00020000}, - {0xa934, 0x02070106}, - {0xa938, 0x00010100}, - {0xa93c, 0x00401c00}, - {0xa940, 0x00000000}, - {0xa944, 0x00000000}, - {0xa948, 0x10000e00}, - {0xa94c, 0x02000004}, - {0xa950, 0x00000001}, - {0xa954, 0x00000004}, - {0xa960, 0x00060000}, - {0xaa3c, 0x00001c00}, - {0xaa54, 0x00000004}, - {0xaa60, 0x00060000}, - {0} -}; - -static const struct gt_powermeter ivb_pm_gt2_17w[] = { - {0xa800, 0x20000000}, - {0xa804, 0x000e3800}, - {0xa808, 0x00000806}, - {0xa80c, 0x0c002f00}, - {0xa810, 0x0c000800}, - {0xa814, 0x00000000}, - {0xa818, 0x00d20d00}, - {0xa81c, 0x000000ff}, - {0xa820, 0x03004b02}, - {0xa824, 0x00000600}, - {0xa828, 0x07000773}, - {0xa82c, 0x00000000}, - {0xa830, 0x00020032}, - {0xa834, 0x1520040d}, - {0xa838, 0x00020105}, - {0xa83c, 0x00083700}, - {0xa840, 0x000016ff}, - {0xa844, 0x00000000}, - {0xa848, 0xff000000}, - {0xa84c, 0x0a000010}, - {0xa850, 0x00000002}, - {0xa854, 0x00000008}, - {0xa858, 0x0000000f}, - {0xa85c, 0x00000000}, - {0xa860, 0x00020000}, - {0xa248, 0x0000221e}, - {0xa900, 0x00000000}, - {0xa904, 0x00003800}, - {0xa908, 0x00000000}, - {0xa90c, 0x0c000000}, - {0xa910, 0x12000800}, - {0xa914, 0x00000000}, - {0xa918, 0x00b20000}, - {0xa91c, 0x00000000}, - {0xa920, 0x08004b02}, - {0xa924, 0x00000300}, - {0xa928, 0x01000820}, - {0xa92c, 0x00000000}, - {0xa930, 0x00030000}, - {0xa934, 0x15150406}, - {0xa938, 0x00020300}, - {0xa93c, 0x00903900}, - {0xa940, 0x00000000}, - {0xa944, 0x00000000}, - {0xa948, 0x20001b00}, - {0xa94c, 0x0a000010}, - {0xa950, 0x00000000}, - {0xa954, 0x00000008}, - {0xa960, 0x00110000}, - {0xaa3c, 0x00003900}, - {0xaa54, 0x00000008}, - {0xaa60, 0x00110000}, - {0} -}; - -static const struct gt_powermeter ivb_pm_gt2_35w[] = { - {0xa800, 0x00000000}, - {0xa804, 0x00030400}, - {0xa808, 0x00000806}, - {0xa80c, 0x0c002f00}, - {0xa810, 0x0c000300}, - {0xa814, 0x00000000}, - {0xa818, 0x00d20d00}, - {0xa81c, 0x000000ff}, - {0xa820, 0x03004b02}, - {0xa824, 0x00000600}, - {0xa828, 0x07000773}, - {0xa82c, 0x00000000}, - {0xa830, 0x00020032}, - {0xa834, 0x1520040d}, - {0xa838, 0x00020105}, - {0xa83c, 0x00083700}, - {0xa840, 0x000016ff}, - {0xa844, 0x00000000}, - {0xa848, 0xff000000}, - {0xa84c, 0x0a000010}, - {0xa850, 0x00000001}, - {0xa854, 0x00000008}, - {0xa858, 0x00000008}, - {0xa85c, 0x00000000}, - {0xa860, 0x00020000}, - {0xa248, 0x0000221e}, - {0xa900, 0x00000000}, - {0xa904, 0x00003800}, - {0xa908, 0x00000000}, - {0xa90c, 0x0c000000}, - {0xa910, 0x12000800}, - {0xa914, 0x00000000}, - {0xa918, 0x00b20000}, - {0xa91c, 0x00000000}, - {0xa920, 0x08004b02}, - {0xa924, 0x00000300}, - {0xa928, 0x01000820}, - {0xa92c, 0x00000000}, - {0xa930, 0x00030000}, - {0xa934, 0x15150406}, - {0xa938, 0x00020300}, - {0xa93c, 0x00903900}, - {0xa940, 0x00000000}, - {0xa944, 0x00000000}, - {0xa948, 0x20001b00}, - {0xa94c, 0x0a000010}, - {0xa950, 0x00000000}, - {0xa954, 0x00000008}, - {0xa960, 0x00110000}, - {0xaa3c, 0x00003900}, - {0xaa54, 0x00000008}, - {0xaa60, 0x00110000}, - {0} -}; - /* some vga option roms are used for several chipsets but they only have one * PCI ID in their header. If we encounter such an option rom, we need to do * the mapping ourselves @@ -281,16 +61,10 @@ void gtt_write(u32 reg, u32 data) write32(res2mmio(gtt_res, reg, 0), data); } -static inline void gtt_write_powermeter(const struct gt_powermeter *pm) -{ - for (; pm && pm->reg; pm++) - gtt_write(pm->reg, pm->value); -} - #define GTT_RETRY 1000 int gtt_poll(u32 reg, u32 mask, u32 value) { - unsigned try = GTT_RETRY; + unsigned int try = GTT_RETRY; u32 data; while (try--) { @@ -317,196 +91,6 @@ void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) gnvs_ptr->aslb = aslb; } -static void gma_pm_init_pre_vbios(struct device *dev) -{ - u32 reg32; - - printk(BIOS_DEBUG, "GT Power Management Init\n"); - - gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (!gtt_res || !gtt_res->base) - return; - - if (bridge_silicon_revision() < IVB_STEP_C0) { - /* 1: Enable force wake */ - gtt_write(0xa18c, 0x00000001); - gtt_poll(0x130090, (1 << 0), (1 << 0)); - } else { - gtt_write(0xa180, 1 << 5); - gtt_write(0xa188, 0xffff0001); - gtt_poll(0x130040, (1 << 0), (1 << 0)); - } - - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { - /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ - reg32 = gtt_read(0x42004); - reg32 |= (1 << 14) | (1 << 15); - gtt_write(0x42004, reg32); - } - - if (bridge_silicon_revision() >= IVB_STEP_A0) { - /* Display Reset Acknowledge Settings */ - reg32 = gtt_read(0x45010); - reg32 |= (1 << 1) | (1 << 0); - gtt_write(0x45010, reg32); - } - - /* 2: Get GT SKU from GTT+0x911c[13] */ - reg32 = gtt_read(0x911c); - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { - if (reg32 & (1 << 13)) { - printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n"); - gtt_write_powermeter(snb_pm_gt1); - } else { - printk(BIOS_DEBUG, "SNB GT2 Power Meter Weights\n"); - gtt_write_powermeter(snb_pm_gt2); - } - } else { - u32 unit = MCHBAR32(0x5938) & 0xf; - - if (reg32 & (1 << 13)) { - /* GT1 SKU */ - printk(BIOS_DEBUG, "IVB GT1 Power Meter Weights\n"); - gtt_write_powermeter(ivb_pm_gt1); - } else { - /* GT2 SKU */ - u32 tdp = MCHBAR32(0x5930) & 0x7fff; - tdp /= (1 << unit); - - if (tdp <= 17) { - /* <=17W ULV */ - printk(BIOS_DEBUG, "IVB GT2 17W " - "Power Meter Weights\n"); - gtt_write_powermeter(ivb_pm_gt2_17w); - } else if ((tdp >= 25) && (tdp <= 35)) { - /* 25W-35W */ - printk(BIOS_DEBUG, "IVB GT2 25W-35W " - "Power Meter Weights\n"); - gtt_write_powermeter(ivb_pm_gt2_35w); - } else { - /* All others */ - printk(BIOS_DEBUG, "IVB GT2 35W " - "Power Meter Weights\n"); - gtt_write_powermeter(ivb_pm_gt2_35w); - } - } - } - - /* 3: Gear ratio map */ - gtt_write(0xa004, 0x00000010); - - /* 4: GFXPAUSE */ - gtt_write(0xa000, 0x00070020); - - /* 5: Dynamic EU trip control */ - gtt_write(0xa080, 0x00000004); - - /* 6: ECO bits */ - reg32 = gtt_read(0xa180); - reg32 |= (1 << 26) | (1 << 31); - /* (bit 20=1 for SNB step D1+ / IVB A0+) */ - if (bridge_silicon_revision() >= SNB_STEP_D1) - reg32 |= (1 << 20); - gtt_write(0xa180, reg32); - - /* 6a: for SnB step D2+ only */ - if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && - (bridge_silicon_revision() >= SNB_STEP_D2)) { - reg32 = gtt_read(0x9400); - reg32 |= (1 << 7); - gtt_write(0x9400, reg32); - - reg32 = gtt_read(0x941c); - reg32 &= 0xf; - reg32 |= (1 << 1); - gtt_write(0x941c, reg32); - gtt_poll(0x941c, (1 << 1), (0 << 1)); - } - - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { - reg32 = gtt_read(0x907c); - reg32 |= (1 << 16); - gtt_write(0x907c, reg32); - - /* 6b: Clocking reset controls */ - gtt_write(0x9424, 0x00000001); - } else { - /* 6b: Clocking reset controls */ - gtt_write(0x9424, 0x00000000); - } - - /* 7 */ - if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { - gtt_write(0x138128, 0x00000029); /* Mailbox Data */ - gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */ - if (gtt_poll(0x138124, (1 << 31), (0 << 31))) - gtt_write(0x138124, 0x8000000a); - gtt_poll(0x138124, (1 << 31), (0 << 31)); - } - - /* 8 */ - gtt_write(0xa090, 0x00000000); /* RC Control */ - gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ - gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ - gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */ - gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */ - gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */ - - /* 9 */ - gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */ - gtt_write(0x12054, 0x0000000a); /* Video Idle Max Count */ - gtt_write(0x22054, 0x0000000a); /* Blitter Idle Max Count */ - - /* 10 */ - gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */ - gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */ - gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */ - gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */ - gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */ - - /* 11 */ - gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */ - gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */ - gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */ - gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */ - gtt_write(0xa068, 0x000186a0); /* RP Up EI */ - gtt_write(0xa06c, 0x000493e0); /* RP Down EI */ - gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */ - - /* 11a: Enable Render Standby (RC6) */ - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { - /* - * IvyBridge should also support DeepRenderStandby. - * - * Unfortunately it does not work reliably on all SKUs so - * disable it here and it can be enabled by the kernel. - */ - gtt_write(0xa090, 0x88040000); /* HW RC Control */ - } else { - gtt_write(0xa090, 0x88040000); /* HW RC Control */ - } - - /* 12: Normal Frequency Request */ - /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */ - /* only the lower 7 bits are used and shifted left by 25 */ - reg32 = MCHBAR32(0x5998); - reg32 >>= 16; - reg32 &= 0x7f; - reg32 <<= 25; - gtt_write(0xa008, reg32); - - /* 13: RP Control */ - gtt_write(0xa024, 0x00000592); - - /* 14: Enable PM Interrupts */ - gtt_write(0x4402c, 0x03000076); - - /* Clear 0x6c024 [8:6] */ - reg32 = gtt_read(0x6c024); - reg32 &= ~0x000001c0; - gtt_write(0x6c024, reg32); -} - static void gma_pm_init_post_vbios(struct device *dev) { struct northbridge_intel_nehalem_config *conf = dev->chip_info; @@ -514,19 +98,6 @@ static void gma_pm_init_post_vbios(struct device *dev) printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); - /* 15: Deassert Force Wake */ - if (bridge_silicon_revision() < IVB_STEP_C0) { - gtt_write(0xa18c, gtt_read(0xa18c) & ~1); - gtt_poll(0x130090, (1 << 0), (0 << 0)); - } else { - gtt_write(0xa188, 0x1fffe); - if (gtt_poll(0x130040, (1 << 0), (0 << 0))) - gtt_write(0xa188, gtt_read(0xa188) | 1); - } - - /* 16: SW RC Control */ - gtt_write(0xa094, 0x00060000); - /* Setup Digital Port Hotplug */ reg32 = gtt_read(0xc4030); if (!reg32) { @@ -600,10 +171,12 @@ static void gma_func0_init(struct device *dev) reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); - /* Init graphics power management */ - gma_pm_init_pre_vbios(dev); + gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!gtt_res || !gtt_res->base) + return; - if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { + if (!acpi_is_wakeup_s3() && + CONFIG(MAINBOARD_USE_LIBGFXINIT)) { struct northbridge_intel_nehalem_config *conf = dev->chip_info; int lightup_ok; printk(BIOS_SPEW, "Initializing VGA without OPROM."); diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c index fd10542832..5de4b80acf 100644 --- a/src/northbridge/intel/nehalem/memmap.c +++ b/src/northbridge/intel/nehalem/memmap.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -43,7 +42,7 @@ static size_t northbridge_get_tseg_size(void) return CONFIG_SMM_TSEG_SIZE; } -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return (void *) smm_region_start(); } diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 21c2a395fe..ebec63d898 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -67,8 +67,6 @@ typedef struct { #define D0F0_MCHBAR_HI 0x4c #define D0F0_GGC 0x52 #define D0F0_DEVEN 0x54 -/* Note: Intel's datasheet is broken. Assume the following values are correct */ -#define DEVEN_PEG60 (1 << 13) #define DEVEN_IGD (1 << 3) #define DEVEN_PEG10 (1 << 1) #define DEVEN_HOST (1 << 0) @@ -177,9 +175,6 @@ typedef struct { #define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) #define MCHBAR32_AND_OR(x, and, or) \ (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) - -#define BIOS_RESET_CPL 0x5da8 /* 8bit */ - /* * EPBAR - Egress Port Root Complex Register Block */ @@ -250,7 +245,6 @@ typedef struct { #define DMIDRCCFG 0xeb4 /* 32bit */ #ifndef __ASSEMBLER__ -static inline void barrier(void) { asm("" ::: "memory"); } #define PCI_DEVICE_ID_SB 0x0104 #define PCI_DEVICE_ID_IB 0x0154 @@ -261,6 +255,8 @@ void intel_nehalem_finalize_smm(void); int bridge_silicon_revision(void); void nehalem_early_initialization(int chipset_type); void nehalem_late_initialization(void); +void mainboard_pre_raminit(void); +void mainboard_get_spd_map(u8 *spd_addrmap); #endif /* !__SMM__ */ diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 4ab89ad054..8f415cb4bf 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -26,7 +26,6 @@ #include #include #include -#include #include "chip.h" #include "nehalem.h" #include @@ -133,7 +132,7 @@ static void mc_read_resources(struct device *dev) D0F0_TOUUD); printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base); - printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned)TOUUD); + printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)TOUUD); /* Report the memory regions */ ram_resource(dev, 3, 0, 640); @@ -226,55 +225,29 @@ static void northbridge_dmi_init(struct device *dev) static void northbridge_init(struct device *dev) { - u8 bios_reset_cpl; - u32 bridge_type; - northbridge_dmi_init(dev); +} - bridge_type = MCHBAR32(0x5f10); - bridge_type &= ~0xff; +/* Disable unused PEG devices based on devicetree before PCI enumeration */ +static void nehalem_init(void *const chip_info) +{ + u32 deven_mask = UINT32_MAX; + const struct device *dev; - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { - /* Enable Power Aware Interrupt Routing */ - u8 pair = MCHBAR8(0x5418); - pair &= ~0xf; /* Clear 3:0 */ - pair |= 0x4; /* Fixed Priority */ - MCHBAR8(0x5418) = pair; - - /* 30h for IvyBridge */ - bridge_type |= 0x30; - } else { - /* 20h for Sandybridge */ - bridge_type |= 0x20; + dev = pcidev_on_root(1, 0); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling PEG10.\n"); + deven_mask &= ~DEVEN_PEG10; } - MCHBAR32(0x5f10) = bridge_type; - - /* - * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU - * that BIOS has initialized memory and power management - */ - bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); - bios_reset_cpl |= 1; - MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; - printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); - - /* Configure turbo power limits 1ms after reset complete bit */ - mdelay(1); -#ifdef DISABLED - set_power_limits(28); - - /* - * CPUs with configurable TDP also need power limits set - * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. - */ - if (cpu_config_tdp_levels()) { - msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT); - MCHBAR32(0x59A0) = msr.lo; - MCHBAR32(0x59A4) = msr.hi; + dev = pcidev_on_root(2, 0); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling IGD.\n"); + deven_mask &= ~DEVEN_IGD; } -#endif - /* Set here before graphics PM init */ - MCHBAR32(0x5500) = 0x00100001; + const struct device *const d0f0 = pcidev_on_root(0, 0); + if (d0f0) + pci_update_config32(d0f0, D0F0_DEVEN, deven_mask, 0); + } static struct pci_operations intel_pci_ops = { @@ -317,5 +290,6 @@ static void enable_dev(struct device *dev) struct chip_operations northbridge_intel_nehalem_ops = { CHIP_NAME("Intel i7 (Nehalem) integrated Northbridge") - .enable_dev = enable_dev, + .enable_dev = enable_dev, + .init = nehalem_init, }; diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index b9d407a58e..a393cb7a51 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include @@ -206,13 +207,13 @@ struct raminfo { u8 mode4030[2]; u16 avg4044[2]; u16 max4048[2]; - unsigned total_memory_mb; - unsigned interleaved_part_mb; - unsigned non_interleaved_part_mb; + unsigned int total_memory_mb; + unsigned int interleaved_part_mb; + unsigned int non_interleaved_part_mb; u32 heci_bar; u64 heci_uma_addr; - unsigned memory_reserved_for_heci_mb; + unsigned int memory_reserved_for_heci_mb; struct ram_training training; u32 last_500_command[2]; @@ -548,14 +549,14 @@ enum { static void calculate_timings(struct raminfo *info) { - unsigned cycletime; - unsigned cas_latency_time; - unsigned supported_cas_latencies; - unsigned channel, slot; - unsigned clock_speed_index; - unsigned min_cas_latency; - unsigned cas_latency; - unsigned max_clock_index; + unsigned int cycletime; + unsigned int cas_latency_time; + unsigned int supported_cas_latencies; + unsigned int channel, slot; + unsigned int clock_speed_index; + unsigned int min_cas_latency; + unsigned int cas_latency; + unsigned int max_clock_index; /* Find common CAS latency */ supported_cas_latencies = 0x3fe; @@ -578,7 +579,7 @@ static void calculate_timings(struct raminfo *info) for (channel = 0; channel < NUM_CHANNELS; channel++) for (slot = 0; slot < NUM_SLOTS; slot++) if (info->populated_ranks[channel][slot][0]) { - unsigned timebase; + unsigned int timebase; timebase = 1000 * info-> @@ -626,9 +627,9 @@ static void calculate_timings(struct raminfo *info) static void program_base_timings(struct raminfo *info) { - unsigned channel; - unsigned slot, rank, lane; - unsigned extended_silicon_revision; + unsigned int channel; + unsigned int slot, rank, lane; + unsigned int extended_silicon_revision; int i; extended_silicon_revision = info->silicon_revision; @@ -789,42 +790,40 @@ static unsigned int cycle_ps(struct raminfo *info) } /* Frequency in 1.(1)=10/9 MHz units. */ -static unsigned frequency_11(struct raminfo *info) +static unsigned int frequency_11(struct raminfo *info) { return (info->clock_speed_index + 3) * 120; } /* Frequency in 0.1 MHz units. */ -static unsigned frequency_01(struct raminfo *info) +static unsigned int frequency_01(struct raminfo *info) { return 100 * frequency_11(info) / 9; } -static unsigned ps_to_halfcycles(struct raminfo *info, unsigned int ps) +static unsigned int ps_to_halfcycles(struct raminfo *info, unsigned int ps) { return (frequency_11(info) * 2) * ps / 900000; } -static unsigned ns_to_cycles(struct raminfo *info, unsigned int ns) +static unsigned int ns_to_cycles(struct raminfo *info, unsigned int ns) { return (frequency_11(info)) * ns / 900; } static void compute_derived_timings(struct raminfo *info) { - unsigned channel, slot, rank; + unsigned int channel, slot, rank; int extended_silicon_revision; int some_delay_1_ps; int some_delay_2_ps; int some_delay_2_halfcycles_ceil; int some_delay_2_halfcycles_floor; int some_delay_3_ps; - int some_delay_3_halfcycles; int some_delay_3_ps_rounded; int some_delay_1_cycle_ceil; int some_delay_1_cycle_floor; - some_delay_3_halfcycles = 0; some_delay_3_ps_rounded = 0; extended_silicon_revision = info->silicon_revision; if (!info->silicon_revision) @@ -872,13 +871,12 @@ static void compute_derived_timings(struct raminfo *info) some_delay_3_ps = halfcycle_ps(info) - some_delay_2_ps % halfcycle_ps(info); if (info->revision_flag_1) { - if (some_delay_3_ps < 150) - some_delay_3_halfcycles = 0; - else - some_delay_3_halfcycles = + if (some_delay_3_ps >= 150) { + const int some_delay_3_halfcycles = (some_delay_3_ps << 6) / halfcycle_ps(info); - some_delay_3_ps_rounded = - halfcycle_ps(info) * some_delay_3_halfcycles >> 6; + some_delay_3_ps_rounded = + halfcycle_ps(info) * some_delay_3_halfcycles >> 6; + } } some_delay_2_halfcycles_ceil = (some_delay_2_ps + halfcycle_ps(info) - 1) / halfcycle_ps(info) - @@ -1156,7 +1154,7 @@ static void jedec_init(struct raminfo *info) static void program_modules_memory_map(struct raminfo *info, int pre_jedec) { - unsigned channel, slot, rank; + unsigned int channel, slot, rank; unsigned int total_mb[2] = { 0, 0 }; /* total memory per channel in MB */ unsigned int channel_0_non_interleaved; @@ -1195,7 +1193,7 @@ static void program_board_delay(struct raminfo *info) int some_delay_ns; int some_delay_3_half_cycles; - unsigned channel, i; + unsigned int channel, i; int high_multiplier; int lane_3_delay; int cas_latency_derived; @@ -1233,7 +1231,7 @@ static void program_board_delay(struct raminfo *info) MCHBAR16(0x125) = 0x1360; MCHBAR8(0x127) = 0x40; if (info->fsb_frequency < frequency_11(info) / 2) { - unsigned some_delay_2_half_cycles; + unsigned int some_delay_2_half_cycles; high_multiplier = 1; some_delay_2_half_cycles = ps_to_halfcycles(info, ((3 * @@ -1486,7 +1484,7 @@ static void collect_system_info(struct raminfo *info) { u32 capid0[3]; int i; - unsigned channel; + unsigned int channel; /* Wait for some bit, maybe TXT clear. */ while (!(read8((u8 *)0xfed40000) & (1 << 7))) @@ -1576,14 +1574,14 @@ static void write_training_data(struct raminfo *info) static void dump_timings(struct raminfo *info) { int channel, slot, rank, lane, i; - printk(RAM_DEBUG, "Timings:\n"); + printk(RAM_SPEW, "Timings:\n"); FOR_POPULATED_RANKS { - printk(RAM_DEBUG, "channel %d, slot %d, rank %d\n", channel, + printk(RAM_SPEW, "channel %d, slot %d, rank %d\n", channel, slot, rank); for (lane = 0; lane < 9; lane++) { - printk(RAM_DEBUG, "lane %d: ", lane); + printk(RAM_SPEW, "lane %d: ", lane); for (i = 0; i < 4; i++) { - printk(RAM_DEBUG, "%x (%x) ", + printk(RAM_SPEW, "%x (%x) ", read_500(info, channel, get_timing_register_addr (lane, i, slot, rank), @@ -1592,12 +1590,12 @@ static void dump_timings(struct raminfo *info) lane_timings[i][channel][slot][rank] [lane]); } - printk(RAM_DEBUG, "\n"); + printk(RAM_SPEW, "\n"); } } - printk(RAM_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7), + printk(RAM_SPEW, "[178] = %x (%x)\n", read_1d0(0x178, 7), info->training.reg_178); - printk(RAM_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), + printk(RAM_SPEW, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), info->training.reg_10b); } @@ -3203,9 +3201,9 @@ static void ram_training(struct raminfo *info) MCHBAR16(0xfc4) = saved_fc4; } -static unsigned gcd(unsigned a, unsigned b) +static unsigned int gcd(unsigned int a, unsigned int b) { - unsigned t; + unsigned int t; if (a > b) { t = a; a = b; @@ -3225,7 +3223,7 @@ static inline int div_roundup(int a, int b) return DIV_ROUND_UP(a, b); } -static unsigned lcm(unsigned a, unsigned b) +static unsigned int lcm(unsigned int a, unsigned int b) { return (a * b) / gcd(a, b); } @@ -3722,7 +3720,7 @@ void chipset_init(const int s3resume) void raminit(const int s3resume, const u8 *spd_addrmap) { - unsigned channel, slot, lane, rank; + unsigned int channel, slot, lane, rank; int i; struct raminfo info; u8 x2ca8; @@ -3730,6 +3728,9 @@ void raminit(const int s3resume, const u8 *spd_addrmap) int cbmem_wasnot_inited; x2ca8 = MCHBAR8(0x2ca8); + + printk(RAM_DEBUG, "Scratchpad MCHBAR8(0x2ca8): 0x%04x\n", x2ca8); + deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN); memset(&info, 0x5a, sizeof(info)); @@ -3762,9 +3763,6 @@ void raminit(const int s3resume, const u8 *spd_addrmap) collect_system_info(&info); - /* Enable SMBUS. */ - enable_smbus(); - memset(&info.populated_ranks, 0, sizeof(info.populated_ranks)); info.use_ecc = 1; @@ -4011,19 +4009,19 @@ void raminit(const int s3resume, const u8 *spd_addrmap) int j; if (s3resume && info.cached_training) { restore_274265(&info); - printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n", + printk(RAM_SPEW, "reg2ca9_bit0 = %x\n", info.cached_training->reg2ca9_bit0); for (i = 0; i < 2; i++) for (j = 0; j < 3; j++) - printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n", + printk(RAM_SPEW, "reg274265[%d][%d] = %x\n", i, j, info.cached_training->reg274265[i][j]); } else { set_274265(&info); - printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n", + printk(RAM_SPEW, "reg2ca9_bit0 = %x\n", info.training.reg2ca9_bit0); for (i = 0; i < 2; i++) for (j = 0; j < 3; j++) - printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n", + printk(RAM_SPEW, "reg274265[%d][%d] = %x\n", i, j, info.training.reg274265[i][j]); } @@ -4241,6 +4239,13 @@ void raminit(const int s3resume, const u8 *spd_addrmap) if (x2ca8 == 0) { MCHBAR8_AND(0x2ca8, ~3); MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8) + 4; // "+" or "|"? + /* This issues a CPU reset without resetting the platform */ + printk(BIOS_DEBUG, "Issuing a CPU reset\n"); + /* Write back the S3 state to PM1_CNT to let the reset CPU + know it also needs to take the s3 path. */ + if (s3resume) + write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) + | (SLP_TYP_S3 << 10)); MCHBAR32_OR(0x1af0, 0x10); halt(); } diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c new file mode 100644 index 0000000000..69383e6520 --- /dev/null +++ b/src/northbridge/intel/nehalem/romstage.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "nehalem.h" +#include +#include +#include +#include +#include +#include +#include +#include + +/* Platform has no romstage entry point under mainboard directory, + * so this one is named with prefix mainboard. + */ +void mainboard_romstage_entry(void) +{ + u32 reg32; + int s3resume = 0; + u8 spd_addrmap[4] = {}; + + enable_lapic(); + + /* TODO, make this configurable */ + nehalem_early_initialization(NEHALEM_MOBILE); + + early_pch_init(); + + s3resume = southbridge_detect_s3_resume(); + if (s3resume) { + u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + if (!(reg8 & 0x20)) { + s3resume = 0; + printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); + } + } + + /* Enable SMBUS. */ + enable_smbus(); + + early_thermal_init(); + + timestamp_add_now(TS_BEFORE_INITRAM); + + chipset_init(s3resume); + + mainboard_pre_raminit(); + + mainboard_get_spd_map(spd_addrmap); + + raminit(s3resume, spd_addrmap); + + timestamp_add_now(TS_AFTER_INITRAM); + + intel_early_me_status(); + + if (s3resume) { + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + } + + romstage_handoff_init(s3resume); +} diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index d1d776b2a5..edf4f2321e 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -30,10 +30,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select PARALLEL_MP select C_ENVIRONMENT_BOOTBLOCK -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/pineview/bootblock.c" - config VGA_BIOS_ID string default "8086,a001" diff --git a/src/northbridge/intel/pineview/acpi/hostbridge.asl b/src/northbridge/intel/pineview/acpi/hostbridge.asl index 3eff101d99..6b6ef4afe2 100644 --- a/src/northbridge/intel/pineview/acpi/hostbridge.asl +++ b/src/northbridge/intel/pineview/acpi/hostbridge.asl @@ -19,7 +19,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Device (MCHC) diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 72f97e4ba9..c7602e10f8 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -16,6 +16,7 @@ #include "hostbridge.asl" #include "../iomap.h" +#include /* PCI Device Resource Consumption */ Device (PDRC) @@ -28,7 +29,7 @@ Device (PDRC) */ Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) /* RCBA */ + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index be6a5e27d6..1638f0e15a 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -135,26 +135,8 @@ static void early_misc_setup(void) pci_write_config8(LPC, 0x8, 0x1d); pci_write_config8(LPC, 0x8, 0x0); RCBA32(0x3410) = 0x00020465; - RCBA32(0x88) = 0x0011d000; - RCBA32(0x1fc) = 0x60f; - RCBA32(0x1f4) = 0x86000040; - RCBA32(0x214) = 0x10030509; - RCBA32(0x218) = 0x00020504; - RCBA32(0x220) = 0xc5; - RCBA32(0x3430) = 0x1; - RCBA32(0x2027) = 0x38f6a70d; - RCBA16(0x3e08) = 0x0080; - RCBA16(0x3e48) = 0x0080; - RCBA32(0x3e0e) = 0x00000080; - RCBA32(0x3e4e) = 0x00000080; - RCBA32(0x2034) = 0xb24577cc; - RCBA32(0x1c) = 0x03128010; - RCBA32(0x2010) = 0x400; - RCBA32(0x3400) = 0x4; - RCBA32(0x2080) = 0x18006007; - RCBA32(0x20a0) = 0x18006007; - RCBA32(0x20c0) = 0x18006007; - RCBA32(0x20e0) = 0x18006007; + + ich7_setup_cir(); pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1); pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1); diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index b4fef6bc76..0aa70cdb34 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -132,7 +132,7 @@ static uintptr_t northbridge_get_tseg_base(void) * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +void *cbmem_top_chipset(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); return (void *) top_of_ram; diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 34cb583c49..fc71bc3b6e 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 5cece4147f..7f59d9197b 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -552,10 +552,12 @@ static void sdram_detect_ram_speed(struct sysinfo *s) static void enable_hpet(void) { u32 reg32; - reg32 = RCBA32(0x3404); + reg32 = RCBA32(HPTC); reg32 &= ~0x3; reg32 |= (1 << 7); - RCBA32(0x3404) = reg32; + RCBA32(HPTC) = reg32; + /* On NM10 this only works if read back */ + RCBA32(HPTC); HPET32(0x10) = HPET32(0x10) | 1; } diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 4c4a509686..8f35137a38 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -18,7 +18,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Device (MCHC) diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 7fdfe4283c..3181fc0a3f 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -17,6 +17,7 @@ #include "hostbridge.asl" #include "peg.asl" +#include /* PCI Device Resource Consumption */ Device (PDRC) @@ -25,7 +26,7 @@ Device (PDRC) Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) // Filled by _CRS Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB) Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB) diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 95bf4584ed..99888fa2ae 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -32,7 +31,7 @@ static uintptr_t smm_region_start(void) return tom; } -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return (void *) smm_region_start(); } diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 58f4a6812d..6337d69020 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -25,7 +25,6 @@ #include #include #include -#include #include "chip.h" #include "sandybridge.h" #include diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index d505728a3b..8664c5d311 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -202,7 +202,6 @@ enum platform_type { #define DMIDRCCFG 0xeb4 /* 32bit */ #ifndef __ASSEMBLER__ -static inline void barrier(void) { asm("" ::: "memory"); } #ifdef __SMM__ void intel_sandybridge_finalize_smm(void); diff --git a/src/northbridge/intel/x4x/acpi/hostbridge.asl b/src/northbridge/intel/x4x/acpi/hostbridge.asl index 90f15c78c1..e3ea18c008 100644 --- a/src/northbridge/intel/x4x/acpi/hostbridge.asl +++ b/src/northbridge/intel/x4x/acpi/hostbridge.asl @@ -20,7 +20,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Device (MCHC) diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 8458db3df2..a486808124 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -17,6 +17,7 @@ #include "hostbridge.asl" #include "../iomap.h" +#include /* PCI Device Resource Consumption */ Device (PDRC) @@ -25,7 +26,7 @@ Device (PDRC) Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 61731fee3e..6956f87b4d 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include "chip.h" diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 41e491200b..1924ddf678 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -128,7 +128,7 @@ static uintptr_t northbridge_get_tseg_base(void) * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +void *cbmem_top_chipset(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); return (void *) top_of_ram; diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index ee705277cb..39f24d302b 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 05479a1602..76d94c6c17 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -18,6 +18,8 @@ #ifndef __NORTHBRIDGE_INTEL_X4X_H__ #define __NORTHBRIDGE_INTEL_X4X_H__ +#include "iomap.h" + /* * D0:F0 */ diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc index bbfe63b45a..247cc249bf 100644 --- a/src/northbridge/via/vx900/Makefile.inc +++ b/src/northbridge/via/vx900/Makefile.inc @@ -28,7 +28,6 @@ romstage-y += ./../../../southbridge/via/common/early_smbus_is_busy.c romstage-y += ./../../../southbridge/via/common/early_smbus_print_error.c romstage-y += ./../../../southbridge/via/common/early_smbus_reset.c romstage-y += ./../../../southbridge/via/common/early_smbus_wait_until_ready.c -romstage-y += ./../../../drivers/pc80/pc/udelay_io.c ramstage-y += pci_util.c ramstage-y += pcie.c diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index cab783e5ba..fd4d5ad2a2 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -235,7 +235,7 @@ static struct device_operations vx900_lpc_ops = { .set_resources = vx900_lpc_set_resources, .enable_resources = pci_dev_enable_resources, .init = vx900_lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c index d11dc65fd6..3121d7406e 100644 --- a/src/northbridge/via/vx900/memmap.c +++ b/src/northbridge/via/vx900/memmap.c @@ -120,7 +120,7 @@ u32 vx900_get_tolm(void) return (pci_read_config16(MCU, 0x84) & 0xfff0) >> 4; } -void *cbmem_top(void) +void *cbmem_top_chipset(void) { uintptr_t tolm; uintptr_t fb_size; diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c index 8f3f6023ad..2ef542afb8 100644 --- a/src/northbridge/via/vx900/traf_ctrl.c +++ b/src/northbridge/via/vx900/traf_ctrl.c @@ -132,7 +132,7 @@ static struct device_operations traf_ctrl_ops = { .init = vx900_traf_ctr_init, /* Need this here, or the IOAPIC driver won't be called. * FIXME: Technically not a LPC bus. */ - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, }; static const struct pci_driver traf_ctrl_driver __pci_driver = { diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc index d24026ae62..38eb65d69c 100644 --- a/src/security/intel/txt/Makefile.inc +++ b/src/security/intel/txt/Makefile.inc @@ -17,4 +17,16 @@ INTERMEDIATE+=add_acm_fit add_acm_fit: $(obj)/coreboot.pre $(IFITTOOL) $(IFITTOOL) -r COREBOOT -a -n txt_bios_acm.bin -t 2 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< +# Initial BootBlock files +ibb-files := $(foreach file,$(cbfs-files), \ + $(if $(shell echo '$(call extract_nth,7,$(file))'|grep -- --ibb), \ + $(call extract_nth,2,$(file)),)) + +ibb-files += bootblock + +INTERMEDIATE+=add_ibb_fit +add_ibb_fit: $(obj)/coreboot.pre $(IFITTOOL) + $(foreach file, $(ibb-files), $(shell $(IFITTOOL) -f $< -a -n $(file) -t 7 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ + -r COREBOOT)) true + endif diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c index 638c41a929..45bee91036 100644 --- a/src/security/memory/memory_clear.c +++ b/src/security/memory/memory_clear.c @@ -127,7 +127,8 @@ static void clear_memory(void *unused) __func__, range_entry_base(r), range_entry_end(r)); /* Does regular memset work? */ - if (!(range_entry_end(r) >> sizeof(void *) * 8)) { + if (sizeof(resource_t) == sizeof(void *) || + !(range_entry_end(r) >> (sizeof(void *) * 8))) { /* fastpath */ memset((void *)(uintptr_t)range_entry_base(r), 0, range_entry_size(r)); diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index 3af6d69e2b..95c0bb9b7d 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -93,4 +93,13 @@ config TPM_RDRESP_NEED_DELAY to work around a race-condition-related issue, possibly caused by ill-programmed TPM firmware. +config TPM_STARTUP_IGNORE_POSTINIT + bool + help + Select this to ignore POSTINIT INVALID return codes on TPM + startup. This is useful on platforms where a previous stage + issued a TPM startup. Examples of use cases are Intel TXT + or VBOOT on the Intel Nehalem northbridge which issues a + CPU-only reset during the romstage. + endmenu # Trusted Platform Module (tpm) diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 4698a4dc8c..966b8b7c77 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -141,6 +141,11 @@ uint32_t tpm_setup(int s3flag) } result = tlcl_startup(); + if (CONFIG(TPM_STARTUP_IGNORE_POSTINIT) + && result == TPM_E_INVALID_POSTINIT) { + printk(BIOS_DEBUG, "TPM: ignoring invalid POSTINIT\n"); + result = TPM_SUCCESS; + } if (result != TPM_SUCCESS) { printk(BIOS_ERR, "TPM: Can't run startup command.\n"); return tpm_setup_epilogue(result); diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index abb8863c02..31c0f5de26 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -155,6 +155,7 @@ $(CONFIG_CBFS_PREFIX)/verstage-options += --xip endif endif +$(CONFIG_CBFS_PREFIX)/verstage-options += $(TXTIBB) else # CONFIG_VBOOT_SEPARATE_VERSTAGE ifeq ($(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK),y) diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index 0c4f33bc11..eccd743012 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -43,7 +43,7 @@ static inline uint8_t vbnv_data(int index) /* Return CRC-8 of the data, using x^8 + x^2 + x + 1 polynomial. */ static uint8_t crc8_vbnv(const uint8_t *data, int len) { - unsigned crc = 0; + unsigned int crc = 0; int i, j; for (j = len; j; j--, data++) { diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index cbd7a2ee23..2d35c6be05 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index d049740776..da6231ae65 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -87,6 +87,11 @@ vb2_error_t vb2ex_read_resource(struct vb2_context *ctx, return VB2_SUCCESS; } +void vb2ex_abort(void) +{ + die("vboot has aborted execution; exit\n"); +} + /* No-op stubs that can be overridden by SoCs with hardware crypto support. */ __weak vb2_error_t vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg, uint32_t data_size) diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index edb3882e6f..7fad456106 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -65,7 +65,39 @@ void pm_io_write32(uint8_t reg, uint32_t value) pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); } -/* smbus pci read/write - access registers at 0xfed80000 - currently unused */ +#if SUPPORTS_ACPIMMIO_SM_PCI_BASE +/* smbus pci read/write - access registers at 0xfed80000 */ + +u8 sm_pci_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +} + +u16 sm_pci_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +} + +u32 sm_pci_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +} + +void sm_pci_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +} + +void sm_pci_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +} + +void sm_pci_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +} +#endif #if SUPPORTS_ACPIMMIO_SMI_BASE /* smi read/write - access registers at 0xfed80200 */ diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index 27510c3fad..c24e32d6be 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2010-2019 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,6 +16,8 @@ #include #include #include +#include +#include static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_SB900_HDA, @@ -36,7 +38,8 @@ static struct device_operations hda_audio_ops = { }; static const struct pci_driver hdaaudio_driver __pci_driver = { - .ops = &hda_audio_ops, + .ops = CONFIG(AZALIA_PLUGIN_SUPPORT) ? + &default_azalia_audio_ops : &hda_audio_ops, .vendor = PCI_VENDOR_ID_AMD, .devices = pci_device_ids, }; diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 59ab9e5f4f..ca57cf5dcc 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -21,6 +21,9 @@ #include /* iomap.h must indicate if the device uses a block, optional if unused. */ #include +#ifndef SUPPORTS_ACPIMMIO_SM_PCI_BASE + #define SUPPORTS_ACPIMMIO_SM_PCI_BASE 0 +#endif #ifndef SUPPORTS_ACPIMMIO_SMI_BASE #define SUPPORTS_ACPIMMIO_SMI_BASE 0 #endif @@ -162,6 +165,14 @@ /* Enable the AcpiMmio range at 0xfed80000 */ void enable_acpimmio_decode(void); +/* Access SMBus PCI registers at 0xfed80000 */ +uint8_t sm_pci_read8(uint8_t reg); +uint16_t sm_pci_read16(uint8_t reg); +uint32_t sm_pci_read32(uint8_t reg); +void sm_pci_write8(uint8_t reg, uint8_t value); +void sm_pci_write16(uint8_t reg, uint16_t value); +void sm_pci_write32(uint8_t reg, uint32_t value); + /* Access PM registers using IO cycles */ uint8_t pm_io_read8(uint8_t reg); uint16_t pm_io_read16(uint8_t reg); diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 11880eb3e6..2874c18879 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -75,6 +75,8 @@ #define LPC_WIDEIO0_ENABLE BIT(2) #define DECODE_ALTERNATE_SIO_ENABLE BIT(1) #define DECODE_SIO_ENABLE BIT(0) +#define LPC_SELECT_SIO_4E4F 1 +#define LPC_SELECT_SIO_2E2F 0 #define WIDEIO_RANGE_ERROR -1 /* Assuming word access to higher word (register 0x4a) */ @@ -151,6 +153,8 @@ void soc_late_lpc_bridge_enable(void); void lpc_enable_port80(void); void lpc_enable_pci_port80(void); void lpc_enable_decode(uint32_t decodes); +/* addr = index/data to enable: LPC_SELECT_SIO_2E2F or LPC_SELECT_SIO_4E4F */ +void lpc_enable_sio_decode(const bool addr); uintptr_t lpc_spibase(void); void lpc_tpm_decode(void); void lpc_tpm_decode_spi(void); diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index c7946015cb..628273dd35 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -330,7 +330,7 @@ static struct device_operations lpc_ops = { .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index 1d46acbf5c..cdf36b2988 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -165,6 +165,18 @@ void lpc_enable_pci_port80(void) pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); } +void lpc_enable_sio_decode(const bool addr) +{ + uint32_t decodes; + uint32_t enable; + + decodes = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); + enable = addr == LPC_SELECT_SIO_2E2F ? + DECODE_SIO_ENABLE : DECODE_ALTERNATE_SIO_ENABLE; + decodes |= enable; + pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, decodes); +} + void lpc_enable_decode(uint32_t decodes) { pci_write_config32(_LPCB_DEV, LPC_IO_PORT_DECODE_ENABLE, decodes); diff --git a/src/soc/amd/common/block/spi/fch_spi_special.c b/src/soc/amd/common/block/spi/fch_spi_special.c index 456a3896f5..fa3c00ac84 100644 --- a/src/soc/amd/common/block/spi/fch_spi_special.c +++ b/src/soc/amd/common/block/spi/fch_spi_special.c @@ -16,7 +16,6 @@ #include #include #include -#include int non_standard_sst_byte_write(u32 offset, const void *buf) { diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index f5f926e734..5f9792b28a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2017 Advanced Micro Devices, Inc. +## Copyright (C) 2019 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -33,12 +33,10 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_GPIO_LIB select IOAPIC select HAVE_USBDEBUG_OPTIONS - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SOC_AMD_COMMON_BLOCK_SPI select TSC_SYNC_LFENCE select UDELAY_TSC - select COLLECT_TIMESTAMPS select SOC_AMD_PI select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK @@ -111,14 +109,14 @@ config MMCONF_BUS_NUMBER config VGA_BIOS_ID string - default "1002,98e4" + default "1002,15d8" help The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c. config VGA_BIOS_FILE string - default "3rdparty/blobs/soc/amd/picasso/VBIOS.bin" + default "3rdparty/blobs/soc/amd/picasso/PicassoGenericVbios.bin" config S3_VGA_ROM_RUN bool @@ -132,58 +130,6 @@ config EHCI_BAR hex default 0xfef00000 -config AMD_PUBKEY_FILE - string "AMD public Key" - default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyST.bin" - -config PICASSO_SATA_MODE - int "SATA Mode" - default 0 - range 0 6 - help - Select the mode in which SATA should be driven. - The default is NATIVE. - 0: NATIVE mode does not require a ROM. - 2: AHCI may work with or without AHCI ROM. It depends on the payload support. - For example, seabios does not require the AHCI ROM. - 3: LEGACY IDE - 4: IDE to AHCI - 5: AHCI7804: ROM Required, and AMD driver required in the OS. - 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. - -comment "NATIVE" - depends on PICASSO_SATA_MODE = 0 - -comment "AHCI" - depends on PICASSO_SATA_MODE = 2 - -comment "LEGACY IDE" - depends on PICASSO_SATA_MODE = 3 - -comment "IDE to AHCI" - depends on PICASSO_SATA_MODE = 4 - -comment "AHCI7804" - depends on PICASSO_SATA_MODE = 5 - -comment "IDE to AHCI7804" - depends on PICASSO_SATA_MODE = 6 - -if PICASSO_SATA_MODE = 2 || PICASSO_SATA_MODE = 5 - -config AHCI_ROM_ID - string "AHCI device PCI IDs" - default "1022,7801" if PICASSO_SATA_MODE = 2 - default "1022,7804" if PICASSO_SATA_MODE = 5 - -endif # PICASSO_SATA_MODE = 2 || PICASSO_SATA_MODE = 5 - -config PICASSO_LEGACY_FREE - bool "System is legacy free" - help - Select y if there is no keyboard controller in the system. - This sets a variable in ACPI. - config SERIRQ_CONTINUOUS_MODE bool default n @@ -205,16 +151,46 @@ config PICASSO_UART select NO_UART_ON_SUPERIO select UART_OVERRIDE_REFCLK help - There are two UART controllers in Picasso. - The UART registers are memory-mapped. UART - controller 0 registers range from FEDC_6000h - to FEDC_6FFFh. UART controller 1 registers - range from FEDC_8000h to FEDC_8FFFh. + There are four memory-mapped UARTs controllers in Picasso at: + 0: 0xfedc9000 + 1: 0xfedca000 + 2: 0xfedc3000 + 3: 0xfedcf000 + +choice PICASSO_UART_CLOCK_SOURCE + prompt "UART Frequency" + depends on PICASSO_UART + default PICASSO_UART_48MZ + +config PICASSO_UART_48MZ + bool "48 MHz clock" + help + Select this option for the most compatibility. + +config PICASSO_UART_1_8MZ + bool "1.8432 MHz clock" + help + Select this option if an old payload or Linux ttyS0 arguments + require it. + +endchoice + +config PICASSO_UART_LEGACY + bool "Decode legacy I/O range" + depends on PICASSO_UART + help + Assign I/O 3F8, 2F8, etc. to a Picasso UART. Only a single UART may + decode legacy addresses and this option enables the one used for the + console. A UART accessed with I/O does not allow all the features + of MMIO. The MMIO decode is still present when this option is used. config CONSOLE_UART_BASE_ADDRESS - depends on CONSOLE_SERIAL + depends on CONSOLE_SERIAL && PICASSO_UART hex - default 0xfedc6000 + default 0xfedc9000 if UART_FOR_CONSOLE = 0 + default 0xfedca000 if UART_FOR_CONSOLE = 1 + default 0xfedc3000 if UART_FOR_CONSOLE = 2 + default 0xfedcf000 if UART_FOR_CONSOLE = 3 config SMM_TSEG_SIZE hex @@ -242,14 +218,30 @@ config ACPI_BERT ACPI Boot Error Record Table. This option reserves an 8MB region for building the error structures. -config USE_PSPSECUREOS - bool "Include PSP SecureOS blobs in AMD firmware" - default y - help - Include the PspSecureOs, PspTrustlet and TrustletKey binaries - in the amdfw section. +config RO_REGION_ONLY + string + depends on CHROMEOS + default "apu/amdfw" - If unsure, answer 'y' +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 + +config PICASSO_LPC_IOMUX + bool + help + Picasso's LPC bus signals are MUXed with some of the EMMC signals. + Select this option if LPC signals are required. + +config MAINBOARD_POWER_RESTORE + def_bool n + help + This option determines what state to go to once power is restored + after having been lost in S0. Select this option to automatically + return to S0. Otherwise the system will remain in S5 once power + is restored. + +menu "PSP Configuration Options" config AMDFW_OUTSIDE_CBFS bool "The AMD firmware is outside CBFS" @@ -292,21 +284,101 @@ comment "AMD Firmware Directory Table set to location for 8MB ROM" comment "AMD Firmware Directory Table set to location for 16MB ROM" depends on AMD_FWM_POSITION_INDEX = 5 -config RO_REGION_ONLY - string - depends on CHROMEOS - default "apu/amdfw" +config AMD_PUBKEY_FILE + string "AMD public Key" + default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin" -config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ - int - default 133 - -config MAINBOARD_POWER_RESTORE - def_bool n +config PSP_APCB_FILE + string "APCB file" help - This option determines what state to go to once power is restored - after having been lost in S0. Select this option to automatically - return to S0. Otherwise the system will remain in S5 once power - is restored. + The name of the AGESA Parameter Customization Block. This image is + instance ID 0 in the PSP's BIOS Directory Table. + +config PSP_APCB1_FILE + string + help + If specified, this image is instance ID 1 in the PSP's BIOS + Directory Table. + +config PSP_APCB2_FILE + string + help + If specified, this image is instance ID 2 in the PSP's BIOS + Directory Table. + +config PSP_APCB3_FILE + string + help + If specified, this image is instance ID 3 in the PSP's BIOS + Directory Table. + +config PSP_APCB4_FILE + string + help + If specified, this image is instance ID 4 in the PSP's BIOS + Directory Table. + +config PSP_APOB_DESTINATION + hex + default 0x9f00000 + help + Location in DRAM where the PSP will copy the AGESA PSP Output + Block. + +config PSP_APOB_NV_ADDRESS + hex "Base address of APOB NV" + default 0xffa68000 + help + Location in flash where the PSP can find the S3 restore information. + Place this on a boundary that the flash device can erase. + TODO: The above default value is arbitrary, but eventually coreboot's + MRC cache base address should be used. + +config PSP_APOB_NV_SIZE + hex "Size of APOB NV to be reserved" + default 0x10000 + help + Size of the S3 restore information. Make this a multiple of the + size the flash device can erase. + TODO: The above default value is arbitrary, but eventually coreboot's + MRC cache size should be used. + +config USE_PSPSCUREOS + bool "Include PSP SecureOS blobs in PSP build" + default y + help + Include the PspSecureOs and PspTrustlet binaries in the PSP build. + + If unsure, answer 'y' + +config PSP_LOAD_MP2_FW + bool "Include MP2 blobs in PSP build" + default y + help + Include the MP2 firmwares and configuration into the PSP build. + + If unsure, answer 'y' + +config PSP_LOAD_S0I3_FW + bool "Include S0I3 blob in PSP build" + help + Select this item to include the S0i3 file into the PSP build. + +config HAVE_PSP_WHITELIST_FILE + bool "Include a debug whitelist file in PSP build" + default n + help + Support secured unlock prior to reset using a whitelisted + number? This feature requires a signed whitelist image and + bootloader from AMD. + + If unsure, answer 'n' + +config PSP_WHITELIST_FILE + string "Debug whitelist file name" + depends on HAVE_PSP_WHITELIST_FILE + default "3rdparty/blobs/soc/amd/picasso/PSP/wtl-rvn.sbin" + +endmenu endif # SOC_AMD_PICASSO diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 38c00a8dd0..76a4d70a8a 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -1,6 +1,6 @@ #***************************************************************************** # -# Copyright (c) 2012, 2016-2017 Advanced Micro Devices, Inc. +# Copyright (c) 2012, 2016-2019 Advanced Micro Devices, Inc. # 2013 - 2014 Sage Electronic Engineering, LLC # All rights reserved. # @@ -72,6 +72,7 @@ ramstage-y += southbridge.c ramstage-y += northbridge.c ramstage-y += pmutil.c ramstage-y += reset.c +ramstage-y += acp.c ramstage-y += sata.c ramstage-y += sm.c ramstage-y += smbus.c @@ -96,126 +97,307 @@ CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi # ROMSIG Normally At ROMBASE + 0x20000 # Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ -# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# |0x55AA55AA | | | | # +-----------+---------------+----------------+------------+ -# |PSPDIR ADDR| -# +-----------+ -# -# EC ROM should be 64K aligned. +# | | PSPDIR ADDR | BIOSDIR ADDR | +# +-----------+---------------+----------------+ + PICASSO_FWM_POSITION=$(call int-add, \ $(call int-subtract, 0xffffffff \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) -### 0 +# +# PSP Directory Table items +# +# Certain ordering requirements apply, however these are ensured by amdfwtool. +# For more information see "AMD Platform Security Processor BIOS Architecture +# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). +# + +# type = 0x0 FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) -FIRMWARE_TYPE=ST -###5 -PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key - -###1 -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin - -###3 -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin - -###4 -PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin - -###8 - Check for SMU firmware named either *.sbin or *.csbin -### TODO: Remove *.sbin section after the blobs repo is updated. -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE).csbin -ifeq ("$(wildcard $(SMUFWM_FILE))","") -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin +# type = 0x1 +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_WL_RV.sbin +else +PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_RV.sbin endif -###95 -SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin +# type = 0x5 +PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSignedRV.key -###9 -PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key +# types = 0x8 and 0x18 +PSP_SMUFW1_SUB1_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmwareRV2.csbin +PSP_SMUFW1_SUB2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmwarePCO.csbin +PSP_SMUFW2_SUB1_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2RV2.csbin +PSP_SMUFW2_SUB2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2PCO.csbin -ifeq ($(CONFIG_USE_PSPSECUREOS),y) -###2 -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin +# type = 0x9 +PSP_SEC_DBG_KEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RavenSecureDebug_PublicKey.bin -###12 -PSPTRUSTLETS_FILE=$(wildcard $(top)/$(FIRMWARE_LOCATE)/PspTrustlets*_prod_$(FIRMWARE_TYPE).cbin) +# type = 0xb - See #55758 (NDA) for bit definitions. +PSP_SOFTFUSE="0x0000000010000001" -###13 -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin +ifeq ($(CONFIG_USE_PSPSCUREOS),y) +# types = 0x2, 0xc +PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/psp_os_combined_prod_RV.sbin +PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/dr_ftpm_prod_RV.csbin endif -###18- Check for SMU firmware2 named either *.sbin or *.csbin -### TODO: Remove *.sbin section after the blobs repo is updated. -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).csbin -ifeq ("$(wildcard $(SMUFIRMWARE2_FILE))","") -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin +# type = 0x13 +PSP_SEC_DEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/secure_unlock_prod_RV.sbin + +# type = 0x21 +PSP_IKEK_FILE=$(top)/$(FIRMWARE_LOCATE)/PspIkekRV.bin + +# type = 0x24 +PSP_SECG1_FILE=$(top)/$(FIRMWARE_LOCATE)/security_policy_RV2_FP5_AM4.sbin +PSP_SECG2_FILE=$(top)/$(FIRMWARE_LOCATE)/security_policy_PCO_FP5_AM4.sbin + +ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) +# type = 0x25 +PSP_MP2FW1_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2I2CFWRV2.sbin +PSP_MP2FW2_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2I2CFWPCO.sbin +# BIOS type = 0x6a +PSP_MP2CFG_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2FWConfig.sbin +else +PSP_SOFTFUSE="0x0000000030000001" endif +# type = 0x28 +PSP_DRIVERS_FILE=$(top)/$(FIRMWARE_LOCATE)/drv_sys_prod_RV.sbin + +ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y) +PSP_S0I3_FILE=$(top)/$(FIRMWARE_LOCATE)/dr_agesa_prod_RV.sbin +endif + +# types = 0x30 - 0x37 +PSP_ABL0_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader0_prod_RV.csbin +PSP_ABL1_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader1_prod_RV.csbin +PSP_ABL2_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader2_prod_RV.csbin +PSP_ABL3_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader3_prod_RV.csbin +PSP_ABL4_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader4_prod_RV.csbin +PSP_ABL5_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader5_prod_RV.csbin +PSP_ABL6_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader6_prod_RV.csbin +PSP_ABL7_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader7_prod_RV.csbin + +# type = 0x3a +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) +endif + +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x60 +PSP_APCB0_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB_FILE)) +PSP_APCB1_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB1_FILE)) +PSP_APCB2_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB2_FILE)) +PSP_APCB3_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB3_FILE)) +PSP_APCB4_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB4_FILE)) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DESTINATION) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_BIOSBIN_DEST=$(CONFIG_ROMSTAGE_ADDR) +PSP_BIOSBIN_SIZE=$(CONFIG_RAM_RESET_VECTOR_STAGE_SIZE) + +# type = 0x63 +PSP_APOBNV_BASE=$(CONFIG_PSP_APOB_NV_ADDRESS) +PSP_APOBNV_SIZE=$(CONFIG_PSP_APOB_NV_SIZE) + +# type2 = 0x64, 0x65 +PSP_PMUI_FILE1=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE2=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_2D_Ddr4_Imem.csbin +PSP_PMUI_FILE3=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_1D_ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE4=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_2D_ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE1=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE2=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_2D_Ddr4_Dmem.csbin +PSP_PMUD_FILE3=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE4=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin + +# type = 0x66 +PSP_UCODE_FILE1=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_PCO_B1.bin +PSP_UCODE_FILE2=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_PCO_B0.bin +PSP_UCODE_FILE3=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_RV2_A0.bin + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) -OPT_SMUFWM_FILE=$(call add_opt_prefix, $(SMUFWM_FILE), --smufirmware) -OPT_PSPRCVR_FILE=$(call add_opt_prefix, $(PSPRCVR_FILE), --recovery) -OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(PUBSIGNEDKEY_FILE), --rtmpubkey) OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(PSPNVRAM_FILE), --nvram) -OPT_PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(PSPSECUREDEBUG_FILE), --securedebug) -ifeq ($(CONFIG_USE_PSPSECUREOS),y) +OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(PUBSIGNEDKEY_FILE), --rtmpubkey) +OPT_SMUFW1_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB1_FILE), --subprogram 1 --smufirmware) +OPT_SMUFW1_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB2_FILE), --subprogram 2 --smufirmware) +OPT_SMUFW2_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB1_FILE), --subprogram 1 --smufirmware2) +OPT_SMUFW2_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB2_FILE), --subprogram 2 --smufirmware2) +OPT_PSP_SEC_DBG_KEY_FILE=$(call add_opt_prefix, $(PSP_SEC_DBG_KEY_FILE), --securedebug) +OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) OPT_PSPSCUREOS_FILE=$(call add_opt_prefix, $(PSPSCUREOS_FILE), --secureos) OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(PSPTRUSTLETS_FILE), --trustlets) -OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(TRUSTLETKEY_FILE), --trustletkey) -endif -OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FILE), --smufirmware2) -OPT_SMUSCS_FILE=$(call add_opt_prefix, $(SMUSCS_FILE), --smuscs) +OPT_SEC_DEBUG_FILE=$(call add_opt_prefix, $(PSP_SEC_DEBUG_FILE), --secdebug) +OPT_IKEK_FILE=$(call add_opt_prefix, $(PSP_IKEK_FILE), --ikek) +OPT_SECG1_FILE=$(call add_opt_prefix, $(PSP_SECG1_FILE), --subprog 1 --sec-gasket) +OPT_SECG2_FILE=$(call add_opt_prefix, $(PSP_SECG2_FILE), --subprog 2 --sec-gasket) +OPT_MP2FW1_FILE=$(call add_opt_prefix, $(PSP_MP2FW1_FILE), --subprog 1 --mp2-fw) +OPT_MP2FW2_FILE=$(call add_opt_prefix, $(PSP_MP2FW2_FILE), --subprog 2 --mp2-fw) +OPT_DRIVERS_FILE=$(call add_opt_prefix, $(PSP_DRIVERS_FILE), --drv-entry-pts) +OPT_PSP_S0I3_FILE=$(call add_opt_prefix, $(PSP_S0I3_FILE), --s0i3drv) +OPT_ABL0_FILE=$(call add_opt_prefix, $(PSP_ABL0_FILE), --abl-image) +OPT_ABL1_FILE=$(call add_opt_prefix, $(PSP_ABL1_FILE), --abl-image) +OPT_ABL2_FILE=$(call add_opt_prefix, $(PSP_ABL2_FILE), --abl-image) +OPT_ABL3_FILE=$(call add_opt_prefix, $(PSP_ABL3_FILE), --abl-image) +OPT_ABL4_FILE=$(call add_opt_prefix, $(PSP_ABL4_FILE), --abl-image) +OPT_ABL5_FILE=$(call add_opt_prefix, $(PSP_ABL5_FILE), --abl-image) +OPT_ABL6_FILE=$(call add_opt_prefix, $(PSP_ABL6_FILE), --abl-image) +OPT_ABL7_FILE=$(call add_opt_prefix, $(PSP_ABL7_FILE), --abl-image) +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) + +OPT_PSP_APCB0_FILE=$(call add_opt_prefix, $(PSP_APCB0_FILE), --instance 0 --apcb) +OPT_PSP_APCB1_FILE=$(call add_opt_prefix, $(PSP_APCB1_FILE), --instance 1 --apcb) +OPT_PSP_APCB2_FILE=$(call add_opt_prefix, $(PSP_APCB2_FILE), --instance 2 --apcb) +OPT_PSP_APCB3_FILE=$(call add_opt_prefix, $(PSP_APCB3_FILE), --instance 3 --apcb) +OPT_PSP_APCB4_FILE=$(call add_opt_prefix, $(PSP_APCB4_FILE), --instance 4 --apcb) +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) +OPT_APOBNV_ADDR=$(call add_opt_prefix, $(PSP_APOBNV_BASE), --apob-nv-base) +OPT_APOBNV_SIZE=$(call add_opt_prefix, $(PSP_APOBNV_SIZE), --apob-nv-size) +OPT_PSP_PMUI_FILE1=$(call add_opt_prefix, $(PSP_PMUI_FILE1), --subprogram 0 --instance 1 --pmu-inst) +OPT_PSP_PMUI_FILE2=$(call add_opt_prefix, $(PSP_PMUI_FILE2), --subprogram 0 --instance 4 --pmu-inst) +OPT_PSP_PMUI_FILE3=$(call add_opt_prefix, $(PSP_PMUI_FILE3), --subprogram 1 --instance 1 --pmu-inst) +OPT_PSP_PMUI_FILE4=$(call add_opt_prefix, $(PSP_PMUI_FILE4), --subprogram 1 --instance 4 --pmu-inst) +OPT_PSP_PMUD_FILE1=$(call add_opt_prefix, $(PSP_PMUD_FILE1), --subprogram 0 --instance 1 --pmu-data) +OPT_PSP_PMUD_FILE2=$(call add_opt_prefix, $(PSP_PMUD_FILE2), --subprogram 0 --instance 4 --pmu-data) +OPT_PSP_PMUD_FILE3=$(call add_opt_prefix, $(PSP_PMUD_FILE3), --subprogram 1 --instance 1 --pmu-data) +OPT_PSP_PMUD_FILE4=$(call add_opt_prefix, $(PSP_PMUD_FILE4), --subprogram 1 --instance 4 --pmu-data) +OPT_PSP_UCODE_FILE1=$(call add_opt_prefix, $(PSP_UCODE_FILE1), --instance 0 --ucode) +OPT_PSP_UCODE_FILE2=$(call add_opt_prefix, $(PSP_UCODE_FILE2), --instance 1 --ucode) +OPT_PSP_UCODE_FILE3=$(call add_opt_prefix, $(PSP_UCODE_FILE3), --instance 2 --ucode) +OPT_MP2CFG_FILE=$(call add_opt_prefix, $(PSP_MP2CFG_FILE), --mp2-config) $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ - $(call strip_quotes, $(PSPRCVR_FILE)) \ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ - $(call strip_quotes, $(PSPNVRAM_FILE)) \ - $(call strip_quotes, $(SMUFWM_FILE)) \ - $(call strip_quotes, $(SMUSCS_FILE)) \ - $(call strip_quotes, $(PSPSECUREDEBUG_FILE)) \ + $(call strip_quotes, $(PSP_SEC_DBG_KEY_FILE)) \ $(call strip_quotes, $(PSPTRUSTLETS_FILE)) \ - $(call strip_quotes, $(TRUSTLETKEY_FILE)) \ - $(call strip_quotes, $(SMUFIRMWARE2_FILE)) \ + $(call strip_quotes, $(PSP_APCB0_FILE)) \ + $(call strip_quotes, $(PSP_APCB1_FILE)) \ + $(call strip_quotes, $(PSP_APCB2_FILE)) \ + $(call strip_quotes, $(PSP_APCB3_FILE)) \ + $(call strip_quotes, $(PSP_APCB4_FILE)) \ + $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $(call strip_quotes, $(PSP_PMUI_FILE1)) \ + $(call strip_quotes, $(PSP_PMUI_FILE2)) \ + $(call strip_quotes, $(PSP_PMUI_FILE3)) \ + $(call strip_quotes, $(PSP_PMUI_FILE4)) \ + $(call strip_quotes, $(PSP_PMUD_FILE1)) \ + $(call strip_quotes, $(PSP_PMUD_FILE2)) \ + $(call strip_quotes, $(PSP_PMUD_FILE3)) \ + $(call strip_quotes, $(PSP_PMUD_FILE4)) \ + $(call strip_quotes, $(PSP_UCODE_FILE1)) \ + $(call strip_quotes, $(PSP_UCODE_FILE2)) \ + $(call strip_quotes, $(PSP_UCODE_FILE3)) \ + $(call strip_quotes, $(PSP_MP2CFG_FILE)) \ + $(call strip_quotes, $(PSP_SMUFW1_SUB1_FILE)) \ + $(call strip_quotes, $(PSP_SMUFW1_SUB2_FILE)) \ + $(call strip_quotes, $(PSP_SMUFW2_SUB1_FILE)) \ + $(call strip_quotes, $(PSP_SMUFW2_SUB2_FILE)) \ + $(call strip_quotes, $(PSP_ABL0_FILE)) \ + $(call strip_quotes, $(PSP_ABL1_FILE)) \ + $(call strip_quotes, $(PSP_ABL2_FILE)) \ + $(call strip_quotes, $(PSP_ABL3_FILE)) \ + $(call strip_quotes, $(PSP_ABL4_FILE)) \ + $(call strip_quotes, $(PSP_ABL5_FILE)) \ + $(call strip_quotes, $(PSP_ABL6_FILE)) \ + $(call strip_quotes, $(PSP_ABL7_FILE)) \ + $(call strip_quotes, $(PSP_WHITELIST_FILE)) \ + $(call strip_quotes, $(PSP_SECG1_FILE)) \ + $(call strip_quotes, $(PSP_SECG2_FILE)) \ + $(call_strip_quotes, $(PSP_DRIVERS_FILE)) \ + $(call_strip_quotes, $(PSP_S0I3_FILE)) \ + $(call_strip_quotes, $(PSP_IKEK_FILE)) \ + $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ $(OPT_AMD_PUBKEY_FILE) \ $(OPT_PSPBTLDR_FILE) \ - $(OPT_SMUFWM_FILE) \ - $(OPT_PSPRCVR_FILE) \ $(OPT_PUBSIGNEDKEY_FILE) \ $(OPT_PSPSCUREOS_FILE) \ - $(OPT_PSPNVRAM_FILE) \ - $(OPT_PSPSECUREDEBUG_FILE) \ + $(OPT_PSP_SEC_DBG_KEY_FILE) \ $(OPT_PSPTRUSTLETS_FILE) \ - $(OPT_TRUSTLETKEY_FILE) \ - $(OPT_SMUFIRMWARE2_FILE) \ - $(OPT_SMUSCS_FILE) \ - $(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ - $(OPT_SMUFWM_FILE) \ - $(OPT_PSPRCVR_FILE) \ - $(OPT_PUBSIGNEDKEY_FILE) \ - $(OPT_PSPSCUREOS_FILE) \ - $(OPT_PSPNVRAM_FILE) \ - $(OPT_PSPSECUREDEBUG_FILE) \ - $(OPT_PSPTRUSTLETS_FILE) \ - $(OPT_TRUSTLETKEY_FILE) \ - $(OPT_SMUFIRMWARE2_FILE) \ - $(OPT_SMUSCS_FILE) \ + $(OPT_SMUFW1_SUB2_FILE) \ + $(OPT_SMUFW2_SUB2_FILE) \ + $(OPT_SMUFW1_SUB1_FILE) \ + $(OPT_SMUFW2_SUB1_FILE) \ + $(OPT_PSP_APCB0_FILE) \ + $(OPT_PSP_APCB1_FILE) \ + $(OPT_PSP_APCB2_FILE) \ + $(OPT_PSP_APCB3_FILE) \ + $(OPT_PSP_APCB4_FILE) \ + $(OPT_APOB_ADDR) \ + $(OPT_APOBNV_ADDR) \ + $(OPT_APOBNV_SIZE) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + $(OPT_PSP_SOFTFUSE) \ + $(OPT_PSP_PMUI_FILE1) \ + $(OPT_PSP_PMUI_FILE2) \ + $(OPT_PSP_PMUI_FILE3) \ + $(OPT_PSP_PMUI_FILE4) \ + $(OPT_PSP_PMUD_FILE1) \ + $(OPT_PSP_PMUD_FILE2) \ + $(OPT_PSP_PMUD_FILE3) \ + $(OPT_PSP_PMUD_FILE4) \ + $(OPT_PSP_UCODE_FILE1) \ + $(OPT_PSP_UCODE_FILE2) \ + $(OPT_PSP_UCODE_FILE3) \ + $(OPT_MP2CFG_FILE) \ + $(OPT_ABL0_FILE) \ + $(OPT_ABL1_FILE) \ + $(OPT_ABL2_FILE) \ + $(OPT_ABL3_FILE) \ + $(OPT_ABL4_FILE) \ + $(OPT_ABL5_FILE) \ + $(OPT_ABL6_FILE) \ + $(OPT_ABL7_FILE) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_SECG1_FILE) \ + $(OPT_SECG2_FILE) \ + $(OPT_MP2FW1_FILE) \ + $(OPT_MP2FW2_FILE) \ + $(OPT_DRIVERS_FILE) \ + $(OPT_PSP_S0I3_FILE) \ + $(OPT_IKEK_FILE) \ + $(OPT_SEC_DEBUG_FILE) \ --combo-capable \ + --token-unlock \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ --output $@ +USE_BIOS_FILE=$(obj)/cbfs/fallback/romstage.elf +$(PSP_BIOSBIN_FILE): $(obj)/cbfs/fallback/romstage.elf $(AMDCOMPRESS) + rm -f $@ + @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" + $(AMDCOMPRESS) --infile $(USE_BIOS_FILE) --outfile $@ --compress \ + --maxsize $(PSP_BIOSBIN_SIZE) + ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) PHONY+=add_amdfw INTERMEDIATE+=add_amdfw @@ -229,8 +411,9 @@ PICASSO_FWM_ROM_POSITION=$(call int-add, \ add_amdfw: $(obj)/coreboot.pre $(obj)/amdfw.rom printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \ "$(PICASSO_FWM_ROM_POSITION)" - dd if=$(obj)/amdfw.rom \ - of=$(obj)/coreboot.pre conv=notrunc bs=1 \ + dd oflag=seek_bytes \ + if=$(obj)/amdfw.rom \ + of=$(obj)/coreboot.pre conv=notrunc \ seek=$(PICASSO_FWM_ROM_POSITION) >/dev/null 2>&1 else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) @@ -242,11 +425,4 @@ apu/amdfw-type := raw endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -cbfs-files-y += smu_fw -cbfs-files-y += smu_fw2 -smu_fw-file := $(SMUFWM_FILE) -smu_fw-type := raw -smu_fw2-file := $(SMUFIRMWARE2_FILE) -smu_fw2-type := raw - endif # ($(CONFIG_SOC_AMD_PICASSO),y) diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c new file mode 100644 index 0000000000..ad5333a266 --- /dev/null +++ b/src/soc/amd/picasso/acp.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include "chip.h" +#include +#include +#include +#include +#include +#include + +static void enable(struct device *dev) +{ + const struct soc_amd_picasso_config *cfg; + const struct device *nb_dev = pcidev_path_on_root(GNB_DEVFN); + struct resource *res; + uintptr_t bar; + + pci_dev_enable_resources(dev); + + /* Set the proper I2S_PIN_CONFIG state */ + if (!nb_dev || !nb_dev->chip_info) + return; + + cfg = nb_dev->chip_info; + + res = dev->resource_list; + if (!res || !res->base) { + printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__); + return; + } + + bar = (uintptr_t)res->base; + write32((void *)(bar + ACP_I2S_PIN_CONFIG), cfg->acp_pin_cfg); + + if (cfg->acp_pin_cfg == I2S_PINS_I2S_TDM) + sb_clk_output_48Mhz(); /* Internal connection to I2S */ +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations acp_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = enable, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver acp_driver __pci_driver = { + .ops = &acp_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICD_ID_AMD_PCO_ACP, +}; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index cc06496326..8597c4e15d 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -135,7 +135,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->day_alrm = 0; /* 0x7d these have to be */ fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ fadt->century = 0; /* 0x7f to make rtc alarm work */ - fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index 04e41a1b57..a373a99e7d 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -55,9 +55,10 @@ Field (GNVS, ByteAcc, NoLock, Preserve) , 1, UT0E, 1, // UART0, 11 UT1E, 1, // UART1, 12 - , 2, - ST_E, 1, // SATA, 15 - , 11, + , 3, + UT2E, 1, // UART2, 16 + , 9, + UT23, 1, // UART3, 26 ESPI, 1, // ESPI, 27 /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index e7975f8d94..680f496611 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -58,7 +58,8 @@ Device (FUR0) Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 10 } - Memory32Fixed (ReadWrite, 0xFEDC6000, 0x2000) + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000) }) Method (_STA, 0x0, NotSerialized) { @@ -71,38 +72,40 @@ Device (FUR1) { Name (_UID, 0x1) Name (_CRS, ResourceTemplate() { - IRQ (Edge, ActiveHigh, Exclusive) { 11 } - Memory32Fixed (ReadWrite, 0xFEDC8000, 0x2000) + IRQ (Edge, ActiveHigh, Exclusive) { 11 } + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) }) Method (_STA, 0x0, NotSerialized) { - Return (0x0F) + Return (0x0F) } } -Device (I2CA) { - Name (_HID, "AMD0010") +Device (FUR2) +{ + Name (_HID, "AMD0020") Name (_UID, 0x0) Name (_CRS, ResourceTemplate() { - IRQ (Edge, ActiveHigh, Exclusive) { 3 } - Memory32Fixed (ReadWrite, 0xFEDC2000, 0x1000) + IRQ (Edge, ActiveHigh, Exclusive) { 15 } + Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC2_BASE, 0x1000) }) - Method (_STA, 0x0, NotSerialized) { Return (0x0F) } } -Device (I2CB) -{ - Name (_HID, "AMD0010") +Device (FUR3) { + Name (_HID, "AMD0020") Name (_UID, 0x1) Name (_CRS, ResourceTemplate() { - IRQ (Edge, ActiveHigh, Exclusive) { 15 } - Memory32Fixed (ReadWrite, 0xFEDC3000, 0x1000) + IRQ (Edge, ActiveHigh, Exclusive) { 5 } + Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC3_BASE, 0x1000) }) Method (_STA, 0x0, NotSerialized) { @@ -110,13 +113,13 @@ Device (I2CB) } } -Device (I2CC) { +Device (I2C2) { Name (_HID, "AMD0010") Name (_UID, 0x2) Name (_CRS, ResourceTemplate() { - IRQ (Edge, ActiveHigh, Exclusive) { 6 } - Memory32Fixed (ReadWrite, 0xFEDC4000, 0x1000) + IRQ (Edge, ActiveHigh, Exclusive) { 4 } + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) }) Method (_STA, 0x0, NotSerialized) @@ -125,13 +128,27 @@ Device (I2CC) { } } -Device (I2CD) +Device (I2C3) { Name (_HID, "AMD0010") Name (_UID, 0x3) + Name (_CRS, ResourceTemplate() { + IRQ (Edge, ActiveHigh, Exclusive) { 6 } + Memory32Fixed(ReadWrite, APU_I2C3_BASE, 0x1000) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (I2C4) +{ + Name (_HID, "AMD0010") + Name (_UID, 0x4) Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 14 } - Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000) + Memory32Fixed(ReadWrite, APU_I2C4_BASE, 0x1000) }) Method (_STA, 0x0, NotSerialized) { diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index b9eeadb4ae..bd340dd4bb 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -236,30 +236,23 @@ Field( SMIC, ByteAcc, NoLock, Preserve) { offset (0x1e59), /* UART1 D3 State */ U1DS, 3, - offset (0x1e5e), /* SATA D3 Control */ - SATD, 2, - , 1, - SAPD, 1, - offset (0x1e5f), /* SATA D3 State */ - SADS, 3, - - offset (0x1e64), /* USB2 D3 Control */ + offset (0x1e60), /* UART2 D3 Control */ U2TD, 2, , 1, U2PD, 1, - offset (0x1e65), /* USB2 D3 State */ + offset (0x1e61), /* UART2 D3 State */ U2DS, 3, - offset (0x1e6e), /* USB3 D3 Control */ - U3TD, 2, - , 1, - U3PD, 1, - offset (0x1e6f), /* USB3 D3 State */ - U3DS, 3, - offset (0x1e71), /* SD D3 State */ SDDS, 3, + offset (0x1e74), /* UART3 D3 Control */ + U3TD, 2, + , 1, + U3PD, 1, + offset (0x1e75), /* UART3 D3 State */ + U3DS, 3, + offset (0x1e80), /* Shadow Register Request */ , 15, RQ15, 1, @@ -329,7 +322,7 @@ Field(FCFG, DwordAcc, NoLock, Preserve) /* * Arg0:device: * 5=I2C0, 6=I2C1, 7=I2C2, 8=I2C3, 11=UART0, 12=UART1, - * 15=SATA, 18=EHCI, 23=xHCI, 24=SD + * 18=EHCI, 23=xHCI, 24=SD * Arg1:D-state */ Mutex (FDAS, 0) /* FCH Device AOAC Semophore */ @@ -396,7 +389,22 @@ Method(FDDC, 2, Serialized) Store(U1DS, Local0) } } -/* todo Case(15) { STD0()} */ /* SATA */ + Case(16) { + Store(0x00, U2TD) + Store(One, U2PD) + Store(U2DS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(U2DS, Local0) + } + } + Case(26) { + Store(0x00, U3TD) + Store(One, U3PD) + Store(U3DS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(U3DS, Local0) + } + } } } else { /* put device into D3cold */ @@ -449,16 +457,29 @@ Method(FDDC, 2, Serialized) } Store(0x03, U1TD) } -/* todo Case(15) { STD3()} */ /* SATA */ + Case(16) { + Store(Zero, U2PD) + Store(U2DS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(U2DS, Local0) + } + Store(0x03, U2TD) + } + Case(26) { + Store(Zero, U3PD) + Store(U3DS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(U3DS, Local0) + } + Store(0x03, U3TD) + } } if(LEqual(I1TD, 3)) { if(LEqual(I2TD, 3)) { if(LEqual(I3TD, 3)) { if(LEqual(U0TD, 3)) { if(LEqual(U1TD, 3)) { - if(LEqual(U2TD, 3)) { - Store(Zero, PG2_) - } + Store(Zero, PG2_) } } } diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 65d98b127d..cf02030391 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include @@ -49,19 +48,6 @@ const char *soc_acpi_name(const struct device *dev) case 0: /* Root Hub */ return "RHUB"; - case 2: - /* USB2 ports */ - switch (dev->path.usb.port_id) { - case 0: return "HS01"; - case 1: return "HS02"; - case 2: return "HS03"; - case 3: return "HS04"; - case 4: return "HS05"; - case 5: return "HS06"; - case 6: return "HS07"; - case 7: return "HS08"; - } - break; case 3: /* USB3 ports */ switch (dev->path.usb.port_id) { diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 39c70269da..4e9e18b984 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -36,6 +36,14 @@ struct soc_amd_picasso_config { */ u8 i2c_scl_reset; struct dw_i2c_bus_config i2c[PICASSO_I2C_DEV_MAX]; + enum { + I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */ + I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */ + I2S_PINS_MIN_HDA = 2, /* HDA w/reset 1xSDI, SW w/Data0-2 */ + I2S_PINS_MIN_MHDA = 3, /* HDA no reset 1xSDI, SW w/Data0-3 */ + I2S_PINS_I2S_TDM = 4, + I2S_PINS_UNCONF = 7, /* All pads will be input mode */ + } acp_pin_cfg; }; typedef struct soc_amd_picasso_config config_t; diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 697011af2a..66dfa6cfa4 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -129,6 +129,7 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x810f80 }, { X86_VENDOR_AMD, 0x810f81 }, { 0, 0 }, }; diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 87866433d1..bcdf3850a8 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -73,11 +73,11 @@ const char *i2c_acpi_name(const struct device *dev) { switch (dev->path.mmio.addr) { case APU_I2C2_BASE: - return "I2CC"; + return "I2C2"; case APU_I2C3_BASE: - return "I2CD"; + return "I2C3"; case APU_I2C4_BASE: - return "I2CE"; + return "I2C4"; default: return NULL; } diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index f141a05714..25b1d66af1 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -20,12 +20,6 @@ #include -#if CONFIG(PICASSO_LEGACY_FREE) - #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE -#else - #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) -#endif - #ifndef FADT_PM_PROFILE #define FADT_PM_PROFILE PM_UNSPECIFIED #endif diff --git a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h index beef2bcc81..fe839e8314 100644 --- a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2017 Advanced Micro Devices, Inc. + * Copyright (C) 2019 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,7 +21,10 @@ * PIRQ and device routing - these define the index into the * FCH PCI_INTR 0xC00/0xC01 interrupt routing table. */ - +/* + * PIRQ and device routing - these define the index into the + * FCH PCI_INTR 0xC00/0xC01 interrupt routing table. + */ #define PIRQ_NC 0x1f /* Not Used */ #define PIRQ_A 0x00 /* INT A */ #define PIRQ_B 0x01 /* INT B */ @@ -31,7 +34,7 @@ #define PIRQ_F 0x05 /* INT F */ #define PIRQ_G 0x06 /* INT G */ #define PIRQ_H 0x07 /* INT H */ -#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */ +#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings */ #define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ #define PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */ #define PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */ @@ -40,22 +43,39 @@ #define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */ #define PIRQ_SIRQD 0x0f /* Serial IRQ INTD */ #define PIRQ_SCI 0x10 /* SCI IRQ */ -#define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ +#define PIRQ_SMBUS 0x11 /* SMBUS */ #define PIRQ_ASF 0x12 /* ASF */ -#define PIRQ_HDA 0x13 /* HDA 14h.2 */ -#define PIRQ_FC 0x14 /* FC */ +/* 0x13-0x15 reserved */ #define PIRQ_PMON 0x16 /* Performance Monitor */ #define PIRQ_SD 0x17 /* SD */ #define PIRQ_SDIO 0x1a /* SDIO */ -#define PIRQ_EHCI 0x30 /* USB EHCI 12h.0 */ -#define PIRQ_XHCI 0x34 /* USB XHCI 10h.0 */ -#define PIRQ_SATA 0x41 /* SATA 11h.0 */ +/* 0x1b-0x1f reserved */ +#define PIRQ_CIR 0x20 /* CIR, no IRQ connected */ +#define PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */ +#define PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */ +#define PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */ +/* 0x24-0x48 reserved */ +#define PIRQ_SATA 0x41 /* SATA */ +/* 0x42 reserved */ +#define PIRQ_EMMC 0x43 /* eMMC */ +/* 0x44-0x4f reserved */ +#define PIRQ_GPP0 0x50 /* GPPInt0 */ +#define PIRQ_GPP1 0x51 /* GPPInt1 */ +#define PIRQ_GPP2 0x52 /* GPPInt2 */ +#define PIRQ_GPP3 0x53 /* GPPInt3 */ +/* 0x54-0x61 reserved */ #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ -#define PIRQ_I2C0 0x70 -#define PIRQ_I2C1 0x71 -#define PIRQ_I2C2 0x72 -#define PIRQ_I2C3 0x73 -#define PIRQ_UART0 0x74 -#define PIRQ_UART1 0x75 +/* 0x63-0x6f reserved */ +#define PIRQ_I2C0 0x70 /* I2C0 */ +#define PIRQ_I2C1 0x71 /* I2C1 */ +#define PIRQ_I2C2 0x72 /* I2C2 */ +#define PIRQ_I2C3 0x73 /* I2C3 */ +#define PIRQ_UART0 0x74 /* UART0 */ +#define PIRQ_UART1 0x75 /* UART1 */ +#define PIRQ_I2C4 0x76 /* I2C4 */ +#define PIRQ_I2C5 0x77 /* I2C5 */ +#define PIRQ_UART2 0x78 /* UART2 */ +#define PIRQ_UART3 0x79 /* UART3 */ +/* 0x7a-0x7f reserved */ #endif /* __AMD_PCI_INT_DEFS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index e57d2d3187..9af4c0c843 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. + * Copyright (C) 2019 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +21,8 @@ #define SOC_EARLY_VMTRR_FLASH 1 #define SOC_EARLY_VMTRR_TEMPRAM 2 +#define CSTATE_BASE_REG 0xc0010073 + void picasso_init_cpus(struct device *dev); int get_cpu_count(void); void check_mca(void); diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h index 6e4357ed45..42d255172e 100644 --- a/src/soc/amd/picasso/include/soc/gpio.h +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -121,9 +121,9 @@ #define GPIO_3_IOMUX_GPIOxx 0 #define GPIO_4_IOMUX_GPIOxx 0 #define GPIO_5_IOMUX_GPIOxx 0 -#define GPIO_5_IOMUX_DEVSLP0_S5 1 +#define GPIO_5_IOMUX_DEVSLP0 1 #define GPIO_6_IOMUX_GPIOxx 0 -#define GPIO_6_IOMUX_DEVSLP1_S5 1 +#define GPIO_6_IOMUX_DEVSLP1 1 #define GPIO_7_IOMUX_GPIOxx 0 #define GPIO_7_IOMUX_ACP_I2S_SDIN 1 #define GPIO_8_IOMUX_GPIOxx 0 @@ -161,7 +161,7 @@ #define GPIO_22_IOMUX_LPC_PME_L 0 #define GPIO_22_IOMUX_EMMC_PRW_CTRL 1 #define GPIO_22_IOMUX_GPIOxx 2 -#define GPIO_23_IOMUX_ACP_PRES 0 +#define GPIO_23_IOMUX_AC_PRES 0 #define GPIO_23_IOMUX_SGPIO_LOAD 1 #define GPIO_23_IOMUX_MDIO1_SDA 2 #define GPIO_23_IOMUX_GPIOxx 3 @@ -240,7 +240,7 @@ #define GPIO_100_IOMUX_GPIOxx 0 #define GPIO_100_IOMUX_SD0_DATA3 1 #define GPIO_104_IOMUX_LAD0 0 -#define GPIO_104_IOMUX_EMMC_SDATA0 1 +#define GPIO_104_IOMUX_EMMC_DATA0 1 #define GPIO_104_IOMUX_GPIOxx 3 #define GPIO_105_IOMUX_LAD1 0 #define GPIO_105_IOMUX_EMMC_DATA1 1 @@ -252,7 +252,7 @@ #define GPIO_107_IOMUX_EMMC_DATA3 1 #define GPIO_107_IOMUX_GPIOxx 3 #define GPIO_108_IOMUX_LDRQ0_L 0 -#define GPIO_108_IOMUX_ESPI_ALERT_D1 1 +#define GPIO_108_IOMUX_ESPI_ALERT_L 1 #define GPIO_108_IOMUX_GPIOxx 2 #define GPIO_109_IOMUX_LFRAME_L 0 #define GPIO_109_IOMUX_EMMC_DS 1 diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index ad0e7c4609..5037a1c2c5 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -22,12 +22,18 @@ #define SPI_BASE_ADDRESS 0xfec10000 #define ESPI_BASE_ADDRESS 0xfec20000 +#if CONFIG(HPET_ADDRESS_OVERRIDE) +#error HPET address override is not allowed and must be fixed at 0xfed00000 +#endif +#define HPET_BASE_ADDRESS 0xfed00000 + /* * AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1]. * All ranges not specified as supported below may, or may not, be listed in * any documentation but should be considered reserved through FED8_1FFFh. */ #include +#define SUPPORTS_ACPIMMIO_SM_PCI_BASE 1 /* 0xfed80000 */ #define SUPPORTS_ACPIMMIO_SMI_BASE 1 /* 0xfed80100 */ #define SUPPORTS_ACPIMMIO_PMIO_BASE 1 /* 0xfed80300 */ #define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 1 /* 0xfed80500 */ @@ -43,25 +49,30 @@ #define ALINK_AHB_ADDRESS 0xfedc0000 -/* I2C fixed address */ +/* Reserved 0xfecd1000-0xfedc3fff */ + #define APU_I2C2_BASE 0xfedc4000 #define APU_I2C3_BASE 0xfedc5000 #define APU_I2C4_BASE 0xfedc6000 -#define APU_I2C_MIN_BUS 2 -#define APU_I2C_MAX_BUS 4 -#define APU_I2C_BLOCK_SIZE 0x1000 -#define I2C_BASE_ADDRESS APU_I2C2_BASE -#define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT 3 +#define APU_I2C_MIN_BUS 2 +#define APU_I2C_MAX_BUS 4 +#define APU_I2C_BLOCK_SIZE 0x1000 +#define I2C_BASE_ADDRESS APU_I2C2_BASE +#define I2C_DEVICE_SIZE 0x00001000 +#define I2C_DEVICE_COUNT 3 - -#if CONFIG(HPET_ADDRESS_OVERRIDE) -#error HPET address override is not allowed and must be fixed at 0xfed00000 -#endif -#define HPET_BASE_ADDRESS 0xfed00000 - -#define APU_UART0_BASE 0xfedc6000 -#define APU_UART1_BASE 0xfedc8000 +#define APU_DMAC0_BASE 0xfedc7000 +#define APU_DMAC1_BASE 0xfedc8000 +#define APU_UART0_BASE 0xfedc9000 +#define APU_UART1_BASE 0xfedca000 +/* Reserved 0xfedcb000 */ +#define APU_DMAC2_BASE 0xfedcc000 +#define APU_DMAC3_BASE 0xfedcd000 +#define APU_UART2_BASE 0xfedce000 +#define APU_UART3_BASE 0xfedcf000 +/* Reserved 0xfedd0000-0xfedd4fff */ +#define APU_EMMC_BASE 0xfedd5000 +#define APU_EMMC_CONFIG_BASE 0xfedd5800 #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index e423ab1aa7..9c7419a997 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -73,6 +73,9 @@ #define D18F1_VGAEN 0xf4 # define VGA_ADDR_ENABLE (1 << 0) +/* Bus A D0F5 - Audio Processor */ +#define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ + void amd_initcpuio(void); void domain_enable_resources(struct device *dev); diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index d6887f9b38..acde4558b1 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -42,7 +42,7 @@ /* Internal Graphics */ #define GFX_DEV 0x1 #define GFX_FUNC 0 -#define GFX_DEVID 0x98e4 /* subject to SKU/OPN variation */ +#define GFX_DEVID 0x15d8 #define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) #define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC) diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index b2ede55f73..0fb187dc52 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -28,17 +28,24 @@ * - fixed addresses offset from 0xfed80000 */ +/* SMBus controller registers: 0xfed80000 or D14F0 */ +#define SMB_UART_CONFIG 0xfc +#define SMB_UART3_1_8M BIT(31) /* defaults are 0 = 48MHz */ +#define SMB_UART2_1_8M BIT(30) +#define SMB_UART1_1_8M BIT(29) +#define SMB_UART0_1_8M BIT(28) +#define SMB_UART_1_8M_SHIFT 28 + /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ #define PM_DECODE_EN 0x00 +#define SMBUS_ASF_IO_EN BIT(4) #define CF9_IO_EN BIT(1) #define LEGACY_IO_EN BIT(0) +#define SMB_ASF_IO_BASE 0x01 /* part of PM_DECODE_EN in PPR */ #define PM_ISA_CONTROL 0x04 #define MMIO_EN BIT(1) #define PM_PCI_CTRL 0x08 #define FORCE_SLPSTATE_RETRY BIT(25) -#define FORCE_STPCLK_RETRY BIT(24) - -#define SMB_ASF_IO_BASE 0x01 /* part of PM_DECODE_EN */ #define PWR_RESET_CFG 0x10 #define TOGGLE_ALL_PWR_GOOD BIT(1) @@ -94,8 +101,6 @@ #define PM_RST_CTRL1 0xbe #define SLPTYPE_CONTROL_EN BIT(5) #define PM_RST_STATUS 0xc0 -#define PM_PCIB_CFG 0xea -#define PM_GENINT_DISABLE BIT(0) #define PM_LPC_GATING 0xec #define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_A20_EN BIT(1) @@ -105,13 +110,13 @@ /* SMBUS MMIO offsets 0xfed80a00 */ #define SMBHSTSTAT 0x0 -#define SMBHST_STAT_FAILED 0x10 -#define SMBHST_STAT_COLLISION 0x08 -#define SMBHST_STAT_ERROR 0x04 -#define SMBHST_STAT_INTERRUPT 0x02 -#define SMBHST_STAT_BUSY 0x01 +#define SMBHST_STAT_FAILED BIT(4) +#define SMBHST_STAT_COLLISION BIT(3) +#define SMBHST_STAT_ERROR BIT(2) +#define SMBHST_STAT_INTERRUPT BIT(1) +#define SMBHST_STAT_BUSY BIT(0) #define SMBHST_STAT_CLEAR 0xff -#define SMBHST_STAT_NOERROR 0x02 +#define SMBHST_STAT_NOERROR BIT(1) #define SMBHST_STAT_VAL_BITS 0x1f #define SMBHST_STAT_ERROR_BITS 0x1c @@ -149,32 +154,27 @@ /* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0x00 -#define GPP_CLK2_REQ_MAP_SHIFT 8 -#define GPP_CLK2_REQ_MAP_MASK (0xf << GPP_CLK2_REQ_MAP_SHIFT) -#define GPP_CLK2_REQ_MAP_CLK_REQ2 3 -#define GPP_CLK0_REQ_MAP_SHIFT 0 -#define GPP_CLK0_REQ_MAP_MASK (0xf << GPP_CLK0_REQ_MAP_SHIFT) -#define GPP_CLK0_REQ_MAP_CLK_REQ0 1 +#define GPP_CLK0_REQ_SHL 0 +#define GPP_CLK1_REQ_SHL 2 +#define GFX_CLK0_REQ_SHL 4 +#define GPP_CLK2_REQ_SHL 6 +#define GPP_CLK3_REQ_SHL 8 +#define GFX_CLK1_REQ_SHL 10 +#define GPP_CLK_REQ_MAP_MASK0 (3 << GPP_CLK0_REQ_SHL) +#define GPP_CLK_REQ_MAP_CLK0 (1 << GPP_CLK0_REQ_SHL) +#define GPP_CLK_REQ_MAP_MASK1 (3 << GPP_CLK1_REQ_SHL) +#define GPP_CLK_REQ_MAP_CLK1 (1 << GPP_CLK1_REQ_SHL) +#define GFX_CLK_REQ_MAP_MASK0 (3 << GFX_CLK0_REQ_SHL) +#define GFX_CLK_REQ_MAP_CLK0 (1 << GFX_CLK0_REQ_SHL) +#define GPP_CLK_REQ_MAP_MASK2 (3 << GPP_CLK2_REQ_SHL) +#define GPP_CLK_REQ_MAP_CLK2 (1 << GPP_CLK2_REQ_SHL) +#define GPP_CLK_REQ_MAP_MASK3 (3 << GPP_CLK3_REQ_SHL) +#define GPP_CLK_REQ_MAP_CLK3 (1 << GPP_CLK3_REQ_SHL) +#define GFX_CLK_REQ_MAP_MASK1 (3 << GPP_CLK1_REQ_SHL) +#define GFX_CLK_REQ_MAP_CLK1 (1 << GPP_CLK1_REQ_SHL) #define MISC_CGPLL_CONFIG1 0x08 #define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0) -#define MISC_CGPLL_CONFIG3 0x10 -#define CG1PLL_REFDIV_SHIFT 0 -#define CG1PLL_REFDIV_MASK (0x3ff << CG1PLL_REFDIV_SHIFT) -#define CG1PLL_FBDIV_SHIFT 10 -#define CG1PLL_FBDIV_MASK (0xfff << CG1PLL_FBDIV_SHIFT) -#define MISC_CGPLL_CONFIG4 0x14 -#define SS_STEP_SIZE_DSFRAC_SHIFT 0 -#define SS_STEP_SIZE_DSFRAC_MASK (0xffff << SS_STEP_SIZE_DSFRAC_SHIFT) -#define SS_AMOUNT_DSFRAC_SHIFT 16 -#define SS_AMOUNT_DSFRAC_MASK (0xffff << SS_AMOUNT_DSFRAC_SHIFT) -#define MISC_CGPLL_CONFIG5 0x18 -#define SS_AMOUNT_NFRAC_SLIP_SHIFT 8 -#define SS_AMOUNT_NFRAC_SLIP_MASK (0xf << SS_AMOUNT_NFRAC_SLIP_SHIFT) -#define MISC_CGPLL_CONFIG6 0x1c -#define CG1PLL_LF_MODE_SHIFT 9 -#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT) #define MISC_CLK_CNTL1 0x40 -#define CG1PLL_FBDIV_TEST BIT(26) #define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ #define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ #define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ @@ -215,7 +215,10 @@ #define FCH_AOAC_DEV_I2C4 9 #define FCH_AOAC_DEV_UART0 11 #define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_UART2 16 #define FCH_AOAC_DEV_AMBA 17 +#define FCH_AOAC_DEV_UART3 26 +#define FCH_AOAC_DEV_ESPI 27 /* Bit definitions for Device D3 Control AOACx0000[40...7E] step 2 */ #define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) @@ -236,6 +239,11 @@ #define FCH_AOAC_STAT0 BIT(6) #define FCH_AOAC_STAT1 BIT(7) +#define FCH_UART_LEGACY_DECODE 0xfedc0020 +#define FCH_LEGACY_3F8_SH 3 +#define FCH_LEGACY_2F8_SH 1 +#define FCH_LEGACY_3E8_SH 2 + #define PM1_LIMIT 16 #define GPE0_LIMIT 28 #define TOTAL_BITS(a) (8 * sizeof(a)) @@ -300,9 +308,10 @@ typedef struct aoac_devs { unsigned int :1; unsigned int ut0e:1; /* 11: UART0 */ unsigned int ut1e:1; /* 12: UART1 */ - unsigned int :2; - unsigned int st_e:1; /* 15: SATA */ - unsigned int :11; + unsigned int :3; + unsigned int ut2e:1; /* 16: UART2 */ + unsigned int :9; + unsigned int ut3e:1; /* 26: UART3 */ unsigned int espi:1; /* 27: ESPI */ unsigned int :4; } __packed aoac_devs_t; @@ -323,8 +332,9 @@ void southbridge_final(void *chip_info); void southbridge_init(void *chip_info); void sb_read_mode(u32 mode); void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); -void bootblock_fch_early_init(void); -void bootblock_fch_init(void); +void fch_pre_init(void); +void fch_early_init(void); +void set_uart_config(int idx); /** * @brief Save the UMA bize * @@ -357,15 +367,6 @@ uint32_t get_uma_size(void); * @return 64bit base address */ uint64_t get_uma_base(void); -/* - * Call the mainboard to get the USB Over Current Map. The mainboard - * returns the map and 0 on Success or -1 on error or no map. There is - * a default weak function in usb.c if the mainboard doesn't have any - * over current support. - */ -#define USB_OC_DISABLE_ALL 0xffff -int mainboard_get_xhci0_oc_map(uint16_t *usb_oc_map); -int mainboard_get_xhci1_oc_map(uint16_t *usb_oc_map); /* Initialize all the i2c buses that are marked with early init. */ void i2c_soc_early_init(void); diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 09af7e4de7..82d6fb6e8e 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -58,7 +58,7 @@ void bert_reserved_region(void **start, size_t *size) *size = BERT_REGION_MAX_SIZE; } -void *cbmem_top(void) +void *cbmem_top_chipset(void) { msr_t tom = rdmsr(TOP_MEM); diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 36135f989e..08807f3321 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -310,20 +310,3 @@ void domain_set_resources(struct device *dev) assign_resources(dev->link_list); } - -/********************************************************************* - * Change the vendor / device IDs to match the generic VBIOS header. * - *********************************************************************/ -u32 map_oprom_vendev(u32 vendev) -{ - u32 new_vendev; - new_vendev = - ((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) ? - 0x100298e0 : vendev; - - if (vendev != new_vendev) - printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", - vendev, new_vendev); - - return new_vendev; -} diff --git a/src/soc/amd/picasso/sata.c b/src/soc/amd/picasso/sata.c index 6740698dd2..d67f5b4a9b 100644 --- a/src/soc/amd/picasso/sata.c +++ b/src/soc/amd/picasso/sata.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 9eddf853b6..4995acb484 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -163,7 +163,6 @@ static void sb_slp_typ_handler(void) /* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */ pci_ctrl = pm_read32(PM_PCI_CTRL); pci_ctrl &= ~FORCE_SLPSTATE_RETRY; - pci_ctrl |= FORCE_STPCLK_RETRY; pm_write32(PM_PCI_CTRL, pci_ctrl); /* Enable SlpTyp */ diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index e6fc0dedc2..fe801d4126 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -17,9 +17,9 @@ #include #include #include +#include #include #include -#include #include #include #include @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -39,6 +40,8 @@ #define FCH_AOAC_UART_FOR_CONSOLE \ (CONFIG_UART_FOR_CONSOLE == 0 ? FCH_AOAC_DEV_UART0 \ : CONFIG_UART_FOR_CONSOLE == 1 ? FCH_AOAC_DEV_UART1 \ + : CONFIG_UART_FOR_CONSOLE == 2 ? FCH_AOAC_DEV_UART2 \ + : CONFIG_UART_FOR_CONSOLE == 3 ? FCH_AOAC_DEV_UART3 \ : -1) #if FCH_AOAC_UART_FOR_CONSOLE == -1 # error Unsupported UART_FOR_CONSOLE chosen @@ -55,6 +58,7 @@ const static int aoac_devs[] = { FCH_AOAC_DEV_I2C2, FCH_AOAC_DEV_I2C3, FCH_AOAC_DEV_I2C4, + FCH_AOAC_DEV_ESPI, }; /* @@ -70,7 +74,7 @@ const static struct irq_idx_name irq_association[] = { { PIRQ_C, "INTC#" }, { PIRQ_D, "INTD#" }, { PIRQ_E, "INTE#" }, - { PIRQ_F, "INTF#" }, + { PIRQ_F, "INTF#/GENINT2" }, { PIRQ_G, "INTG#" }, { PIRQ_H, "INTH#" }, { PIRQ_MISC, "Misc" }, @@ -84,14 +88,19 @@ const static struct irq_idx_name irq_association[] = { { PIRQ_SCI, "SCI" }, { PIRQ_SMBUS, "SMBUS" }, { PIRQ_ASF, "ASF" }, - { PIRQ_HDA, "HDA" }, - { PIRQ_FC, "FC" }, { PIRQ_PMON, "PerMon" }, { PIRQ_SD, "SD" }, - { PIRQ_SDIO, "SDIOt" }, - { PIRQ_EHCI, "EHCI" }, - { PIRQ_XHCI, "XHCI" }, + { PIRQ_SDIO, "SDIO" }, + { PIRQ_CIR, "CIR" }, + { PIRQ_GPIOA, "GPIOa" }, + { PIRQ_GPIOB, "GPIOb" }, + { PIRQ_GPIOC, "GPIOc" }, { PIRQ_SATA, "SATA" }, + { PIRQ_EMMC, "eMMC" }, + { PIRQ_GPP0, "GPP0" }, + { PIRQ_GPP1, "GPP1" }, + { PIRQ_GPP2, "GPP2" }, + { PIRQ_GPP3, "GPP3" }, { PIRQ_GPIO, "GPIO" }, { PIRQ_I2C0, "I2C0" }, { PIRQ_I2C1, "I2C1" }, @@ -99,6 +108,10 @@ const static struct irq_idx_name irq_association[] = { { PIRQ_I2C3, "I2C3" }, { PIRQ_UART0, "UART0" }, { PIRQ_UART1, "UART1" }, + { PIRQ_I2C4, "I2C4" }, + { PIRQ_I2C5, "I2C5" }, + { PIRQ_UART2, "UART2" }, + { PIRQ_UART3, "UART3" }, }; const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) @@ -174,31 +187,6 @@ static void sb_enable_lpc(void) pm_io_write8(PM_LPC_GATING, byte); } -static void sb_lpc_decode(void) -{ - u32 tmp = 0; - - /* Enable I/O decode to LPC bus */ - tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 - | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 - | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 - | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 - | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 - | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 - | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 - | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 - | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 - | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT - | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT - | DECODE_ENABLE_ADLIB_PORT; - - /* Decode SIOs at 2E/2F and 4E/4F */ - if (CONFIG(PICASSO_LEGACY_FREE)) - tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE; - - lpc_enable_decode(tmp); -} - static void sb_enable_cf9_io(void) { uint32_t reg = pm_read32(PM_DECODE_EN); @@ -263,72 +251,6 @@ void sb_read_mode(u32 mode) & ~SPI_READ_MODE_MASK) | mode); } -static void setup_spread_spectrum(int *reboot) -{ - uint16_t rstcfg = pm_read16(PWR_RESET_CFG); - - rstcfg &= ~TOGGLE_ALL_PWR_GOOD; - pm_write16(PWR_RESET_CFG, rstcfg); - - uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1); - - if (cntl1 & CG1PLL_FBDIV_TEST) { - printk(BIOS_DEBUG, "Spread spectrum is ready\n"); - misc_write32(MISC_CGPLL_CONFIG1, - misc_read32(MISC_CGPLL_CONFIG1) | - CG1PLL_SPREAD_SPECTRUM_ENABLE); - - return; - } - - printk(BIOS_DEBUG, "Setting up spread spectrum\n"); - - uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6); - cfg6 &= ~CG1PLL_LF_MODE_MASK; - cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK; - misc_write32(MISC_CGPLL_CONFIG6, cfg6); - - uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3); - cfg3 &= ~CG1PLL_REFDIV_MASK; - cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK; - cfg3 &= ~CG1PLL_FBDIV_MASK; - cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK; - misc_write32(MISC_CGPLL_CONFIG3, cfg3); - - uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5); - cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK; - cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK; - misc_write32(MISC_CGPLL_CONFIG5, cfg5); - - uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4); - cfg4 &= ~SS_AMOUNT_DSFRAC_MASK; - cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK; - cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK; - cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT) - & SS_STEP_SIZE_DSFRAC_MASK; - misc_write32(MISC_CGPLL_CONFIG4, cfg4); - - rstcfg |= TOGGLE_ALL_PWR_GOOD; - pm_write16(PWR_RESET_CFG, rstcfg); - - cntl1 |= CG1PLL_FBDIV_TEST; - misc_write32(MISC_CLK_CNTL1, cntl1); - - *reboot = 1; -} - -static void setup_misc(int *reboot) -{ - /* Undocumented register */ - uint32_t reg = misc_read32(0x50); - if (!(reg & BIT(16))) { - reg |= BIT(16); - - misc_write32(0x50, reg); - *reboot = 1; - } -} - static void fch_smbus_init(void) { pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8); @@ -341,28 +263,29 @@ static void fch_smbus_init(void) } /* Before console init */ -void bootblock_fch_early_init(void) +void fch_pre_init(void) { - int reboot = 0; - - lpc_enable_rom(); + /* Turn on LPC in case the PSP didn't use it. However, ensure all + * decoding is cleared as the PSP may have enabled decode paths. */ sb_enable_lpc(); - lpc_enable_port80(); - sb_lpc_decode(); + lpc_disable_decodes(); + + if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80) + && CONFIG(PICASSO_LPC_IOMUX)) + lpc_enable_port80(); lpc_enable_spi_prefetch(); sb_init_spi_base(); - sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ + sb_disable_4dw_burst(); + sb_set_spi100(SPI_SPEED_33M, SPI_SPEED_33M, + SPI_SPEED_16M, SPI_SPEED_16M); enable_acpimmio_decode(); fch_smbus_init(); sb_enable_cf9_io(); - setup_spread_spectrum(&reboot); - setup_misc(&reboot); - - if (reboot) - warm_reset(); - sb_enable_legacy_io(); enable_aoac_devices(); + sb_reset_i2c_slaves(); + if (CONFIG(PICASSO_UART)) + set_uart_config(CONFIG_UART_FOR_CONSOLE); } static void print_num_status_bits(int num_bits, uint32_t status, @@ -418,9 +341,10 @@ static void sb_print_pmxc0_status(void) } /* After console init */ -void bootblock_fch_init(void) +void fch_early_init(void) { sb_print_pmxc0_status(); + i2c_soc_early_init(); } void sb_enable(struct device *dev) @@ -431,6 +355,7 @@ void sb_enable(struct device *dev) static void sb_init_acpi_ports(void) { u32 reg; + msr_t cst_addr; /* We use some of these ports in SMM regardless of whether or not * ACPI tables are generated. Enable these ports indiscriminately. @@ -440,8 +365,11 @@ static void sb_init_acpi_ports(void) pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); + /* CpuControl is in \_PR.CP00, 6 bytes */ - pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); + cst_addr.hi = 0; + cst_addr.lo = ACPI_CPU_CONTROL; + wrmsr(CSTATE_BASE_REG, cst_addr); if (CONFIG(HAVE_SMI_HANDLER)) { /* APMC - SMI Command Port */ @@ -454,7 +382,6 @@ static void sb_init_acpi_ports(void) */ reg = pm_read32(PM_PCI_CTRL); reg |= FORCE_SLPSTATE_RETRY; - reg &= ~FORCE_STPCLK_RETRY; pm_write32(PM_PCI_CTRL, reg); /* Disable SlpTyp feature */ @@ -531,8 +458,6 @@ void southbridge_init(void *chip_info) static void set_sb_final_nvs(void) { - const struct device *sata; - struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (gnvs == NULL) return; @@ -542,9 +467,8 @@ static void set_sb_final_nvs(void) gnvs->aoac.ic4e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C4); gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0); gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1); - /* Rely on these being in sync with devicetree */ - sata = pcidev_path_on_root(SATA_DEVFN); - gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0; + gnvs->aoac.ut2e = is_aoac_device_enabled(FCH_AOAC_DEV_UART2); + gnvs->aoac.ut3e = is_aoac_device_enabled(FCH_AOAC_DEV_UART3); gnvs->aoac.espi = 1; } diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index d5d30061bf..445862430a 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2019 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,18 +13,77 @@ * GNU General Public License for more details. */ +#include #include +#include +#include +#include #include +#include + +static const struct _uart_info { + uintptr_t base; + struct soc_amd_gpio mux[2]; +} uart_info[] = { + [0] = { APU_UART0_BASE, { + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + } }, + [1] = { APU_UART1_BASE, { + PAD_NF(GPIO_143, UART1_TXD, PULL_NONE), + PAD_NF(GPIO_141, UART1_RXD, PULL_NONE), + } }, + [2] = { APU_UART2_BASE, { + PAD_NF(GPIO_137, UART2_TXD, PULL_NONE), + PAD_NF(GPIO_135, UART2_RXD, PULL_NONE), + } }, + [3] = { APU_UART3_BASE, { + PAD_NF(GPIO_140, UART3_TXD, PULL_NONE), + PAD_NF(GPIO_142, UART3_RXD, PULL_NONE), + } }, +}; uintptr_t uart_platform_base(int idx) { - if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1) + if (idx < 0 || idx > ARRAY_SIZE(uart_info)) return 0; - return (uintptr_t)(APU_UART0_BASE + 0x2000 * (idx & 1)); + return uart_info[idx].base; +} + +void set_uart_config(int idx) +{ + uint32_t uart_ctrl; + uint16_t uart_leg; + + if (idx < 0 || idx > ARRAY_SIZE(uart_info)) + return; + + program_gpios(uart_info[idx].mux, 2); + + if (CONFIG(PICASSO_UART_1_8MZ)) { + uart_ctrl = sm_pci_read32(SMB_UART_CONFIG); + uart_ctrl |= 1 << (SMB_UART_1_8M_SHIFT + idx); + sm_pci_write32(SMB_UART_CONFIG, uart_ctrl); + } + + if (CONFIG(PICASSO_UART_LEGACY) && idx != 3) { + /* Force 3F8 if idx=0, 2F8 if idx=1, 3E8 if idx=2 */ + + /* TODO: make clearer once PPR is updated */ + uart_leg = (idx << 8) | (idx << 10) | (idx << 12) | (idx << 14); + if (idx == 0) + uart_leg |= 1 << FCH_LEGACY_3F8_SH; + else if (idx == 1) + uart_leg |= 1 << FCH_LEGACY_2F8_SH; + else if (idx == 2) + uart_leg |= 1 << FCH_LEGACY_3E8_SH; + + write16((void *)FCH_UART_LEGACY_DECODE, uart_leg); + } } unsigned int uart_platform_refclk(void) { - return 48000000; + return CONFIG(PICASSO_UART_48MZ) ? 48000000 : 115200 * 16; } diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c index 66c8266cd3..80e960cd86 100644 --- a/src/soc/amd/picasso/usb.c +++ b/src/soc/amd/picasso/usb.c @@ -24,31 +24,11 @@ #include #include -static void set_usb_over_current(struct device *dev) +static void picasso_usb_init(struct device *dev) { - uint16_t map = USB_OC_DISABLE_ALL; + /* USB overcurrent configuration is programmed inside the FSP */ - if (dev->path.pci.devfn == XHCI0_DEVFN) { - if (mainboard_get_xhci0_oc_map(&map) == 0) - ; // TODO - } - - if (dev->path.pci.devfn == XHCI1_DEVFN) { - if (mainboard_get_xhci1_oc_map(&map) == 0) - ; // TODO - } -} - -int __weak mainboard_get_xhci0_oc_map(uint16_t *map) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); - return -1; -} - -int __weak mainboard_get_xhci1_oc_map(uint16_t *map) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); - return -1; + printk(BIOS_DEBUG, "%s\n", __func__); } static struct pci_operations lops_pci = { @@ -56,22 +36,18 @@ static struct pci_operations lops_pci = { }; static struct device_operations usb_ops = { - .read_resources = pci_ehci_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = set_usb_over_current, - .scan_bus = scan_usb_bus, + .init = picasso_usb_init, + .scan_bus = scan_static_bus, .acpi_name = soc_acpi_name, .ops_pci = &lops_pci, }; static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_SB900_USB_18_0, - PCI_DEVICE_ID_AMD_SB900_USB_18_2, - PCI_DEVICE_ID_AMD_SB900_USB_20_5, - PCI_DEVICE_ID_AMD_CZ_USB_0, - PCI_DEVICE_ID_AMD_CZ_USB_1, - PCI_DEVICE_ID_AMD_CZ_USB3_0, + PCI_DEVICE_ID_AMD_PCO_XHCI0, + PCI_DEVICE_ID_AMD_PCO_XHCI1, 0 }; diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 72719d7179..0d6f2ff0bc 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -54,7 +54,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_USBDEBUG_OPTIONS select SOC_AMD_COMMON_BLOCK_SPI select TSC_SYNC_LFENCE - select COLLECT_TIMESTAMPS select SOC_AMD_PI select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK @@ -86,10 +85,6 @@ config VBOOT select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH -config UDELAY_LAPIC_FIXED_FSB - int - default 200 - # TODO: Sync these with definitions in PI vendorcode. # DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. # DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 09af7e4de7..82d6fb6e8e 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -58,7 +58,7 @@ void bert_reserved_region(void **start, size_t *size) *size = BERT_REGION_MAX_SIZE; } -void *cbmem_top(void) +void *cbmem_top_chipset(void) { msr_t tom = rdmsr(TOP_MEM); diff --git a/src/soc/amd/stoneyridge/sata.c b/src/soc/amd/stoneyridge/sata.c index 6740698dd2..d67f5b4a9b 100644 --- a/src/soc/amd/stoneyridge/sata.c +++ b/src/soc/amd/stoneyridge/sata.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 45408ead02..d7a09aaf57 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c index 00f82375e8..3c621910e2 100644 --- a/src/soc/amd/stoneyridge/usb.c +++ b/src/soc/amd/stoneyridge/usb.c @@ -63,7 +63,7 @@ static struct device_operations usb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = set_usb_over_current, - .scan_bus = scan_usb_bus, + .scan_bus = scan_static_bus, .acpi_name = soc_acpi_name, .ops_pci = &lops_pci, }; diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc index 3a36bfa6c0..ece705fd92 100644 --- a/src/soc/cavium/cn81xx/Makefile.inc +++ b/src/soc/cavium/cn81xx/Makefile.inc @@ -35,7 +35,6 @@ verstage-y += gpio.c verstage-y += timer.c verstage-y += spi.c verstage-y += uart.c -verstage-y += cbmem.c ################################################################################ # romstage @@ -65,7 +64,6 @@ ramstage-y += soc.c ramstage-y += cpu.c ramstage-y += cpu_secondary.S ramstage-y += ecam0.c -ramstage-y += cbmem.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index bb6fa18f20..a39bf4fe35 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -20,7 +20,7 @@ #include #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { /* Make sure not to overlap with reserved ATF scratchpad */ return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB); diff --git a/src/soc/cavium/cn81xx/twsi.c b/src/soc/cavium/cn81xx/twsi.c index 7137531d49..afa98c6adc 100644 --- a/src/soc/cavium/cn81xx/twsi.c +++ b/src/soc/cavium/cn81xx/twsi.c @@ -667,7 +667,7 @@ int twsi_init(unsigned int bus, enum i2c_speed hz) return 0; } -int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, +int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int seg_count) { int result; diff --git a/src/soc/cavium/common/Makefile.inc b/src/soc/cavium/common/Makefile.inc index 96e38c3b0c..766c44db63 100644 --- a/src/soc/cavium/common/Makefile.inc +++ b/src/soc/cavium/common/Makefile.inc @@ -17,7 +17,8 @@ ifeq ($(CONFIG_SOC_CAVIUM_COMMON),y) subdirs-y += pci -CFLAGS_arm64 += -Wstack-usage=$(CONFIG_STACK_SIZE) +# -Wstack-usage doesn't recognize hexadecimal numbers. +CFLAGS_arm64 += -Wstack-usage=$(shell printf "%d" $(CONFIG_STACK_SIZE)) bootblock-$(CONFIG_BOOTBLOCK_CUSTOM) += bootblock.c diff --git a/src/soc/cavium/common/pci/uart.c b/src/soc/cavium/common/pci/uart.c index 6e41e1d3d6..ff002ea5ec 100644 --- a/src/soc/cavium/common/pci/uart.c +++ b/src/soc/cavium/common/pci/uart.c @@ -38,3 +38,7 @@ static const struct pci_driver soc_cavium_uart __pci_driver = { .vendor = PCI_VENDOR_CAVIUM, .device = PCI_DEVICE_ID_CAVIUM_THUNDERX_UART, }; + +struct chip_operations soc_cavium_common_pci_ops = { + CHIP_NAME("Cavium ThunderX UART") +}; diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc index 6e8d539d8e..9392d302a2 100644 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ b/src/soc/imgtec/pistachio/Makefile.inc @@ -28,7 +28,6 @@ ramstage-y += uart.c bootblock-y += monotonic_timer.c -ramstage-y += cbmem.c ramstage-y += monotonic_timer.c ramstage-y += soc.c ramstage-y += reset.c diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c index 112df7ccc9..92bc1ce868 100644 --- a/src/soc/imgtec/pistachio/cbmem.c +++ b/src/soc/imgtec/pistachio/cbmem.c @@ -18,7 +18,7 @@ #include #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return _dram + (CONFIG_DRAM_SIZE_MB << 20); } diff --git a/src/soc/imgtec/pistachio/include/soc/gpio.h b/src/soc/imgtec/pistachio/include/soc/gpio.h index f2427f241a..64f2e27c8b 100644 --- a/src/soc/imgtec/pistachio/include/soc/gpio.h +++ b/src/soc/imgtec/pistachio/include/soc/gpio.h @@ -16,6 +16,6 @@ #ifndef __SOC_IMGTECH_PISTACHIO_GPIO_H__ #define __SOC_IMGTECH_PISTACHIO_GPIO_H__ -typedef unsigned gpio_t; +typedef unsigned int gpio_t; #endif // __SOC_IMGTECH_PISTACHIO_GPIO_H__ diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c index bbcd8a179d..3bc65a54ae 100644 --- a/src/soc/imgtec/pistachio/monotonic_timer.c +++ b/src/soc/imgtec/pistachio/monotonic_timer.c @@ -24,7 +24,7 @@ static int get_count_mhz_freq(void) { - static unsigned count_mhz_freq; + static unsigned int count_mhz_freq; if (!count_mhz_freq) { if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON) diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c index 1eb232aa13..d5042d546d 100644 --- a/src/soc/imgtec/pistachio/uart.c +++ b/src/soc/imgtec/pistachio/uart.c @@ -34,12 +34,12 @@ #define UART_SHIFT 2 #define GEN_ACCESSOR(name, idx) \ -static inline uint8_t read_##name(unsigned base_port) \ +static inline uint8_t read_##name(unsigned int base_port) \ { \ return read8((void *)(base_port + (idx << UART_SHIFT))); \ } \ \ -static inline void write_##name(unsigned base_port, uint8_t val) \ +static inline void write_##name(unsigned int base_port, uint8_t val) \ { \ write8((void *)(base_port + (idx << UART_SHIFT)), val); \ } @@ -54,12 +54,12 @@ GEN_ACCESSOR(lsr, UART8250_LSR) GEN_ACCESSOR(dll, UART8250_DLL) GEN_ACCESSOR(dlm, UART8250_DLM) -static int uart8250_mem_can_tx_byte(unsigned base_port) +static int uart8250_mem_can_tx_byte(unsigned int base_port) { return read_lsr(base_port) & UART8250_LSR_THRE; } -static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) +static void uart8250_mem_tx_byte(unsigned int base_port, unsigned char data) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while (i-- && !uart8250_mem_can_tx_byte(base_port)) @@ -67,19 +67,19 @@ static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) write_tbr(base_port, data); } -static void uart8250_mem_tx_flush(unsigned base_port) +static void uart8250_mem_tx_flush(unsigned int base_port) { unsigned long int i = FIFO_TIMEOUT; while (i-- && !(read_lsr(base_port) & UART8250_LSR_TEMT)) udelay(1); } -static int uart8250_mem_can_rx_byte(unsigned base_port) +static int uart8250_mem_can_rx_byte(unsigned int base_port) { return read_lsr(base_port) & UART8250_LSR_DR; } -static unsigned char uart8250_mem_rx_byte(unsigned base_port) +static unsigned char uart8250_mem_rx_byte(unsigned int base_port) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while (i-- && !uart8250_mem_can_rx_byte(base_port)) @@ -90,7 +90,7 @@ static unsigned char uart8250_mem_rx_byte(unsigned base_port) return 0x0; } -static void uart8250_mem_init(unsigned base_port, unsigned divisor) +static void uart8250_mem_init(unsigned int base_port, unsigned int divisor) { /* Disable interrupts */ write_ier(base_port, 0x0); diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a1d3c07093..026f6da669 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -40,7 +40,6 @@ config CPU_SPECIFIC_OPTIONS # Misc options select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS - select COLLECT_TIMESTAMPS select COMMON_FADT select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS select GENERIC_GPIO_LIB @@ -96,7 +95,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_CSE select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select PLATFORM_USES_FSP2_0 select UDK_2015_BINDING if !SOC_INTEL_GLK diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 41faf7243b..5530e5c5ab 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -22,7 +22,7 @@ bootblock-y += uart.c romstage-y += car.c romstage-y += ../../../cpu/intel/car/romstage.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c +romstage-y += romstage.c romstage-y += gspi.c romstage-y += heci.c romstage-y += i2c.c diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl index b9a2cf1b97..de556e08d8 100644 --- a/src/soc/intel/apollolake/acpi/gpio.asl +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -23,7 +23,6 @@ scope (\_SB) { Device (GPO0) { - Name (_ADR, 0) Name (_HID, GPIO_COMM_NAME) Name (_CID, GPIO_COMM_NAME) Name (_DDN, GPIO_COMM_0_DESC) @@ -54,7 +53,6 @@ scope (\_SB) { Device (GPO1) { - Name (_ADR, 0) Name (_HID, GPIO_COMM_NAME) Name (_CID, GPIO_COMM_NAME) Name (_DDN, GPIO_COMM_1_DESC) @@ -85,7 +83,6 @@ scope (\_SB) { Device (GPO2) { - Name (_ADR, 0) Name (_HID, GPIO_COMM_NAME) Name (_CID, GPIO_COMM_NAME) Name (_DDN, GPIO_COMM_2_DESC) @@ -116,7 +113,6 @@ scope (\_SB) { Device (GPO3) { - Name (_ADR, 0) Name (_HID, GPIO_COMM_NAME) Name (_CID, GPIO_COMM_NAME) Name (_DDN, GPIO_COMM_3_DESC) diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 919026aae5..2f2a064f1b 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -17,7 +17,6 @@ Name(_HID, EISAID("PNP0A08")) /* PCIe */ Name(_CID, EISAID("PNP0A03")) /* PCI */ - Name(_ADR, 0) Name(_BBN, 0) Device (MCHC) diff --git a/src/soc/intel/apollolake/acpi/sleepstates.asl b/src/soc/intel/apollolake/acpi/sleepstates.asl deleted file mode 100644 index e79f2f0cd0..0000000000 --- a/src/soc/intel/apollolake/acpi/sleepstates.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name (\_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) -Name (\_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) -Name (\_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 7c9c873ddb..9acb9aeb03 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -33,7 +33,7 @@ #include "xhci.asl" /* LPC */ -#include "lpc.asl" +#include /* eMMC */ #include "scs.asl" diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 8e516f8a84..1aab8a1b7a 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -751,6 +751,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) /* Set VTD feature according to devicetree */ silconfig->VtdEnable = cfg->enable_vtd; + dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) + silconfig->PeiGraphicsPeimInit = 1; + else + silconfig->PeiGraphicsPeimInit = 0; + mainboard_silicon_init_params(silconfig); } diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 33496273d2..6e826b863c 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -72,10 +72,12 @@ static const struct reg_script core_msr_script[] = { void soc_core_init(struct device *cpu) { + config_t *conf = config_of_soc(); + /* Clear out pending MCEs */ /* TODO(adurbin): Some of these banks are core vs package scope. For now every CPU clears every bank. */ - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) || + if ((CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable) || acpi_get_sleep_type() == ACPI_S5) mca_configure(); @@ -89,7 +91,7 @@ void soc_core_init(struct device *cpu) enable_pm_timer_emulation(); /* Configure Core PRMRR for SGX. */ - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable) prmrr_core_configure(); /* Set Max Non-Turbo ratio if RAPL is disabled. */ @@ -253,9 +255,11 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, static void post_mp_init(void) { + config_t *conf = config_of_soc(); + smm_southbridge_enable(PWRBTN_EN | GBL_EN); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable) mp_run_on_all_cpus(sgx_configure, NULL); } @@ -287,17 +291,3 @@ void apollolake_init_cpus(struct device *dev) CONFIG(BOOT_DEVICE_SPI_FLASH)) fast_spi_cache_bios_region(); } - -void cpu_lock_sgx_memory(void) -{ - /* Do nothing because MCHECK while loading microcode and enabling - * IA untrusted mode takes care of necessary locking */ -} - -int soc_fill_sgx_param(struct sgx_param *sgx_param) -{ - config_t *conf = config_of_soc(); - - sgx_param->enable = conf->sgx_enable; - return 0; -} diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 4b82365284..3057fbe33e 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -25,6 +25,8 @@ #define MCH_BASE_ADDRESS 0xfed10000 #define MCH_BASE_SIZE (32 * KiB) +#define HPET_BASE_ADDRESS 0xfed00000 + #define ACPI_BASE_ADDRESS 0x400 #define ACPI_BASE_SIZE 0x100 #define R_ACPI_PM1_TMR 0x8 diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 2d59f7de22..636dd03a3e 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 77711ebf26..567ff1ebc6 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -15,19 +15,12 @@ * GNU General Public License for more details. */ -#include -#include #include -#include -#include -#include -#include #include -#include #include "chip.h" -void *cbmem_top(void) +void *cbmem_top_chipset(void) { const config_t *config; void *tolum = (void *)sa_get_tseg_base(); @@ -43,28 +36,3 @@ void *cbmem_top(void) return tolum; } - -void smm_region(uintptr_t *start, size_t *size) -{ - *start = sa_get_tseg_base(); - *size = sa_get_tseg_size(); -} - -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - - /* - * We need to make sure ramstage will be run cached. At this point exact - * location of ramstage in cbmem is not known. Instruct postcar to cache - * 16 megs under cbmem top which is a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - /* cbmem_top() needs to be at least 16 MiB aligned */ - assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); - postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB, - MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); -} diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index c833c5360f..397e86768c 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -27,7 +27,6 @@ config CPU_SPECIFIC_OPTIONS select SMP select SPI_FLASH select SSE2 - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index c322cce0ad..db6b27148b 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -131,37 +131,6 @@ static int acpi_sci_irq(void) return sci_irq; } -void acpi_create_intel_hpet(acpi_hpet_t * hpet) -{ - acpi_header_t *header = &(hpet->header); - acpi_addr_t *addr = &(hpet->addr); - - memset((void *) hpet, 0, sizeof(acpi_hpet_t)); - - /* fill out header fields */ - memcpy(header->signature, "HPET", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_hpet_t); - header->revision = get_acpi_table_revision(HPET); - - /* fill out HPET address */ - addr->space_id = 0; /* Memory */ - addr->bit_width = 64; - addr->bit_offset = 0; - addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; - addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; - - hpet->id = 0x8086a201; /* Intel */ - hpet->number = 0x00; - hpet->min_tick = 0x0080; - - header->checksum = - acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl index 00aac51e23..7cdf1aa5d0 100644 --- a/src/soc/intel/baytrail/acpi/lpc.asl +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -59,7 +59,7 @@ Device (LPCB) Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400) }) } diff --git a/src/soc/intel/baytrail/acpi/platform.asl b/src/soc/intel/baytrail/acpi/platform.asl index 2bd43a74b6..885a7d57f2 100644 --- a/src/soc/intel/baytrail/acpi/platform.asl +++ b/src/soc/intel/baytrail/acpi/platform.asl @@ -14,43 +14,7 @@ * GNU General Public License for more details. */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} +#include /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/soc/intel/baytrail/acpi/sleepstates.asl b/src/soc/intel/baytrail/acpi/sleepstates.asl deleted file mode 100644 index 4d1d0b3ea2..0000000000 --- a/src/soc/intel/baytrail/acpi/sleepstates.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -// Name(\_S1, Package(){0x1,0x1,0x0,0x0}) -Name(\_S3, Package(){0x5,0x5,0x0,0x0}) -Name(\_S4, Package(){0x6,0x6,0x0,0x0}) -Name(\_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 14731ee27c..4465c222b0 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -47,7 +47,6 @@ Scope(\) Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Name (MCRS, ResourceTemplate() diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h index 29acda707a..2851f9201b 100644 --- a/src/soc/intel/baytrail/include/soc/acpi.h +++ b/src/soc/intel/baytrail/include/soc/acpi.h @@ -19,7 +19,6 @@ #include #include -void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index 5038bf87db..825e7f2372 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -39,7 +39,7 @@ #define MSR_CPU_THERM_SENS_CFG 0x675 /* Read BCLK from MSR */ -unsigned bus_freq_khz(void); +unsigned int bus_freq_khz(void); void set_max_freq(void); #endif /* _BAYTRAIL_MSR_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/pattrs.h b/src/soc/intel/baytrail/include/soc/pattrs.h index 7d10cea2cb..7b46345a47 100644 --- a/src/soc/intel/baytrail/include/soc/pattrs.h +++ b/src/soc/intel/baytrail/include/soc/pattrs.h @@ -42,7 +42,7 @@ struct pattrs { const void *microcode_patch; int address_bits; int num_cpus; - unsigned bclk_khz; + unsigned int bclk_khz; }; /* This is just to hide the abstraction w/o relying on how the underlying diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index 9636640108..3fa5459cea 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -42,7 +42,7 @@ #define FIRMWARE_REG_BASE_C0 0x144000 #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) -static void assign_device_nvs(struct device *dev, u32 *field, unsigned index) +static void assign_device_nvs(struct device *dev, u32 *field, unsigned int index) { struct resource *res; diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index d9f6160dfc..e0aac9f423 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -29,7 +29,7 @@ static size_t smm_region_size(void) return CONFIG_SMM_TSEG_SIZE; } -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return (void *) smm_region_start(); } diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 8f65433f05..fb6143efb0 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -351,7 +351,7 @@ static void hda_work_around(struct device *dev) static int place_device_in_d3hot(struct device *dev) { - unsigned offset; + unsigned int offset; /* Parts of the HDA block are used for LPE audio as well. * Therefore assume the HDA will never be put into D3Hot. */ @@ -530,7 +530,7 @@ static struct device_operations device_ops = { .enable_resources = NULL, .init = sc_init, .enable = southcluster_enable_dev, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 26b717c65e..e43900258e 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -76,7 +76,7 @@ typedef struct ich_spi_controller { uint16_t *optype; uint32_t *addr; uint8_t *data; - unsigned databytes; + unsigned int databytes; uint8_t *status; uint16_t *control; uint32_t *bbar; @@ -140,7 +140,7 @@ static u8 readb_(const void *addr) { u8 v = read8((unsigned long)addr); printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned int) addr & 0xffff) - 0xf020); return v; } @@ -148,7 +148,7 @@ static u16 readw_(const void *addr) { u16 v = read16((unsigned long)addr); printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned int) addr & 0xffff) - 0xf020); return v; } @@ -156,7 +156,7 @@ static u32 readl_(const void *addr) { u32 v = read32((unsigned long)addr); printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned int) addr & 0xffff) - 0xf020); return v; } @@ -164,21 +164,21 @@ static void writeb_(u8 b, void *addr) { write8(addr, b); printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned int) addr & 0xffff) - 0xf020); } static void writew_(u16 b, void *addr) { write16(addr, b); printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned int) addr & 0xffff) - 0xf020); } static void writel_(u32 b, void *addr) { write32(addr, b); printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned int) addr & 0xffff) - 0xf020); } #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ @@ -285,13 +285,13 @@ typedef struct spi_transaction { uint32_t offset; } spi_transaction; -static inline void spi_use_out(spi_transaction *trans, unsigned bytes) +static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) { trans->out += bytes; trans->bytesout -= bytes; } -static inline void spi_use_in(spi_transaction *trans, unsigned bytes) +static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) { trans->in += bytes; trans->bytesin -= bytes; diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index 5b2d13599d..edc31c1e47 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -18,7 +18,7 @@ #include #include -unsigned bus_freq_khz(void) +unsigned int bus_freq_khz(void) { msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL); switch (clk_info.lo & 0x3) { @@ -38,7 +38,7 @@ unsigned bus_freq_khz(void) unsigned long tsc_freq_mhz(void) { msr_t platform_info; - unsigned bclk_khz = bus_freq_khz(); + unsigned int bclk_khz = bus_freq_khz(); if (!bclk_khz) return 0; diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5d6438fee5..7ea01863ae 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -14,7 +14,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select COLLECT_TIMESTAMPS select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_IN_BLOB_REPO select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED @@ -35,7 +34,6 @@ config CPU_SPECIFIC_OPTIONS select SMP select SPI_FLASH select SSE2 - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 9caa8f17eb..a8604d6c68 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -71,7 +71,7 @@ Device (LPCB) Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400) }) } #endif diff --git a/src/soc/intel/braswell/acpi/platform.asl b/src/soc/intel/braswell/acpi/platform.asl index 85aae11e93..fdf27887e5 100644 --- a/src/soc/intel/braswell/acpi/platform.asl +++ b/src/soc/intel/braswell/acpi/platform.asl @@ -16,45 +16,8 @@ /* Enable ACPI _SWS methods */ #include +#include -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, /* APM command */ - APMS, 8 /* APM status */ -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) /* SMI Function */ - Store (0, TRP0) /* Generate trap */ - Return (SMIF) /* Return value of SMI handler */ -} - -/* - * The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store(Arg0, PICM) -} /* * The _PTS method (Prepare To Sleep) is called before the OS is diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index 9ecf67a971..4b2deb3ee1 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -47,7 +47,6 @@ Scope(\) Name(_HID,EISAID("PNP0A08")) /* PCIe */ Name(_CID,EISAID("PNP0A03")) /* PCI */ -Name(_ADR, 0) Name(_BBN, 0) Method (_CRS, 0, Serialized) diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index d502aed9f9..e43c5469f6 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -33,7 +33,7 @@ void smm_region(uintptr_t *start, size_t *size) *size = smm_region_size(); } -void *cbmem_top(void) +void *cbmem_top_chipset(void) { uintptr_t smm_base; size_t smm_size; diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 67e941c511..9118f00a66 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -598,7 +598,7 @@ static struct device_operations device_ops = { .write_acpi_tables = southcluster_write_acpi_tables, .init = sc_init, .enable = southcluster_enable_dev, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 5856ef1e50..0bbb668c98 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -27,9 +27,9 @@ config CPU_SPECIFIC_OPTIONS select SMP select SPI_FLASH select SSE2 - select TSC_CONSTANT_RATE select TSC_SYNC_MFENCE select UDELAY_TSC + select TSC_MONOTONIC_TIMER select SOC_INTEL_COMMON select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 91a3da02c6..055a0049af 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -39,11 +39,6 @@ ramstage-y += memmap.c romstage-y += memmap.c postcar-y += memmap.c ramstage-y += minihd.c -bootblock-y += monotonic_timer.c -romstage-y += monotonic_timer.c -postcar-y += monotonic_timer.c -ramstage-y += monotonic_timer.c -smm-y += monotonic_timer.c ramstage-y += pch.c romstage-y += pch.c ramstage-y += pcie.c diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 7acde68db1..fe65a0113e 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -185,37 +185,6 @@ void acpi_init_gnvs(global_nvs_t *gnvs) #endif } -void acpi_create_intel_hpet(acpi_hpet_t *hpet) -{ - acpi_header_t *header = &(hpet->header); - acpi_addr_t *addr = &(hpet->addr); - - memset((void *) hpet, 0, sizeof(acpi_hpet_t)); - - /* fill out header fields */ - memcpy(header->signature, "HPET", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_hpet_t); - header->revision = get_acpi_table_revision(HPET); - - /* fill out HPET address */ - addr->space_id = 0; /* Memory */ - addr->bit_width = 64; - addr->bit_offset = 0; - addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; - addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; - - hpet->id = 0x8086a201; /* Intel */ - hpet->number = 0x00; - hpet->min_tick = 0x0080; - - header->checksum = - acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/acpi/lpc.asl index 70dd6e5a26..ca44c5c90c 100644 --- a/src/soc/intel/broadwell/acpi/lpc.asl +++ b/src/soc/intel/broadwell/acpi/lpc.asl @@ -74,7 +74,7 @@ Device (LPCB) Name (BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -99,15 +99,15 @@ Device (LPCB) \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) } If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) } If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } } diff --git a/src/soc/intel/broadwell/acpi/platform.asl b/src/soc/intel/broadwell/acpi/platform.asl index 7c6bdd708f..15a820ff56 100644 --- a/src/soc/intel/broadwell/acpi/platform.asl +++ b/src/soc/intel/broadwell/acpi/platform.asl @@ -16,44 +16,7 @@ /* Enable ACPI _SWS methods */ #include - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method (TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method (_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store (Arg0, PICM) -} +#include /* * The _PTS method (Prepare To Sleep) is called before the OS is diff --git a/src/soc/intel/broadwell/acpi/sleepstates.asl b/src/soc/intel/broadwell/acpi/sleepstates.asl deleted file mode 100644 index 585da9e26e..0000000000 --- a/src/soc/intel/broadwell/acpi/sleepstates.asl +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name (\_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) -Name (\_S1, Package () { 0x1, 0x1, 0x0, 0x0 }) -Name (\_S2, Package () { 0x1, 0x1, 0x0, 0x0 }) -Name (\_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) -Name (\_S4, Package () { 0x6, 0x6, 0x0, 0x0 }) -Name (\_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) diff --git a/src/soc/intel/broadwell/acpi/systemagent.asl b/src/soc/intel/broadwell/acpi/systemagent.asl index c45d48d202..18bf914cf7 100644 --- a/src/soc/intel/broadwell/acpi/systemagent.asl +++ b/src/soc/intel/broadwell/acpi/systemagent.asl @@ -19,7 +19,6 @@ Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_CID, EISAID ("PNP0A03")) // PCI -Name (_ADR, 0) Name (_BBN, 0) Device (MCHC) diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 456a4354ca..18a65857a7 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -117,8 +117,11 @@ struct soc_intel_broadwell_config { u16 gpu_panel_power_backlight_off_delay; /* Panel backlight settings */ - u32 gpu_cpu_backlight; - u32 gpu_pch_backlight; + unsigned int gpu_pch_backlight_pwm_hz; + enum { + GPU_BACKLIGHT_POLARITY_HIGH = 0, + GPU_BACKLIGHT_POLARITY_LOW, + } gpu_pch_backlight_polarity; /* * Graphics CD Clock Frequency diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index dab2d15750..31476809dc 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -335,14 +336,34 @@ static void igd_setup_panel(struct device *dev) gtt_write(PCH_PP_DIVISOR, reg32); } - /* Enable Backlight if needed */ - if (conf->gpu_cpu_backlight) { - gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE); - gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight); - } - if (conf->gpu_pch_backlight) { - gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE); - gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight); + /* So far all devices seem to use the PCH PWM function. + The CPU PWM registers are all zero after reset. */ + if (conf->gpu_pch_backlight_pwm_hz) { + /* For Lynx Point-LP: + Reference clock is 24MHz. We can choose either a 16 + or a 128 step increment. Use 16 if we would have less + than 100 steps otherwise. */ + const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100; + unsigned int pwm_increment, pwm_period; + u32 south_chicken2; + + south_chicken2 = gtt_read(SOUTH_CHICKEN2); + if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { + pwm_increment = 16; + south_chicken2 &= ~(1 << 5); + } else { + pwm_increment = 128; + south_chicken2 |= 1 << 5; + } + gtt_write(SOUTH_CHICKEN2, south_chicken2); + + pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + /* Start with a 50% duty cycle. */ + gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); + + gtt_write(BLC_PWM_PCH_CTL1, + (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | + BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE); } } @@ -574,6 +595,12 @@ static void igd_init(struct device *dev) DDI_INIT_DISPLAY_DETECTED); } + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { + int lightup_ok; + gma_gfxinit(&lightup_ok); + gfx_set_init_done(lightup_ok); + } + intel_gma_restore_opregion(); } diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h index 24fe3ae7aa..d07546490f 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/soc/intel/broadwell/include/soc/acpi.h @@ -25,7 +25,6 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -void acpi_create_intel_hpet(acpi_hpet_t *hpet); void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index b385d6b637..873f594530 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -634,7 +633,7 @@ static struct device_operations device_ops = { .acpi_inject_dsdt_generator = southcluster_inject_dsdt, .write_acpi_tables = broadwell_write_acpi_tables, .init = &lpc_init, - .scan_bus = &scan_lpc_bus, + .scan_bus = &scan_static_bus, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index f4a9d0ed24..ad50dd35db 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -41,7 +41,7 @@ static uintptr_t dpr_region_start(void) return tom; } -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return (void *) dpr_region_start(); } diff --git a/src/soc/intel/broadwell/monotonic_timer.c b/src/soc/intel/broadwell/monotonic_timer.c deleted file mode 100644 index 84eade8a30..0000000000 --- a/src/soc/intel/broadwell/monotonic_timer.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -static struct monotonic_counter { - int initialized; - struct mono_time time; - uint32_t last_value; -} mono_counter; - -static inline uint32_t read_counter_msr(void) -{ - /* Even though the MSR is 64-bit it is assumed that the hardware - * is polled frequently enough to only use the lower 32-bits. */ - msr_t counter_msr; - - counter_msr = rdmsr(MSR_COUNTER_24_MHZ); - - return counter_msr.lo; -} - -void timer_monotonic_get(struct mono_time *mt) -{ - uint32_t current_tick; - uint32_t usecs_elapsed; - - if (!mono_counter.initialized) { - mono_counter.last_value = read_counter_msr(); - mono_counter.initialized = 1; - } - - current_tick = read_counter_msr(); - usecs_elapsed = (current_tick - mono_counter.last_value) / 24; - - /* Update current time and tick values only if a full tick occurred. */ - if (usecs_elapsed) { - mono_time_add_usecs(&mono_counter.time, usecs_elapsed); - mono_counter.last_value = current_tick; - } - - /* Save result. */ - *mt = mono_counter.time; -} diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index fc3f2ac3c2..0e43cf1822 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -87,6 +87,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_EBDA select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA @@ -100,7 +101,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_RESET select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_2017_BINDING @@ -119,11 +119,12 @@ config DCACHE_RAM_SIZE config DCACHE_BSP_STACK_SIZE hex - default 0x20000 if FSP_USES_CB_STACK + default 0x20400 if FSP_USES_CB_STACK default 0x4000 help The amount of anticipated stack usage in CAR by bootblock and - other stages. + other stages. In the case of FSP_USES_CB_STACK default value will be + sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). config FSP_TEMP_RAM_SIZE hex diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 724e141d39..5bc9409521 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -49,7 +49,7 @@ ramstage-y += nhlt.c ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c -ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c diff --git a/src/soc/intel/cannonlake/acpi/globalnvs.asl b/src/soc/intel/cannonlake/acpi/globalnvs.asl deleted file mode 100644 index 940cf4396b..0000000000 --- a/src/soc/intel/cannonlake/acpi/globalnvs.asl +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Global Variables */ - -Name (\PICM, 0) // IOAPIC/8259 - -/* - * Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External (NVSA) - -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - /* Miscellaneous */ - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PCNT, 8, // 0x03 - Processor Count - PPCM, 8, // 0x04 - Max PPC State - TLVL, 8, // 0x05 - Throttle Level Limit - LIDS, 8, // 0x06 - LID State - PWRS, 8, // 0x07 - AC Power State - CBMC, 32, // 0x08 - 0x0b AC Power State - PM1I, 64, // 0x0c - 0x13 PM1 wake status bit - GPEI, 64, // 0x14 - 0x17 GPE wake status bit - DPTE, 8, // 0x1c - Enable DPTF - NHLA, 64, // 0x1d - 0x24 NHLT Address - NHLL, 32, // 0x25 - 0x28 NHLT Length - CID1, 16, // 0x29 - 0x2a Wifi Country Identifier - U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap - U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap - UIOR, 8, // 0x2f - UART debug controller init on S3 resume - - /* ChromeOS specific */ - Offset (0x100), - #include -} diff --git a/src/soc/intel/cannonlake/acpi/northbridge.asl b/src/soc/intel/cannonlake/acpi/northbridge.asl index 7fb4c09179..22ddad7fbb 100644 --- a/src/soc/intel/cannonlake/acpi/northbridge.asl +++ b/src/soc/intel/cannonlake/acpi/northbridge.asl @@ -23,7 +23,6 @@ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_SEG, Zero) // _SEG: PCI Segment -Name (_ADR, Zero) // _ADR: Address Name (_UID, Zero) // _UID: Unique ID Device (MCHC) diff --git a/src/soc/intel/cannonlake/acpi/platform.asl b/src/soc/intel/cannonlake/acpi/platform.asl index 773cdcb14b..da61619342 100644 --- a/src/soc/intel/cannonlake/acpi/platform.asl +++ b/src/soc/intel/cannonlake/acpi/platform.asl @@ -20,15 +20,6 @@ /* Generic indicator for sleep state */ #include -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - /* * The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 8ba3d89b0f..b52de65e36 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -32,7 +32,7 @@ #endif /* LPC 0:1f.0 */ -#include "lpc.asl" +#include /* PCH HDA */ #include "pch_hda.asl" diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index a3252c2560..39433a26d9 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -90,7 +90,7 @@ static void soc_config_pwrmbase(void) /* Enable Bus Master and MMIO Space */ reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 |= PCI_COMMAND_MEMORY; + reg32 |= PCI_COMMAND_MEMORY; pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); /* Enable PWRM in PMC */ diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index c58b9ad693..7f38279def 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -399,7 +399,7 @@ static void enable_pm_timer_emulation(void) * frequency is used. */ msr.hi = (3579545ULL << 32) / CTC_FREQ; - /* Set PM1 timer IO port and enable*/ + /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); wrmsr(MSR_EMULATE_PM_TIMER, msr); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index b7aa39f175..1a8c3aca26 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -192,6 +192,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->SataPortsDevSlpResetConfig)); #endif } + params->SlpS0WithGbeSupport = 0; + params->PchPmSlpS0VmRuntimeControl = config->PchPmSlpS0VmRuntimeControl; + params->PchPmSlpS0Vm070VSupport = config->PchPmSlpS0Vm070VSupport; + params->PchPmSlpS0Vm075VSupport = config->PchPmSlpS0Vm075VSupport; /* Lan */ dev = pcidev_path_on_root(PCH_DEVFN_GBE); @@ -199,7 +203,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchLanEnable = 0; else { params->PchLanEnable = dev->enabled; - if (config->s0ix_enable) { + if (config->s0ix_enable && params->PchLanEnable) { + /* + * The VmControl UPDs need to be set as per board + * design to allow voltage margining in S0ix to lower + * power consumption. + * But if GbE is enabled, voltage magining cannot be + * enabled, so the Vm control UPDs need to be set to 0. + */ params->SlpS0WithGbeSupport = 1; params->PchPmSlpS0VmRuntimeControl = 0; params->PchPmSlpS0Vm070VSupport = 0; @@ -452,6 +463,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SpiFlashCfgLockDown = 1; #endif } + + dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) + params->PeiGraphicsPeimInit = 1; + else + params->PeiGraphicsPeimInit = 0; } /* Mainboard GPIO Configuration */ diff --git a/src/soc/intel/cannonlake/include/soc/nvs.h b/src/soc/intel/cannonlake/include/soc/nvs.h index 1cb22faa74..3bd7bc2bca 100644 --- a/src/soc/intel/cannonlake/include/soc/nvs.h +++ b/src/soc/intel/cannonlake/include/soc/nvs.h @@ -18,34 +18,6 @@ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ -#include -#include - -typedef struct global_nvs_t { - /* Miscellaneous */ - u16 osys; /* 0x00 - 0x01 Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 pcnt; /* 0x03 - Processor Count */ - u8 ppcm; /* 0x04 - Max PPC State */ - u8 tlvl; /* 0x05 - Throttle Level Limit */ - u8 lids; /* 0x06 - LID State */ - u8 pwrs; /* 0x07 - AC Power State */ - u32 cbmc; /* 0x08 - 0xb AC Power State */ - u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */ - u64 gpei; /* 0x14 - 0x1b GPE wake status bit */ - u8 dpte; /* 0x1c - Enable DPTF */ - u64 nhla; /* 0x1d - 0x24 NHLT Address */ - u32 nhll; /* 0x25 - 0x28 NHLT Length */ - u16 cid1; /* 0x29 - 0x2a Wifi Country Identifier */ - u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */ - u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */ - u8 uior; /* 0x2f - UART debug controller init on S3 resume */ - u8 unused[208]; - - /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - +#include #endif diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 7adaa30b18..386cd9551a 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -31,10 +31,20 @@ #include "chip.h" -void smm_region(uintptr_t *start, size_t *size) +static bool is_ptt_enable(void) { - *start = sa_get_tseg_base(); - *size = sa_get_tseg_size(); + if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == + PTT_PRESENT) + return true; + + return false; +} + +/* Calculate PTT size */ +static size_t get_ptt_size(void) +{ + /* Allocate 4KB for PTT if enabled */ + return is_ptt_enable() ? 4*KiB : 0; } static bool is_ptt_enable(void) @@ -211,21 +221,6 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size) return dram_base; } -/* - * SoC implementation - * - * SoC call to summarize all Intel Reserve MMIO size and report to SA - */ -size_t soc_reserved_mmio_size(void) -{ - struct ebda_config cfg; - - retrieve_ebda_object(&cfg); - - /* Get Intel Reserved Memory Range Size */ - return cfg.reserved_mem_size; -} - /* Fill up memory layout information */ void fill_soc_memmap_ebda(struct ebda_config *cfg) { @@ -268,38 +263,11 @@ void cbmem_top_init(void) * | | * +-------------------------+ */ -void *cbmem_top(void) +void *cbmem_top_chipset(void) { struct ebda_config ebda_cfg; - /* - * Check if Tseg has been initialized, we will use this as a flag - * to check if the MRC is done, and only then continue to read the - * PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before - * PRMRR_MASK MSR lock bit is set. - */ - if (sa_get_tseg_base() == 0) - return NULL; - retrieve_ebda_object(&ebda_cfg); return (void *)(uintptr_t)ebda_cfg.tolum_base; } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); -} diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index e01c22c463..4758faf7c5 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -19,7 +19,6 @@ #include #include #include -#include #include void do_global_reset(void) diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 493d0030cf..6680bf3717 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/icelake/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl similarity index 97% rename from src/soc/intel/icelake/acpi/globalnvs.asl rename to src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 678ce5ac23..8e8241bc78 100644 --- a/src/soc/intel/icelake/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -30,7 +30,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PCNT, 8, // 0x03 - Processor Count diff --git a/src/soc/intel/icelake/acpi/ipu.asl b/src/soc/intel/common/block/acpi/acpi/ipu.asl similarity index 100% rename from src/soc/intel/icelake/acpi/ipu.asl rename to src/soc/intel/common/block/acpi/acpi/ipu.asl diff --git a/src/soc/intel/cannonlake/acpi/lpc.asl b/src/soc/intel/common/block/acpi/acpi/lpc.asl similarity index 79% rename from src/soc/intel/cannonlake/acpi/lpc.asl rename to src/soc/intel/common/block/acpi/acpi/lpc.asl index f1c1bf3bc3..e7f6660645 100644 --- a/src/soc/intel/cannonlake/acpi/lpc.asl +++ b/src/soc/intel/common/block/acpi/acpi/lpc.asl @@ -15,11 +15,29 @@ * GNU General Public License for more details. */ +/* Intel LPC/eSPI Bus Device - 0:1f.0 */ +#include + Device (LPCB) { Name (_ADR, 0x001f0000) Name (_DDN, "LPC Bus Device") + /* DMA Controller */ + Device (DMAC) + { + Name (_HID, EISAID("PNP0200")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x00, 0x00, 0x01, 0x20) + IO (Decode16, 0x81, 0x81, 0x01, 0x11) + IO (Decode16, 0x93, 0x93, 0x01, 0x0d) + IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) + DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } + }) + } + + /* Firmware Hub */ Device (FWH) { Name (_HID, EISAID ("INT0800")) @@ -30,9 +48,11 @@ Device (LPCB) }) } + /* High Precision Event Timer */ Device (HPET) { Name (_HID, EISAID ("PNP0103")) + Name (_CID, 0x010CD041) Name (_DDN, "High Precision Event Timer") Name (_CRS, ResourceTemplate () { @@ -40,10 +60,22 @@ Device (LPCB) }) Method (_STA, 0) { - Return (0xf) + Return (0xF) } } + /* FPU */ + Device(MATH) + { + Name (_HID, EISAID("PNP0C04")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) + IRQNoFlags() { 13 } + }) + } + + /* AT Interrupt Controller */ Device (PIC) { Name (_HID, EISAID ("PNP0000")) @@ -71,6 +103,7 @@ Device (LPCB) }) } + /* LPC device: Resource consumption */ Device (LDRC) { Name (_HID, EISAID ("PNP0C02")) @@ -92,6 +125,7 @@ Device (LPCB) }) } + /* Real Time Clock Device */ Device (RTC) { Name (_HID, EISAID ("PNP0B00")) @@ -102,6 +136,7 @@ Device (LPCB) }) } + /* Timer */ Device (TIMR) { Name (_HID, EISAID ("PNP0100")) @@ -113,5 +148,4 @@ Device (LPCB) IRQNoFlags () {0} }) } - } diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c index 5ab8f6b07d..6551e9182a 100644 --- a/src/soc/intel/common/block/chip/chip.c +++ b/src/soc/intel/common/block/chip/chip.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 75e71120e0..71e4dbf01b 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -23,10 +23,10 @@ #include #include #include +#include #include #include #include -#include #include #include @@ -320,3 +320,8 @@ void mca_configure(void) (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); } } + +void cpu_lt_lock_memory(void *unused) +{ + msr_set_bit(MSR_LT_CONTROL, LT_CONTROL_LOCK_BIT); +} diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index d268893d3c..277b6c5aab 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -23,7 +23,7 @@ static struct device_operations dsp_dev_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .ops_pci = &pci_dev_ops_pci, - .scan_bus = scan_static_bus, + .scan_bus = enable_static_devices, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 7aece76ca6..8e79eab54e 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -136,19 +136,35 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1, PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM, + PCI_DEVICE_ID_INTEL_KBL_GT1_SHALM_1, + PCI_DEVICE_ID_INTEL_KBL_GT1_SHALM_2, + PCI_DEVICE_ID_INTEL_KBL_GT1_SSRVM, + PCI_DEVICE_ID_INTEL_KBL_GT1F_DT2, PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM, PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM, PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR, + PCI_DEVICE_ID_INTEL_KBL_GT2_SSRVM, + PCI_DEVICE_ID_INTEL_KBL_GT2_SWSTM, PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM, PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2, + PCI_DEVICE_ID_INTEL_KBL_GT2F_SULTM, + PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1, + PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2, + PCI_DEVICE_ID_INTEL_KBL_GT4_SHALM, PCI_DEVICE_ID_INTEL_AML_GT2_ULX, + PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2, PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM, PCI_DEVICE_ID_INTEL_SKL_GT2_DT2P1, PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM, PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM, PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM, PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM, + PCI_DEVICE_ID_INTEL_SKL_GT3_SULTM, + PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_1, + PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_2, + PCI_DEVICE_ID_INTEL_SKL_GT3FE_SSRVM, PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM, + PCI_DEVICE_ID_INTEL_SKL_GT4E_SWSTM, PCI_DEVICE_ID_INTEL_CFL_H_GT2, PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2, PCI_DEVICE_ID_INTEL_CFL_S_GT2_1, diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 0cf9baa3ef..be8319c058 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -68,7 +68,7 @@ static struct device_operations hda_ops = { .init = hda_init, #endif .ops_pci = &pci_dev_ops_pci, - .scan_bus = scan_static_bus, + .scan_bus = enable_static_devices, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 8630fd1eb5..1aa88e156d 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -161,4 +161,7 @@ uint32_t cpu_get_max_turbo_ratio(void); /* Configure Machine Check Architecture support */ void mca_configure(void); +/* Lock chipset memory registers to protect SMM */ +void cpu_lt_lock_memory(void *unused); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 6fdf26e202..3e67fd779d 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -67,6 +67,8 @@ #define MSR_POWER_CTL 0x1fc #define POWER_CTL_C1E_MASK (1 << 1) #define MSR_EVICT_CTL 0x2e0 +#define MSR_LT_CONTROL 0x2e7 +#define LT_CONTROL_LOCK_BIT (0) #define MSR_SGX_OWNEREPOCH0 0x300 #define MSR_SGX_OWNEREPOCH1 0x301 #define SMM_FEATURE_CONTROL_MSR 0x4e0 diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h new file mode 100644 index 0000000000..5f367b68b3 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_NVS_H +#define SOC_INTEL_COMMON_BLOCK_NVS_H + +#include +#include + +typedef struct global_nvs_t { + /* Miscellaneous */ + u16 osys; /* 0x00 - 0x01 Operating System */ + u8 smif; /* 0x02 - SMI function call ("TRAP") */ + u8 pcnt; /* 0x03 - Processor Count */ + u8 ppcm; /* 0x04 - Max PPC State */ + u8 tlvl; /* 0x05 - Throttle Level Limit */ + u8 lids; /* 0x06 - LID State */ + u8 pwrs; /* 0x07 - AC Power State */ + u32 cbmc; /* 0x08 - 0xb AC Power State */ + u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */ + u64 gpei; /* 0x14 - 0x1b GPE wake status bit */ + u8 dpte; /* 0x1c - Enable DPTF */ + u64 nhla; /* 0x1d - 0x24 NHLT Address */ + u32 nhll; /* 0x25 - 0x28 NHLT Length */ + u16 cid1; /* 0x29 - 0x2a Wifi Country Identifier */ + u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */ + u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */ + u8 uior; /* 0x2f - UART debug controller init on S3 resume */ + u8 unused[208]; + + /* ChromeOS specific (0x100 - 0xfff) */ + chromeos_acpi_t chromeos; +} __packed global_nvs_t; +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); + +#endif diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h index 502483f7e9..36634d3fa1 100644 --- a/src/soc/intel/common/block/include/intelblocks/sgx.h +++ b/src/soc/intel/common/block/include/intelblocks/sgx.h @@ -18,16 +18,6 @@ #include -struct sgx_param { - uint8_t enable; -}; - -/* - * Lock SGX memory. - * CPU specific code needs to provide the implementation. - */ -void cpu_lock_sgx_memory(void); - /* * Configure core PRMRR. * PRMRR needs to configured first on all cores and then @@ -40,10 +30,6 @@ void prmrr_core_configure(void); */ void sgx_configure(void *unused); -/* SOC specific API to get SGX params. - * returns 0, if able to get SGX params; otherwise returns -1 */ -int soc_fill_sgx_param(struct sgx_param *sgx_param); - /* Fill GNVS data with SGX status, EPC base and length */ void sgx_fill_gnvs(global_nvs_t *gnvs); diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index 133047c5b7..ae9213c395 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -106,8 +106,4 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt); /* SoC specific APIs to get UNCORE PRMRR base and mask values * returns 0, if able to get base and mask values; otherwise returns -1 */ int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, uint64_t *mask); - -/* SoC call to summarize all Intel Reserve MMIO size and report to SA */ -size_t soc_reserved_mmio_size(void); - #endif /* SOC_INTEL_COMMON_BLOCK_SA_H */ diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 46dfd7ff57..eb7de081bc 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -115,7 +115,7 @@ static struct device_operations device_ops = { .write_acpi_tables = southbridge_write_acpi_tables, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .init = lpc_soc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/common/block/lpc/lpc_def.h b/src/soc/intel/common/block/lpc/lpc_def.h index c066f68f17..9a72580af6 100644 --- a/src/soc/intel/common/block/lpc/lpc_def.h +++ b/src/soc/intel/common/block/lpc/lpc_def.h @@ -37,7 +37,7 @@ #define LPC_LGMR_WINDOW_SIZE (64 * KiB) #define LPC_BIOS_CNTL 0xdc #define LPC_BC_BILD (1 << 7) /* BILD */ -#define LPC_BC_LE (1 << 2) /* LE */ +#define LPC_BC_LE (1 << 1) /* LE */ #define LPC_BC_EISS (1 << 5) /* EISS */ #define LPC_PCCTL 0xE0 /* PCI Clock Control */ #define LPC_PCCTL_CLKRUN_EN (1 << 0) diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 1df05679dd..14e1fd90eb 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -155,6 +155,8 @@ static void read_resources(struct device *dev) /* * There's only one resource on the P2SB device. It's also already * manually set to a fixed address in earlier boot stages. + * The following code makes sure that it doesn't change if the device + * is visible and the resource allocator is being run. */ mmio_resource(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB); } @@ -170,6 +172,9 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_GLK_P2SB, PCI_DEVICE_ID_INTEL_LWB_P2SB, PCI_DEVICE_ID_INTEL_LWB_P2SB_SUPER, + PCI_DEVICE_ID_INTEL_SKL_LP_P2SB, + PCI_DEVICE_ID_INTEL_SKL_P2SB, + PCI_DEVICE_ID_INTEL_KBL_P2SB, PCI_DEVICE_ID_INTEL_CNL_P2SB, PCI_DEVICE_ID_INTEL_CNP_H_P2SB, PCI_DEVICE_ID_INTEL_ICL_P2SB, diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index f6f0983227..2b148f2021 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -119,7 +119,7 @@ static struct device_operations device_ops = { .enable_resources = pci_dev_enable_resources, .init = pmc_soc_init, .ops_pci = &pci_dev_ops_pci, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig index 0852bfbf49..026c6afb0d 100644 --- a/src/soc/intel/common/block/sgx/Kconfig +++ b/src/soc/intel/common/block/sgx/Kconfig @@ -1,7 +1,16 @@ config SOC_INTEL_COMMON_BLOCK_SGX bool + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_HYPERTHREADING default n help Software Guard eXtension(SGX) Feature. Intel SGX is a set of new CPU instructions that can be used by applications to set aside private regions of code and data. + +config SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY + bool + depends on SOC_INTEL_COMMON_BLOCK_SGX + default n + help + Lock memory before SGX activation. This is only needed if MCHECK does not do it. diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 60714d9ce2..842eb43994 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -17,16 +17,14 @@ #include #include #include +#include +#include #include #include #include #include #include #include -#include - -static bool sgx_param_valid; -static struct sgx_param g_sgx_param; static inline uint64_t sgx_resource(uint32_t low, uint32_t high) { @@ -36,28 +34,6 @@ static inline uint64_t sgx_resource(uint32_t low, uint32_t high) return val; } -static const struct sgx_param *get_sgx_param(void) -{ - if (sgx_param_valid) - return &g_sgx_param; - - memset(&g_sgx_param, 0, sizeof(g_sgx_param)); - if (soc_fill_sgx_param(&g_sgx_param) < 0) { - printk(BIOS_ERR, "SGX : Failed to get soc sgx param\n"); - return NULL; - } - sgx_param_valid = true; - printk(BIOS_INFO, "SGX : param.enable = %d\n", g_sgx_param.enable); - - return &g_sgx_param; -} - -static int soc_sgx_enabled(void) -{ - const struct sgx_param *sgx_param = get_sgx_param(); - return sgx_param ? sgx_param->enable : 0; -} - static int is_sgx_supported(void) { struct cpuid_result cpuid_regs; @@ -79,9 +55,18 @@ void prmrr_core_configure(void) } prmrr_base, prmrr_mask; msr_t msr; - if (!soc_sgx_enabled() || !is_sgx_supported()) + /* + * Software Developer's Manual Volume 4: + * Order Number: 335592-068US + * Chapter 2.16.1 + * MSR_PRMRR_PHYS_MASK is in scope "Core" + * MSR_PRMRR_PHYS_BASE is in scope "Core" + * Return if Hyper-Threading is enabled and not thread 0 + */ + if (!is_sgx_supported() || intel_ht_sibling()) return; + /* PRMRR_PHYS_MASK is in scope "Core" */ msr = rdmsr(MSR_PRMRR_PHYS_MASK); /* If it is locked don't attempt to write PRMRR MSRs. */ if (msr.lo & PRMRR_PHYS_MASK_LOCK) @@ -134,6 +119,12 @@ static void enable_sgx(void) { msr_t msr; + /* + * Intel 64 and IA-32 ArchitecturesSoftware Developer's ManualVolume 3C + * Order Number: 326019-060US + * Chapter 35.10.2 "Additional MSRs Supported by Intel" + * IA32_FEATURE_CONTROL is in scope "Thread" + */ msr = rdmsr(IA32_FEATURE_CONTROL); /* Only enable it when it is not locked */ if ((msr.lo & FEATURE_CONTROL_LOCK_BIT) == 0) { @@ -146,6 +137,12 @@ static void lock_sgx(void) { msr_t msr; + /* + * Intel 64 and IA-32 ArchitecturesSoftware Developer's ManualVolume 3C + * Order Number: 326019-060US + * Chapter 35.10.2 "Additional MSRs Supported by Intel" + * IA32_FEATURE_CONTROL is in scope "Thread" + */ msr = rdmsr(IA32_FEATURE_CONTROL); /* If it is locked don't attempt to lock it again. */ if ((msr.lo & 1) == 0) { @@ -160,6 +157,7 @@ static int owner_epoch_update(void) * for PoC just write '0's to the MSRs. */ msr_t msr = {0, 0}; + /* SGX_OWNEREPOCH is in scope "Package" */ wrmsr(MSR_SGX_OWNEREPOCH0, msr); wrmsr(MSR_SGX_OWNEREPOCH1, msr); return 0; @@ -200,29 +198,49 @@ static int is_prmrr_approved(void) return 0; } +/* + * Configures SGX according to "Intel Software Guard Extensions Technology" + * Document Number: 565432 + */ void sgx_configure(void *unused) { - const void *microcode_patch = intel_mp_current_microcode(); - if (!soc_sgx_enabled() || !is_sgx_supported() || !is_prmrr_set()) { + if (!is_sgx_supported() || !is_prmrr_set()) { printk(BIOS_ERR, "SGX: pre-conditions not met\n"); return; } - /* Enable the SGX feature */ + /* Enable the SGX feature on all threads. */ enable_sgx(); /* Update the owner epoch value */ if (owner_epoch_update() < 0) return; - /* Ensure to lock memory before reload microcode patch */ - cpu_lock_sgx_memory(); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY)) + /* Ensure to lock memory before reload microcode patch */ + cpu_lt_lock_memory(NULL); - /* Reload the microcode patch */ - intel_microcode_load_unlocked(microcode_patch); + /* + * Update just on the first CPU in the core. Other siblings + * get the update automatically according to Document: 253668-060US + * Intel SDM Chapter 9.11.6.3 + * "Update in a System Supporting Intel Hyper-Threading Technology" + * Intel Hyper-Threading Technology has implications on the loading of the + * microcode update. The update must be loaded for each core in a physical + * processor. Thus, for a processor supporting Intel Hyper-Threading + * Technology, only one logical processor per core is required to load the + * microcode update. Each individual logical processor can independently + * load the update. However, MP initialization must provide some mechanism + * (e.g. a software semaphore) to force serialization of microcode update + * loads and to prevent simultaneous load attempts to the same core. + */ + if (!intel_ht_sibling()) { + const void *microcode_patch = intel_mp_current_microcode(); + intel_microcode_load_unlocked(microcode_patch); + } - /* Lock the SGX feature */ + /* Lock the SGX feature on all threads. */ lock_sgx(); /* Activate the SGX feature, if PRMRR config was approved by MCHECK */ @@ -234,9 +252,9 @@ void sgx_fill_gnvs(global_nvs_t *gnvs) { struct cpuid_result cpuid_regs; - if (!soc_sgx_enabled() || !is_sgx_supported()) { + if (!is_sgx_supported()) { printk(BIOS_DEBUG, - "SGX: not enabled or not supported. skip gnvs fill\n"); + "SGX: not supported. skip gnvs fill\n"); return; } diff --git a/src/soc/intel/common/block/systemagent/Makefile.inc b/src/soc/intel/common/block/systemagent/Makefile.inc index 0c29636a94..7e49ec7291 100644 --- a/src/soc/intel/common/block/systemagent/Makefile.inc +++ b/src/soc/intel/common/block/systemagent/Makefile.inc @@ -3,3 +3,6 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent_early.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent_early.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent_early.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c new file mode 100644 index 0000000000..ea22aa6d18 --- /dev/null +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +void smm_region(uintptr_t *start, size_t *size) +{ + *start = sa_get_tseg_base(); + *size = sa_get_tseg_size(); +} + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + + /* + * We need to make sure ramstage will be run cached. At this + * point exact location of ramstage in cbmem is not known. + * Instruct postcar to cache 16 megs under cbmem top which is + * a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); + top_of_ram -= 16*MiB; + postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); +} diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 0312cac94e..e03942fb30 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -46,11 +46,6 @@ __weak int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, return -1; } -__weak size_t soc_reserved_mmio_size(void) -{ - return 0; -} - __weak unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current, struct acpi_rsdp *rsdp) @@ -125,8 +120,7 @@ static void sa_get_mem_map(struct device *dev, uint64_t *values) * These are the host memory ranges that should be added: * - 0 -> 0xa0000: cacheable * - 0xc0000 -> top_of_ram : cacheable - * - top_of_ram -> TSEG - DPR: uncacheable - * - TESG - DPR -> BGSM: cacheable with standard MTRRs and reserved + * - top_of_ram -> BGSM: cacheable with standard MTRRs and reserved * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved * - 4GiB -> TOUUD: cacheable * @@ -155,18 +149,11 @@ static void sa_get_mem_map(struct device *dev, uint64_t *values) static void sa_add_dram_resources(struct device *dev, int *resource_count) { uintptr_t base_k, touud_k; - size_t dpr_size = 0, size_k; - size_t reserved_mmio_size; + size_t size_k; uint64_t sa_map_values[MAX_MAP_ENTRIES]; uintptr_t top_of_ram; int index = *resource_count; - if (CONFIG(SA_ENABLE_DPR)) - dpr_size = sa_get_dpr_size(); - - /* Get SoC reserve memory size as per user selection */ - reserved_mmio_size = soc_reserved_mmio_size(); - top_of_ram = (uintptr_t)cbmem_top(); /* 0 - > 0xa0000 */ @@ -181,14 +168,8 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count) sa_get_mem_map(dev, &sa_map_values[0]); - /* top_of_ram -> TSEG - DPR - Intel Reserve Memory Size*/ + /* top_of_ram -> BGSM */ base_k = top_of_ram; - size_k = sa_map_values[SA_TSEG_REG] - dpr_size - base_k - - reserved_mmio_size; - mmio_resource(dev, index++, base_k / KiB, size_k / KiB); - - /* TSEG - DPR - Intel Reserve Memory Size -> BGSM */ - base_k = sa_map_values[SA_TSEG_REG] - dpr_size - reserved_mmio_size; size_k = sa_map_values[SA_BGSM_REG] - base_k; reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB); diff --git a/src/soc/intel/common/block/timer/timer.c b/src/soc/intel/common/block/timer/timer.c index 70072cc850..94e2e65683 100644 --- a/src/soc/intel/common/block/timer/timer.c +++ b/src/soc/intel/common/block/timer/timer.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include @@ -31,11 +30,6 @@ static int get_processor_model(void) return c.x86_model; } -static unsigned int get_max_cpuid_func(void) -{ - return cpuid_eax(0); -} - static unsigned long get_hardcoded_crystal_freq(void) { unsigned long core_crystal_nominal_freq_khz = 0; @@ -73,7 +67,7 @@ static unsigned long calculate_tsc_freq_from_core_crystal(void) unsigned long core_crystal_nominal_freq_khz; struct cpuid_result cpuidr_15h; - if (get_max_cpuid_func() < 0x15) + if (cpuid_get_max_func() < 0x15) return 0; /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ @@ -104,7 +98,7 @@ static unsigned long calculate_tsc_freq_from_core_crystal(void) */ static unsigned long get_freq_from_cpuid16h(void) { - if (get_max_cpuid_func() < 0x16) + if (cpuid_get_max_func() < 0x16) return 0; return cpuid_eax(0x16); diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index c5c5e6c6d6..293fd36464 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -113,7 +113,7 @@ static struct device_operations usb_xhci_ops = { .enable_resources = pci_dev_enable_resources, .init = soc_xhci_init, .ops_pci = &pci_dev_ops_pci, - .scan_bus = scan_usb_bus, + .scan_bus = scan_static_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = soc_acpi_name, #endif diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index 7ece95497c..993593da2b 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -19,7 +19,6 @@ config PCH_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_DSP - select SOC_INTEL_COMMON_BLOCK_EBDA select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 2aadcae584..cb3713d3b0 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -50,7 +50,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_PCR - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC diff --git a/src/soc/intel/denverton_ns/acpi/lpc.asl b/src/soc/intel/denverton_ns/acpi/lpc.asl index cc36451de2..4b6e78698c 100644 --- a/src/soc/intel/denverton_ns/acpi/lpc.asl +++ b/src/soc/intel/denverton_ns/acpi/lpc.asl @@ -16,10 +16,11 @@ */ // Intel LPC Bus Device - 0:1f.0 +#include -Device (LPCB) +Scope (\_SB.PCI0.LPCB) { - Name(_ADR, 0x001f0000) + #include "irqlinks.asl" OperationRegion(LPC0, PCI_Config, 0x00, 0x100) Field (LPC0, AnyAcc, NoLock, Preserve) @@ -29,8 +30,6 @@ Device (LPCB) IOD1, 8, } - #include "irqlinks.asl" - Device(APIC) // IO APIC { Name(_HID,EISAID("PNP0003")) @@ -40,96 +39,6 @@ Device (LPCB) }) } - Device (HPET) - { - Name (_HID, EISAID("PNP0103")) - Name (_CID, 0x010CD041) - - Method (_STA, 0) // Device Status - { - Return (0xF) // Enable and show device - } - - Name(_CRS, ResourceTemplate() - { - Memory32Fixed(ReadOnly, DEFAULT_HPET_ADDR, 0x400) - }) - } - - Device(PIC) // 8259 Interrupt Controller - { - Name(_HID,EISAID("PNP0000")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x20, 0x20, 0x01, 0x02) - IO (Decode16, 0x24, 0x24, 0x01, 0x02) - IO (Decode16, 0x28, 0x28, 0x01, 0x02) - IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) - IO (Decode16, 0x30, 0x30, 0x01, 0x02) - IO (Decode16, 0x34, 0x34, 0x01, 0x02) - IO (Decode16, 0x38, 0x38, 0x01, 0x02) - IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) - IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) - IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) - IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) - IO (Decode16, 0xac, 0xac, 0x01, 0x02) - IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) - IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) - IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) - IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) - IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) - IRQNoFlags () { 2 } - }) - } - - Device(LDRC) // LPC device: Resource consumption - { - Name (_HID, EISAID("PNP0C02")) - Name (_UID, 2) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO - IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x70, 0x70, 0x1, 0x01) // NMI Enable. - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - //IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap - - // BIOS ROM shadow memory range - Memory32Fixed(ReadOnly, 0x000E0000, 0x20000) - - // BIOS flash 16MB - Memory32Fixed(ReadOnly,0xFF000000,0x1000000) - }) - } - - Device (RTC) // Real Time Clock - { - Name (_HID, EISAID("PNP0B00")) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } - }) - } - - Device (TIMR) // Intel 8254 timer - { - Name(_HID, EISAID("PNP0100")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags() {0} - }) - } - Device(IUR3) // Internal UART 1 { Name(_HID, EISAID("PNP0501")) diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl index f212557a56..58d63c26cf 100644 --- a/src/soc/intel/denverton_ns/acpi/northcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl @@ -20,7 +20,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Device (MCHC) diff --git a/src/soc/intel/denverton_ns/acpi/sleepstates.asl b/src/soc/intel/denverton_ns/acpi/sleepstates.asl deleted file mode 100644 index 7da84135c2..0000000000 --- a/src/soc/intel/denverton_ns/acpi/sleepstates.asl +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 - 2009 coresystems GmbH - * Copyright (C) 2014 - 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -//Name(\_S1, Package(){0x1,0x1,0x0,0x0}) -Name(\_S3, Package(){0x5,0x5,0x0,0x0}) -Name(\_S4, Package(){0x6,0x6,0x0,0x0}) -Name(\_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index 5de58eac67..5ab77e0221 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -21,7 +21,6 @@ #include #include -void acpi_create_intel_hpet(acpi_hpet_t *hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index 8bcef91c2e..c512d55fd0 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -31,6 +31,8 @@ #define ACPI_BASE_ADDRESS DEFAULT_PMBASE #define DEFAULT_TCO_BASE 0x400 +#define HPET_BASE_ADDRESS 0xfed00000 + /* Southbridge internal device MEM BARs (Set to match FSP settings) */ #define DEFAULT_PCR_BASE 0xfd000000 #define DEFAULT_PWRM_BASE 0xfe000000 diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 5af0781422..123fb24cda 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -317,7 +317,7 @@ static struct device_operations device_ops = { .enable_resources = lpc_enable_resources, .init = lpc_init, .enable = southcluster_enable_dev, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index 9f788ddb41..b4761dbeef 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -60,7 +60,7 @@ u32 top_of_32bit_ram(void) power_of_2(iqat_region_size + tseg_region_size); } -void *cbmem_top(void) { return (void *)top_of_32bit_ram(); } +void *cbmem_top_chipset(void) { return (void *)top_of_32bit_ram(); } static inline uintptr_t smm_region_start(void) { diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 072df295a5..5a8bec995b 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS select SMP select SPI_FLASH select SSE2 - select TSC_CONSTANT_RATE select TSC_SYNC_MFENCE select UDELAY_TSC select TSC_MONOTONIC_TIMER @@ -44,6 +43,7 @@ config CPU_SPECIFIC_OPTIONS select MICROCODE_BLOB_NOT_HOOKED_UP select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT + select DRIVERS_I2C_DESIGNWARE # Microcode header files are delivered in FSP package select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN @@ -103,6 +103,14 @@ config CPU_MICROCODE_HEADER_FILES string default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h" +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 + +config SOC_INTEL_I2C_DEV_MAX + int + default 7 + ## Baytrail Specific FSP Kconfig source src/soc/intel/fsp_baytrail/fsp/Kconfig diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index fa719320ee..0d89832f7d 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -3,7 +3,7 @@ # # Copyright (C) 2010 Google Inc. # Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -# Copyright (C) 2016 Siemens AG +# Copyright (C) 2016-2019 Siemens AG # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -34,6 +34,7 @@ romstage-y += memmap.c romstage-y += pmutil.c romstage-y += spi.c romstage-y += tsc_freq.c +romstage-y += i2c.c postcar-y += tsc_freq.c diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index fb941ab24b..5efa82f3b7 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -128,37 +128,6 @@ static int acpi_sci_irq(void) return sci_irq; } -void acpi_create_intel_hpet(acpi_hpet_t * hpet) -{ - acpi_header_t *header = &(hpet->header); - acpi_addr_t *addr = &(hpet->addr); - - memset((void *) hpet, 0, sizeof(acpi_hpet_t)); - - /* fill out header fields */ - memcpy(header->signature, "HPET", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_hpet_t); - header->revision = get_acpi_table_revision(HPET); - - /* fill out HPET address */ - addr->space_id = 0; /* Memory */ - addr->bit_width = 64; - addr->bit_offset = 0; - addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; - addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; - - hpet->id = 0x8086a201; /* Intel */ - hpet->number = 0x00; - hpet->min_tick = 0x0080; - - header->checksum = - acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, @@ -175,7 +144,7 @@ typedef struct soc_intel_fsp_baytrail_config config_t; void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - struct device *lpcdev = pcidev_path_on_root(FADT_SOC_LPC_DEVFN); + struct device *lpcdev = pcidev_path_on_root(PCH_DEVFN_LPC); u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; config_t *config = config_of(lpcdev); diff --git a/src/soc/intel/fsp_baytrail/acpi/lpc.asl b/src/soc/intel/fsp_baytrail/acpi/lpc.asl index 00aac51e23..7cdf1aa5d0 100644 --- a/src/soc/intel/fsp_baytrail/acpi/lpc.asl +++ b/src/soc/intel/fsp_baytrail/acpi/lpc.asl @@ -59,7 +59,7 @@ Device (LPCB) Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400) }) } diff --git a/src/soc/intel/fsp_baytrail/acpi/platform.asl b/src/soc/intel/fsp_baytrail/acpi/platform.asl index 270464e6bd..01be3514fd 100644 --- a/src/soc/intel/fsp_baytrail/acpi/platform.asl +++ b/src/soc/intel/fsp_baytrail/acpi/platform.asl @@ -14,43 +14,7 @@ * GNU General Public License for more details. */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} +#include /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl deleted file mode 100644 index 8e47f5c7a0..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -// Name(\_S1, Package(){0x1,0x1,0x0,0x0}) -#if CONFIG(HAVE_ACPI_RESUME) -Name(\_S3, Package(){0x5,0x5,0x0,0x0}) -#endif -Name(\_S4, Package(){0x6,0x6,0x0,0x0}) -Name(\_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl index a38b7425be..ef4523b004 100644 --- a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl +++ b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl @@ -48,7 +48,6 @@ Scope(\) Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Name (MCRS, ResourceTemplate() diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h index b73aa14904..e3167885b2 100644 --- a/src/soc/intel/fsp_baytrail/chip.h +++ b/src/soc/intel/fsp_baytrail/chip.h @@ -20,6 +20,7 @@ #include #include +#include /* The devicetree parser expects chip.h to reside directly in the path * specified by the devicetree. */ @@ -346,6 +347,9 @@ struct soc_intel_fsp_baytrail_config { int lpe_codec_clk_freq; /* 19 or 25 are valid. */ int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */ + /* Structure for designware I2C controller */ + struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX]; + /* ***** ACPI configuration ***** */ /* Options for these are in src/arch/x86/include/arch/acpi.h */ uint8_t fadt_pm_profile; diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c0b0998d42..01c876d3b8 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -79,7 +79,7 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U DEVTREE_CONST config_t *config; printk(FSP_INFO_LEVEL, "Configure Default UPD Data\n"); - dev = pcidev_path_on_root(SOC_DEV_FUNC); + dev = pcidev_path_on_root(SOC_DEVFN_SOC); config = config_of(dev); /* Set up default verb tables - Just HDMI audio */ @@ -142,26 +142,26 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U continue; switch (dev->path.pci.devfn) { - UPD_DEVICE_CHECK(SDIO_DEV_FUNC, PcdEnableSdio, "Sdio:\t\t\t"); - UPD_DEVICE_CHECK(SD_DEV_FUNC, PcdEnableSdcard, "Sdcard:\t\t\t"); - UPD_DEVICE_CHECK(SIO_DMA1_DEV_FUNC, PcdEnableDma0, "SIO Dma 0:\t\t"); - UPD_DEVICE_CHECK(I2C1_DEV_FUNC, PcdEnableI2C0, "SIO I2C0:\t\t"); - UPD_DEVICE_CHECK(I2C2_DEV_FUNC, PcdEnableI2C1, "SIO I2C1:\t\t"); - UPD_DEVICE_CHECK(I2C3_DEV_FUNC, PcdEnableI2C2, "SIO I2C2:\t\t"); - UPD_DEVICE_CHECK(I2C4_DEV_FUNC, PcdEnableI2C3, "SIO I2C3:\t\t"); - UPD_DEVICE_CHECK(I2C5_DEV_FUNC, PcdEnableI2C4, "SIO I2C4:\t\t"); - UPD_DEVICE_CHECK(I2C6_DEV_FUNC, PcdEnableI2C5, "SIO I2C5:\t\t"); - UPD_DEVICE_CHECK(I2C7_DEV_FUNC, PcdEnableI2C6, "SIO I2C6:\t\t"); - UPD_DEVICE_CHECK(SIO_DMA2_DEV_FUNC, PcdEnableDma1, "SIO Dma1:\t\t"); - UPD_DEVICE_CHECK(PWM1_DEV_FUNC, PcdEnablePwm0, "Pwm0:\t\t\t"); - UPD_DEVICE_CHECK(PWM2_DEV_FUNC, PcdEnablePwm1, "Pwm1:\t\t\t"); - UPD_DEVICE_CHECK(HSUART1_DEV_FUNC, PcdEnableHsuart0, "Hsuart0:\t\t"); - UPD_DEVICE_CHECK(HSUART2_DEV_FUNC, PcdEnableHsuart1, "Hsuart1:\t\t"); - UPD_DEVICE_CHECK(SPI_DEV_FUNC, PcdEnableSpi, "Spi:\t\t\t"); - UPD_DEVICE_CHECK(SATA_DEV_FUNC, PcdEnableSata, "SATA:\t\t\t"); - UPD_DEVICE_CHECK(HDA_DEV_FUNC, PcdEnableAzalia, "Azalia:\t\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_SDIO, PcdEnableSdio, "Sdio:\t\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_SD, PcdEnableSdcard, "Sdcard:\t\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_SIO_DMA1, PcdEnableDma0, "SIO Dma 0:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_I2C1, PcdEnableI2C0, "SIO I2C0:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_I2C2, PcdEnableI2C1, "SIO I2C1:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_I2C3, PcdEnableI2C2, "SIO I2C2:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_I2C4, PcdEnableI2C3, "SIO I2C3:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_I2C5, PcdEnableI2C4, "SIO I2C4:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_I2C6, PcdEnableI2C5, "SIO I2C5:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_I2C7, PcdEnableI2C6, "SIO I2C6:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_SIO_DMA2, PcdEnableDma1, "SIO Dma1:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_PWM1, PcdEnablePwm0, "Pwm0:\t\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_PWM2, PcdEnablePwm1, "Pwm1:\t\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_HSUART1, PcdEnableHsuart0, "Hsuart0:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_HSUART2, PcdEnableHsuart1, "Hsuart1:\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_SPI, PcdEnableSpi, "Spi:\t\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_SATA, PcdEnableSata, "SATA:\t\t\t"); + UPD_DEVICE_CHECK(SOC_DEVFN_HDA, PcdEnableAzalia, "Azalia:\t\t\t"); - case MIPI_DEV_FUNC: /* Camera / Image Signal Processing */ + case SOC_DEVFN_MIPI: /* Camera / Image Signal Processing */ if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { UpdData->ISPEnable = dev->enabled; } else { @@ -174,24 +174,24 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U printk(FSP_INFO_LEVEL, "MIPI/ISP:\t\t%s\n", dev->enabled?"Enabled":"Disabled"); break; - case EMMC_DEV_FUNC: /* EMMC 4.1*/ + case SOC_DEVFN_EMMC: /* EMMC 4.1*/ if ((dev->enabled) && (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) UpdData->PcdeMMCBootMode = EMMC_4_1 - EMMC_DISABLED; break; - case MMC45_DEV_FUNC: /* MMC 4.5*/ + case SOC_DEVFN_MMC45: /* MMC 4.5*/ if ((dev->enabled) && (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) UpdData->PcdeMMCBootMode = EMMC_4_5 - EMMC_DISABLED; break; - case XHCI_DEV_FUNC: + case SOC_DEVFN_XHCI: UpdData->PcdEnableXhci = dev->enabled; break; - case EHCI_DEV_FUNC: + case SOC_DEVFN_EHCI: UpdData->PcdEnableXhci = !(dev->enabled); break; - case LPE_DEV_FUNC: + case SOC_DEVFN_LPE: if (dev->enabled) UpdData->PcdEnableLpe = config->LpeAcpiModeEnable; else diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c index 3ea91e3b5e..37ce2d0b21 100644 --- a/src/soc/intel/fsp_baytrail/i2c.c +++ b/src/soc/intel/fsp_baytrail/i2c.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Siemens AG + * Copyright (C) 2014-2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,258 +13,282 @@ * GNU General Public License for more details. */ -#include -#include +#include #include -#include -#include -#include -#include -#include +#include +#include +#include +#include +#include #include +#include +#include +#include +#include -/* Wait for the transmit FIFO till there is at least one slot empty. - * FIFO stall due to transmit abort will be checked and resolved - */ -static int wait_tx_fifo(char *base_adr) +#include "chip.h" + +/* Convert I2C bus number to PCI device and function */ +int dw_i2c_soc_bus_to_devfn(unsigned int bus) { - int i; - u32 as; - - as = read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff; - if (as) { - /* Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO */ - i = read32(base_adr + I2C_CLR_TX_ABRT); - return I2C_ERR_ABORT | as; - } - - /* Wait here for a free slot in TX-FIFO */ - i = I2C_TIMEOUT_US; - while (!(read32(base_adr + I2C_STATUS) & I2C_TFNF)) { - udelay(1); - if (!--i) - return I2C_ERR_TIMEOUT; - } - - return I2C_SUCCESS; + if (bus <= 6) + return PCI_DEVFN(SIO1_DEV, bus + 1); + else + return -1; } -/* Wait for the receive FIFO till there is at least one valid entry to read. - * FIFO stall due to transmit abort will be checked and resolved - */ -static int wait_rx_fifo(char *base_adr) +/* Convert PCI device and function to I2C bus number */ +int dw_i2c_soc_dev_to_bus(struct device *dev) { - int i; - u32 as; - - as = read32(base_adr + I2C_ABORT_SOURCE) & 0x1ffff; - if (as) { - /* Reading back I2C_CLR_TX_ABRT resets abort lock on TX FIFO */ - i = read32(base_adr + I2C_CLR_TX_ABRT); - return I2C_ERR_ABORT | as; - } - - /* Wait here for a received entry in RX-FIFO */ - i = I2C_TIMEOUT_US; - while (!(read32(base_adr + I2C_STATUS) & I2C_RFNE)) { - udelay(1); - if (!--i) - return I2C_ERR_TIMEOUT; - } - - return I2C_SUCCESS; + pci_devfn_t devfn = dev->path.pci.devfn; + if ((devfn >= SOC_DEVFN_I2C1) && (devfn <= SOC_DEVFN_I2C7)) + return PCI_FUNC(devfn) - 1; + else + return -1; } -/* When there will be a fast switch between send and receive, one have - * to wait until the first operation is completely finished - * before starting the second operation - */ -static int wait_for_idle(char *base_adr) +/* Getting I2C bus configuration from devicetree config */ +const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { - int i; - int status; + const struct soc_intel_fsp_baytrail_config *config; + const struct device *dev = pcidev_path_on_root(SOC_DEVFN_SOC); - /* For IDLE, increase timeout by ten times */ - i = I2C_TIMEOUT_US * 10; - status = read32(base_adr + I2C_STATUS); - while (((status & I2C_MST_ACTIVITY) || (!(status & I2C_TFE)))) { - status = read32(base_adr + I2C_STATUS); - udelay(1); - if (!--i) - return I2C_ERR_TIMEOUT; + if (dev && dev->chip_info) { + config = dev->chip_info; + return &config->i2c[bus]; } - return I2C_SUCCESS; + die("Could not find SA_DEV_ROOT devicetree config!\n"); } -/** \brief Enables I2C-controller, sets up BAR and timing parameters - * @param bus Number of the I2C-controller to use (0...6) - * @return I2C_SUCCESS on success, otherwise error code - */ -int i2c_init(unsigned bus) +#if !ENV_RAMSTAGE +static int lpss_i2c_early_init_bus(unsigned int bus) { - struct device *dev; - int base_adr[7] = {I2C0_MEM_BASE, I2C1_MEM_BASE, I2C2_MEM_BASE, - I2C3_MEM_BASE, I2C4_MEM_BASE, I2C5_MEM_BASE, - I2C6_MEM_BASE}; - char *base_ptr; + const struct dw_i2c_bus_config *config; + const struct device *tree_dev; + pci_devfn_t dev; + int devfn; + uintptr_t base; - /* Ensure the desired device is valid */ - if (bus >= ARRAY_SIZE(base_adr)) { - printk(BIOS_ERR, "I2C: Only I2C controllers 0...6 are available.\n"); - return I2C_ERR; + /* Find the PCI device for this bus controller */ + devfn = dw_i2c_soc_bus_to_devfn(bus); + if (devfn < 0) { + printk(BIOS_ERR, "I2C%u device not found\n", bus); + return -1; } - base_ptr = (char*)base_adr[bus]; - /* Set the I2C-device the user wants to use */ - dev = pcidev_on_root(I2C1_DEV, bus + 1); - - /* Ensure we have the right PCI device */ - if ((pci_read_config16(dev, 0x0) != I2C_PCI_VENDOR_ID) || - (pci_read_config16(dev, 0x2) != (I2C0_PCI_DEV_ID + bus))) { - printk(BIOS_ERR, "I2C: Controller %d not found!\n", bus); - return I2C_ERR; + /* Look up the controller device in the devicetree */ + dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + tree_dev = pcidev_path_on_root(devfn); + if (!tree_dev || !tree_dev->enabled) { + printk(BIOS_ERR, "I2C%u device not enabled\n", bus); + return -1; } - /* Set memory base */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, (int)base_ptr); + /* Skip if not enabled for early init */ + config = dw_i2c_get_soc_cfg(bus); + if (!config || !config->early_init) { + printk(BIOS_DEBUG, "I2C%u not enabled for early init\n", bus); + return -1; + } - /* Enable memory space */ + /* Prepare early base address for access before memory */ + base = EARLY_I2C_BASE(bus); + pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); pci_write_config32(dev, PCI_COMMAND, - (pci_read_config32(dev, PCI_COMMAND) | 0x2)); + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - /* Set up some settings of I2C controller */ - write32(base_ptr + I2C_CTRL, - I2C_RESTART_EN | (I2C_STANDARD_MODE << 1) | I2C_MASTER_ENABLE); - /* Adjust frequency for standard mode to 100 kHz */ - /* The counter value can be computed by N=100MHz/2/I2C_CLK */ - /* Thus, for 100 kHz I2C_CLK, N is 0x1F4 */ - write32(base_ptr + I2C_SS_SCL_HCNT, 0x1f4); - write32(base_ptr + I2C_SS_SCL_LCNT, 0x1f4); - /* For 400 kHz, the counter value is 0x7d */ - write32(base_ptr + I2C_FS_SCL_HCNT, 0x7d); - write32(base_ptr + I2C_FS_SCL_LCNT, 0x7d); - /* no interrupts in BIOS */ - write32(base_ptr + I2C_INTR_MASK, 0); + /* Take device out of reset */ + write32((void *)((uint32_t)base + I2C_SOFTWARE_RESET), I2C_RESET_APB | I2C_RESET_FUNC); - /* Enable the I2C controller for operation */ - write32(base_ptr + I2C_ENABLE, 0x1); + /* Initialize the controller */ + if (dw_i2c_init(bus, config) < 0) { + printk(BIOS_ERR, "I2C%u failed to initialize\n", bus); + return -1; + } - printk(BIOS_INFO, "I2C: Controller %d enabled.\n", bus); - return I2C_SUCCESS; + return 0; } -/** \brief Read bytes over I2C-Bus from a slave. This function tries only one - * time to transmit data. In case of an error (abort) error code is - * returned. Retransmission has to be done from caller! - * @param bus Number of the I2C-controller to use (0...6) - * @param chip 7 Bit of the slave address on I2C bus - * @param addr Address inside slave where to read from - * @param *buf Pointer to the buffer where to store read data - * @param len Number of bytes to read - * @return I2C_SUCCESS when read was successful, otherwise error code - */ -int i2c_read(unsigned bus, unsigned chip, unsigned addr, - uint8_t *buf, unsigned len) +uintptr_t dw_i2c_base_address(unsigned int bus) { - int i = 0; - char *base_ptr = NULL; - struct device *dev; - unsigned int val; - int stat; + int devfn; + pci_devfn_t dev; + uintptr_t base; - /* Get base address of desired I2C-controller */ - dev = pcidev_on_root(I2C1_DEV, bus + 1); - base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); - if (base_ptr == NULL) { - printk(BIOS_INFO, "I2C: Invalid Base address\n"); - return I2C_ERR_INVALID_ADR; - } + /* Find device+function for this controller */ + devfn = dw_i2c_soc_bus_to_devfn(bus); + if (devfn < 0) + return 0; - /* Ensure I2C controller is not active before setting slave address */ - stat = wait_for_idle(base_ptr); - if (stat != I2C_SUCCESS) - return stat; + /* Form a PCI address for this device */ + dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - /* clear any abort status from a previous transaction */ - read32(base_ptr + I2C_CLR_TX_ABRT); + /* Read the first base address for this device */ + base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & 0xfffffff0; - /* Now we can program the desired slave address and start transfer */ - write32(base_ptr + I2C_TARGET_ADR, chip & 0xff); - /* Send address inside slave to read from */ - write32(base_ptr + I2C_DATA_CMD, addr & 0xff); - - /* For the next byte we need a repeated start condition */ - val = I2C_RW_CMD | I2C_RESTART; - /* Now we can read desired amount of data over I2C */ - for (i = 0; i < len; i++) { - /* A read is initiated by writing dummy data to the DATA-register */ - write32(base_ptr + I2C_DATA_CMD, val); - stat = wait_rx_fifo(base_ptr); - if (stat) - return stat; - buf[i] = read32(base_ptr + I2C_DATA_CMD) & 0xff; - val = I2C_RW_CMD; - if (i == (len - 2)) { - /* For the last byte we need a stop condition to be generated */ - val |= I2C_STOP; - } - } - return I2C_SUCCESS; + /* Attempt to initialize bus if base is not set yet */ + if (!base && !lpss_i2c_early_init_bus(bus)) + base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & 0xfffffff0; + return base; } +#else -/** \brief Write bytes over I2C-Bus from a slave. This function tries only one - * time to transmit data. In case of an error (abort) error code is - * returned. Retransmission has to be done from caller! - * @param bus Number of the I2C-controller to use (0...6) - * @param chip 7 Bit of the slave address on I2C bus - * @param addr Address inside slave where to write to - * @param *buf Pointer to the buffer where data to write is stored - * @param len Number of bytes to write - * @return I2C_SUCCESS when read was successful, otherwise error code - */ -int i2c_write(unsigned bus, unsigned chip, unsigned addr, - const uint8_t *buf, unsigned len) +uintptr_t dw_i2c_base_address(unsigned int bus) { - int i; - char *base_ptr; + int devfn; struct device *dev; - unsigned int val; - int stat; + struct resource *bar = NULL; - /* Get base address of desired I2C-controller */ - dev = pcidev_on_root(I2C1_DEV, bus + 1); - base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); - if (base_ptr == NULL) { - return I2C_ERR_INVALID_ADR; + /* bus -> devfn */ + devfn = dw_i2c_soc_bus_to_devfn(bus); + + if (devfn < 0) + return (uintptr_t)NULL; + + /* devfn -> dev */ + dev = pcidev_path_on_root(devfn); + if (dev && dev->enabled) { + /* dev -> bar0 */ + bar = find_resource(dev, PCI_BASE_ADDRESS_0); } - /* Ensure I2C controller is not active yet */ - stat = wait_for_idle(base_ptr); - if (stat) { - return stat; - } - - /* clear any abort status from a previous transaction */ - read32(base_ptr + I2C_CLR_TX_ABRT); - - /* Program slave address to use for this transfer */ - write32(base_ptr + I2C_TARGET_ADR, chip & 0xff); - - /* Send address inside slave to write data to */ - write32(base_ptr + I2C_DATA_CMD, addr & 0xff); - - for (i = 0; i < len; i++) { - val = (unsigned int)(buf[i] & 0xff); /* Take only 8 bits */ - if (i == (len - 1)) { - /* For the last byte we need a stop condition */ - val |= I2C_STOP; - } - stat = wait_tx_fifo(base_ptr); - if (stat) { - return stat; - } - write32(base_ptr + I2C_DATA_CMD, val); - } - return I2C_SUCCESS; + if (bar) + return bar->base; + else + return (uintptr_t)NULL; } + +static void i2c_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) +{ + struct resource *bar; + global_nvs_t *gnvs; + uint32_t val; + + /* Find ACPI NVS to update BARs */ + gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_ERR, "Unable to locate Global NVS\n"); + return; + } + + /* Save BAR0 and BAR1 to ACPI NVS */ + bar = find_resource(dev, PCI_BASE_ADDRESS_0); + if (bar) + gnvs->dev.lpss_bar0[nvs_index] = (uint32_t)bar->base; + + bar = find_resource(dev, PCI_BASE_ADDRESS_1); + if (bar) + gnvs->dev.lpss_bar1[nvs_index] = (uint32_t)bar->base; + + /* Device is enabled in ACPI mode */ + gnvs->dev.lpss_en[nvs_index] = 1; + + /* Put device in ACPI mode */ + val = iosf_lpss_read(iosf_reg); + val |= (LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN); + iosf_lpss_write(iosf_reg, val); + val = pci_read_config32(dev, PCI_COMMAND); + val |= PCI_COMMAND_INT_DISABLE; + pci_write_config32(dev, PCI_COMMAND, val); +} + +static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg) +{ + uint32_t val; + + val = iosf_lpss_read(iosf_reg); + val &= ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP); + val |= (LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT); + iosf_lpss_write(iosf_reg, val); +} + +static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) +{ + int bus; + + bus = dw_i2c_soc_dev_to_bus(dev); + if (bus >= 0) { + *iosf_reg = LPSS_I2C1_CTL + (bus * 8); + *nvs_index = bus + 1; + } else { + + *iosf_reg = -1; + *nvs_index = -1; + } +} + +static void i2c_disable_resets(struct device *dev) +{ + uint32_t base; + + printk(BIOS_DEBUG, "Releasing I2C device from reset.\n"); + base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & 0xfffffff0; + write32((void *)(base + I2C_SOFTWARE_RESET), I2C_RESET_APB | I2C_RESET_FUNC); +} + +static void i2c_lpss_init(struct device *dev) +{ + struct soc_intel_fsp_baytrail_config *config = dev->chip_info; + int iosf_reg, nvs_index; + + dev_ctl_reg(dev, &iosf_reg, &nvs_index); + + if (iosf_reg < 0) { + int slot = PCI_SLOT(dev->path.pci.devfn); + int func = PCI_FUNC(dev->path.pci.devfn); + printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", + slot, func); + return; + } + dev_enable_snoop_and_pm(dev, iosf_reg); + i2c_disable_resets(dev); + + if (config && (config->PcdLpssSioEnablePciMode == LPSS_PCI_MODE_DISABLE)) + i2c_enable_acpi_mode(dev, iosf_reg, nvs_index); +} +/* + * This function ensures that the device is actually out of reset and + * it is ready for initialization sequence. + */ +static void dw_i2c_device_init(struct device *dev) +{ + int bus = dw_i2c_soc_dev_to_bus(dev); + + if (bus < 0) + return; + + if (!dw_i2c_base_address(bus)) + return; + i2c_lpss_init(dev); + dw_i2c_dev_init(dev); +} + +static struct device_operations i2c_dev_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = scan_smbus, + .ops_i2c_bus = &dw_i2c_bus_ops, + .ops_pci = &pci_dev_ops_pci, + .init = dw_i2c_device_init, + .acpi_fill_ssdt_generator = dw_i2c_acpi_fill_ssdt, +}; + +static const unsigned short pci_device_ids[] = { + I2C1_DEVID, + I2C2_DEVID, + I2C3_DEVID, + I2C4_DEVID, + I2C5_DEVID, + I2C6_DEVID, + I2C7_DEVID, + 0 +}; + +static const struct pci_driver pch_i2c __pci_driver = { + .ops = &i2c_dev_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; +#endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/acpi.h b/src/soc/intel/fsp_baytrail/include/soc/acpi.h index 27b700096f..917419e4df 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/acpi.h +++ b/src/soc/intel/fsp_baytrail/include/soc/acpi.h @@ -21,7 +21,6 @@ #include #include -void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); unsigned long acpi_madt_irq_overrides(unsigned long current); diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h index 3a2fcaa635..de902aac6f 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h +++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h @@ -47,8 +47,6 @@ #ifndef __ASSEMBLER__ #include -static inline void barrier(void) { asm("" ::: "memory"); } - int bridge_silicon_revision(void); void rangeley_early_initialization(void); void set_max_freq(void); diff --git a/src/soc/intel/fsp_baytrail/include/soc/i2c.h b/src/soc/intel/fsp_baytrail/include/soc/i2c.h index f0ae0b37ad..3a4ff2c32b 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/i2c.h +++ b/src/soc/intel/fsp_baytrail/include/soc/i2c.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Siemens AG + * Copyright (C) 2014-2019 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,116 +16,8 @@ #ifndef __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ #define __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ -#include -#include - -/* SMBus controller settings in PCI configuration space */ -#define I2C_PCI_VENDOR_ID 0x8086 -#define I2C0_PCI_DEV_ID 0x0f41 -#define I2C1_PCI_DEV_ID 0x0f42 -#define I2C2_PCI_DEV_ID 0x0f43 -#define I2C3_PCI_DEV_ID 0x0f44 -#define I2C4_PCI_DEV_ID 0x0f45 -#define I2C5_PCI_DEV_ID 0x0f46 -#define I2C6_PCI_DEV_ID 0x0f47 - -#define I2C0_MEM_BASE 0xd0921000 -#define I2C1_MEM_BASE 0xd0923000 -#define I2C2_MEM_BASE 0xd0925000 -#define I2C3_MEM_BASE 0xd0927000 -#define I2C4_MEM_BASE 0xd0929000 -#define I2C5_MEM_BASE 0xd092b000 -#define I2C6_MEM_BASE 0xd092d000 - -#define I2C_STANDARD_MODE 0x1 -#define I2C_FAST_MODE 0x2 - -/* Define relevant registers in PCI space */ -#define I2C_PCI_COMMAND 0x4 -#define I2C_PCI_STATUS 0x6 - -/* Define memory mapped registers */ -#define I2C_CTRL 0x0 -#define I2C_SLAVE_DISABLE 0x40 -#define I2C_RESTART_EN 0x20 -#define I2C_ADR_MODE 0x10 -#define I2C_SPEED_MASK 0x6 -#define I2C_STD_MODE 0x1 -#define I2C_FAST_MODE 0x2 -#define I2C_MASTER_ENABLE 0x1 - -#define I2C_TARGET_ADR 0x4 -#define I2C_TARGET_ADR_MASK 0x3ff - -#define I2C_DATA_CMD 0x10 -#define I2C_RESTART 0x400 -#define I2C_STOP 0x200 -#define I2C_RW_CMD 0x100 - -#define I2C_SS_SCL_HCNT 0x14 /* Counter for high period for 100 kHz SCL */ -#define I2C_SS_SCL_LCNT 0x18 /* Counter for low period for 100 kHz SCL */ -#define I2C_FS_SCL_HCNT 0x1c /* Counter for high period for 400 kHz SCL */ -#define I2C_FS_SCL_LCNT 0x20 /* Counter for low period for 400 kHz SCL */ - -#define I2C_INTR_STAT 0x2c /* Interrupt status register, read only */ -#define I2C_INTR_MASK 0x30 /* Interrupt mask register */ -#define I2C_RAW_INTR_STAT 0x34 /* Raw interrupt status, read only */ -#define I2C_START_DETECT 0x400 -#define I2C_STOP_DETECT 0x200 -#define I2C_ACTIVITY 0x100 -#define I2C_TX_ABORT 0x40 -#define I2C_RD_REQ 0x20 /* Read request in slave mode */ -#define I2C_TX_EMPTY 0x10 -#define I2C_TX_OVERFLOW 0x8 -#define I2C_RX_FULL 0x4 -#define I2C_RX_OVERFLOW 0x2 -#define I2C_RX_UNDERFLOW 0x1 - -#define I2C_RX_TL 0x38 /* Rx FIFO threshold level 0..255 */ -#define I2C_TX_TL 0x3c /* Tx FIFO threshold level 0..255 */ -#define I2C_CLR_INTR 0x40 /* Clear all events with a read */ -#define I2C_CLR_TX_ABRT 0x54 /* Clear TX-Abort event with a read */ - -/* There are a bunch of interrupt clearing registers now which are not used! */ -/* So proceed somewhat later with definition */ -#define I2C_ENABLE 0x6c /* 0: disable I2C controller, 1: enable */ -#define I2C_STATUS 0x70 -#define I2C_MST_ACTIVITY 0x20 /* Master FSM activity */ -#define I2C_RFF 0x10 /* Receive FIFO completely full */ -#define I2C_RFNE 0x8 /* Receive FIFO not empty */ -#define I2C_TFE 0x4 /* Transmit FIFO completely empty */ -#define I2C_TFNF 0x2 /* Transmit FIFO not full */ -#define I2C_ACTIVE 0x1 /* 1: I2C currently in operation */ - -#define I2C_TXFLR 0x74 /* Current transmit FIFO level */ -#define I2C_RXFLR 0x78 /* Current receive FIFO level */ -#define I2C_SDA_HOLD 0x7c /* Data hold time after SCL goes low */ -#define I2C_ABORT_SOURCE 0x80 -#define I2C_ARB_LOST 0x1000 /* Arbitration lost */ -#define I2C_MASTER_DIS 0x800 /* Master was disabled by user */ -#define I2C_10B_RD_NORSTRT 0x400 /* 10 bit address read and RESTART disabled */ -#define I2C_SBYTE_NORSTRT 0x200 /* START with RESTART disabled */ -#define I2C_START_ACKDET 0x80 /* START byte was acknowledged */ -#define I2C_TX_DATA_NOACK 0x8 /* TX data not acknowledged */ -#define I2C_10B_ADR2_NOACK 0x4 /* Second address byte in 10 bit mode NACK */ -#define I2C_10B_ADR1_NOACK 0x2 /* First address byte in 10 bit NACK */ -#define I2C_7B_ADDR_NACK 0x1 /* 7 bit address byte not acknowledged */ - -#define I2C_ENABLE_STATUS 0x9c - -/* Define some status and error values */ -#define I2C_ERR_INVALID_ADR 0x1000000 -#define I2C_ERR_TIMEOUT 0x2000000 -#define I2C_ERR_ABORT 0x4000000 -#define I2C_ERR 0x8000000 -#define I2C_SUCCESS 0x0000000 - - -#define I2C_TIMEOUT_US 2000 /* Use 2000 us as time */ - -/* Prototype section*/ -int i2c_init(unsigned bus); -int i2c_read(unsigned bus, unsigned chip, unsigned addr, uint8_t *buf, unsigned len); -int i2c_write(unsigned bus, unsigned chip, unsigned addr, const uint8_t *buf, unsigned len); +#define I2C_SOFTWARE_RESET 0x804 +#define I2C_RESET_APB (1 << 1) +#define I2C_RESET_FUNC (1 << 0) #endif /* __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/iomap.h b/src/soc/intel/fsp_baytrail/include/soc/iomap.h index 11c01e311d..d54d3fcc29 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/iomap.h +++ b/src/soc/intel/fsp_baytrail/include/soc/iomap.h @@ -65,6 +65,8 @@ /* Temporary Base Address */ #define TEMP_BASE_ADDRESS 0xfd000000 +#define EARLY_I2C_BASE_ADDRESS 0xfe020000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) /* * IO Port bases. diff --git a/src/soc/intel/fsp_baytrail/include/soc/lpc.h b/src/soc/intel/fsp_baytrail/include/soc/lpc.h index 5abe719e44..defd34a2f5 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/lpc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/lpc.h @@ -17,8 +17,6 @@ #ifndef _BAYTRAIL_LPC_H_ #define _BAYTRAIL_LPC_H_ -#define FADT_SOC_LPC_DEVFN PCI_DEVFN(0x1f, 0) - /* PCI config registers in LPC bridge. */ #define REVID 0x08 #define ABASE 0x40 /* IO BAR */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h index b8fe7fe7ce..8edab59bdf 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/msr.h +++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h @@ -29,6 +29,6 @@ #define MSR_IACORE_TURBO_VIDS 0x66d /* Read BCLK from MSR */ -unsigned bus_freq_khz(void); +unsigned int bus_freq_khz(void); #endif /* _BAYTRAIL_MSR_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pattrs.h b/src/soc/intel/fsp_baytrail/include/soc/pattrs.h index 7d10cea2cb..7b46345a47 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pattrs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pattrs.h @@ -42,7 +42,7 @@ struct pattrs { const void *microcode_patch; int address_bits; int num_cpus; - unsigned bclk_khz; + unsigned int bclk_khz; }; /* This is just to hide the abstraction w/o relying on how the underlying diff --git a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h index a920194a8a..5e5b8071df 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h @@ -26,40 +26,39 @@ /* SoC transaction router */ #define SOC_DEV 0x0 #define SOC_FUNC 0 -# define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC) +# define SOC_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC) /* Graphics and Display */ #define GFX_DEV 0x2 #define GFX_FUNC 0 -# define GFX_DEV_FUNC PCI_DEVFN(GFX_DEV,GFX_FUNC) +# define SOC_DEVFN_GFX PCI_DEVFN(GFX_DEV,GFX_FUNC) /* MIPI */ #define MIPI_DEV 0x3 #define MIPI_FUNC 0 -# define MIPI_DEV_FUNC PCI_DEVFN(MIPI_DEV,MIPI_FUNC) +# define SOC_DEVFN_MIPI PCI_DEVFN(MIPI_DEV,MIPI_FUNC) /* SDIO Port */ #define EMMC_DEV 0x10 #define EMMC_FUNC 0 -# define EMMC_DEV_FUNC PCI_DEVFN(EMMC_DEV,EMMC_FUNC) +# define SOC_DEVFN_EMMC PCI_DEVFN(EMMC_DEV,EMMC_FUNC) /* SDIO Port */ #define SDIO_DEV 0x11 #define SDIO_FUNC 0 -# define SDIO_DEV_FUNC PCI_DEVFN(SDIO_DEV,SDIO_FUNC) +# define SOC_DEVFN_SDIO PCI_DEVFN(SDIO_DEV,SDIO_FUNC) /* SD Port */ #define SD_DEV 0x12 #define SD_FUNC 0 -# define SD_DEV_FUNC PCI_DEVFN(SD_DEV,SD_FUNC) +# define SOC_DEVFN_SD PCI_DEVFN(SD_DEV,SD_FUNC) /* SATA */ #define SATA_DEV 0x13 #define SATA_FUNC 0 -# define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV,SATA_FUNC) - +# define SOC_DEVFN_SATA PCI_DEVFN(SATA_DEV,SATA_FUNC) /* xHCI */ #define XHCI_DEV 0x14 @@ -67,22 +66,22 @@ # define XHCI_FUS_REG 0xE0 # define XHCI_FUNC_DISABLE (1 << 0) # define XHCI_USB2PR_REG 0xD0 -# define XHCI_DEV_FUNC PCI_DEVFN(XHCI_DEV,XHCI_FUNC) +# define SOC_DEVFN_XHCI PCI_DEVFN(XHCI_DEV,XHCI_FUNC) /* LPE Audio */ #define LPE_DEV 0x15 #define LPE_FUNC 0 -# define LPE_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC) +# define SOC_DEVFN_LPE PCI_DEVFN(LPE_DEV,LPE_FUNC) /* OTG */ #define OTG_DEV 0x16 #define OTG_FUNC 0 -# define OTG_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC) +# define SOC_DEVFN_OTG PCI_DEVFN(LPE_DEV,LPE_FUNC) /* MMC Port */ #define MMC45_DEV 0x17 #define MMC45_FUNC 0 -# define MMC45_DEV_FUNC PCI_DEVFN(MMC45_DEV,MMC45_FUNC) +# define SOC_DEVFN_MMC45 PCI_DEVFN(MMC45_DEV,MMC45_FUNC) /* Serial IO 1 */ #define SIO1_DEV 0x18 @@ -102,24 +101,26 @@ # define I2C6_FUNC 6 # define I2C7_DEV SIO1_DEV # define I2C7_FUNC 7 -# define SIO_DMA1_DEV_FUNC PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC) -# define I2C1_DEV_FUNC PCI_DEVFN(I2C1_DEV,I2C1_FUNC) -# define I2C2_DEV_FUNC PCI_DEVFN(I2C2_DEV,I2C2_FUNC) -# define I2C3_DEV_FUNC PCI_DEVFN(I2C3_DEV,I2C3_FUNC) -# define I2C4_DEV_FUNC PCI_DEVFN(I2C4_DEV,I2C4_FUNC) -# define I2C5_DEV_FUNC PCI_DEVFN(I2C5_DEV,I2C5_FUNC) -# define I2C6_DEV_FUNC PCI_DEVFN(I2C6_DEV,I2C6_FUNC) -# define I2C7_DEV_FUNC PCI_DEVFN(I2C7_DEV,I2C7_FUNC) +# define SOC_DEVFN_SIO_DMA1 PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC) +# define SOC_DEVFN_I2C1 PCI_DEVFN(I2C1_DEV,I2C1_FUNC) +# define SOC_DEVFN_I2C2 PCI_DEVFN(I2C2_DEV,I2C2_FUNC) +# define SOC_DEVFN_I2C3 PCI_DEVFN(I2C3_DEV,I2C3_FUNC) +# define SOC_DEVFN_I2C4 PCI_DEVFN(I2C4_DEV,I2C4_FUNC) +# define SOC_DEVFN_I2C5 PCI_DEVFN(I2C5_DEV,I2C5_FUNC) +# define SOC_DEVFN_I2C6 PCI_DEVFN(I2C6_DEV,I2C6_FUNC) +# define SOC_DEVFN_I2C7 PCI_DEVFN(I2C7_DEV,I2C7_FUNC) + +#define PCH_DEV_SLOT_I2C1 I2C1_DEV /* Trusted Execution Engine */ #define TXE_DEV 0x1a #define TXE_FUNC 0 -# define TXE_DEV_FUNC PCI_DEVFN(TXE_DEV,TXE_FUNC) +# define SOC_DEVFN_TXE PCI_DEVFN(TXE_DEV,TXE_FUNC) /* HD Audio */ #define HDA_DEV 0x1b #define HDA_FUNC 0 -# define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV,HDA_FUNC) +# define SOC_DEVFN_HDA PCI_DEVFN(HDA_DEV,HDA_FUNC) /* PCIe Ports */ #define PCIE_DEV 0x1c @@ -131,15 +132,15 @@ # define PCIE_PORT3_FUNC 2 # define PCIE_PORT4_DEV PCIE_DEV # define PCIE_PORT4_FUNC 3 -# define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) -# define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC) -# define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC) -# define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC) +# define SOC_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) +# define SOC_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC) +# define SOC_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC) +# define SOC_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC) /* EHCI */ #define EHCI_DEV 0x1d #define EHCI_FUNC 0 -# define EHCI_DEV_FUNC PCI_DEVFN(EHCI_DEV,EHCI_FUNC) +# define SOC_DEVFN_EHCI PCI_DEVFN(EHCI_DEV,EHCI_FUNC) /* Serial IO 2 */ #define SIO2_DEV 0x1e @@ -155,23 +156,24 @@ # define HSUART2_FUNC 4 # define SPI_DEV SIO2_DEV # define SPI_FUNC 5 -# define SIO_DMA2_DEV_FUNC PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC) -# define PWM1_DEV_FUNC PCI_DEVFN(PWM1_DEV,PWM1_FUNC) -# define PWM2_DEV_FUNC PCI_DEVFN(PWM2_DEV,PWM2_FUNC) -# define HSUART1_DEV_FUNC PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC) -# define HSUART2_DEV_FUNC PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC) -# define SPI_DEV_FUNC PCI_DEVFN(SPI_DEV,SPI_FUNC) +# define SOC_DEVFN_SIO_DMA2 PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC) +# define SOC_DEVFN_PWM1 PCI_DEVFN(PWM1_DEV,PWM1_FUNC) +# define SOC_DEVFN_PWM2 PCI_DEVFN(PWM2_DEV,PWM2_FUNC) +# define SOC_DEVFN_HSUART1 PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC) +# define SOC_DEVFN_HSUART2 PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC) +# define SOC_DEVFN_SPI PCI_DEVFN(SPI_DEV,SPI_FUNC) /* Platform Controller Unit */ #define PCU_DEV 0x1f # define LPC_DEV PCU_DEV # define LPC_FUNC 0 +# define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC) +# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC) + # define SMBUS_DEV PCU_DEV # define SMBUS_FUNC 3 -# define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC) -# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC) -# define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) +# define SOC_DEVFN_SMBUS PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) #define SOC_DEVID 0x0f00 #define GFX_DEVID 0x0f31 diff --git a/src/soc/intel/fsp_baytrail/lpe.c b/src/soc/intel/fsp_baytrail/lpe.c index 8baba3e295..91f8880a18 100644 --- a/src/soc/intel/fsp_baytrail/lpe.c +++ b/src/soc/intel/fsp_baytrail/lpe.c @@ -42,7 +42,7 @@ #define FIRMWARE_REG_BASE_C0 0x144000 #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) -static void assign_device_nvs(struct device *dev, u32 *field, unsigned index) +static void assign_device_nvs(struct device *dev, u32 *field, unsigned int index) { struct resource *res; diff --git a/src/soc/intel/fsp_baytrail/lpss.c b/src/soc/intel/fsp_baytrail/lpss.c index 154a70ad19..2ad6fb3804 100644 --- a/src/soc/intel/fsp_baytrail/lpss.c +++ b/src/soc/intel/fsp_baytrail/lpss.c @@ -89,20 +89,6 @@ static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) switch (dev->path.pci.devfn) { SET_IOSF_REG(SIO_DMA1); break; - SET_IOSF_REG(I2C1); - break; - SET_IOSF_REG(I2C2); - break; - SET_IOSF_REG(I2C3); - break; - SET_IOSF_REG(I2C4); - break; - SET_IOSF_REG(I2C5); - break; - SET_IOSF_REG(I2C6); - break; - SET_IOSF_REG(I2C7); - break; SET_IOSF_REG(SIO_DMA2); break; SET_IOSF_REG(PWM1); @@ -118,33 +104,6 @@ static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) } } -static void i2c_disable_resets(struct device *dev) -{ - /* Release the I2C devices from reset. */ - static const struct reg_script ops[] = { - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x804, 0x3), - REG_SCRIPT_END, - }; - -#define CASE_I2C(name_) \ - case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) - - switch (dev->path.pci.devfn) { - CASE_I2C(I2C1): - CASE_I2C(I2C2): - CASE_I2C(I2C3): - CASE_I2C(I2C4): - CASE_I2C(I2C5): - CASE_I2C(I2C6): - CASE_I2C(I2C7): - printk(BIOS_DEBUG, "Releasing I2C device from reset.\n"); - reg_script_run_on_dev(dev, ops); - break; - default: - return; - } -} - static void lpss_init(struct device *dev) { struct soc_intel_fsp_baytrail_config *config = config_of(dev); @@ -160,7 +119,6 @@ static void lpss_init(struct device *dev) return; } dev_enable_snoop_and_pm(dev, iosf_reg); - i2c_disable_resets(dev); if (config->PcdLpssSioEnablePciMode == LPSS_PCI_MODE_DISABLE) dev_enable_acpi_mode(dev, iosf_reg, nvs_index); @@ -178,13 +136,6 @@ static struct device_operations device_ops = { static const unsigned short pci_device_ids[] = { SIO_DMA1_DEVID, - I2C1_DEVID, - I2C2_DEVID, - I2C3_DEVID, - I2C4_DEVID, - I2C5_DEVID, - I2C6_DEVID, - I2C7_DEVID, SIO_DMA2_DEVID, PWM1_DEVID, PWM2_DEVID, diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 7fec7f9764..d8dcf49acb 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -40,7 +40,7 @@ static size_t smm_region_size(void) * @return pointer to the first byte of reserved memory */ -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 356b855f3b..59411ec5f8 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -489,7 +489,7 @@ static void hda_work_around(struct device *dev) static int place_device_in_d3hot(struct device *dev) { - unsigned offset; + unsigned int offset; /* Parts of the HDA block are used for LPE audio as well. * Therefore assume the HDA will never be put into D3Hot. */ @@ -605,7 +605,7 @@ static struct device_operations device_ops = { .enable_resources = NULL, .init = sc_init, .enable = southcluster_enable_dev, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 0b52ea9611..8aa6290386 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -76,7 +76,7 @@ typedef struct ich_spi_controller { uint16_t *optype; uint32_t *addr; uint8_t *data; - unsigned databytes; + unsigned int databytes; uint8_t *status; uint16_t *control; } ich_spi_controller; @@ -266,13 +266,13 @@ typedef struct spi_transaction { uint32_t offset; } spi_transaction; -static inline void spi_use_out(spi_transaction *trans, unsigned bytes) +static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) { trans->out += bytes; trans->bytesout -= bytes; } -static inline void spi_use_in(spi_transaction *trans, unsigned bytes) +static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) { trans->in += bytes; trans->bytesin -= bytes; diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c index 6605575691..d31ddd9be3 100644 --- a/src/soc/intel/fsp_baytrail/tsc_freq.c +++ b/src/soc/intel/fsp_baytrail/tsc_freq.c @@ -19,7 +19,7 @@ #include #include -unsigned bus_freq_khz(void) +unsigned int bus_freq_khz(void) { msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL); switch (clk_info.lo & 0x3) { @@ -39,7 +39,7 @@ unsigned bus_freq_khz(void) unsigned long tsc_freq_mhz(void) { msr_t platform_info; - unsigned bclk_khz = bus_freq_khz(); + unsigned int bclk_khz = bus_freq_khz(); if (!bclk_khz) return 0; diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 6c74a749a4..4c50828e0d 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -24,7 +24,6 @@ config CPU_SPECIFIC_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select TSC_MONOTONIC_TIMER - select TSC_CONSTANT_RATE select HAVE_FSP_BIN select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SOC_INTEL_COMMON diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index 6b1d3f621b..5349c30758 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -114,36 +114,6 @@ static int acpi_sci_irq(void) return sci_irq; } -void acpi_create_intel_hpet(acpi_hpet_t *hpet) -{ - acpi_header_t *header = &(hpet->header); - acpi_addr_t *addr = &(hpet->addr); - - memset((void *) hpet, 0, sizeof(acpi_hpet_t)); - - /* fill out header fields */ - memcpy(header->signature, "HPET", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_hpet_t); - header->revision = get_acpi_table_revision(HPET); - - /* fill out HPET address */ - addr->space_id = 0; /* Memory */ - addr->bit_width = 64; - addr->bit_offset = 0; - addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; - addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; - - hpet->id = 0x8086a201; /* Intel */ - hpet->number = 0x00; - hpet->min_tick = 0x0080; - - header->checksum = acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, @@ -316,7 +286,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) static unsigned long acpi_fill_dmar(unsigned long current) { uint32_t vtbar, tmp = current; - struct device *dev = pcidev_path_on_root(VTD_DEV_FUNC); + struct device *dev = pcidev_path_on_root(IIO_DEVFN_VTD); uint16_t bdf, hpet_bdf[8]; uint8_t i, j; @@ -333,7 +303,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) current += acpi_create_dmar_ds_ioapic(current, 9, 0, 5, 4); /* Get the PCI BDF for the PCH I/O APIC */ - dev = pcidev_path_on_root(LPC_DEV_FUNC); + dev = pcidev_path_on_root(PCH_DEVFN_LPC); bdf = pci_read_config16(dev, 0x6c); current += acpi_create_dmar_ds_ioapic(current, 8, (bdf >> 8), PCI_SLOT(bdf), PCI_FUNC(bdf)); diff --git a/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl b/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl index 6a7a2f132f..ef1e655100 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl +++ b/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl @@ -44,7 +44,7 @@ Device (LPC0) Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400) }) } diff --git a/src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl b/src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl index fa83f59e03..ff30f9f758 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl +++ b/src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl @@ -21,7 +21,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Name (MCRS, ResourceTemplate() { diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c index ac4dcc92dd..b94ee78d7a 100644 --- a/src/soc/intel/fsp_broadwell_de/cpu.c +++ b/src/soc/intel/fsp_broadwell_de/cpu.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -27,6 +28,8 @@ #include #include #include +#include +#include #include #include #include @@ -98,6 +101,25 @@ static void set_max_ratio(void) wrmsr(IA32_PERF_CTL, perf_ctl); } +unsigned int smbios_cpu_get_max_speed_mhz(void) +{ + msr_t msr; + uint32_t uncore_max_ratio, turbo_max_ratio = 0; + + /* + * Use turbo's max ratio if it is enabled, otherwise use + * uncore's max ratio. + */ + msr = rdmsr(MSR_UNCORE_RATIO_LIMIT); + uncore_max_ratio = msr.lo & 0x7f; + if (get_turbo_state() == TURBO_ENABLED) { + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + turbo_max_ratio = msr.lo & 0xff; /* 1 core */ + } + + return MAX(uncore_max_ratio, turbo_max_ratio) * CPU_BCLK; +} + static void alt_smm_lock(void) { struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h index 44e17d0daf..419f229938 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h @@ -20,7 +20,6 @@ #include -void acpi_create_intel_hpet(acpi_hpet_t *hpet); void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); unsigned long acpi_madt_irq_overrides(unsigned long current); uint16_t get_pmbase(void); diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h index 4167895729..a44b857c1f 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h @@ -31,6 +31,15 @@ size_t sa_get_tseg_size(void); #define TSEG_BASE 0xa8 /* TSEG base */ #define TSEG_LIMIT 0xac /* TSEG limit */ +#define IIO_LTDPR 0x290 +#define DPR_LOCK (1 << 0) +#define DPR_EPM (1 << 2) +#define DPR_PRS (1 << 1) +#define DPR_SIZE_MASK 0xff0 +#define DPR_SIZE_SHIFT 4 +#define DPR_ADDR_MASK 0xfff00000 +#define DPR_ADDR_SHIFT 20 + /* CPU bus clock is fixed at 100MHz */ #define CPU_BCLK 100 diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h index e4b8c50e20..f9fdffb2bf 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h @@ -23,6 +23,7 @@ #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 +#define MSR_UNCORE_RATIO_LIMIT 0x620 #define MSR_CONFIG_TDP_NOMINAL 0x648 #define SMM_MCA_CAP_MSR 0x17d diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h index 8de4d19982..6a68b2f81f 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h @@ -24,7 +24,6 @@ #define SOC_DEV 0 #define SOC_FUNC 0 -#define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV, SOC_FUNC) /* DMI2/PCIe link to PCH */ #define PCIE_IIO_PORT_0_DEV 0x00 @@ -51,51 +50,42 @@ #define VTD_DEV 5 #define VTD_FUNC 0 -#define VTD_DEV_FUNC PCI_DEVFN(VTD_DEV, VTD_FUNC) +#define IIO_DEVFN_VTD PCI_DEVFN(VTD_DEV, VTD_FUNC) #define VTD_PCI_DEV PCI_DEV(BUS0, VTD_DEV, VTD_FUNC) #define LPC_DEV 31 #define LPC_FUNC 0 -#define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV, LPC_FUNC) +#define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV, LPC_FUNC) #define SATA_DEV 31 #define SATA_FUNC 2 -#define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV, SATA_FUNC) #define SMBUS_DEV 31 #define SMBUS_FUNC 3 -#define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) #define SATA2_DEV 31 #define SATA2_FUNC 5 -#define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV, SATA2_FUNC) #define EHCI1_DEV 29 #define EHCI1_FUNC 0 -#define EHCI1_DEV_FUNC PCI_DEVFN(EHCI_DEV1, EHCI_FUNC1) #define EHCI2_DEV 26 #define EHCI2_FUNC 0 -#define EHCI2_DEV_FUNC PCI_DEVFN(EHCI_DEV2, EHCI_FUNC2) #define XHCI_DEV 20 #define XHCI_FUNC 0 #define XHCI_FUS_REG 0xE0 #define XHCI_FUNC_DISABLE (1 << 0) #define XHCI_USB2PR_REG 0xD0 -#define XHCI_DEV_FUNC PCI_DEVFN(XHCI_DEV, XHCI_FUNC) #define GBE_DEV 25 #define GBE_FUNC 0 -#define GBE_DEV_FUNC PCI_DEVFN(GBE_DEV, GBE_FUNC) #define ME_DEV 22 #define ME_FUNC 0 -#define ME_DEV_FUNC PCI_DEVFN(ME_DEV, ME_FUNC) #define HDA_DEV 27 #define HDA_FUNC 0 -#define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV, HDA_FUNC) /* Ports from PCH block with adjustable burification settings */ #define PCIE_DEV 28 @@ -115,20 +105,11 @@ #define PCIE_PORT7_FUNC 6 #define PCIE_PORT8_DEV PCIE_DEV #define PCIE_PORT8_FUNC 7 -#define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT1_FUNC) -#define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT2_FUNC) -#define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT3_FUNC) -#define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT4_FUNC) -#define PCIE_PORT5_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT5_FUNC) -#define PCIE_PORT6_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT6_FUNC) -#define PCIE_PORT7_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT7_FUNC) -#define PCIE_PORT8_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT8_FUNC) /* The SMM device is located on bus 0xff (QPI) */ #define QPI_BUS 0xff #define SMM_DEV 0x10 #define SMM_FUNC 0x06 -#define SMM_DEV_FUNC PCI_DEVFN(SMM_DEV, SMM_FUNC) #define IMC_DEV0 19 #define IMC_FUNC0 0 diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h b/src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h index 785b689558..69fb687276 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h @@ -24,6 +24,8 @@ void broadwell_de_init_pre_device(void); void broadwell_de_init_cpus(struct device *dev); void southcluster_enable_dev(struct device *dev); +void broadwell_de_set_dpr(const uintptr_t addr, const size_t size); +void broadwell_de_lock_dpr(void); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smbus.h b/src/soc/intel/fsp_broadwell_de/include/soc/smbus.h index 0a7dbaeeab..4d9d3e1f57 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/smbus.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/smbus.h @@ -40,9 +40,9 @@ #define SMBUS_TIMEOUT (10 * 1000 * 100) #define SMBUS_SLAVE_ADDR 0x24 -int do_smbus_read_byte(unsigned smbus_base, unsigned device, - unsigned address); -int do_smbus_write_byte(unsigned smbus_base, unsigned device, - unsigned address, unsigned data); +int do_smbus_read_byte(unsigned int smbus_base, unsigned int device, + unsigned int address); +int do_smbus_write_byte(unsigned int smbus_base, unsigned int device, + unsigned int address, unsigned int data); #endif diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/ubox.h b/src/soc/intel/fsp_broadwell_de/include/soc/ubox.h index baaeac55cb..3c2e6f50a6 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/ubox.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/ubox.h @@ -40,6 +40,5 @@ #define UBOX_DEVHIDE0 0xb0 -void iio_hide(const uint8_t devno, const uint8_t funcno); - +void iio_hide(DEVTREE_CONST struct device *dev); #endif diff --git a/src/soc/intel/fsp_broadwell_de/memmap.c b/src/soc/intel/fsp_broadwell_de/memmap.c index cbd3cf7788..96eb20502c 100644 --- a/src/soc/intel/fsp_broadwell_de/memmap.c +++ b/src/soc/intel/fsp_broadwell_de/memmap.c @@ -23,7 +23,7 @@ #include #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } diff --git a/src/soc/intel/fsp_broadwell_de/ramstage.c b/src/soc/intel/fsp_broadwell_de/ramstage.c index 96b3888d0b..fd5a0392ff 100644 --- a/src/soc/intel/fsp_broadwell_de/ramstage.c +++ b/src/soc/intel/fsp_broadwell_de/ramstage.c @@ -28,6 +28,7 @@ #include #include #include +#include /* Global PATTRS */ DEFINE_PATTRS; @@ -82,3 +83,47 @@ void broadwell_de_init_pre_device(void) { fill_in_pattrs(); } + +/* + * Set DPR region. + */ +void broadwell_de_set_dpr(const uintptr_t addr, const size_t size) +{ + struct device *dev; + uint32_t dpr_reg; + /* + * DMA Protected Range can be reserved below TSEG for PCODE patch + * or TXT/BootGuard related data. Rather than reporting a base address + * the DPR register reports the TOP of the region, which is the same + * as TSEG base. The region size is reported in MiB in bits 11:4. + */ + dev = pcidev_on_root(VTD_DEV, VTD_FUNC); + dpr_reg = pci_read_config32(dev, IIO_LTDPR); + if (dpr_reg & DPR_LOCK) { + printk(BIOS_ERR, "ERROR: HOSTBRIDGE[DPR] is already locked\n"); + return; + } + + dpr_reg &= ~(DPR_ADDR_MASK | DPR_SIZE_MASK); + dpr_reg |= addr & DPR_ADDR_MASK; + dpr_reg |= (size >> (20 - DPR_SIZE_SHIFT)) & DPR_SIZE_MASK; + dpr_reg |= DPR_EPM; + pci_write_config32(dev, IIO_LTDPR, dpr_reg); +} + +/* + * Lock DPR register. + */ +void broadwell_de_lock_dpr(void) +{ + struct device *dev; + uint32_t dpr_reg; + dev = pcidev_on_root(VTD_DEV, VTD_FUNC); + dpr_reg = pci_read_config32(dev, IIO_LTDPR); + if (dpr_reg & DPR_LOCK) { + printk(BIOS_ERR, "ERROR: HOSTBRIDGE[DPR] is already locked\n"); + return; + } + dpr_reg |= DPR_LOCK; + pci_write_config32(dev, IIO_LTDPR, dpr_reg); +} diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index b0fad3f02b..8438b1035c 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -94,6 +94,37 @@ static void enable_integrated_uart(uint8_t port) pci_mmio_write_config32(ubox_dev, UBOX_UART_ENABLE, ubox_uart_en); } +static void early_iio_hide(void) +{ + DEVTREE_CONST struct device *dev; + + const pci_devfn_t iio_rootport[] = { + PCI_DEVFN(PCIE_IIO_PORT_1_DEV, PCIE_IIO_PORT_1A_FUNC), + PCI_DEVFN(PCIE_IIO_PORT_1_DEV, PCIE_IIO_PORT_1B_FUNC), + PCI_DEVFN(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2A_FUNC), + PCI_DEVFN(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2B_FUNC), + PCI_DEVFN(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2C_FUNC), + PCI_DEVFN(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2D_FUNC), + PCI_DEVFN(PCIE_IIO_PORT_3_DEV, PCIE_IIO_PORT_3A_FUNC), + PCI_DEVFN(PCIE_IIO_PORT_3_DEV, PCIE_IIO_PORT_3B_FUNC), + PCI_DEVFN(PCIE_IIO_PORT_3_DEV, PCIE_IIO_PORT_3C_FUNC), + PCI_DEVFN(PCIE_IIO_PORT_3_DEV, PCIE_IIO_PORT_3D_FUNC), + }; + + /* Walk through IIO root ports and hide if it is disabled in devtree */ + for (int i = 0; i < ARRAY_SIZE(iio_rootport); i++) { + dev = pcidev_path_on_bus(BUS0, iio_rootport[i]); + if (dev && !dev->enabled) { + printk(BIOS_DEBUG, "Hiding IIO root port: %d:%d.%d\n", + BUS0, + PCI_SLOT(iio_rootport[i]), + PCI_FUNC(iio_rootport[i])); + iio_hide(dev); + } + } + +} + /* Entry from cache-as-ram.inc. */ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) { @@ -121,14 +152,15 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) init_rtc(); setup_gpio_io_address(); + /* Hide before MemoryInit since hiding later seems to break FSP */ + early_iio_hide(); timestamp_add_now(TS_BEFORE_INITRAM); - + post_code(0x48); /* * Call early init to initialize memory and chipset. This function returns * to the romstage_main_continue function with a pointer to the HOB * structure. */ - post_code(0x48); printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); fsp_early_init(fsp_info_header); die_with_post_code(POST_INVALID_VENDOR_BINARY, diff --git a/src/soc/intel/fsp_broadwell_de/smbus-imc.c b/src/soc/intel/fsp_broadwell_de/smbus-imc.c index 35e42da409..61dc080c50 100644 --- a/src/soc/intel/fsp_broadwell_de/smbus-imc.c +++ b/src/soc/intel/fsp_broadwell_de/smbus-imc.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/soc/intel/fsp_broadwell_de/smbus_common.c b/src/soc/intel/fsp_broadwell_de/smbus_common.c index e179b55987..0c5da4f4f4 100644 --- a/src/soc/intel/fsp_broadwell_de/smbus_common.c +++ b/src/soc/intel/fsp_broadwell_de/smbus_common.c @@ -31,7 +31,7 @@ static void smbus_delay(void) static int smbus_wait_until_ready(u16 smbus_base) { - unsigned loops = SMBUS_TIMEOUT; + unsigned int loops = SMBUS_TIMEOUT; unsigned char byte; do { smbus_delay(); @@ -44,7 +44,7 @@ static int smbus_wait_until_ready(u16 smbus_base) static int smbus_wait_until_done(u16 smbus_base) { - unsigned loops = SMBUS_TIMEOUT; + unsigned int loops = SMBUS_TIMEOUT; unsigned char byte; do { smbus_delay(); @@ -55,7 +55,7 @@ static int smbus_wait_until_done(u16 smbus_base) return loops ? 0 : -1; } -int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address) +int do_smbus_read_byte(unsigned int smbus_base, unsigned int device, unsigned int address) { unsigned char global_status_register; unsigned char byte; @@ -101,8 +101,8 @@ int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address) return byte; } -int do_smbus_write_byte(unsigned smbus_base, unsigned device, - unsigned address, unsigned data) +int do_smbus_write_byte(unsigned int smbus_base, unsigned int device, + unsigned int address, unsigned int data) { unsigned char global_status_register; diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index cb52e56e8a..fb8af87b62 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -257,30 +257,17 @@ void southcluster_enable_dev(struct device *dev) const int slot = PCI_SLOT(dev->path.pci.devfn); const int func = PCI_FUNC(dev->path.pci.devfn); - switch (slot) { - case PCIE_IIO_PORT_0_DEV: - die("should not hide PCH link"); - case PCIE_IIO_PORT_1_DEV: /* fallthrough */ - case PCIE_IIO_PORT_2_DEV: /* fallthrough */ - case PCIE_IIO_PORT_3_DEV: /* fallthrough */ - printk(BIOS_DEBUG, "%s: Disabling IOU bridge %02x.%01x\n", dev_path(dev), slot, - func); - iio_hide(slot, func); - break; - default: - printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", dev_path(dev), slot, - func); - /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); - } + printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", dev_path(dev), slot, func); + /* Ensure memory, io, and bus master are all disabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32); } #if CONFIG(HAVE_ACPI_TABLES) static const char *lpc_acpi_name(const struct device *dev) { - if (dev->path.pci.devfn == LPC_DEV_FUNC) + if (dev->path.pci.devfn == PCH_DEVFN_LPC) return "LPC0"; else return NULL; @@ -294,7 +281,7 @@ static struct device_operations device_ops = { .write_acpi_tables = southcluster_write_acpi_tables, .init = sc_init, .enable = southcluster_enable_dev, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &soc_pci_ops, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = lpc_acpi_name, diff --git a/src/soc/intel/fsp_broadwell_de/ubox.c b/src/soc/intel/fsp_broadwell_de/ubox.c index d7352ad667..e3e55e0624 100644 --- a/src/soc/intel/fsp_broadwell_de/ubox.c +++ b/src/soc/intel/fsp_broadwell_de/ubox.c @@ -18,10 +18,13 @@ #include #include -void iio_hide(const uint8_t devno, const uint8_t funcno) +void iio_hide(DEVTREE_CONST struct device *dev) { pci_devfn_t ubox_dev; + uint8_t slot, func; + slot = PCI_SLOT(dev->path.pci.devfn); + func = PCI_FUNC(dev->path.pci.devfn); ubox_dev = PCI_DEV(get_busno1(), UBOX_DEV, UBOX_FUNC); - pci_or_config32(ubox_dev, UBOX_DEVHIDE0 + funcno * 4, 1 << devno); + pci_or_config32(ubox_dev, UBOX_DEVHIDE0 + func * 4, 1 << slot); } diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 05fe423fac..a04993ddf2 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -43,6 +43,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_EBDA select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA @@ -52,7 +53,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_RESET select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_2017_BINDING @@ -70,11 +70,11 @@ config DCACHE_RAM_SIZE config DCACHE_BSP_STACK_SIZE hex - default 0x20000 if FSP_USES_CB_STACK - default 0x4000 + default 0x20400 help The amount of anticipated stack usage in CAR by bootblock and - other stages. + other stages. In the case of FSP_USES_CB_STACK default value will be + sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). config FSP_TEMP_RAM_SIZE hex diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 15f7030ba0..a4ebd20580 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -8,29 +8,26 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc +# all (bootblock, verstage, romstage, postcar, ramstage) +all-y += gspi.c +all-y += i2c.c +all-y += pmutil.c +all-y += spi.c +all-y += uart.c + bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c -bootblock-y += pmutil.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c bootblock-y += gpio.c -bootblock-y += gspi.c -bootblock-y += i2c.c bootblock-y += memmap.c -bootblock-y += spi.c bootblock-y += p2sb.c -bootblock-y += uart.c romstage-y += espi.c romstage-y += gpio.c -romstage-y += gspi.c -romstage-y += i2c.c romstage-y += memmap.c -romstage-y += pmutil.c romstage-y += reset.c -romstage-y += spi.c -romstage-y += uart.c ramstage-y += acpi.c ramstage-y += chip.c @@ -41,18 +38,13 @@ ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += gpio.c ramstage-y += graphics.c -ramstage-y += gspi.c -ramstage-y += i2c.c ramstage-y += lockdown.c ramstage-y += memmap.c ramstage-y += p2sb.c ramstage-y += pmc.c -ramstage-y += pmutil.c -ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-y += reset.c ramstage-y += smmrelocate.c -ramstage-y += spi.c ramstage-y += systemagent.c -ramstage-y += uart.c ramstage-y += sd.c smm-y += gpio.c @@ -63,17 +55,6 @@ smm-y += smihandler.c smm-y += uart.c postcar-y += memmap.c -postcar-y += pmutil.c -postcar-y += i2c.c -postcar-y += gspi.c -postcar-y += spi.c -postcar-y += uart.c - -verstage-y += gspi.c -verstage-y += i2c.c -verstage-y += pmutil.c -verstage-y += spi.c -verstage-y += uart.c CPPFLAGS_common += -I$(src)/soc/intel/icelake CPPFLAGS_common += -I$(src)/soc/intel/icelake/include diff --git a/src/soc/intel/icelake/acpi/espi.asl b/src/soc/intel/icelake/acpi/espi.asl deleted file mode 100644 index 4456812ba6..0000000000 --- a/src/soc/intel/icelake/acpi/espi.asl +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/* Device identifier is not changed to ESPI to maintain coherency with ec.asl */ -Device (LPCB) -{ - Name (_ADR, 0x001f0000) - Name (_DDN, "ESPI Bus Device") - - Device (FWH) - { - Name (_HID, EISAID ("INT0800")) - Name (_DDN, "Firmware Hub") - Name (_CRS, ResourceTemplate () - { - Memory32Fixed (ReadOnly, 0xff000000, 0x01000000) - }) - } - - Device (HPET) - { - Name (_HID, EISAID ("PNP0103")) - Name (_DDN, "High Precision Event Timer") - Name (_CRS, ResourceTemplate () - { - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - Method (_STA, 0) - { - Return (0xf) - } - } - - Device (PIC) - { - Name (_HID, EISAID ("PNP0000")) - Name (_DDN, "8259 Interrupt Controller") - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x20, 0x20, 0x01, 0x02) - IO (Decode16, 0x24, 0x24, 0x01, 0x02) - IO (Decode16, 0x28, 0x28, 0x01, 0x02) - IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) - IO (Decode16, 0x30, 0x30, 0x01, 0x02) - IO (Decode16, 0x34, 0x34, 0x01, 0x02) - IO (Decode16, 0x38, 0x38, 0x01, 0x02) - IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) - IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) - IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) - IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) - IO (Decode16, 0xac, 0xac, 0x01, 0x02) - IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) - IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) - IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) - IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) - IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) - IRQNoFlags () { 2 } - }) - } - - Device (LDRC) - { - Name (_HID, EISAID ("PNP0C02")) - Name (_UID, 2) - Name (_DDN, "Legacy Device Resources") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO - IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, - 0x1, 0xff) - }) - } - - Device (RTC) - { - Name (_HID, EISAID ("PNP0B00")) - Name (_DDN, "Real Time Clock") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x70, 0x70, 1, 8) - }) - } - - Device (TIMR) - { - Name (_HID, EISAID ("PNP0100")) - Name (_DDN, "8254 Timer") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags () {0} - }) - } - -} diff --git a/src/soc/intel/icelake/acpi/northbridge.asl b/src/soc/intel/icelake/acpi/northbridge.asl index efd0f9ab8c..e99e7edf1f 100644 --- a/src/soc/intel/icelake/acpi/northbridge.asl +++ b/src/soc/intel/icelake/acpi/northbridge.asl @@ -22,7 +22,6 @@ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_SEG, Zero) // _SEG: PCI Segment -Name (_ADR, Zero) // _ADR: Address Name (_UID, Zero) // _UID: Unique ID Device (MCHC) diff --git a/src/soc/intel/icelake/acpi/platform.asl b/src/soc/intel/icelake/acpi/platform.asl index 080bf7b960..b89fd4685a 100644 --- a/src/soc/intel/icelake/acpi/platform.asl +++ b/src/soc/intel/icelake/acpi/platform.asl @@ -18,15 +18,6 @@ /* Generic indicator for sleep state */ #include -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - /* * The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index ffd2fcca71..389963e79c 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -33,7 +33,7 @@ #include "gpio.asl" /* ESPI 0:1f.0 */ -#include "espi.asl" +#include /* PCH HDA */ #include "pch_hda.asl" diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c index db43e50ec8..f348c1be6a 100644 --- a/src/soc/intel/icelake/bootblock/bootblock.c +++ b/src/soc/intel/icelake/bootblock/bootblock.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include diff --git a/src/soc/intel/icelake/bootblock/cpu.c b/src/soc/intel/icelake/bootblock/cpu.c index e23286c2d2..da7b7ea153 100644 --- a/src/soc/intel/icelake/bootblock/cpu.c +++ b/src/soc/intel/icelake/bootblock/cpu.c @@ -13,14 +13,19 @@ * GNU General Public License for more details. */ -#include #include #include void bootblock_cpu_init(void) { - /* Temporarily cache the memory-mapped boot media. */ - if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) && - CONFIG(BOOT_DEVICE_SPI_FLASH)) - fast_spi_cache_bios_region(); + /* + * Icelake platform doesn't support booting from any other media + * (like eMMC on APL/GLK platform) than only booting from SPI device + * and on IA platform SPI is memory mapped hence enabling temporarily + * cacheing on memory-mapped spi boot media. + * + * This assumption will not hold good for APL/GLK platform where boot + * from eMMC is also possible options. + */ + fast_spi_cache_bios_region(); } diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index aefcaa5a47..e95220b90e 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -72,7 +72,7 @@ static void soc_config_pwrmbase(void) /* Enable Bus Master and MMIO Space */ reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 |= PCI_COMMAND_MEMORY; + reg32 |= PCI_COMMAND_MEMORY; pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); /* Enable PWRM in PMC */ diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c index a9eef40756..660aab9101 100644 --- a/src/soc/intel/icelake/bootblock/report_platform.c +++ b/src/soc/intel/icelake/bootblock/report_platform.c @@ -93,7 +93,8 @@ static void report_cpu_info(void) { struct cpuid_result cpuidr; u32 i, index, cpu_id, cpu_feature_flag; - char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ + const char cpu_not_found[] = "Platform info not available"; + const char *cpu_name = cpu_not_found; /* 48 bytes are reported */ int vt, txt, aes; msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; @@ -102,9 +103,7 @@ static void report_cpu_info(void) index = 0x80000000; cpuidr = cpuid(index); - if (cpuidr.eax < 0x80000004) { - strcpy(cpu_string, "Platform info not available"); - } else { + if (cpuidr.eax >= 0x80000004) { int j = 0; for (i = 2; i <= 4; i++) { @@ -116,10 +115,11 @@ static void report_cpu_info(void) } p[12] = 0; cpu_name = (char *)p; + + /* Skip leading spaces in CPU name string */ + while (cpu_name[0] == ' ' && strlen(cpu_name) > 0) + cpu_name++; } - /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ') - cpu_name++; microcode_ver.lo = 0; microcode_ver.hi = 0; diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 0ecccb94e5..a2d9f7a6bc 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -127,7 +127,7 @@ static void enable_pm_timer_emulation(void) * frequency is used. */ msr.hi = (3579545ULL << 32) / CTC_FREQ; - /* Set PM1 timer IO port and enable*/ + /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); wrmsr(MSR_EMULATE_PM_TIMER, msr); diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 8819e7d033..62c69da2f2 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -94,15 +94,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) mainboard_silicon_init_params(params); dev = pcidev_path_on_root(SA_DEVFN_IGD); - - if (!dev || !dev->enabled) { - /* - * Skip IGD initialization in FSP in case device is disabled - * in the devicetree.cb. - */ - params->PeiGraphicsPeimInit = 0; - } else { + if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) params->PeiGraphicsPeimInit = 1; + else + params->PeiGraphicsPeimInit = 0; + if (dev && dev->enabled) { params->GtFreqMax = 2; params->CdClock = 3; } diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index 07090331cb..91f40b9c86 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -52,14 +52,14 @@ void graphics_soc_init(struct device *dev) /* * GFX PEIM module inside FSP binary is taking care of graphics - * initialization based on INTEL_GMA_ADD_VBT Kconfig + * initialization based on RUN_FSP_GOP Kconfig * option and input VBT file. Hence no need to load/execute legacy VGA * OpROM in order to initialize GFX. * * In case of non-FSP solution, SoC need to select VGA_ROM_RUN * Kconfig to perform GFX initialization through VGA OpRom. */ - if (CONFIG(INTEL_GMA_ADD_VBT)) + if (CONFIG(RUN_FSP_GOP)) return; /* IGD needs to Bus Master */ diff --git a/src/soc/intel/icelake/include/soc/bootblock.h b/src/soc/intel/icelake/include/soc/bootblock.h index 2f6473da02..4ca2c37288 100644 --- a/src/soc/intel/icelake/include/soc/bootblock.h +++ b/src/soc/intel/icelake/include/soc/bootblock.h @@ -16,8 +16,6 @@ #ifndef _SOC_ICELAKE_BOOTBLOCK_H_ #define _SOC_ICELAKE_BOOTBLOCK_H_ -#include - /* Bootblock pre console init programming */ void bootblock_cpu_init(void); void bootblock_pch_early_init(void); diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h index b5722da742..7d17058004 100644 --- a/src/soc/intel/icelake/include/soc/cpu.h +++ b/src/soc/intel/icelake/include/soc/cpu.h @@ -16,7 +16,6 @@ #ifndef _SOC_ICELAKE_CPU_H_ #define _SOC_ICELAKE_CPU_H_ -#include #include /* Latency times in units of 32768ns */ diff --git a/src/soc/intel/icelake/include/soc/nvs.h b/src/soc/intel/icelake/include/soc/nvs.h index b2d903a4f5..c855df0305 100644 --- a/src/soc/intel/icelake/include/soc/nvs.h +++ b/src/soc/intel/icelake/include/soc/nvs.h @@ -16,34 +16,6 @@ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ -#include -#include - -typedef struct global_nvs_t { - /* Miscellaneous */ - u16 osys; /* 0x00 - 0x01 Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 pcnt; /* 0x03 - Processor Count */ - u8 ppcm; /* 0x04 - Max PPC State */ - u8 tlvl; /* 0x05 - Throttle Level Limit */ - u8 lids; /* 0x06 - LID State */ - u8 pwrs; /* 0x07 - AC Power State */ - u32 cbmc; /* 0x08 - 0xb AC Power State */ - u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */ - u64 gpei; /* 0x14 - 0x1b GPE wake status bit */ - u8 dpte; /* 0x1c - Enable DPTF */ - u64 nhla; /* 0x1d - 0x24 NHLT Address */ - u32 nhll; /* 0x25 - 0x28 NHLT Length */ - u16 cid1; /* 0x29 - 0x2a Wifi Country Identifier */ - u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */ - u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */ - u8 uior; /* 0x2f - UART debug controller init on S3 resume */ - u8 unused[208]; - - /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - +#include #endif diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 20c4e6fb7d..76a8128520 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -29,12 +29,6 @@ #include #include -void smm_region(uintptr_t *start, size_t *size) -{ - *start = sa_get_tseg_base(); - *size = sa_get_tseg_size(); -} - /* Calculate ME Stolen size */ static size_t get_imr_size(void) { @@ -190,21 +184,6 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size) return dram_base; } -/* - * SoC implementation - * - * SoC call to summarize all Intel Reserve MMIO size and report to SA - */ -size_t soc_reserved_mmio_size(void) -{ - struct ebda_config cfg; - - retrieve_ebda_object(&cfg); - - /* Get Intel Reserved Memory Range Size */ - return cfg.reserved_mem_size; -} - /* Fill up memory layout information */ void fill_soc_memmap_ebda(struct ebda_config *cfg) { @@ -247,38 +226,11 @@ void cbmem_top_init(void) * | | * +-------------------------+ */ -void *cbmem_top(void) +void *cbmem_top_chipset(void) { struct ebda_config ebda_cfg; - /* - * Check if Tseg has been initialized, we will use this as a flag - * to check if the MRC is done, and only then continue to read the - * PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before - * PRMRR_MASK MSR lock bit is set. - */ - if (sa_get_tseg_base() == 0) - return NULL; - retrieve_ebda_object(&ebda_cfg); return (void *)(uintptr_t)ebda_cfg.tolum_base; } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); -} diff --git a/src/soc/intel/icelake/reset.c b/src/soc/intel/icelake/reset.c index d83b3ee3fa..5526a42545 100644 --- a/src/soc/intel/icelake/reset.c +++ b/src/soc/intel/icelake/reset.c @@ -19,7 +19,6 @@ #include #include #include -#include #include void do_global_reset(void) diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 65505c4b27..8f56ad6650 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -179,6 +178,13 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) const u32 rmask = ~(4 * KiB - 1); smm_region(&tseg_base, &tseg_size); + + if (!IS_ALIGNED(tseg_base, tseg_size)) { + printk(BIOS_WARNING, + "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n"); + return; + } + smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); /* SMRR has 32-bits of valid address aligned to 4KiB. */ diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 4ed0377a7b..461d230371 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -29,13 +29,14 @@ config CPU_SPECIFIC_OPTIONS select C_ENVIRONMENT_BOOTBLOCK select NO_MMCONF_SUPPORT select REG_SCRIPT + select PLATFORM_USES_FSP2_0 select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select SOC_SETS_MSRS select SPI_FLASH - select TSC_CONSTANT_RATE select UART_OVERRIDE_REFCLK select UDELAY_TSC + select TSC_MONOTONIC_TIMER select UNCOMPRESSED_RAMSTAGE select USE_MARCH_586 select NO_SMM @@ -113,8 +114,7 @@ config ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY select ENABLE_DEBUG_LED help Indicate that bootblock_c_entry was entered. If the SD LED does not - light then debug the code between ESRAM and bootblock_c_entry. For - FSP 1.1, use ENABLE_DEBUG_LED_FINDFSP to split this code. + light then debug the code between ESRAM and bootblock_c_entry. config ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY bool "SD LED indicates bootblock_soc_early_init successfully entered" @@ -192,12 +192,10 @@ config FSP_ESRAM_LOC config FSP_M_FILE string - depends on PLATFORM_USES_FSP2_0 default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP_M.fd" config FSP_S_FILE string - depends on PLATFORM_USES_FSP2_0 default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP_S.fd" ##### diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index f1382f5efa..3a58cc9235 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -37,11 +37,10 @@ romstage-y += reg_access.c romstage-$(CONFIG_STORAGE_TEST) += storage_test.c romstage-y += tsc_freq.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +romstage-y += reset.c -postcar-y += fsp2_0.c +postcar-y += fsp_params.c postcar-y += i2c.c -postcar-y += memmap.c postcar-y += reg_access.c postcar-y += tsc_freq.c postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c @@ -49,14 +48,13 @@ postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c -ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c +ramstage-y += fsp_params.c ramstage-y += gpio_i2c.c ramstage-y += i2c.c ramstage-y += lpc.c -ramstage-y += memmap.c ramstage-y += northcluster.c ramstage-y += reg_access.c -ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-y += reset.c ramstage-y += sd.c ramstage-y += spi.c ramstage-y += spi_debug.c diff --git a/src/soc/intel/quark/fsp2_0.c b/src/soc/intel/quark/fsp_params.c similarity index 100% rename from src/soc/intel/quark/fsp2_0.c rename to src/soc/intel/quark/fsp_params.c diff --git a/src/soc/intel/quark/lpc.c b/src/soc/intel/quark/lpc.c index 19f7ceb215..df5bdcac2a 100644 --- a/src/soc/intel/quark/lpc.c +++ b/src/soc/intel/quark/lpc.c @@ -53,7 +53,7 @@ static struct device_operations device_ops = { .read_resources = pmc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, }; static const struct pci_driver pmc __pci_driver = { diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index b8b85063a8..9ccaf55a1f 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -18,7 +18,7 @@ #include #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { uint32_t top_of_memory; diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 13963d4b23..d90a3af5d4 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -14,10 +14,8 @@ # romstage-y += car.c -ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-$(CONFIG_DISPLAY_UPD_DATA) += debug.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c -endif # CONFIG_PLATFORM_USES_FSP2_0 +romstage-y += fsp_params.c romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp_params.c similarity index 100% rename from src/soc/intel/quark/romstage/fsp2_0.c rename to src/soc/intel/quark/romstage/fsp_params.c diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c index e6d0369eff..fa5bd67efe 100644 --- a/src/soc/intel/quark/tsc_freq.c +++ b/src/soc/intel/quark/tsc_freq.c @@ -14,21 +14,10 @@ * GNU General Public License for more details. */ -#include -#include #include -#include unsigned long tsc_freq_mhz(void) { /* CPU freq = 400 MHz */ return 400; } - -void timer_monotonic_get(struct mono_time *mt) -{ - uint64_t tsc_value; - - tsc_value = rdtscll(); - mt->microseconds = tsc_value / tsc_freq_mhz(); -} diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 901e5f9b21..d4720a21be 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -10,7 +10,6 @@ config SOC_INTEL_SKYLAKE config SOC_INTEL_KABYLAKE bool select SOC_INTEL_COMMON_SKYLAKE_BASE - select MAINBOARD_USES_FSP2_0 help Intel Kabylake support @@ -27,12 +26,12 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select COLLECT_TIMESTAMPS select COMMON_FADT select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_INTEL_COMMON_HYPERTHREADING select C_ENVIRONMENT_BOOTBLOCK - select FSP_M_XIP if MAINBOARD_USES_FSP2_0 + select FSP_M_XIP select FSP_T_XIP if FSP_CAR select GENERIC_GPIO_LIB select HAVE_FSP_GOP @@ -40,12 +39,14 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SMI_HANDLER select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI + select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC select MRC_SETTINGS_PROTECT select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK select PCIEX_LENGTH_64MB + select PLATFORM_USES_FSP2_0 select REG_SCRIPT select SA_ENABLE_DPR select SMP @@ -57,6 +58,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_EBDA select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL @@ -64,6 +66,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SGX + select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_UART @@ -73,38 +76,19 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_RESET select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC + select UDK_2015_BINDING config FSP_HYPERTHREADING bool "Enable Hyper-Threading" - depends on MAINBOARD_USES_FSP2_0 default y config CPU_INTEL_NUM_FIT_ENTRIES int default 10 -config MAINBOARD_USES_FSP2_0 - bool - default n - -config USE_FSP2_0_DRIVER - def_bool y - depends on MAINBOARD_USES_FSP2_0 - select PLATFORM_USES_FSP2_0 - select UDK_2015_BINDING - select INTEL_GMA_ADD_VBT if RUN_FSP_GOP - -config USE_FSP1_1_DRIVER - def_bool y - depends on !MAINBOARD_USES_FSP2_0 - select PLATFORM_USES_FSP1_1 - select DISPLAY_FSP_ENTRY_POINTS - select SKIP_FSP_CAR - config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC @@ -242,17 +226,14 @@ config NHLT_DA7219 config FSP_HEADER_PATH string "Location of FSP headers" - depends on MAINBOARD_USES_FSP2_0 # Use KabylakeFsp for both Skylake and Kabylake as it supports both. # SkylakeFsp is FSP 1.1 and therefore incompatible. - default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_SKYLAKE - default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_KABYLAKE + default "3rdparty/fsp/KabylakeFspBinPkg/Include/" config FSP_FD_PATH string depends on FSP_USE_REPO - default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_SKYLAKE - default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_KABYLAKE + default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" config SPI_FLASH_INCLUDE_ALL_DRIVERS bool @@ -260,8 +241,7 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS config MAX_ROOT_PORTS int - default 24 if PLATFORM_USES_FSP2_0 - default 20 if PLATFORM_USES_FSP1_1 + default 24 config NO_FADT_8042 bool diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ef741f808b..cb0906c1d5 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -37,13 +37,12 @@ romstage-y += memmap.c romstage-y += me.c romstage-y += pmc.c romstage-y += pmutil.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +romstage-y += reset.c romstage-y += spi.c romstage-y += uart.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c -ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c -ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += chip_fsp20.c +ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += elog.c ramstage-y += finalize.c @@ -59,7 +58,7 @@ ramstage-y += memmap.c ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c -ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-y += reset.c ramstage-y += sd.c ramstage-y += smmrelocate.c ramstage-y += spi.c @@ -102,13 +101,6 @@ endif CPPFLAGS_common += -I$(src)/soc/intel/skylake CPPFLAGS_common += -I$(src)/soc/intel/skylake/include -ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) -CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp11 -CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake -else -CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20 -endif - # Currently used for microcode path. CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index de37341a08..2af5a53149 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -205,7 +205,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) + if (config->sgx_enable) sgx_fill_gnvs(gnvs); } diff --git a/src/soc/intel/skylake/acpi/ipu.asl b/src/soc/intel/skylake/acpi/ipu.asl index c78b5be4a5..66dcd3b8f5 100644 --- a/src/soc/intel/skylake/acpi/ipu.asl +++ b/src/soc/intel/skylake/acpi/ipu.asl @@ -13,13 +13,7 @@ * GNU General Public License for more details. */ -/* IPU3 input system - Device 05, Function 0 */ -Device (IMGU) -{ - Name (_ADR, 0x00050000) - Name (_DDN, "Imaging Unit") - Name (CAMD, 0x01) -} +#include /* IPU3 processing system - Device 14, Function 3 */ Device (CIO2) diff --git a/src/soc/intel/skylake/acpi/lpc.asl b/src/soc/intel/skylake/acpi/lpc.asl index c9167ad4ec..7dd0298cb7 100644 --- a/src/soc/intel/skylake/acpi/lpc.asl +++ b/src/soc/intel/skylake/acpi/lpc.asl @@ -15,105 +15,11 @@ * GNU General Public License for more details. */ -Device (LPCB) +// Intel LPC Bus Device - 0:1f.0 +#include + +Scope (\_SB.PCI0.LPCB) { - Name (_ADR, 0x001f0000) - Name (_DDN, "LPC Bus Device") - - Device (FWH) - { - Name (_HID, EISAID ("INT0800")) - Name (_DDN, "Firmware Hub") - Name (_CRS, ResourceTemplate () - { - Memory32Fixed (ReadOnly, 0xff000000, 0x01000000) - }) - } - - Device (HPET) - { - Name (_HID, EISAID ("PNP0103")) - Name (_DDN, "High Precision Event Timer") - Name (_CRS, ResourceTemplate () - { - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - Method (_STA, 0) - { - Return (0xf) - } - } - - Device (PIC) - { - Name (_HID, EISAID ("PNP0000")) - Name (_DDN, "8259 Interrupt Controller") - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x20, 0x20, 0x01, 0x02) - IO (Decode16, 0x24, 0x24, 0x01, 0x02) - IO (Decode16, 0x28, 0x28, 0x01, 0x02) - IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) - IO (Decode16, 0x30, 0x30, 0x01, 0x02) - IO (Decode16, 0x34, 0x34, 0x01, 0x02) - IO (Decode16, 0x38, 0x38, 0x01, 0x02) - IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) - IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) - IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) - IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) - IO (Decode16, 0xac, 0xac, 0x01, 0x02) - IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) - IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) - IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) - IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) - IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) - IRQNoFlags () { 2 } - }) - } - - Device (LDRC) - { - Name (_HID, EISAID ("PNP0C02")) - Name (_UID, 2) - Name (_DDN, "Legacy Device Resources") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO - IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, - 0x1, 0xff) - }) - } - - Device (RTC) - { - Name (_HID, EISAID ("PNP0B00")) - Name (_DDN, "Real Time Clock") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x70, 0x70, 1, 8) - }) - } - - Device (TIMR) - { - Name (_HID, EISAID ("PNP0100")) - Name (_DDN, "8254 Timer") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags () {0} - }) - } - #include #include } diff --git a/src/soc/intel/skylake/acpi/platform.asl b/src/soc/intel/skylake/acpi/platform.asl index 39debe1476..36c3ae3915 100644 --- a/src/soc/intel/skylake/acpi/platform.asl +++ b/src/soc/intel/skylake/acpi/platform.asl @@ -18,41 +18,6 @@ /* Enable ACPI _SWS methods */ #include -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* IO-Trap at 0x800. - * This is the ACPI->SMI communication interface. - */ -OperationRegion (IO_T, SystemIO, 0x800, 0x10) -Field (IO_T, ByteAcc, NoLock, Preserve) -{ - Offset (0x8), - TRP0, 8 /* IO-Trap at 0x808 */ -} - -/* SMI I/O Trap */ -Method (TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - /* * The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index a04fe9eb6a..e7b2d90463 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -23,7 +23,6 @@ Name (_HID, EISAID ("PNP0A08")) /* PCIe */ Name (_CID, EISAID ("PNP0A03")) /* PCI */ -Name (_ADR, 0) Name (_BBN, 0) Device (MCHC) diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index e9ca2d8af2..596e3f184f 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -38,10 +38,6 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { - /* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */ - if (CONFIG(PLATFORM_USES_FSP1_1)) - bootblock_fsp_temp_ram_init(); - /* * Perform early chipset initialization before fsp memory init * example: pirq->irq programming, enabling smbus, set pmcbase diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 89dd1547c0..0bd65c3def 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -119,18 +119,36 @@ static struct { u16 igdid; const char *name; } igd_table[] = { - { PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM, "Skylake ULT GT1"}, + { PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2, "Skylake DT GT1F" }, + { PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM, "Skylake ULT GT1" }, + { PCI_DEVICE_ID_INTEL_SKL_GT1F_SHALM, "Skylake HALO GT1F" }, { PCI_DEVICE_ID_INTEL_SKL_GT2_DT2P1, "Skylake DT GT2" }, - { PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM, "Skylake ULX GT2" }, { PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM, "Skylake ULT GT2" }, { PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM, "Skylake HALO GT2" }, + { PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM, "Skylake Mobile Xeon GT2"}, + { PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM, "Skylake ULX GT2" }, + { PCI_DEVICE_ID_INTEL_SKL_GT3_SULTM, "Skylake ULT GT3" }, + { PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_1, "Skylake ULT (15W) GT3E" }, + { PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_2, "Skylake ULT (28W) GT3E" }, + { PCI_DEVICE_ID_INTEL_SKL_GT3FE_SSRVM, "Skylake Media Server GT3FE" }, { PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM, "Skylake HALO GT4" }, - { PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM, "Kabylake ULT GT1"}, - { PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM, "Kabylake ULX GT2" }, - { PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM, "Kabylake ULT GT2" }, - { PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR, "Kabylake-R ULT GT2"}, - { PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM, "Kabylake HALO GT2" }, - { PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2, "Kabylake DT GT2" }, + { PCI_DEVICE_ID_INTEL_SKL_GT4E_SWSTM, "Skylake Workstation GT4E" }, + { PCI_DEVICE_ID_INTEL_KBL_GT1F_DT2, "Kaby Lake DT GT1F" }, + { PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM, "Kaby Lake ULT GT1" }, + { PCI_DEVICE_ID_INTEL_KBL_GT1_SHALM_1, "Kaby Lake HALO GT1" }, + { PCI_DEVICE_ID_INTEL_KBL_GT1_SHALM_2, "Kaby Lake HALO GT1" }, + { PCI_DEVICE_ID_INTEL_KBL_GT1_SSRVM, "Kaby Lake SRV GT1" }, + { PCI_DEVICE_ID_INTEL_KBL_GT2_SSRVM, "Kaby Lake Media Server GT2" }, + { PCI_DEVICE_ID_INTEL_KBL_GT2_SWSTM, "Kaby Lake Workstation GT2" }, + { PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM, "Kaby Lake ULX GT2" }, + { PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM, "Kaby Lake ULT GT2" }, + { PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR, "Kaby Lake-R ULT GT2" }, + { PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM, "Kaby Lake HALO GT2" }, + { PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2, "Kaby Lake DT GT2" }, + { PCI_DEVICE_ID_INTEL_KBL_GT2F_SULTM, "Kaby Lake ULT GT2F" }, + { PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1, "Kaby Lake ULT (15W) GT3E" }, + { PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2, "Kaby Lake ULT (28W) GT3E" }, + { PCI_DEVICE_ID_INTEL_KBL_GT4_SHALM, "Kaby Lake HALO GT4" }, { PCI_DEVICE_ID_INTEL_AML_GT2_ULX, "Amberlake ULX GT2" }, }; diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index ddb29327a1..7987f46954 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. + * Copyright (C) 2016-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,26 +13,160 @@ * GNU General Public License for more details. */ +#include +#include +#include +#include #include +#include #include #include -#include +#include #include #include #include #include +#include #include +#include #include +#include #include +#include #include +#include #include #include #include #include +#include #include #include "chip.h" +struct pcie_entry { + unsigned int devfn; + unsigned int func_count; +}; + +/* + * According to table 2-2 in doc#546717: + * PCI bus[function] ID + * D28:[F0 - F7] 0xA110 - 0xA117 + * D29:[F0 - F7] 0xA118 - 0xA11F + * D27:[F0 - F3] 0xA167 - 0xA16A + */ +static const struct pcie_entry pcie_table_skl_pch_h[] = { + {PCH_DEVFN_PCIE1, 8}, + {PCH_DEVFN_PCIE9, 8}, + {PCH_DEVFN_PCIE17, 4}, +}; + +/* + * According to table 2-2 in doc#564464: + * PCI bus[function] ID + * D28:[F0 - F7] 0xA290 - 0xA297 + * D29:[F0 - F7] 0xA298 - 0xA29F + * D27:[F0 - F7] 0xA2E7 - 0xA2EE + */ +static const struct pcie_entry pcie_table_kbl_pch_h[] = { + {PCH_DEVFN_PCIE1, 8}, + {PCH_DEVFN_PCIE9, 8}, + {PCH_DEVFN_PCIE17, 8}, +}; + +/* + * According to table 2-2 in doc#567995/545659: + * PCI bus[function] ID + * D28:[F0 - F7] 0x9D10 - 0x9D17 + * D29:[F0 - F3] 0x9D18 - 0x9D1B + */ +static const struct pcie_entry pcie_table_skl_pch_lp[] = { + {PCH_DEVFN_PCIE1, 8}, + {PCH_DEVFN_PCIE9, 4}, +}; + +/* + * If the PCIe root port at function 0 is disabled, + * the PCIe root ports might be coalesced after FSP silicon init. + * The below function will swap the devfn of the first enabled device + * in devicetree and function 0 resides a pci device + * so that it won't confuse coreboot. + */ +static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group, + size_t pci_groups) +{ + struct device *func0; + unsigned int devfn, devfn0; + int i, group; + unsigned int inc = PCI_DEVFN(0, 1); + + for (group = 0; group < pci_groups; group++) { + devfn0 = pcie_rp_group[group].devfn; + func0 = pcidev_path_on_root(devfn0); + if (func0 == NULL) + continue; + + /* No more functions if function 0 is disabled. */ + if (pci_read_config32(func0, PCI_VENDOR_ID) == 0xffffffff) + continue; + + devfn = devfn0 + inc; + + /* + * Increase function by 1. + * Then find first enabled device to replace func0 + * as that port was move to func0. + */ + for (i = 1; i < pcie_rp_group[group].func_count; + i++, devfn += inc) { + struct device *dev = pcidev_path_on_root(devfn); + if (dev == NULL || !dev->enabled) + continue; + + /* + * Found the first enabled device in + * a given dev number. + */ + printk(BIOS_INFO, "PCI func %d was swapped" + " to func 0.\n", i); + func0->path.pci.devfn = dev->path.pci.devfn; + dev->path.pci.devfn = devfn0; + break; + } + } +} + +static void pcie_override_devicetree_after_silicon_init(void) +{ + uint16_t id, id_mask; + + id = pci_read_config16(PCH_DEV_PCIE1, PCI_DEVICE_ID); + /* + * We may read an ID other than func 0 after FSP-S. + * Strip out 4 least significant bits. + */ + id_mask = id & ~0xf; + printk(BIOS_INFO, "Override DT after FSP-S, PCH is "); + if (id_mask == (PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 & ~0xf)) { + printk(BIOS_INFO, "KBL/SKL PCH-LP SKU\n"); + pcie_update_device_tree(&pcie_table_skl_pch_lp[0], + ARRAY_SIZE(pcie_table_skl_pch_lp)); + } else if (id_mask == (PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1 & ~0xf)) { + printk(BIOS_INFO, "KBL PCH-H SKU\n"); + pcie_update_device_tree(&pcie_table_kbl_pch_h[0], + ARRAY_SIZE(pcie_table_kbl_pch_h)); + } else if (id_mask == (PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1 & ~0xf)) { + printk(BIOS_INFO, "SKL PCH-H SKU\n"); + pcie_update_device_tree(&pcie_table_skl_pch_h[0], + ARRAY_SIZE(pcie_table_skl_pch_h)); + } else { + printk(BIOS_ERR, "[BUG] PCIE Root Port id 0x%x" + " is not found\n", id); + return; + } +} + void soc_init_pre_device(void *chip_info) { /* Snapshot the current GPIO IRQ polarities. FSP is setting a @@ -41,15 +174,25 @@ void soc_init_pre_device(void *chip_info) itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); /* Perform silicon specific init. */ - intel_silicon_init(); + fsp_silicon_init(romstage_handoff_is_resume()); + + /* + * Keep the P2SB device visible so it and the other devices are + * visible in coreboot for driver support and PCI resource allocation. + * There is no UPD setting for this. + */ + p2sb_unhide(); /* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + + /* swap enabled PCI ports in device tree if needed */ + pcie_override_devicetree_after_silicon_init(); } void soc_fsp_load(void) { - fsp_load(); + fsps_load(romstage_handoff_is_resume()); } static void pci_domain_set_resources(struct device *dev) @@ -68,6 +211,9 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = generate_cpu_entries, @@ -84,34 +230,46 @@ static void soc_enable(struct device *dev) } struct chip_operations soc_intel_skylake_ops = { - CHIP_NAME("Intel Skylake") - .enable_dev = &soc_enable, - .init = &soc_init_pre_device, + CHIP_NAME("Intel 6th Gen") + .enable_dev = &soc_enable, + .init = &soc_init_pre_device, }; /* UPD parameters to be initialized before SiliconInit */ -void soc_silicon_init_params(SILICON_INIT_UPD *params) +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { - struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); - const struct soc_intel_skylake_config *config = config_of(dev); + FSP_S_CONFIG *params = &supd->FspsConfig; + FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; + struct soc_intel_skylake_config *config; + struct device *dev; + uintptr_t vbt_data = (uintptr_t)vbt_get(); int i; - memcpy(params->SerialIoDevMode, config->SerialIoDevMode, - sizeof(params->SerialIoDevMode)); + config = config_of_soc(); + + mainboard_silicon_init_params(params); + /* Set PsysPmax if it is available from DT */ + if (config->psys_pmax) { + /* PsysPmax is in unit of 1/8 Watt */ + tconfig->PsysPmax = config->psys_pmax * 8; + printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax); + } + + params->GraphicsConfigPtr = (u32) vbt_data; for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = - config->usb2_ports[i].enable; + config->usb2_ports[i].enable; params->Usb2OverCurrentPin[i] = - config->usb2_ports[i].ocpin; + config->usb2_ports[i].ocpin; params->Usb2AfePetxiset[i] = - config->usb2_ports[i].pre_emp_bias; + config->usb2_ports[i].pre_emp_bias; params->Usb2AfeTxiset[i] = - config->usb2_ports[i].tx_bias; + config->usb2_ports[i].tx_bias; params->Usb2AfePredeemp[i] = - config->usb2_ports[i].tx_emp_enable; + config->usb2_ports[i].tx_emp_enable; params->Usb2AfePehalfbit[i] = - config->usb2_ports[i].pre_emp_bit; + config->usb2_ports[i].pre_emp_bit; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { @@ -129,86 +287,158 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) } } - memcpy(params->PcieRpEnable, config->PcieRpEnable, - sizeof(params->PcieRpEnable)); - memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, - sizeof(params->PcieRpClkReqSupport)); - memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, - sizeof(params->PcieRpClkReqNumber)); - memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, - sizeof(params->PcieRpHotPlug)); - - params->EnableLan = config->EnableLan; - params->Cio2Enable = config->Cio2Enable; - params->SataSalpSupport = config->SataSalpSupport; memcpy(params->SataPortsEnable, config->SataPortsEnable, - sizeof(params->SataPortsEnable)); + sizeof(params->SataPortsEnable)); memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, - sizeof(params->SataPortsDevSlp)); + sizeof(params->SataPortsDevSlp)); + memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, + sizeof(params->SataPortsHotPlug)); + memcpy(params->SataPortsSpinUp, config->SataPortsSpinUp, + sizeof(params->SataPortsSpinUp)); + memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, + sizeof(params->PcieRpClkReqSupport)); + memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, + sizeof(params->PcieRpClkReqNumber)); + memcpy(params->PcieRpAdvancedErrorReporting, + config->PcieRpAdvancedErrorReporting, + sizeof(params->PcieRpAdvancedErrorReporting)); + memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, + sizeof(params->PcieRpLtrEnable)); + memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, + sizeof(params->PcieRpHotPlug)); + + /* + * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for + * all the enabled PCIe root ports, invalid(0x1F) is set for + * disabled PCIe root ports. + */ + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { + if (config->PcieRpClkReqSupport[i]) + params->PcieRpClkSrcNumber[i] = + config->PcieRpClkSrcNumber[i]; + else + params->PcieRpClkSrcNumber[i] = 0x1F; + } + + /* disable Legacy PME */ + memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + + /* Legacy 8254 timer support */ + params->Early8254ClockGatingEnable = !CONFIG_USE_LEGACY_8254_TIMER; + + memcpy(params->SerialIoDevMode, config->SerialIoDevMode, + sizeof(params->SerialIoDevMode)); + + params->PchCio2Enable = config->Cio2Enable; + params->SaImguEnable = config->SaImguEnable; + params->Heci3Enabled = config->Heci3Enabled; + + params->LogoPtr = config->LogoPtr; + params->LogoSize = config->LogoSize; + + params->CpuConfig.Bits.VmxEnable = CONFIG(ENABLE_VMX); + + params->PchPmWoWlanEnable = config->PchPmWoWlanEnable; + params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; + params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; + + params->PchLanEnable = config->EnableLan; + if (config->EnableLan) { + params->PchLanLtrEnable = config->EnableLanLtr; + params->PchLanK1OffEnable = config->EnableLanK1Off; + params->PchLanClkReqSupported = config->LanClkReqSupported; + params->PchLanClkReqNumber = config->LanClkReqNumber; + } + params->SataSalpSupport = config->SataSalpSupport; params->SsicPortEnable = config->SsicPortEnable; - params->SmbusEnable = config->SmbusEnable; params->ScsEmmcEnabled = config->ScsEmmcEnabled; params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; params->ScsSdCardEnabled = config->ScsSdCardEnabled; - /* Enable ISH if device is on */ - dev = pcidev_path_on_root(PCH_DEVFN_ISH); - params->IshEnable = dev ? dev->enabled : 0; + if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) { + params->PchScsEmmcHs400DllDataValid = + !!config->EmmcHs400DllNeed; + params->PchScsEmmcHs400RxStrobeDll1 = + config->ScsEmmcHs400RxStrobeDll1; + params->PchScsEmmcHs400TxDataDll = + config->ScsEmmcHs400TxDataDll; + } - params->EnableAzalia = config->EnableAzalia; - params->IoBufferOwnership = config->IoBufferOwnership; - params->DspEnable = config->DspEnable; + /* If ISH is enabled, enable ISH elements */ + dev = pcidev_path_on_root(PCH_DEVFN_ISH); + params->PchIshEnable = dev ? dev->enabled : 0; + + params->PchHdaEnable = config->EnableAzalia; + params->PchHdaVcType = config->PchHdaVcType; + params->PchHdaIoBufferOwnership = config->IoBufferOwnership; + params->PchHdaDspEnable = config->DspEnable; params->Device4Enable = config->Device4Enable; - params->EnableSata = config->EnableSata; + params->SataEnable = config->EnableSata; params->SataMode = config->SataMode; - params->LockDownConfigGlobalSmi = config->LockDownConfigGlobalSmi; - params->LockDownConfigRtcLock = config->LockDownConfigRtcLock; + params->SataSpeedLimit = config->SataSpeedLimit; + params->SataPwrOptEnable = config->SataPwrOptEnable; + params->EnableTcoTimer = !config->PmTimerDisabled; + + tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; + tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; + tconfig->PowerLimit4 = config->PowerLimit4; + tconfig->SataTestMode = config->SataTestMode; + /* + * To disable HECI, the Psf needs to be left unlocked + * by FSP till end of post sequence. Based on the devicetree + * setting, we set the appropriate PsfUnlock policy in FSP, + * do the changes and then lock it back in coreboot during finalize. + */ + tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { - params->LockDownConfigBiosInterface = 0; - params->LockDownConfigBiosLock = 0; - params->LockDownConfigSpiEiss = 0; + tconfig->PchLockDownBiosInterface = 0; + params->PchLockDownBiosLock = 0; + params->PchLockDownSpiEiss = 0; + /* + * Skip Spi Flash Lockdown from inside FSP. + * Making this config "0" means FSP won't set the FLOCKDN bit + * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). + * So, it becomes coreboot's responsibility to set this bit + * before end of POST for security concerns. + */ + params->SpiFlashCfgLockDown = 0; } /* only replacing preexisting subsys ID defaults when non-zero */ - if (CONFIG_SUBSYSTEM_VENDOR_ID != 0) - params->PchConfigSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID; + if (CONFIG_SUBSYSTEM_VENDOR_ID != 0) { + params->DefaultSvid = CONFIG_SUBSYSTEM_VENDOR_ID; + params->PchSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID; + } - if (CONFIG_SUBSYSTEM_DEVICE_ID != 0) - params->PchConfigSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; + if (CONFIG_SUBSYSTEM_DEVICE_ID != 0) { + params->DefaultSid = CONFIG_SUBSYSTEM_DEVICE_ID; + params->PchSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; + } - params->WakeConfigWolEnableOverride = - config->WakeConfigWolEnableOverride; - params->WakeConfigPcieWakeFromDeepSx = - config->WakeConfigPcieWakeFromDeepSx; - params->PmConfigDeepSxPol = config->PmConfigDeepSxPol; - params->PmConfigSlpS3MinAssert = config->PmConfigSlpS3MinAssert; - params->PmConfigSlpS4MinAssert = config->PmConfigSlpS4MinAssert; - params->PmConfigSlpSusMinAssert = config->PmConfigSlpSusMinAssert; - params->PmConfigSlpAMinAssert = config->PmConfigSlpAMinAssert; - params->PmConfigPciClockRun = config->PmConfigPciClockRun; - params->PmConfigSlpStrchSusUp = config->PmConfigSlpStrchSusUp; - params->PmConfigPwrBtnOverridePeriod = - config->PmConfigPwrBtnOverridePeriod; - params->PmConfigPwrCycDur = config->PmConfigPwrCycDur; - params->SerialIrqConfigSirqEnable = config->serirq_mode != SERIRQ_OFF; - params->SerialIrqConfigSirqMode = - config->serirq_mode == SERIRQ_CONTINUOUS; - params->SerialIrqConfigStartFramePulse = - config->SerialIrqConfigStartFramePulse; + params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; + params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; + params->PchPmDeepSxPol = config->PmConfigDeepSxPol; + params->PchPmSlpS0Enable = config->s0ix_enable; + params->PchPmSlpS3MinAssert = config->PmConfigSlpS3MinAssert; + params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert; + params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert; + params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; + params->PchPmLpcClockRun = config->PmConfigPciClockRun; + params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; + params->PchPmPwrBtnOverridePeriod = + config->PmConfigPwrBtnOverridePeriod; + params->PchPmPwrCycDur = config->PmConfigPwrCycDur; - params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + /* Indicate whether platform supports Voltage Margining */ + params->PchPmSlpS0VmEnable = config->PchPmSlpS0VmEnable; + + params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF; + params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS; + + params->CpuConfig.Bits.SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++) params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; - /* - * To disable Heci, the Psf needs to be left unlocked - * by FSP after end of post sequence. Based on the devicetree - * setting, we set the appropriate PsfUnlock policy in Fsp, - * do the changes and then lock it back in coreboot - * - */ - params->PsfUnlock = !config->HeciEnabled; - for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) fill_vr_domain_config(params, i, &config->domain_vr_config[i]); @@ -226,636 +456,70 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->XdciEnable = 0; } - params->SendVrMbxCmd = config->SendVrMbxCmd; + /* Enable or disable Gaussian Mixture Model in devicetree */ + dev = pcidev_path_on_root(SA_DEVFN_GMM); + params->GmmEnable = dev ? dev->enabled : 0; + + /* + * Send VR specific mailbox commands: + * 000b - no VR specific command sent + * 001b - VR mailbox command specifically for the MPS IMPV8 VR + * will be sent + * 010b - VR specific command sent for PS4 exit issue + * 100b - VR specific command sent for MPS VR decay issue + */ + params->SendVrMbxCmd1 = config->SendVrMbxCmd; + + /* + * Activates VR mailbox command for Intersil VR C-state issues. + * 0 - no mailbox command sent. + * 1 - VR mailbox command sent for IA/GT rails only. + * 2 - VR mailbox command sent for IA/GT/SA rails. + */ + params->IslVrCmd = config->IslVrCmd; /* Acoustic Noise Mitigation */ params->AcousticNoiseMitigation = config->AcousticNoiseMitigation; params->SlowSlewRateForIa = config->SlowSlewRateForIa; params->SlowSlewRateForGt = config->SlowSlewRateForGt; params->SlowSlewRateForSa = config->SlowSlewRateForSa; - params->FastPkgCRampDisable = config->FastPkgCRampDisable; + params->FastPkgCRampDisableIa = config->FastPkgCRampDisableIa; + params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt; + params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa; - /* Legacy 8254 timer support */ - params->Early8254ClockGatingEnable = !CONFIG_USE_LEGACY_8254_TIMER; + /* Enable PMC XRAM read */ + tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; + + /* Enable/Disable EIST */ + tconfig->Eist = config->eist_enable; + + /* Set TccActivationOffset */ + tconfig->TccActivationOffset = config->tcc_offset; + + /* Enable VT-d and X2APIC */ + if (!config->ignore_vtd && soc_is_vtd_capable()) { + params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS; + params->X2ApicOptOut = 0; + tconfig->VtdDisable = 0; + + params->PchIoApicBdfValid = 1; + params->PchIoApicBusNumber = V_P2SB_IBDF_BUS; + params->PchIoApicDeviceNumber = V_P2SB_IBDF_DEV; + params->PchIoApicFunctionNumber = V_P2SB_IBDF_FUN; + } + + dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) + params->PeiGraphicsPeimInit = 1; + else + params->PeiGraphicsPeimInit = 0; soc_irq_settings(params); } -void soc_display_silicon_init_params(const SILICON_INIT_UPD *original, - SILICON_INIT_UPD *params) +/* Mainboard GPIO Configuration */ +__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) { - /* Display the parameters for SiliconInit */ - printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); - fsp_display_upd_value("LogoPtr", 4, - (uint32_t)original->LogoPtr, - (uint32_t)params->LogoPtr); - fsp_display_upd_value("LogoSize", 4, - (uint32_t)original->LogoSize, - (uint32_t)params->LogoSize); - fsp_display_upd_value("GraphicsConfigPtr", 4, - (uint32_t)original->GraphicsConfigPtr, - (uint32_t)params->GraphicsConfigPtr); - fsp_display_upd_value("MicrocodeRegionBase", 4, - (uint32_t)original->MicrocodeRegionBase, - (uint32_t)params->MicrocodeRegionBase); - fsp_display_upd_value("MicrocodeRegionSize", 4, - (uint32_t)original->MicrocodeRegionSize, - (uint32_t)params->MicrocodeRegionSize); - fsp_display_upd_value("TurboMode", 1, - (uint32_t)original->TurboMode, - (uint32_t)params->TurboMode); - fsp_display_upd_value("Device4Enable", 1, - original->Device4Enable, - params->Device4Enable); - fsp_display_upd_value("PcieRpEnable[0]", 1, original->PcieRpEnable[0], - params->PcieRpEnable[0]); - fsp_display_upd_value("PcieRpEnable[1]", 1, original->PcieRpEnable[1], - params->PcieRpEnable[1]); - fsp_display_upd_value("PcieRpEnable[2]", 1, original->PcieRpEnable[2], - params->PcieRpEnable[2]); - fsp_display_upd_value("PcieRpEnable[3]", 1, original->PcieRpEnable[3], - params->PcieRpEnable[3]); - fsp_display_upd_value("PcieRpEnable[4]", 1, original->PcieRpEnable[4], - params->PcieRpEnable[4]); - fsp_display_upd_value("PcieRpEnable[5]", 1, original->PcieRpEnable[5], - params->PcieRpEnable[5]); - fsp_display_upd_value("PcieRpEnable[6]", 1, original->PcieRpEnable[6], - params->PcieRpEnable[6]); - fsp_display_upd_value("PcieRpEnable[7]", 1, original->PcieRpEnable[7], - params->PcieRpEnable[7]); - fsp_display_upd_value("PcieRpEnable[8]", 1, original->PcieRpEnable[8], - params->PcieRpEnable[8]); - fsp_display_upd_value("PcieRpEnable[9]", 1, original->PcieRpEnable[9], - params->PcieRpEnable[9]); - fsp_display_upd_value("PcieRpEnable[10]", 1, original->PcieRpEnable[10], - params->PcieRpEnable[10]); - fsp_display_upd_value("PcieRpEnable[11]", 1, original->PcieRpEnable[11], - params->PcieRpEnable[11]); - fsp_display_upd_value("PcieRpEnable[12]", 1, original->PcieRpEnable[12], - params->PcieRpEnable[12]); - fsp_display_upd_value("PcieRpEnable[13]", 1, original->PcieRpEnable[13], - params->PcieRpEnable[13]); - fsp_display_upd_value("PcieRpEnable[14]", 1, original->PcieRpEnable[14], - params->PcieRpEnable[14]); - fsp_display_upd_value("PcieRpEnable[15]", 1, original->PcieRpEnable[15], - params->PcieRpEnable[15]); - fsp_display_upd_value("PcieRpEnable[16]", 1, original->PcieRpEnable[16], - params->PcieRpEnable[16]); - fsp_display_upd_value("PcieRpEnable[17]", 1, original->PcieRpEnable[17], - params->PcieRpEnable[17]); - fsp_display_upd_value("PcieRpEnable[18]", 1, original->PcieRpEnable[18], - params->PcieRpEnable[18]); - fsp_display_upd_value("PcieRpEnable[19]", 1, original->PcieRpEnable[19], - params->PcieRpEnable[19]); - fsp_display_upd_value("PcieRpClkReqSupport[0]", 1, - original->PcieRpClkReqSupport[0], - params->PcieRpClkReqSupport[0]); - fsp_display_upd_value("PcieRpClkReqSupport[1]", 1, - original->PcieRpClkReqSupport[1], - params->PcieRpClkReqSupport[1]); - fsp_display_upd_value("PcieRpClkReqSupport[2]", 1, - original->PcieRpClkReqSupport[2], - params->PcieRpClkReqSupport[2]); - fsp_display_upd_value("PcieRpClkReqSupport[3]", 1, - original->PcieRpClkReqSupport[3], - params->PcieRpClkReqSupport[3]); - fsp_display_upd_value("PcieRpClkReqSupport[4]", 1, - original->PcieRpClkReqSupport[4], - params->PcieRpClkReqSupport[4]); - fsp_display_upd_value("PcieRpClkReqSupport[5]", 1, - original->PcieRpClkReqSupport[5], - params->PcieRpClkReqSupport[5]); - fsp_display_upd_value("PcieRpClkReqSupport[6]", 1, - original->PcieRpClkReqSupport[6], - params->PcieRpClkReqSupport[6]); - fsp_display_upd_value("PcieRpClkReqSupport[7]", 1, - original->PcieRpClkReqSupport[7], - params->PcieRpClkReqSupport[7]); - fsp_display_upd_value("PcieRpClkReqSupport[8]", 1, - original->PcieRpClkReqSupport[8], - params->PcieRpClkReqSupport[8]); - fsp_display_upd_value("PcieRpClkReqSupport[9]", 1, - original->PcieRpClkReqSupport[9], - params->PcieRpClkReqSupport[9]); - fsp_display_upd_value("PcieRpClkReqSupport[10]", 1, - original->PcieRpClkReqSupport[10], - params->PcieRpClkReqSupport[10]); - fsp_display_upd_value("PcieRpClkReqSupport[11]", 1, - original->PcieRpClkReqSupport[11], - params->PcieRpClkReqSupport[11]); - fsp_display_upd_value("PcieRpClkReqSupport[12]", 1, - original->PcieRpClkReqSupport[12], - params->PcieRpClkReqSupport[12]); - fsp_display_upd_value("PcieRpClkReqSupport[13]", 1, - original->PcieRpClkReqSupport[13], - params->PcieRpClkReqSupport[13]); - fsp_display_upd_value("PcieRpClkReqSupport[14]", 1, - original->PcieRpClkReqSupport[14], - params->PcieRpClkReqSupport[14]); - fsp_display_upd_value("PcieRpClkReqSupport[15]", 1, - original->PcieRpClkReqSupport[15], - params->PcieRpClkReqSupport[15]); - fsp_display_upd_value("PcieRpClkReqSupport[16]", 1, - original->PcieRpClkReqSupport[16], - params->PcieRpClkReqSupport[16]); - fsp_display_upd_value("PcieRpClkReqSupport[17]", 1, - original->PcieRpClkReqSupport[17], - params->PcieRpClkReqSupport[17]); - fsp_display_upd_value("PcieRpClkReqSupport[18]", 1, - original->PcieRpClkReqSupport[18], - params->PcieRpClkReqSupport[18]); - fsp_display_upd_value("PcieRpClkReqSupport[19]", 1, - original->PcieRpClkReqSupport[19], - params->PcieRpClkReqSupport[19]); - fsp_display_upd_value("PcieRpClkReqNumber[0]", 1, - original->PcieRpClkReqNumber[0], - params->PcieRpClkReqNumber[0]); - fsp_display_upd_value("PcieRpClkReqNumber[1]", 1, - original->PcieRpClkReqNumber[1], - params->PcieRpClkReqNumber[1]); - fsp_display_upd_value("PcieRpClkReqNumber[2]", 1, - original->PcieRpClkReqNumber[2], - params->PcieRpClkReqNumber[2]); - fsp_display_upd_value("PcieRpClkReqNumber[3]", 1, - original->PcieRpClkReqNumber[3], - params->PcieRpClkReqNumber[3]); - fsp_display_upd_value("PcieRpClkReqNumber[4]", 1, - original->PcieRpClkReqNumber[4], - params->PcieRpClkReqNumber[4]); - fsp_display_upd_value("PcieRpClkReqNumber[5]", 1, - original->PcieRpClkReqNumber[5], - params->PcieRpClkReqNumber[5]); - fsp_display_upd_value("PcieRpClkReqNumber[6]", 1, - original->PcieRpClkReqNumber[6], - params->PcieRpClkReqNumber[6]); - fsp_display_upd_value("PcieRpClkReqNumber[7]", 1, - original->PcieRpClkReqNumber[7], - params->PcieRpClkReqNumber[7]); - fsp_display_upd_value("PcieRpClkReqNumber[8]", 1, - original->PcieRpClkReqNumber[8], - params->PcieRpClkReqNumber[8]); - fsp_display_upd_value("PcieRpClkReqNumber[9]", 1, - original->PcieRpClkReqNumber[9], - params->PcieRpClkReqNumber[9]); - fsp_display_upd_value("PcieRpClkReqNumber[10]", 1, - original->PcieRpClkReqNumber[10], - params->PcieRpClkReqNumber[10]); - fsp_display_upd_value("PcieRpClkReqNumber[11]", 1, - original->PcieRpClkReqNumber[11], - params->PcieRpClkReqNumber[11]); - fsp_display_upd_value("PcieRpClkReqNumber[12]", 1, - original->PcieRpClkReqNumber[12], - params->PcieRpClkReqNumber[12]); - fsp_display_upd_value("PcieRpClkReqNumber[13]", 1, - original->PcieRpClkReqNumber[13], - params->PcieRpClkReqNumber[13]); - fsp_display_upd_value("PcieRpClkReqNumber[14]", 1, - original->PcieRpClkReqNumber[14], - params->PcieRpClkReqNumber[14]); - fsp_display_upd_value("PcieRpClkReqNumber[15]", 1, - original->PcieRpClkReqNumber[15], - params->PcieRpClkReqNumber[15]); - fsp_display_upd_value("PcieRpClkReqNumber[16]", 1, - original->PcieRpClkReqNumber[16], - params->PcieRpClkReqNumber[16]); - fsp_display_upd_value("PcieRpClkReqNumber[17]", 1, - original->PcieRpClkReqNumber[17], - params->PcieRpClkReqNumber[17]); - fsp_display_upd_value("PcieRpClkReqNumber[18]", 1, - original->PcieRpClkReqNumber[18], - params->PcieRpClkReqNumber[18]); - fsp_display_upd_value("PcieRpClkReqNumber[19]", 1, - original->PcieRpClkReqNumber[19], - params->PcieRpClkReqNumber[19]); - fsp_display_upd_value("EnableLan", 1, original->EnableLan, - params->EnableLan); - fsp_display_upd_value("Cio2Enable", 1, original->Cio2Enable, - params->Cio2Enable); - fsp_display_upd_value("SataSalpSupport", 1, original->SataSalpSupport, - params->SataSalpSupport); - fsp_display_upd_value("SataPortsEnable[0]", 1, - original->SataPortsEnable[0], params->SataPortsEnable[0]); - fsp_display_upd_value("SataPortsEnable[1]", 1, - original->SataPortsEnable[1], params->SataPortsEnable[1]); - fsp_display_upd_value("SataPortsEnable[2]", 1, - original->SataPortsEnable[2], params->SataPortsEnable[2]); - fsp_display_upd_value("SataPortsEnable[3]", 1, - original->SataPortsEnable[3], params->SataPortsEnable[3]); - fsp_display_upd_value("SataPortsEnable[4]", 1, - original->SataPortsEnable[4], params->SataPortsEnable[4]); - fsp_display_upd_value("SataPortsEnable[5]", 1, - original->SataPortsEnable[5], params->SataPortsEnable[5]); - fsp_display_upd_value("SataPortsEnable[6]", 1, - original->SataPortsEnable[6], params->SataPortsEnable[6]); - fsp_display_upd_value("SataPortsEnable[7]", 1, - original->SataPortsEnable[7], params->SataPortsEnable[7]); - fsp_display_upd_value("SataPortsDevSlp[0]", 1, - original->SataPortsDevSlp[0], params->SataPortsDevSlp[0]); - fsp_display_upd_value("SataPortsDevSlp[1]", 1, - original->SataPortsDevSlp[1], params->SataPortsDevSlp[1]); - fsp_display_upd_value("SataPortsDevSlp[2]", 1, - original->SataPortsDevSlp[2], params->SataPortsDevSlp[2]); - fsp_display_upd_value("SataPortsDevSlp[3]", 1, - original->SataPortsDevSlp[3], params->SataPortsDevSlp[3]); - fsp_display_upd_value("SataPortsDevSlp[4]", 1, - original->SataPortsDevSlp[4], params->SataPortsDevSlp[4]); - fsp_display_upd_value("SataPortsDevSlp[5]", 1, - original->SataPortsDevSlp[5], params->SataPortsDevSlp[5]); - fsp_display_upd_value("SataPortsDevSlp[6]", 1, - original->SataPortsDevSlp[6], params->SataPortsDevSlp[6]); - fsp_display_upd_value("SataPortsDevSlp[7]", 1, - original->SataPortsDevSlp[7], params->SataPortsDevSlp[7]); - fsp_display_upd_value("EnableAzalia", 1, - original->EnableAzalia, params->EnableAzalia); - fsp_display_upd_value("DspEnable", 1, original->DspEnable, - params->DspEnable); - fsp_display_upd_value("IoBufferOwnership", 1, - original->IoBufferOwnership, params->IoBufferOwnership); - fsp_display_upd_value("PortUsb20Enable[0]", 1, - original->PortUsb20Enable[0], params->PortUsb20Enable[0]); - fsp_display_upd_value("PortUsb20Enable[1]", 1, - original->PortUsb20Enable[1], params->PortUsb20Enable[1]); - fsp_display_upd_value("PortUsb20Enable[2]", 1, - original->PortUsb20Enable[2], params->PortUsb20Enable[2]); - fsp_display_upd_value("PortUsb20Enable[3]", 1, - original->PortUsb20Enable[3], params->PortUsb20Enable[3]); - fsp_display_upd_value("PortUsb20Enable[4]", 1, - original->PortUsb20Enable[4], params->PortUsb20Enable[4]); - fsp_display_upd_value("PortUsb20Enable[5]", 1, - original->PortUsb20Enable[5], params->PortUsb20Enable[5]); - fsp_display_upd_value("PortUsb20Enable[6]", 1, - original->PortUsb20Enable[6], params->PortUsb20Enable[6]); - fsp_display_upd_value("PortUsb20Enable[7]", 1, - original->PortUsb20Enable[7], params->PortUsb20Enable[7]); - fsp_display_upd_value("PortUsb20Enable[8]", 1, - original->PortUsb20Enable[8], params->PortUsb20Enable[8]); - fsp_display_upd_value("PortUsb20Enable[9]", 1, - original->PortUsb20Enable[9], params->PortUsb20Enable[9]); - fsp_display_upd_value("PortUsb20Enable[10]", 1, - original->PortUsb20Enable[10], params->PortUsb20Enable[10]); - fsp_display_upd_value("PortUsb20Enable[11]", 1, - original->PortUsb20Enable[11], params->PortUsb20Enable[11]); - fsp_display_upd_value("PortUsb20Enable[12]", 1, - original->PortUsb20Enable[12], params->PortUsb20Enable[12]); - fsp_display_upd_value("PortUsb20Enable[13]", 1, - original->PortUsb20Enable[13], params->PortUsb20Enable[13]); - fsp_display_upd_value("PortUsb20Enable[14]", 1, - original->PortUsb20Enable[14], params->PortUsb20Enable[14]); - fsp_display_upd_value("PortUsb20Enable[15]", 1, - original->PortUsb20Enable[15], params->PortUsb20Enable[15]); - fsp_display_upd_value("PortUsb30Enable[0]", 1, - original->PortUsb30Enable[0], params->PortUsb30Enable[0]); - fsp_display_upd_value("PortUsb30Enable[1]", 1, - original->PortUsb30Enable[1], params->PortUsb30Enable[1]); - fsp_display_upd_value("PortUsb30Enable[2]", 1, - original->PortUsb30Enable[2], params->PortUsb30Enable[2]); - fsp_display_upd_value("PortUsb30Enable[3]", 1, - original->PortUsb30Enable[3], params->PortUsb30Enable[3]); - fsp_display_upd_value("PortUsb30Enable[4]", 1, - original->PortUsb30Enable[4], params->PortUsb30Enable[4]); - fsp_display_upd_value("PortUsb30Enable[5]", 1, - original->PortUsb30Enable[5], params->PortUsb30Enable[5]); - fsp_display_upd_value("PortUsb30Enable[6]", 1, - original->PortUsb30Enable[6], params->PortUsb30Enable[6]); - fsp_display_upd_value("PortUsb30Enable[7]", 1, - original->PortUsb30Enable[7], params->PortUsb30Enable[7]); - fsp_display_upd_value("PortUsb30Enable[8]", 1, - original->PortUsb30Enable[8], params->PortUsb30Enable[8]); - fsp_display_upd_value("PortUsb30Enable[9]", 1, - original->PortUsb30Enable[9], params->PortUsb30Enable[9]); - fsp_display_upd_value("XdciEnable", 1, original->XdciEnable, - params->XdciEnable); - fsp_display_upd_value("SsicPortEnable", 1, original->SsicPortEnable, - params->SsicPortEnable); - fsp_display_upd_value("SmbusEnable", 1, original->SmbusEnable, - params->SmbusEnable); - fsp_display_upd_value("SerialIoDevMode[0]", 1, - original->SerialIoDevMode[0], params->SerialIoDevMode[0]); - fsp_display_upd_value("SerialIoDevMode[1]", 1, - original->SerialIoDevMode[1], params->SerialIoDevMode[1]); - fsp_display_upd_value("SerialIoDevMode[2]", 1, - original->SerialIoDevMode[2], params->SerialIoDevMode[2]); - fsp_display_upd_value("SerialIoDevMode[3]", 1, - original->SerialIoDevMode[3], params->SerialIoDevMode[3]); - fsp_display_upd_value("SerialIoDevMode[4]", 1, - original->SerialIoDevMode[4], params->SerialIoDevMode[4]); - fsp_display_upd_value("SerialIoDevMode[5]", 1, - original->SerialIoDevMode[5], params->SerialIoDevMode[5]); - fsp_display_upd_value("SerialIoDevMode[6]", 1, - original->SerialIoDevMode[6], params->SerialIoDevMode[6]); - fsp_display_upd_value("SerialIoDevMode[7]", 1, - original->SerialIoDevMode[7], params->SerialIoDevMode[7]); - fsp_display_upd_value("SerialIoDevMode[8]", 1, - original->SerialIoDevMode[8], params->SerialIoDevMode[8]); - fsp_display_upd_value("SerialIoDevMode[9]", 1, - original->SerialIoDevMode[9], params->SerialIoDevMode[9]); - fsp_display_upd_value("SerialIoDevMode[10]", 1, - original->SerialIoDevMode[10], params->SerialIoDevMode[10]); - fsp_display_upd_value("ScsEmmcEnabled", 1, original->ScsEmmcEnabled, - params->ScsEmmcEnabled); - fsp_display_upd_value("ScsEmmcHs400Enabled", 1, - original->ScsEmmcHs400Enabled, params->ScsEmmcHs400Enabled); - fsp_display_upd_value("ScsSdCardEnabled", 1, original->ScsSdCardEnabled, - params->ScsSdCardEnabled); - fsp_display_upd_value("IshEnable", 1, original->IshEnable, - params->IshEnable); - fsp_display_upd_value("ShowSpiController", 1, - original->ShowSpiController, params->ShowSpiController); - fsp_display_upd_value("HsioMessaging", 1, original->HsioMessaging, - params->HsioMessaging); - fsp_display_upd_value("Heci3Enabled", 1, original->Heci3Enabled, - params->Heci3Enabled); - fsp_display_upd_value("EnableSata", 1, original->EnableSata, - params->EnableSata); - fsp_display_upd_value("SataMode", 1, original->SataMode, - params->SataMode); - fsp_display_upd_value("NumOfDevIntConfig", 1, - original->NumOfDevIntConfig, - params->NumOfDevIntConfig); - fsp_display_upd_value("PxRcConfig[PARC]", 1, - original->PxRcConfig[PCH_PARC], - params->PxRcConfig[PCH_PARC]); - fsp_display_upd_value("PxRcConfig[PBRC]", 1, - original->PxRcConfig[PCH_PBRC], - params->PxRcConfig[PCH_PBRC]); - fsp_display_upd_value("PxRcConfig[PCRC]", 1, - original->PxRcConfig[PCH_PCRC], - params->PxRcConfig[PCH_PCRC]); - fsp_display_upd_value("PxRcConfig[PDRC]", 1, - original->PxRcConfig[PCH_PDRC], - params->PxRcConfig[PCH_PDRC]); - fsp_display_upd_value("PxRcConfig[PERC]", 1, - original->PxRcConfig[PCH_PERC], - params->PxRcConfig[PCH_PERC]); - fsp_display_upd_value("PxRcConfig[PFRC]", 1, - original->PxRcConfig[PCH_PFRC], - params->PxRcConfig[PCH_PFRC]); - fsp_display_upd_value("PxRcConfig[PGRC]", 1, - original->PxRcConfig[PCH_PGRC], - params->PxRcConfig[PCH_PGRC]); - fsp_display_upd_value("PxRcConfig[PHRC]", 1, - original->PxRcConfig[PCH_PHRC], - params->PxRcConfig[PCH_PHRC]); - fsp_display_upd_value("GpioIrqRoute", 1, - original->GpioIrqRoute, - params->GpioIrqRoute); - fsp_display_upd_value("SciIrqSelect", 1, - original->SciIrqSelect, - params->SciIrqSelect); - fsp_display_upd_value("TcoIrqSelect", 1, - original->TcoIrqSelect, - params->TcoIrqSelect); - fsp_display_upd_value("TcoIrqEnable", 1, - original->TcoIrqEnable, - params->TcoIrqEnable); - fsp_display_upd_value("LockDownConfigGlobalSmi", 1, - original->LockDownConfigGlobalSmi, - params->LockDownConfigGlobalSmi); - fsp_display_upd_value("LockDownConfigBiosInterface", 1, - original->LockDownConfigBiosInterface, - params->LockDownConfigBiosInterface); - fsp_display_upd_value("LockDownConfigRtcLock", 1, - original->LockDownConfigRtcLock, - params->LockDownConfigRtcLock); - fsp_display_upd_value("LockDownConfigBiosLock", 1, - original->LockDownConfigBiosLock, - params->LockDownConfigBiosLock); - fsp_display_upd_value("LockDownConfigSpiEiss", 1, - original->LockDownConfigSpiEiss, - params->LockDownConfigSpiEiss); - fsp_display_upd_value("PchConfigSubSystemVendorId", 1, - original->PchConfigSubSystemVendorId, - params->PchConfigSubSystemVendorId); - fsp_display_upd_value("PchConfigSubSystemId", 1, - original->PchConfigSubSystemId, - params->PchConfigSubSystemId); - fsp_display_upd_value("WakeConfigWolEnableOverride", 1, - original->WakeConfigWolEnableOverride, - params->WakeConfigWolEnableOverride); - fsp_display_upd_value("WakeConfigPcieWakeFromDeepSx", 1, - original->WakeConfigPcieWakeFromDeepSx, - params->WakeConfigPcieWakeFromDeepSx); - fsp_display_upd_value("PmConfigDeepSxPol", 1, - original->PmConfigDeepSxPol, - params->PmConfigDeepSxPol); - fsp_display_upd_value("PmConfigSlpS3MinAssert", 1, - original->PmConfigSlpS3MinAssert, - params->PmConfigSlpS3MinAssert); - fsp_display_upd_value("PmConfigSlpS4MinAssert", 1, - original->PmConfigSlpS4MinAssert, - params->PmConfigSlpS4MinAssert); - fsp_display_upd_value("PmConfigSlpSusMinAssert", 1, - original->PmConfigSlpSusMinAssert, - params->PmConfigSlpSusMinAssert); - fsp_display_upd_value("PmConfigSlpAMinAssert", 1, - original->PmConfigSlpAMinAssert, - params->PmConfigSlpAMinAssert); - fsp_display_upd_value("PmConfigPciClockRun", 1, - original->PmConfigPciClockRun, - params->PmConfigPciClockRun); - fsp_display_upd_value("PmConfigSlpStrchSusUp", 1, - original->PmConfigSlpStrchSusUp, - params->PmConfigSlpStrchSusUp); - fsp_display_upd_value("PmConfigPwrBtnOverridePeriod", 1, - original->PmConfigPwrBtnOverridePeriod, - params->PmConfigPwrBtnOverridePeriod); - fsp_display_upd_value("PmConfigPwrCycDur", 1, - original->PmConfigPwrCycDur, - params->PmConfigPwrCycDur); - fsp_display_upd_value("SerialIrqConfigSirqEnable", 1, - original->SerialIrqConfigSirqEnable, - params->SerialIrqConfigSirqEnable); - fsp_display_upd_value("SerialIrqConfigSirqMode", 1, - original->SerialIrqConfigSirqMode, - params->SerialIrqConfigSirqMode); - fsp_display_upd_value("SerialIrqConfigStartFramePulse", 1, - original->SerialIrqConfigStartFramePulse, - params->SerialIrqConfigStartFramePulse); - - fsp_display_upd_value("Psi1Threshold[0]", 1, - original->Psi1Threshold[0], - params->Psi1Threshold[0]); - fsp_display_upd_value("Psi1Threshold[1]", 1, - original->Psi1Threshold[1], - params->Psi1Threshold[1]); - fsp_display_upd_value("Psi1Threshold[2]", 1, - original->Psi1Threshold[2], - params->Psi1Threshold[2]); - fsp_display_upd_value("Psi1Threshold[3]", 1, - original->Psi1Threshold[3], - params->Psi1Threshold[3]); - fsp_display_upd_value("Psi1Threshold[4]", 1, - original->Psi1Threshold[4], - params->Psi1Threshold[4]); - fsp_display_upd_value("Psi2Threshold[0]", 1, - original->Psi2Threshold[0], - params->Psi2Threshold[0]); - fsp_display_upd_value("Psi2Threshold[1]", 1, - original->Psi2Threshold[1], - params->Psi2Threshold[1]); - fsp_display_upd_value("Psi2Threshold[2]", 1, - original->Psi2Threshold[2], - params->Psi2Threshold[2]); - fsp_display_upd_value("Psi2Threshold[3]", 1, - original->Psi2Threshold[3], - params->Psi2Threshold[3]); - fsp_display_upd_value("Psi2Threshold[4]", 1, - original->Psi2Threshold[4], - params->Psi2Threshold[4]); - fsp_display_upd_value("Psi3Threshold[0]", 1, - original->Psi3Threshold[0], - params->Psi3Threshold[0]); - fsp_display_upd_value("Psi3Threshold[1]", 1, - original->Psi3Threshold[1], - params->Psi3Threshold[1]); - fsp_display_upd_value("Psi3Threshold[2]", 1, - original->Psi3Threshold[2], - params->Psi3Threshold[2]); - fsp_display_upd_value("Psi3Threshold[3]", 1, - original->Psi3Threshold[3], - params->Psi3Threshold[3]); - fsp_display_upd_value("Psi3Threshold[4]", 1, - original->Psi3Threshold[4], - params->Psi3Threshold[4]); - fsp_display_upd_value("Psi3Enable[0]", 1, - original->Psi3Enable[0], - params->Psi3Enable[0]); - fsp_display_upd_value("Psi3Enable[1]", 1, - original->Psi3Enable[1], - params->Psi3Enable[1]); - fsp_display_upd_value("Psi3Enable[2]", 1, - original->Psi3Enable[2], - params->Psi3Enable[2]); - fsp_display_upd_value("Psi3Enable[3]", 1, - original->Psi3Enable[3], - params->Psi3Enable[3]); - fsp_display_upd_value("Psi3Enable[4]", 1, - original->Psi3Enable[4], - params->Psi3Enable[4]); - fsp_display_upd_value("Psi4Enable[0]", 1, - original->Psi4Enable[0], - params->Psi4Enable[0]); - fsp_display_upd_value("Psi4Enable[1]", 1, - original->Psi4Enable[1], - params->Psi4Enable[1]); - fsp_display_upd_value("Psi4Enable[2]", 1, - original->Psi4Enable[2], - params->Psi4Enable[2]); - fsp_display_upd_value("Psi4Enable[3]", 1, - original->Psi4Enable[3], - params->Psi4Enable[3]); - fsp_display_upd_value("Psi4Enable[4]", 1, - original->Psi4Enable[4], - params->Psi4Enable[4]); - fsp_display_upd_value("ImonSlope[0]", 1, - original->ImonSlope[0], - params->ImonSlope[0]); - fsp_display_upd_value("ImonSlope[1]", 1, - original->ImonSlope[1], - params->ImonSlope[1]); - fsp_display_upd_value("ImonSlope[2]", 1, - original->ImonSlope[2], - params->ImonSlope[2]); - fsp_display_upd_value("ImonSlope[3]", 1, - original->ImonSlope[3], - params->ImonSlope[3]); - fsp_display_upd_value("ImonSlope[4]", 1, - original->ImonSlope[4], - params->ImonSlope[4]); - fsp_display_upd_value("ImonOffse[0]t", 1, - original->ImonOffset[0], - params->ImonOffset[0]); - fsp_display_upd_value("ImonOffse[1]t", 1, - original->ImonOffset[1], - params->ImonOffset[1]); - fsp_display_upd_value("ImonOffse[2]t", 1, - original->ImonOffset[2], - params->ImonOffset[2]); - fsp_display_upd_value("ImonOffse[3]t", 1, - original->ImonOffset[3], - params->ImonOffset[3]); - fsp_display_upd_value("ImonOffse[4]t", 1, - original->ImonOffset[4], - params->ImonOffset[4]); - fsp_display_upd_value("IccMax[0]", 1, - original->IccMax[0], - params->IccMax[0]); - fsp_display_upd_value("IccMax[1]", 1, - original->IccMax[1], - params->IccMax[1]); - fsp_display_upd_value("IccMax[2]", 1, - original->IccMax[2], - params->IccMax[2]); - fsp_display_upd_value("IccMax[3]", 1, - original->IccMax[3], - params->IccMax[3]); - fsp_display_upd_value("IccMax[4]", 1, - original->IccMax[4], - params->IccMax[4]); - fsp_display_upd_value("VrVoltageLimit[0]", 1, - original->VrVoltageLimit[0], - params->VrVoltageLimit[0]); - fsp_display_upd_value("VrVoltageLimit[1]", 1, - original->VrVoltageLimit[1], - params->VrVoltageLimit[1]); - fsp_display_upd_value("VrVoltageLimit[2]", 1, - original->VrVoltageLimit[2], - params->VrVoltageLimit[2]); - fsp_display_upd_value("VrVoltageLimit[3]", 1, - original->VrVoltageLimit[3], - params->VrVoltageLimit[3]); - fsp_display_upd_value("VrVoltageLimit[4]", 1, - original->VrVoltageLimit[4], - params->VrVoltageLimit[4]); - fsp_display_upd_value("VrConfigEnable[0]", 1, - original->VrConfigEnable[0], - params->VrConfigEnable[0]); - fsp_display_upd_value("VrConfigEnable[1]", 1, - original->VrConfigEnable[1], - params->VrConfigEnable[1]); - fsp_display_upd_value("VrConfigEnable[2]", 1, - original->VrConfigEnable[2], - params->VrConfigEnable[2]); - fsp_display_upd_value("VrConfigEnable[3]", 1, - original->VrConfigEnable[3], - params->VrConfigEnable[3]); - fsp_display_upd_value("VrConfigEnable[4]", 1, - original->VrConfigEnable[4], - params->VrConfigEnable[4]); - fsp_display_upd_value("SerialIoI2cVoltage[0]", 1, - original->SerialIoI2cVoltage[0], - params->SerialIoI2cVoltage[0]); - fsp_display_upd_value("SerialIoI2cVoltage[1]", 1, - original->SerialIoI2cVoltage[1], - params->SerialIoI2cVoltage[1]); - fsp_display_upd_value("SerialIoI2cVoltage[2]", 1, - original->SerialIoI2cVoltage[2], - params->SerialIoI2cVoltage[2]); - fsp_display_upd_value("SerialIoI2cVoltage[3]", 1, - original->SerialIoI2cVoltage[3], - params->SerialIoI2cVoltage[3]); - fsp_display_upd_value("SerialIoI2cVoltage[4]", 1, - original->SerialIoI2cVoltage[4], - params->SerialIoI2cVoltage[4]); - fsp_display_upd_value("SerialIoI2cVoltage[5]", 1, - original->SerialIoI2cVoltage[5], - params->SerialIoI2cVoltage[5]); - fsp_display_upd_value("SendVrMbxCmd", 1, - original->SendVrMbxCmd, - params->SendVrMbxCmd); - fsp_display_upd_value("AcousticNoiseMitigation", 1, - original->AcousticNoiseMitigation, - params->AcousticNoiseMitigation); - fsp_display_upd_value("SlowSlewRateForIa", 1, - original->SlowSlewRateForIa, - params->SlowSlewRateForIa); - fsp_display_upd_value("SlowSlewRateForGt", 1, - original->SlowSlewRateForGt, - params->SlowSlewRateForGt); - fsp_display_upd_value("SlowSlewRateForSa", 1, - original->SlowSlewRateForSa, - params->SlowSlewRateForSa); - fsp_display_upd_value("FastPkgCRampDisable", 1, - original->FastPkgCRampDisable, - params->FastPkgCRampDisable); + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c deleted file mode 100644 index 55fedd3cf5..0000000000 --- a/src/soc/intel/skylake/chip_fsp20.c +++ /dev/null @@ -1,511 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016-2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "chip.h" - -struct pcie_entry { - unsigned int devfn; - unsigned int func_count; -}; - -/* - * According to table 2-2 in doc#546717: - * PCI bus[function] ID - * D28:[F0 - F7] 0xA110 - 0xA117 - * D29:[F0 - F7] 0xA118 - 0xA11F - * D27:[F0 - F3] 0xA167 - 0xA16A - */ -static const struct pcie_entry pcie_table_skl_pch_h[] = { - {PCH_DEVFN_PCIE1, 8}, - {PCH_DEVFN_PCIE9, 8}, - {PCH_DEVFN_PCIE17, 4}, -}; - -/* - * According to table 2-2 in doc#564464: - * PCI bus[function] ID - * D28:[F0 - F7] 0xA290 - 0xA297 - * D29:[F0 - F7] 0xA298 - 0xA29F - * D27:[F0 - F7] 0xA2E7 - 0xA2EE - */ -static const struct pcie_entry pcie_table_kbl_pch_h[] = { - {PCH_DEVFN_PCIE1, 8}, - {PCH_DEVFN_PCIE9, 8}, - {PCH_DEVFN_PCIE17, 8}, -}; - -/* - * According to table 2-2 in doc#567995/545659: - * PCI bus[function] ID - * D28:[F0 - F7] 0x9D10 - 0x9D17 - * D29:[F0 - F3] 0x9D18 - 0x9D1B - */ -static const struct pcie_entry pcie_table_skl_pch_lp[] = { - {PCH_DEVFN_PCIE1, 8}, - {PCH_DEVFN_PCIE9, 4}, -}; - -/* - * If the PCIe root port at function 0 is disabled, - * the PCIe root ports might be coalesced after FSP silicon init. - * The below function will swap the devfn of the first enabled device - * in devicetree and function 0 resides a pci device - * so that it won't confuse coreboot. - */ -static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group, - size_t pci_groups) -{ - struct device *func0; - unsigned int devfn, devfn0; - int i, group; - unsigned int inc = PCI_DEVFN(0, 1); - - for (group = 0; group < pci_groups; group++) { - devfn0 = pcie_rp_group[group].devfn; - func0 = pcidev_path_on_root(devfn0); - if (func0 == NULL) - continue; - - /* No more functions if function 0 is disabled. */ - if (pci_read_config32(func0, PCI_VENDOR_ID) == 0xffffffff) - continue; - - devfn = devfn0 + inc; - - /* - * Increase function by 1. - * Then find first enabled device to replace func0 - * as that port was move to func0. - */ - for (i = 1; i < pcie_rp_group[group].func_count; - i++, devfn += inc) { - struct device *dev = pcidev_path_on_root(devfn); - if (dev == NULL || !dev->enabled) - continue; - - /* - * Found the first enabled device in - * a given dev number. - */ - printk(BIOS_INFO, "PCI func %d was swapped" - " to func 0.\n", i); - func0->path.pci.devfn = dev->path.pci.devfn; - dev->path.pci.devfn = devfn0; - break; - } - } -} - -static void pcie_override_devicetree_after_silicon_init(void) -{ - uint16_t id, id_mask; - - id = pci_read_config16(PCH_DEV_PCIE1, PCI_DEVICE_ID); - /* - * We may read an ID other than func 0 after FSP-S. - * Strip out 4 least significant bits. - */ - id_mask = id & ~0xf; - printk(BIOS_INFO, "Override DT after FSP-S, PCH is "); - if (id_mask == (PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 & ~0xf)) { - printk(BIOS_INFO, "KBL/SKL PCH-LP SKU\n"); - pcie_update_device_tree(&pcie_table_skl_pch_lp[0], - ARRAY_SIZE(pcie_table_skl_pch_lp)); - } else if (id_mask == (PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1 & ~0xf)) { - printk(BIOS_INFO, "KBL PCH-H SKU\n"); - pcie_update_device_tree(&pcie_table_kbl_pch_h[0], - ARRAY_SIZE(pcie_table_kbl_pch_h)); - } else if (id_mask == (PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1 & ~0xf)) { - printk(BIOS_INFO, "SKL PCH-H SKU\n"); - pcie_update_device_tree(&pcie_table_skl_pch_h[0], - ARRAY_SIZE(pcie_table_skl_pch_h)); - } else { - printk(BIOS_ERR, "[BUG] PCIE Root Port id 0x%x" - " is not found\n", id); - return; - } -} - -void soc_init_pre_device(void *chip_info) -{ - /* Snapshot the current GPIO IRQ polarities. FSP is setting a - * default policy that doesn't honor boards' requirements. */ - itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - - /* Perform silicon specific init. */ - fsp_silicon_init(romstage_handoff_is_resume()); - - /* Restore GPIO IRQ polarities back to previous settings. */ - itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - - /* swap enabled PCI ports in device tree if needed */ - pcie_override_devicetree_after_silicon_init(); -} - -void soc_fsp_load(void) -{ - fsps_load(romstage_handoff_is_resume()); -} - -static void pci_domain_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - -static struct device_operations pci_domain_ops = { - .read_resources = &pci_domain_read_resources, - .set_resources = &pci_domain_set_resources, - .scan_bus = &pci_domain_scan_bus, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = &northbridge_write_acpi_tables, - .acpi_name = &soc_acpi_name, -#endif -}; - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = DEVICE_NOOP, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt_generator = generate_cpu_entries, -#endif -}; - -static void soc_enable(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) - dev->ops = &pci_domain_ops; - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) - dev->ops = &cpu_bus_ops; -} - -struct chip_operations soc_intel_skylake_ops = { - CHIP_NAME("Intel 6th Gen") - .enable_dev = &soc_enable, - .init = &soc_init_pre_device, -}; - -/* UPD parameters to be initialized before SiliconInit */ -void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) -{ - FSP_S_CONFIG *params = &supd->FspsConfig; - FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; - struct soc_intel_skylake_config *config; - struct device *dev; - uintptr_t vbt_data = (uintptr_t)vbt_get(); - int i; - - config = config_of_soc(); - - mainboard_silicon_init_params(params); - /* Set PsysPmax if it is available from DT */ - if (config->psys_pmax) { - /* PsysPmax is in unit of 1/8 Watt */ - tconfig->PsysPmax = config->psys_pmax * 8; - printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax); - } - - params->GraphicsConfigPtr = (u32) vbt_data; - - for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { - params->PortUsb20Enable[i] = - config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = - config->usb2_ports[i].ocpin; - params->Usb2AfePetxiset[i] = - config->usb2_ports[i].pre_emp_bias; - params->Usb2AfeTxiset[i] = - config->usb2_ports[i].tx_bias; - params->Usb2AfePredeemp[i] = - config->usb2_ports[i].tx_emp_enable; - params->Usb2AfePehalfbit[i] = - config->usb2_ports[i].pre_emp_bit; - } - - for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { - params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; - if (config->usb3_ports[i].tx_de_emp) { - params->Usb3HsioTxDeEmphEnable[i] = 1; - params->Usb3HsioTxDeEmph[i] = - config->usb3_ports[i].tx_de_emp; - } - if (config->usb3_ports[i].tx_downscale_amp) { - params->Usb3HsioTxDownscaleAmpEnable[i] = 1; - params->Usb3HsioTxDownscaleAmp[i] = - config->usb3_ports[i].tx_downscale_amp; - } - } - - memcpy(params->SataPortsEnable, config->SataPortsEnable, - sizeof(params->SataPortsEnable)); - memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, - sizeof(params->SataPortsDevSlp)); - memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, - sizeof(params->SataPortsHotPlug)); - memcpy(params->SataPortsSpinUp, config->SataPortsSpinUp, - sizeof(params->SataPortsSpinUp)); - memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, - sizeof(params->PcieRpClkReqSupport)); - memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, - sizeof(params->PcieRpClkReqNumber)); - memcpy(params->PcieRpAdvancedErrorReporting, - config->PcieRpAdvancedErrorReporting, - sizeof(params->PcieRpAdvancedErrorReporting)); - memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, - sizeof(params->PcieRpLtrEnable)); - memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, - sizeof(params->PcieRpHotPlug)); - - /* - * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for - * all the enabled PCIe root ports, invalid(0x1F) is set for - * disabled PCIe root ports. - */ - for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { - if (config->PcieRpClkReqSupport[i]) - params->PcieRpClkSrcNumber[i] = - config->PcieRpClkSrcNumber[i]; - else - params->PcieRpClkSrcNumber[i] = 0x1F; - } - - /* disable Legacy PME */ - memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); - - /* Legacy 8254 timer support */ - params->Early8254ClockGatingEnable = !CONFIG_USE_LEGACY_8254_TIMER; - - memcpy(params->SerialIoDevMode, config->SerialIoDevMode, - sizeof(params->SerialIoDevMode)); - - params->PchCio2Enable = config->Cio2Enable; - params->SaImguEnable = config->SaImguEnable; - params->Heci3Enabled = config->Heci3Enabled; - - params->LogoPtr = config->LogoPtr; - params->LogoSize = config->LogoSize; - - params->CpuConfig.Bits.VmxEnable = CONFIG(ENABLE_VMX); - - params->PchPmWoWlanEnable = config->PchPmWoWlanEnable; - params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; - params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; - - params->PchLanEnable = config->EnableLan; - if (config->EnableLan) { - params->PchLanLtrEnable = config->EnableLanLtr; - params->PchLanK1OffEnable = config->EnableLanK1Off; - params->PchLanClkReqSupported = config->LanClkReqSupported; - params->PchLanClkReqNumber = config->LanClkReqNumber; - } - params->SataSalpSupport = config->SataSalpSupport; - params->SsicPortEnable = config->SsicPortEnable; - params->ScsEmmcEnabled = config->ScsEmmcEnabled; - params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; - params->ScsSdCardEnabled = config->ScsSdCardEnabled; - - if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) { - params->PchScsEmmcHs400DllDataValid = - !!config->EmmcHs400DllNeed; - params->PchScsEmmcHs400RxStrobeDll1 = - config->ScsEmmcHs400RxStrobeDll1; - params->PchScsEmmcHs400TxDataDll = - config->ScsEmmcHs400TxDataDll; - } - - /* If ISH is enabled, enable ISH elements */ - dev = pcidev_path_on_root(PCH_DEVFN_ISH); - params->PchIshEnable = dev ? dev->enabled : 0; - - params->PchHdaEnable = config->EnableAzalia; - params->PchHdaVcType = config->PchHdaVcType; - params->PchHdaIoBufferOwnership = config->IoBufferOwnership; - params->PchHdaDspEnable = config->DspEnable; - params->Device4Enable = config->Device4Enable; - params->SataEnable = config->EnableSata; - params->SataMode = config->SataMode; - params->SataSpeedLimit = config->SataSpeedLimit; - params->SataPwrOptEnable = config->SataPwrOptEnable; - params->EnableTcoTimer = !config->PmTimerDisabled; - - tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; - tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; - tconfig->PowerLimit4 = config->PowerLimit4; - tconfig->SataTestMode = config->SataTestMode; - /* - * To disable HECI, the Psf needs to be left unlocked - * by FSP till end of post sequence. Based on the devicetree - * setting, we set the appropriate PsfUnlock policy in FSP, - * do the changes and then lock it back in coreboot during finalize. - */ - tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; - if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { - tconfig->PchLockDownBiosInterface = 0; - params->PchLockDownBiosLock = 0; - params->PchLockDownSpiEiss = 0; - /* - * Skip Spi Flash Lockdown from inside FSP. - * Making this config "0" means FSP won't set the FLOCKDN bit - * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). - * So, it becomes coreboot's responsibility to set this bit - * before end of POST for security concerns. - */ - params->SpiFlashCfgLockDown = 0; - } - /* only replacing preexisting subsys ID defaults when non-zero */ - if (CONFIG_SUBSYSTEM_VENDOR_ID != 0) { - params->DefaultSvid = CONFIG_SUBSYSTEM_VENDOR_ID; - params->PchSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID; - } - - if (CONFIG_SUBSYSTEM_DEVICE_ID != 0) { - params->DefaultSid = CONFIG_SUBSYSTEM_DEVICE_ID; - params->PchSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; - } - - params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; - params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; - params->PchPmDeepSxPol = config->PmConfigDeepSxPol; - params->PchPmSlpS0Enable = config->s0ix_enable; - params->PchPmSlpS3MinAssert = config->PmConfigSlpS3MinAssert; - params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert; - params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert; - params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; - params->PchPmLpcClockRun = config->PmConfigPciClockRun; - params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; - params->PchPmPwrBtnOverridePeriod = - config->PmConfigPwrBtnOverridePeriod; - params->PchPmPwrCycDur = config->PmConfigPwrCycDur; - - /* Indicate whether platform supports Voltage Margining */ - params->PchPmSlpS0VmEnable = config->PchPmSlpS0VmEnable; - - params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF; - params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS; - - params->CpuConfig.Bits.SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; - - for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++) - params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; - - for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) - fill_vr_domain_config(params, i, &config->domain_vr_config[i]); - - /* Show SPI controller if enabled in devicetree.cb */ - dev = pcidev_path_on_root(PCH_DEVFN_SPI); - params->ShowSpiController = dev ? dev->enabled : 0; - - /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); - if (dev) { - if (!xdci_can_enable()) - dev->enabled = 0; - params->XdciEnable = dev->enabled; - } else { - params->XdciEnable = 0; - } - - /* Enable or disable Gaussian Mixture Model in devicetree */ - dev = pcidev_path_on_root(SA_DEVFN_GMM); - params->GmmEnable = dev ? dev->enabled : 0; - - /* - * Send VR specific mailbox commands: - * 000b - no VR specific command sent - * 001b - VR mailbox command specifically for the MPS IMPV8 VR - * will be sent - * 010b - VR specific command sent for PS4 exit issue - * 100b - VR specific command sent for MPS VR decay issue - */ - params->SendVrMbxCmd1 = config->SendVrMbxCmd; - - /* - * Activates VR mailbox command for Intersil VR C-state issues. - * 0 - no mailbox command sent. - * 1 - VR mailbox command sent for IA/GT rails only. - * 2 - VR mailbox command sent for IA/GT/SA rails. - */ - params->IslVrCmd = config->IslVrCmd; - - /* Acoustic Noise Mitigation */ - params->AcousticNoiseMitigation = config->AcousticNoiseMitigation; - params->SlowSlewRateForIa = config->SlowSlewRateForIa; - params->SlowSlewRateForGt = config->SlowSlewRateForGt; - params->SlowSlewRateForSa = config->SlowSlewRateForSa; - params->FastPkgCRampDisableIa = config->FastPkgCRampDisableIa; - params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt; - params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa; - - /* Enable PMC XRAM read */ - tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; - - /* Enable/Disable EIST */ - tconfig->Eist = config->eist_enable; - - /* Set TccActivationOffset */ - tconfig->TccActivationOffset = config->tcc_offset; - - /* Enable VT-d and X2APIC */ - if (!config->ignore_vtd && soc_is_vtd_capable()) { - params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; - params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS; - params->X2ApicOptOut = 0; - tconfig->VtdDisable = 0; - - params->PchIoApicBdfValid = 1; - params->PchIoApicBusNumber = V_P2SB_IBDF_BUS; - params->PchIoApicDeviceNumber = V_P2SB_IBDF_DEV; - params->PchIoApicFunctionNumber = V_P2SB_IBDF_FUN; - } - - soc_irq_settings(params); -} - -/* Mainboard GPIO Configuration */ -__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); -} diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5424c91c58..bfed528a06 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -414,15 +414,36 @@ static void enable_pm_timer_emulation(void) * frequency is used. */ msr.hi = (3579545ULL << 32) / CTC_FREQ; - /* Set PM1 timer IO port and enable*/ + /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); wrmsr(MSR_EMULATE_PM_TIMER, msr); } +/* + * Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended disabling + * as suggested in Intel document 325384-070US. + */ +static void cpu_lock_aesni(void) +{ + msr_t msr; + + /* Only run once per core as specified in the MSR datasheet */ + if (intel_ht_sibling()) + return; + + msr = rdmsr(MSR_FEATURE_CONFIG); + if ((msr.lo & 1) == 0) { + msr.lo |= 1; + wrmsr(MSR_FEATURE_CONFIG, msr); + } +} + /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { + config_t *conf = config_of_soc(); + /* Clear out pending MCEs */ /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears @@ -442,6 +463,9 @@ void soc_core_init(struct device *cpu) /* Configure Intel Speed Shift */ configure_isst(); + /* Lock AES-NI MSR */ + cpu_lock_aesni(); + /* Enable ACPI Timer Emulation via MSR 0x121 */ enable_pm_timer_emulation(); @@ -455,7 +479,8 @@ void soc_core_init(struct device *cpu) enable_turbo(); /* Configure Core PRMRR for SGX. */ - prmrr_core_configure(); + if (conf->sgx_enable) + prmrr_core_configure(); } static void per_cpu_smm_trigger(void) @@ -477,6 +502,7 @@ static void fc_lock_configure(void *unused) static void post_mp_init(void) { int ret = 0; + config_t *conf = config_of_soc(); /* Set Max Ratio */ cpu_set_max_ratio(); @@ -493,7 +519,8 @@ static void post_mp_init(void) ret |= mp_run_on_all_cpus(vmx_configure, NULL); - ret |= mp_run_on_all_cpus(sgx_configure, NULL); + if (conf->sgx_enable) + ret |= mp_run_on_all_cpus(sgx_configure, NULL); ret |= mp_run_on_all_cpus(fc_lock_configure, NULL); @@ -548,22 +575,3 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) return (msr1.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1); } - -void cpu_lock_sgx_memory(void) -{ - msr_t msr; - - msr = rdmsr(MSR_LT_LOCK_MEMORY); - if ((msr.lo & 1) == 0) { - msr.lo |= 1; /* Lock it */ - wrmsr(MSR_LT_LOCK_MEMORY, msr); - } -} - -int soc_fill_sgx_param(struct sgx_param *sgx_param) -{ - config_t *conf = config_of_soc(); - - sgx_param->enable = conf->sgx_enable; - return 0; -} diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 47d6137ec7..795139418d 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -121,7 +121,7 @@ static void pch_log_pme_internal_wake_source(void) #define RP_PME_STS_BIT (1 << 16) static void pch_log_rp_wake_source(void) { - size_t i; + size_t i, maxports; #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev; #else @@ -142,9 +142,23 @@ static void pch_log_rp_wake_source(void) { PCH_DEV_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 }, { PCH_DEV_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 }, { PCH_DEV_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 }, + { PCH_DEV_PCIE13, 0x60, ELOG_WAKE_SOURCE_PME_PCIE13 }, + { PCH_DEV_PCIE14, 0x60, ELOG_WAKE_SOURCE_PME_PCIE14 }, + { PCH_DEV_PCIE15, 0x60, ELOG_WAKE_SOURCE_PME_PCIE15 }, + { PCH_DEV_PCIE16, 0x60, ELOG_WAKE_SOURCE_PME_PCIE16 }, + { PCH_DEV_PCIE17, 0x60, ELOG_WAKE_SOURCE_PME_PCIE17 }, + { PCH_DEV_PCIE18, 0x60, ELOG_WAKE_SOURCE_PME_PCIE18 }, + { PCH_DEV_PCIE19, 0x60, ELOG_WAKE_SOURCE_PME_PCIE19 }, + { PCH_DEV_PCIE20, 0x60, ELOG_WAKE_SOURCE_PME_PCIE20 }, + { PCH_DEV_PCIE21, 0x60, ELOG_WAKE_SOURCE_PME_PCIE21 }, + { PCH_DEV_PCIE22, 0x60, ELOG_WAKE_SOURCE_PME_PCIE22 }, + { PCH_DEV_PCIE23, 0x60, ELOG_WAKE_SOURCE_PME_PCIE23 }, + { PCH_DEV_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 }, }; - for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) { + maxports = min(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info)); + + for (i = 0; i < maxports; i++) { dev = pme_status_info[i].dev; if (!dev) diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 0d6f7370a5..58a87012d7 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -46,14 +47,6 @@ #define PCR_PSFX_T0_SHDW_PCIEN 0x1C #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) -static void disable_sideband_access(void) -{ - p2sb_disable_sideband_access(); - - /* hide p2sb device */ - p2sb_hide(); -} - static void pch_disable_heci(void) { /* unhide p2sb device */ @@ -63,7 +56,7 @@ static void pch_disable_heci(void) pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN, PCR_PSFX_T0_SHDW_PCIEN_FUNDIS); - disable_sideband_access(); + p2sb_disable_sideband_access(); } static void pch_finalize_script(struct device *dev) @@ -113,6 +106,9 @@ static void pch_finalize_script(struct device *dev) /* we should disable Heci1 based on the devicetree policy */ if (config->HeciEnabled == 0) pch_disable_heci(); + + /* Hide p2sb device as the OS must not change BAR0. */ + p2sb_hide(); } static void soc_lockdown(struct device *dev) @@ -128,6 +124,9 @@ static void soc_lockdown(struct device *dev) reg8 |= SMI_LOCK; pci_write_config8(dev, GEN_PMCON_A, reg8); } + + /* Lock chipset memory registers to protect SMM */ + mp_run_on_all_cpus(cpu_lt_lock_memory, NULL); } static void soc_finalize(void *unused) diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h deleted file mode 100644 index 2071d58b49..0000000000 --- a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_RAMSTAGE_H_ -#define _SOC_RAMSTAGE_H_ - -#include -#include -#include - -#include "../../../chip.h" - -#define FSP_SIL_UPD SILICON_INIT_UPD -#define FSP_MEM_UPD MEMORY_INIT_UPD - -void soc_irq_settings(FSP_SIL_UPD *params); -void soc_init_pre_device(void *chip_info); -void soc_fsp_load(void); -const char *soc_acpi_name(const struct device *dev); - -/* Get igd framebuffer bar */ -uintptr_t fsp_soc_get_igd_bar(void); - -#endif diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index 74328b217e..a40f439936 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -18,12 +18,6 @@ #include -#if CONFIG(PLATFORM_USES_FSP1_1) -#include -#else -static inline void bootblock_fsp_temp_ram_init(void) {} -#endif - /* Bootblock pre console init programming */ void bootblock_cpu_init(void); void bootblock_pch_early_init(void); diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 615edac097..18b0c15d64 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -169,14 +169,6 @@ struct chipset_power_state { uint32_t prev_sleep_state; } __packed; -/* - * This is used only in FSP1_1 as we wanted to keep the flow unchanged. - * Internally fill_power_state calls the new pmc_fill_power_state now - */ -#if CONFIG(PLATFORM_USES_FSP1_1) -struct chipset_power_state *fill_power_state(void); -#endif - /* Return the selected ACPI SCI IRQ */ int acpi_sci_irq(void); diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h similarity index 97% rename from src/soc/intel/skylake/include/fsp20/soc/ramstage.h rename to src/soc/intel/skylake/include/soc/ramstage.h index e5660a6f66..4157c4e09b 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ b/src/soc/intel/skylake/include/soc/ramstage.h @@ -21,7 +21,7 @@ #include #include -#include "../../../chip.h" +#include "../../chip.h" #define FSP_SIL_UPD FSP_S_CONFIG #define FSP_MEM_UPD FSP_M_CONFIG diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h similarity index 100% rename from src/soc/intel/skylake/include/fsp20/soc/romstage.h rename to src/soc/intel/skylake/include/soc/romstage.h diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index aebbbdff4a..5bd649cefc 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -19,11 +19,7 @@ #ifndef _SOC_VR_CONFIG_H_ #define _SOC_VR_CONFIG_H_ -#if CONFIG(PLATFORM_USES_FSP1_1) -#include -#else #include -#endif struct vr_config { @@ -70,20 +66,6 @@ struct vr_config { #define VR_CFG_AMP(i) ((i) * 4) #define VR_CFG_MOHMS(i) (uint16_t)((i) * 100) -#if CONFIG(PLATFORM_USES_FSP1_1) -/* VrConfig Settings for 5 domains - * 0 = System Agent, 1 = IA Core, 2 = Ring, - * 3 = GT unsliced, 4 = GT sliced - */ -enum vr_domain { - VR_SYSTEM_AGENT, - VR_IA_CORE, - VR_RING, - VR_GT_UNSLICED, - VR_GT_SLICED, - NUM_VR_DOMAINS -}; -#else /* VrConfig Settings for 4 domains * 0 = System Agent, 1 = IA Core, * 2 = GT unsliced, 3 = GT sliced @@ -95,7 +77,23 @@ enum vr_domain { VR_GT_SLICED, NUM_VR_DOMAINS }; -#endif + +#define VR_CFG_ALL_DOMAINS_ICC(sa, ia, gt_unsl, gt_sl) \ + { \ + [VR_SYSTEM_AGENT] = VR_CFG_AMP(sa), \ + [VR_IA_CORE] = VR_CFG_AMP(ia), \ + [VR_GT_UNSLICED] = VR_CFG_AMP(gt_unsl), \ + [VR_GT_SLICED] = VR_CFG_AMP(gt_sl), \ + } + +#define VR_CFG_ALL_DOMAINS_LOADLINE(sa, ia, gt_unsl, gt_sl) \ + { \ + [VR_SYSTEM_AGENT] = VR_CFG_MOHMS(sa), \ + [VR_IA_CORE] = VR_CFG_MOHMS(ia), \ + [VR_GT_UNSLICED] = VR_CFG_MOHMS(gt_unsl), \ + [VR_GT_SLICED] = VR_CFG_MOHMS(gt_sl), \ + } + void fill_vr_domain_config(void *params, int domain, const struct vr_config *cfg); diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 5a378a2954..f90a165051 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -24,7 +24,6 @@ #include #include #include -#include /* HFSTS1[3:0] Current Working State Values */ diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 29f2517468..09dc6e9f0d 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -32,12 +32,6 @@ #include "chip.h" -void smm_region(uintptr_t *start, size_t *size) -{ - *start = sa_get_tseg_base(); - *size = sa_get_tseg_size(); -} - static bool is_ptt_enable(void) { if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == @@ -84,12 +78,7 @@ static size_t get_prmrr_size(uintptr_t dram_base, const struct soc_intel_skylake_config *config) { uintptr_t prmrr_base = dram_base; - size_t prmrr_size; - - if (CONFIG(PLATFORM_USES_FSP1_1)) - prmrr_size = 1*MiB; - else - prmrr_size = config->PrmrrSize; + size_t prmrr_size = config->PrmrrSize; if (!prmrr_size) return 0; @@ -217,21 +206,6 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size) return dram_base; } -/* - * SoC implementation - * - * SoC call to summarize all Intel Reserve MMIO size and report to SA - */ -size_t soc_reserved_mmio_size(void) -{ - struct ebda_config cfg; - - retrieve_ebda_object(&cfg); - - /* Get Intel Reserved Memory Range Size */ - return cfg.reserved_mem_size; -} - /* Fill up memory layout information */ void fill_soc_memmap_ebda(struct ebda_config *cfg) { @@ -274,41 +248,11 @@ void cbmem_top_init(void) * | | * +-------------------------+ */ -void *cbmem_top(void) +void *cbmem_top_chipset(void) { struct ebda_config ebda_cfg; - /* - * Check if Tseg has been initialized, we will use this as a flag - * to check if the MRC is done, and only then continue to read the - * PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before - * PRMRR_MASK MSR lock bit is set. - */ - if (sa_get_tseg_base() == 0) - return NULL; - retrieve_ebda_object(&ebda_cfg); return (void *)(uintptr_t)ebda_cfg.tolum_base; } - -#if CONFIG(PLATFORM_USES_FSP2_0) -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); -} -#endif diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 7bb9d4bc03..dff89ce2dc 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,4 +1,3 @@ romstage-y += ../../../../cpu/intel/car/romstage.c -romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c +romstage-y += romstage.c romstage-y += systemagent.c diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index f354af3442..af89441194 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,76 +13,314 @@ * GNU General Public License for more details. */ -#include +#include +#include #include +#include +#include +#include #include -#include -#include -#include #include -#include +#include #include +#include +#include +#include +#include #include #include -#include -#include #include -#include -#include -#include -#include +#include +#include +#include #include "../chip.h" -/* SOC initialization before RAM is enabled */ -void soc_pre_ram_init(struct romstage_params *params) -{ - const struct soc_intel_skylake_config *config; - - /* Program MCHBAR and DMIBAR */ - systemagent_early_init(); - - config = config_of_soc(); - - /* Force a full memory train if RMT is enabled */ - params->disable_saved_data = config->Rmt; +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ + 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } -/* UPD parameters to be initialized before MemoryInit */ -void soc_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *upd) +/* Memory Channel Present Status */ +enum { + CHANNEL_NOT_PRESENT, + CHANNEL_DISABLED, + CHANNEL_PRESENT +}; + +/* Save the DIMM information for SMBIOS table 17 */ +static void save_dimm_info(void) { - const struct soc_intel_skylake_config *config; + int channel, dimm, dimm_max, index; + size_t hob_size; + uint8_t ddr_type; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const MEMORY_INFO_DATA_HOB *memory_info_hob; + const uint8_t smbios_memory_info_guid[16] = + FSP_SMBIOS_MEMORY_INFO_GUID; - /* Set the parameters for MemoryInit */ - - config = config_of_soc(); + /* Locate the memory info HOB, presence validated by raminit */ + memory_info_hob = + fsp_find_extension_hob_by_guid(smbios_memory_info_guid, + &hob_size); + if (memory_info_hob == NULL || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } /* - * Set IGD stolen size to 64MB. The FBC hardware for skylake does not - * have access to the bios_reserved range so it always assumes 8MB is - * used and so the kernel will avoid the last 8MB of the stolen window. - * With the default stolen size of 32MB(-8MB) there is not enough space - * for FBC to work with a high resolution panel. + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 */ - upd->IgdDvmt50PreAlloc = 2; + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); - upd->MmioSize = 0x800; /* 2GB in MB */ - upd->TsegSize = CONFIG_SMM_TSEG_SIZE; - upd->IedSize = CONFIG_IED_REGION_SIZE; - upd->ProbelessTrace = config->ProbelessTrace; - upd->EnableTraceHub = config->EnableTraceHub; - if (vboot_recovery_mode_enabled()) - upd->SaGv = 0; /* Disable SaGv in recovery mode. */ - else - upd->SaGv = config->SaGv; - upd->RMT = config->Rmt; - upd->DdrFreqLimit = config->DdrFreqLimit; - upd->FspCarBase = CONFIG_DCACHE_RAM_BASE; - upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE; + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + ctrlr_info = &memory_info_hob->Controller[0]; + for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + if (channel_info->Status != CHANNEL_PRESENT) + continue; + for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + + if (src_dimm->Status != DIMM_PRESENT) + continue; + + switch (memory_info_hob->MemoryType) { + case MRC_DDR_TYPE_DDR4: + ddr_type = MEMORY_TYPE_DDR4; + break; + case MRC_DDR_TYPE_DDR3: + ddr_type = MEMORY_TYPE_DDR3; + break; + case MRC_DDR_TYPE_LPDDR3: + ddr_type = MEMORY_TYPE_LPDDR3; + break; + default: + ddr_type = MEMORY_TYPE_UNKNOWN; + break; + } + u8 memProfNum = memory_info_hob->MemoryProfile; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + ddr_type, + memory_info_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, + channel_info->ChannelId, + src_dimm->DimmId, + (const char *)src_dimm->ModulePartNum, + sizeof(src_dimm->ModulePartNum), + src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType); + index++; + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg, +void mainboard_romstage_entry(void) +{ + bool s3wake; + struct chipset_power_state *ps; + + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ + systemagent_early_init(); + + ps = pmc_get_power_state(); + s3wake = pmc_fill_power_state(ps) == ACPI_S3; + fsp_memory_init(s3wake); + pmc_set_disb(); + if (!s3wake) + save_dimm_info(); +} + +static void cpu_flex_override(FSP_M_CONFIG *m_cfg) +{ + msr_t flex_ratio; + m_cfg->CpuRatioOverride = 1; + /* + * Set cpuratio to that value set in bootblock, This will ensure FSPM + * knows the intended flex ratio. + */ + flex_ratio = rdmsr(MSR_FLEX_RATIO); + m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; +} + +static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, + FSP_M_TEST_CONFIG *m_t_cfg, + const struct soc_intel_skylake_config *config) +{ + const struct device *dev; + /* + * To enable or disable the corresponding PEG root port you need to + * add to the devicetree.cb: + * + * device pci 01.0 on end # enable PEG0 root port + * device pci 01.1 off end # do not configure PEG1 + * + * If PEG port is not defined in the device tree, it will be disabled + * in FSP + */ + dev = pcidev_on_root(SA_DEV_SLOT_PEG, 0); /* PEG 0:1:0 */ + if (!dev || !dev->enabled) + m_cfg->Peg0Enable = 0; + else if (dev->enabled) { + m_cfg->Peg0Enable = dev->enabled; + m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth; + /* Use maximum possible link speed */ + m_cfg->Peg0MaxLinkSpeed = 0; + /* Power down unused lanes based on the max possible width */ + m_cfg->Peg0PowerDownUnusedLanes = 1; + /* Set [Auto] for options to enable equalization methods */ + m_t_cfg->Peg0Gen3EqPh2Enable = 2; + m_t_cfg->Peg0Gen3EqPh3Method = 0; + } + + dev = pcidev_on_root(SA_DEV_SLOT_PEG, 1); /* PEG 0:1:1 */ + if (!dev || !dev->enabled) + m_cfg->Peg1Enable = 0; + else if (dev->enabled) { + m_cfg->Peg1Enable = dev->enabled; + m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth; + m_cfg->Peg1MaxLinkSpeed = 0; + m_cfg->Peg1PowerDownUnusedLanes = 1; + m_t_cfg->Peg1Gen3EqPh2Enable = 2; + m_t_cfg->Peg1Gen3EqPh3Method = 0; + } + + dev = pcidev_on_root(SA_DEV_SLOT_PEG, 2); /* PEG 0:1:2 */ + if (!dev || !dev->enabled) + m_cfg->Peg2Enable = 0; + else if (dev->enabled) { + m_cfg->Peg2Enable = dev->enabled; + m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth; + m_cfg->Peg2MaxLinkSpeed = 0; + m_cfg->Peg2PowerDownUnusedLanes = 1; + m_t_cfg->Peg2Gen3EqPh2Enable = 2; + m_t_cfg->Peg2Gen3EqPh3Method = 0; + } +} + +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_skylake_config *config) +{ + int i; + uint32_t mask = 0; + + m_cfg->MmioSize = 0x800; /* 2GB in MB */ + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->ProbelessTrace = config->ProbelessTrace; + m_cfg->SaGv = config->SaGv; + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; + m_cfg->RMT = config->Rmt; + m_cfg->CmdTriStateDis = config->CmdTriStateDis; + m_cfg->DdrFreqLimit = config->DdrFreqLimit; + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + m_cfg->PrmrrSize = config->PrmrrSize; + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1<PcieRpEnableMask = mask; + + cpu_flex_override(m_cfg); + + if (!config->ignore_vtd) { + m_cfg->PchHpetBdfValid = 1; + m_cfg->PchHpetBusNumber = V_P2SB_HBDF_BUS; + m_cfg->PchHpetDeviceNumber = V_P2SB_HBDF_DEV; + m_cfg->PchHpetFunctionNumber = V_P2SB_HBDF_FUN; + } + m_cfg->HyperThreading = CONFIG(FSP_HYPERTHREADING); +} + +static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_skylake_config *config) +{ + const struct device *dev; + + dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (!dev || !dev->enabled) { + /* + * If iGPU is disabled or not defined in the devicetree.cb, + * the FSP does not initialize this device + */ + m_cfg->InternalGfx = 0; + m_cfg->IgdDvmt50PreAlloc = 0; + } else { + m_cfg->InternalGfx = 1; + /* + * Set IGD stolen size to 64MB. The FBC hardware for skylake + * does not have access to the bios_reserved range so it always + * assumes 8MB is used and so the kernel will avoid the last + * 8MB of the stolen window. With the default stolen size of + * 32MB(-8MB) there is not enough space for FBC to work with + * a high resolution panel + */ + m_cfg->IgdDvmt50PreAlloc = 2; + } + m_cfg->PrimaryDisplay = config->PrimaryDisplay; +} + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + const struct soc_intel_skylake_config *config; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; + + config = config_of_soc(); + + soc_memory_init_params(m_cfg, config); + soc_peg_init_params(m_cfg, m_t_cfg, config); + + /* Skip creating Management Engine MBP HOB */ + m_t_cfg->SkipMbpHob = 0x01; + + /* Enable DMI Virtual Channel for ME */ + m_t_cfg->DmiVcm = 0x01; + + /* Enable Sending DID to ME */ + m_t_cfg->SendDidMsg = 0x01; + m_t_cfg->DidInitStat = 0x01; + + /* DCI and TraceHub configs */ + m_t_cfg->PchDciEn = config->PchDciEn; + m_cfg->EnableTraceHub = config->EnableTraceHub; + m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; + m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; + + /* Enable SMBus controller based on config */ + m_cfg->SmbusEnable = config->SmbusEnable; + + /* Set primary graphic device */ + soc_primary_gfx_config_params(m_cfg, config); + m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan; + + mainboard_memory_init_params(mupd); +} + +void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, struct mma_config_param *mma_cfg) { /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ @@ -101,161 +338,7 @@ void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg, memory_cfg->SaGv = 0x02; } -void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, - MEMORY_INIT_UPD *new) +__weak void mainboard_memory_init_params(FSPM_UPD *mupd) { - /* Display the parameters for MemoryInit */ - printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); - - fsp_display_upd_value("PlatformMemorySize", 8, - old->PlatformMemorySize, new->PlatformMemorySize); - fsp_display_upd_value("MemorySpdPtr00", 4, old->MemorySpdPtr00, - new->MemorySpdPtr00); - fsp_display_upd_value("MemorySpdPtr01", 4, old->MemorySpdPtr01, - new->MemorySpdPtr01); - fsp_display_upd_value("MemorySpdPtr10", 4, old->MemorySpdPtr10, - new->MemorySpdPtr10); - fsp_display_upd_value("MemorySpdPtr11", 4, old->MemorySpdPtr11, - new->MemorySpdPtr11); - fsp_display_upd_value("MemorySpdDataLen", 2, old->MemorySpdDataLen, - new->MemorySpdDataLen); - fsp_display_upd_value("DqByteMapCh0[0]", 1, old->DqByteMapCh0[0], - new->DqByteMapCh0[0]); - fsp_display_upd_value("DqByteMapCh0[1]", 1, old->DqByteMapCh0[1], - new->DqByteMapCh0[1]); - fsp_display_upd_value("DqByteMapCh0[2]", 1, old->DqByteMapCh0[2], - new->DqByteMapCh0[2]); - fsp_display_upd_value("DqByteMapCh0[3]", 1, old->DqByteMapCh0[3], - new->DqByteMapCh0[3]); - fsp_display_upd_value("DqByteMapCh0[4]", 1, old->DqByteMapCh0[4], - new->DqByteMapCh0[4]); - fsp_display_upd_value("DqByteMapCh0[5]", 1, old->DqByteMapCh0[5], - new->DqByteMapCh0[5]); - fsp_display_upd_value("DqByteMapCh0[6]", 1, old->DqByteMapCh0[6], - new->DqByteMapCh0[6]); - fsp_display_upd_value("DqByteMapCh0[7]", 1, old->DqByteMapCh0[7], - new->DqByteMapCh0[7]); - fsp_display_upd_value("DqByteMapCh0[8]", 1, old->DqByteMapCh0[8], - new->DqByteMapCh0[8]); - fsp_display_upd_value("DqByteMapCh0[9]", 1, old->DqByteMapCh0[9], - new->DqByteMapCh0[9]); - fsp_display_upd_value("DqByteMapCh0[10]", 1, old->DqByteMapCh0[10], - new->DqByteMapCh0[10]); - fsp_display_upd_value("DqByteMapCh0[11]", 1, old->DqByteMapCh0[11], - new->DqByteMapCh0[11]); - fsp_display_upd_value("DqByteMapCh1[0]", 1, old->DqByteMapCh1[0], - new->DqByteMapCh1[0]); - fsp_display_upd_value("DqByteMapCh1[1]", 1, old->DqByteMapCh1[1], - new->DqByteMapCh1[1]); - fsp_display_upd_value("DqByteMapCh1[2]", 1, old->DqByteMapCh1[2], - new->DqByteMapCh1[2]); - fsp_display_upd_value("DqByteMapCh1[3]", 1, old->DqByteMapCh1[3], - new->DqByteMapCh1[3]); - fsp_display_upd_value("DqByteMapCh1[4]", 1, old->DqByteMapCh1[4], - new->DqByteMapCh1[4]); - fsp_display_upd_value("DqByteMapCh1[5]", 1, old->DqByteMapCh1[5], - new->DqByteMapCh1[5]); - fsp_display_upd_value("DqByteMapCh1[6]", 1, old->DqByteMapCh1[6], - new->DqByteMapCh1[6]); - fsp_display_upd_value("DqByteMapCh1[7]", 1, old->DqByteMapCh1[7], - new->DqByteMapCh1[7]); - fsp_display_upd_value("DqByteMapCh1[8]", 1, old->DqByteMapCh1[8], - new->DqByteMapCh1[8]); - fsp_display_upd_value("DqByteMapCh1[9]", 1, old->DqByteMapCh1[9], - new->DqByteMapCh1[9]); - fsp_display_upd_value("DqByteMapCh1[10]", 1, old->DqByteMapCh1[10], - new->DqByteMapCh1[10]); - fsp_display_upd_value("DqByteMapCh1[11]", 1, old->DqByteMapCh1[11], - new->DqByteMapCh1[11]); - fsp_display_upd_value("DqsMapCpu2DramCh0[0]", 1, - old->DqsMapCpu2DramCh0[0], new->DqsMapCpu2DramCh0[0]); - fsp_display_upd_value("DqsMapCpu2DramCh0[1]", 1, - old->DqsMapCpu2DramCh0[1], new->DqsMapCpu2DramCh0[1]); - fsp_display_upd_value("DqsMapCpu2DramCh0[2]", 1, - old->DqsMapCpu2DramCh0[2], new->DqsMapCpu2DramCh0[2]); - fsp_display_upd_value("DqsMapCpu2DramCh0[3]", 1, - old->DqsMapCpu2DramCh0[3], new->DqsMapCpu2DramCh0[3]); - fsp_display_upd_value("DqsMapCpu2DramCh0[4]", 1, - old->DqsMapCpu2DramCh0[4], new->DqsMapCpu2DramCh0[4]); - fsp_display_upd_value("DqsMapCpu2DramCh0[5]", 1, - old->DqsMapCpu2DramCh0[5], new->DqsMapCpu2DramCh0[5]); - fsp_display_upd_value("DqsMapCpu2DramCh0[6]", 1, - old->DqsMapCpu2DramCh0[6], new->DqsMapCpu2DramCh0[6]); - fsp_display_upd_value("DqsMapCpu2DramCh0[7]", 1, - old->DqsMapCpu2DramCh0[7], new->DqsMapCpu2DramCh0[7]); - fsp_display_upd_value("DqsMapCpu2DramCh1[0]", 1, - old->DqsMapCpu2DramCh1[0], new->DqsMapCpu2DramCh1[0]); - fsp_display_upd_value("DqsMapCpu2DramCh1[1]", 1, - old->DqsMapCpu2DramCh1[1], new->DqsMapCpu2DramCh1[1]); - fsp_display_upd_value("DqsMapCpu2DramCh1[2]", 1, - old->DqsMapCpu2DramCh1[2], new->DqsMapCpu2DramCh1[2]); - fsp_display_upd_value("DqsMapCpu2DramCh1[3]", 1, - old->DqsMapCpu2DramCh1[3], new->DqsMapCpu2DramCh1[3]); - fsp_display_upd_value("DqsMapCpu2DramCh1[4]", 1, - old->DqsMapCpu2DramCh1[4], new->DqsMapCpu2DramCh1[4]); - fsp_display_upd_value("DqsMapCpu2DramCh1[5]", 1, - old->DqsMapCpu2DramCh1[5], new->DqsMapCpu2DramCh1[5]); - fsp_display_upd_value("DqsMapCpu2DramCh1[6]", 1, - old->DqsMapCpu2DramCh1[6], new->DqsMapCpu2DramCh1[6]); - fsp_display_upd_value("DqsMapCpu2DramCh1[7]", 1, - old->DqsMapCpu2DramCh1[7], new->DqsMapCpu2DramCh1[7]); - fsp_display_upd_value("DqPinsInterleaved", 1, - old->DqPinsInterleaved, new->DqPinsInterleaved); - fsp_display_upd_value("RcompResistor[0]", 2, old->RcompResistor[0], - new->RcompResistor[0]); - fsp_display_upd_value("RcompResistor[1]", 2, old->RcompResistor[1], - new->RcompResistor[1]); - fsp_display_upd_value("RcompResistor[2]", 2, old->RcompResistor[2], - new->RcompResistor[2]); - fsp_display_upd_value("RcompTarget[0]", 1, old->RcompTarget[0], - new->RcompTarget[0]); - fsp_display_upd_value("RcompTarget[1]", 1, old->RcompTarget[1], - new->RcompTarget[1]); - fsp_display_upd_value("RcompTarget[2]", 1, old->RcompTarget[2], - new->RcompTarget[2]); - fsp_display_upd_value("RcompTarget[3]", 1, old->RcompTarget[3], - new->RcompTarget[3]); - fsp_display_upd_value("RcompTarget[4]", 1, old->RcompTarget[4], - new->RcompTarget[4]); - fsp_display_upd_value("CaVrefConfig", 1, old->CaVrefConfig, - new->CaVrefConfig); - fsp_display_upd_value("SmramMask", 1, old->SmramMask, new->SmramMask); - fsp_display_upd_value("MrcFastBoot", 1, old->MrcFastBoot, - new->MrcFastBoot); - fsp_display_upd_value("IedSize", 4, old->IedSize, new->IedSize); - fsp_display_upd_value("TsegSize", 4, old->TsegSize, new->TsegSize); - fsp_display_upd_value("MmioSize", 2, old->MmioSize, new->MmioSize); - fsp_display_upd_value("EnableTraceHub", 1, old->EnableTraceHub, - new->EnableTraceHub); - fsp_display_upd_value("IgdDvmt50PreAlloc", 1, old->IgdDvmt50PreAlloc, - new->IgdDvmt50PreAlloc); - fsp_display_upd_value("InternalGfx", 1, old->InternalGfx, - new->InternalGfx); - fsp_display_upd_value("ApertureSize", 1, old->ApertureSize, - new->ApertureSize); - fsp_display_upd_value("SaGv", 1, old->SaGv, new->SaGv); - fsp_display_upd_value("RMT", 1, old->RMT, new->RMT); - fsp_display_upd_value("FspCarBase", 1, old->FspCarBase, - new->FspCarBase); - fsp_display_upd_value("FspCarSize", 1, old->FspCarSize, - new->FspCarSize); -} - -/* SOC initialization after RAM is enabled. */ -void soc_after_ram_init(struct romstage_params *params) -{ - /* Set the DISB as soon as possible after DRAM - * init and MRC cache is saved. - */ - pmc_set_disb(); -} - -struct chipset_power_state *fill_power_state(void) -{ - struct chipset_power_state *ps; - - ps = pmc_get_power_state(); - pmc_fill_power_state(ps); - - return ps; + /* Do nothing */ } diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c deleted file mode 100644 index af89441194..0000000000 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ /dev/null @@ -1,344 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../chip.h" - -#define FSP_SMBIOS_MEMORY_INFO_GUID \ -{ \ - 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ - 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ -} - -/* Memory Channel Present Status */ -enum { - CHANNEL_NOT_PRESENT, - CHANNEL_DISABLED, - CHANNEL_PRESENT -}; - -/* Save the DIMM information for SMBIOS table 17 */ -static void save_dimm_info(void) -{ - int channel, dimm, dimm_max, index; - size_t hob_size; - uint8_t ddr_type; - const CONTROLLER_INFO *ctrlr_info; - const CHANNEL_INFO *channel_info; - const DIMM_INFO *src_dimm; - struct dimm_info *dest_dimm; - struct memory_info *mem_info; - const MEMORY_INFO_DATA_HOB *memory_info_hob; - const uint8_t smbios_memory_info_guid[16] = - FSP_SMBIOS_MEMORY_INFO_GUID; - - /* Locate the memory info HOB, presence validated by raminit */ - memory_info_hob = - fsp_find_extension_hob_by_guid(smbios_memory_info_guid, - &hob_size); - if (memory_info_hob == NULL || hob_size == 0) { - printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); - return; - } - - /* - * Allocate CBMEM area for DIMM information used to populate SMBIOS - * table 17 - */ - mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); - if (mem_info == NULL) { - printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); - return; - } - memset(mem_info, 0, sizeof(*mem_info)); - - /* Describe the first N DIMMs in the system */ - index = 0; - dimm_max = ARRAY_SIZE(mem_info->dimm); - ctrlr_info = &memory_info_hob->Controller[0]; - for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { - channel_info = &ctrlr_info->ChannelInfo[channel]; - if (channel_info->Status != CHANNEL_PRESENT) - continue; - for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { - src_dimm = &channel_info->DimmInfo[dimm]; - dest_dimm = &mem_info->dimm[index]; - - if (src_dimm->Status != DIMM_PRESENT) - continue; - - switch (memory_info_hob->MemoryType) { - case MRC_DDR_TYPE_DDR4: - ddr_type = MEMORY_TYPE_DDR4; - break; - case MRC_DDR_TYPE_DDR3: - ddr_type = MEMORY_TYPE_DDR3; - break; - case MRC_DDR_TYPE_LPDDR3: - ddr_type = MEMORY_TYPE_LPDDR3; - break; - default: - ddr_type = MEMORY_TYPE_UNKNOWN; - break; - } - u8 memProfNum = memory_info_hob->MemoryProfile; - - /* Populate the DIMM information */ - dimm_info_fill(dest_dimm, - src_dimm->DimmCapacity, - ddr_type, - memory_info_hob->ConfiguredMemoryClockSpeed, - src_dimm->RankInDimm, - channel_info->ChannelId, - src_dimm->DimmId, - (const char *)src_dimm->ModulePartNum, - sizeof(src_dimm->ModulePartNum), - src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, - memory_info_hob->DataWidth, - memory_info_hob->VddVoltage[memProfNum], - memory_info_hob->EccSupport, - src_dimm->MfgId, - src_dimm->SpdModuleType); - index++; - } - } - mem_info->dimm_cnt = index; - printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); -} - -void mainboard_romstage_entry(void) -{ - bool s3wake; - struct chipset_power_state *ps; - - /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ - systemagent_early_init(); - - ps = pmc_get_power_state(); - s3wake = pmc_fill_power_state(ps) == ACPI_S3; - fsp_memory_init(s3wake); - pmc_set_disb(); - if (!s3wake) - save_dimm_info(); -} - -static void cpu_flex_override(FSP_M_CONFIG *m_cfg) -{ - msr_t flex_ratio; - m_cfg->CpuRatioOverride = 1; - /* - * Set cpuratio to that value set in bootblock, This will ensure FSPM - * knows the intended flex ratio. - */ - flex_ratio = rdmsr(MSR_FLEX_RATIO); - m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; -} - -static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, - FSP_M_TEST_CONFIG *m_t_cfg, - const struct soc_intel_skylake_config *config) -{ - const struct device *dev; - /* - * To enable or disable the corresponding PEG root port you need to - * add to the devicetree.cb: - * - * device pci 01.0 on end # enable PEG0 root port - * device pci 01.1 off end # do not configure PEG1 - * - * If PEG port is not defined in the device tree, it will be disabled - * in FSP - */ - dev = pcidev_on_root(SA_DEV_SLOT_PEG, 0); /* PEG 0:1:0 */ - if (!dev || !dev->enabled) - m_cfg->Peg0Enable = 0; - else if (dev->enabled) { - m_cfg->Peg0Enable = dev->enabled; - m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth; - /* Use maximum possible link speed */ - m_cfg->Peg0MaxLinkSpeed = 0; - /* Power down unused lanes based on the max possible width */ - m_cfg->Peg0PowerDownUnusedLanes = 1; - /* Set [Auto] for options to enable equalization methods */ - m_t_cfg->Peg0Gen3EqPh2Enable = 2; - m_t_cfg->Peg0Gen3EqPh3Method = 0; - } - - dev = pcidev_on_root(SA_DEV_SLOT_PEG, 1); /* PEG 0:1:1 */ - if (!dev || !dev->enabled) - m_cfg->Peg1Enable = 0; - else if (dev->enabled) { - m_cfg->Peg1Enable = dev->enabled; - m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth; - m_cfg->Peg1MaxLinkSpeed = 0; - m_cfg->Peg1PowerDownUnusedLanes = 1; - m_t_cfg->Peg1Gen3EqPh2Enable = 2; - m_t_cfg->Peg1Gen3EqPh3Method = 0; - } - - dev = pcidev_on_root(SA_DEV_SLOT_PEG, 2); /* PEG 0:1:2 */ - if (!dev || !dev->enabled) - m_cfg->Peg2Enable = 0; - else if (dev->enabled) { - m_cfg->Peg2Enable = dev->enabled; - m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth; - m_cfg->Peg2MaxLinkSpeed = 0; - m_cfg->Peg2PowerDownUnusedLanes = 1; - m_t_cfg->Peg2Gen3EqPh2Enable = 2; - m_t_cfg->Peg2Gen3EqPh3Method = 0; - } -} - -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, - const struct soc_intel_skylake_config *config) -{ - int i; - uint32_t mask = 0; - - m_cfg->MmioSize = 0x800; /* 2GB in MB */ - m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->IedSize = CONFIG_IED_REGION_SIZE; - m_cfg->ProbelessTrace = config->ProbelessTrace; - m_cfg->SaGv = config->SaGv; - m_cfg->UserBd = BOARD_TYPE_ULT_ULX; - m_cfg->RMT = config->Rmt; - m_cfg->CmdTriStateDis = config->CmdTriStateDis; - m_cfg->DdrFreqLimit = config->DdrFreqLimit; - m_cfg->VmxEnable = CONFIG(ENABLE_VMX); - m_cfg->PrmrrSize = config->PrmrrSize; - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1<PcieRpEnableMask = mask; - - cpu_flex_override(m_cfg); - - if (!config->ignore_vtd) { - m_cfg->PchHpetBdfValid = 1; - m_cfg->PchHpetBusNumber = V_P2SB_HBDF_BUS; - m_cfg->PchHpetDeviceNumber = V_P2SB_HBDF_DEV; - m_cfg->PchHpetFunctionNumber = V_P2SB_HBDF_FUN; - } - m_cfg->HyperThreading = CONFIG(FSP_HYPERTHREADING); -} - -static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg, - const struct soc_intel_skylake_config *config) -{ - const struct device *dev; - - dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (!dev || !dev->enabled) { - /* - * If iGPU is disabled or not defined in the devicetree.cb, - * the FSP does not initialize this device - */ - m_cfg->InternalGfx = 0; - m_cfg->IgdDvmt50PreAlloc = 0; - } else { - m_cfg->InternalGfx = 1; - /* - * Set IGD stolen size to 64MB. The FBC hardware for skylake - * does not have access to the bios_reserved range so it always - * assumes 8MB is used and so the kernel will avoid the last - * 8MB of the stolen window. With the default stolen size of - * 32MB(-8MB) there is not enough space for FBC to work with - * a high resolution panel - */ - m_cfg->IgdDvmt50PreAlloc = 2; - } - m_cfg->PrimaryDisplay = config->PrimaryDisplay; -} - -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -{ - const struct soc_intel_skylake_config *config; - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; - - config = config_of_soc(); - - soc_memory_init_params(m_cfg, config); - soc_peg_init_params(m_cfg, m_t_cfg, config); - - /* Skip creating Management Engine MBP HOB */ - m_t_cfg->SkipMbpHob = 0x01; - - /* Enable DMI Virtual Channel for ME */ - m_t_cfg->DmiVcm = 0x01; - - /* Enable Sending DID to ME */ - m_t_cfg->SendDidMsg = 0x01; - m_t_cfg->DidInitStat = 0x01; - - /* DCI and TraceHub configs */ - m_t_cfg->PchDciEn = config->PchDciEn; - m_cfg->EnableTraceHub = config->EnableTraceHub; - m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; - m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; - - /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; - - /* Set primary graphic device */ - soc_primary_gfx_config_params(m_cfg, config); - m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan; - - mainboard_memory_init_params(mupd); -} - -void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, - struct mma_config_param *mma_cfg) -{ - /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - - memory_cfg->MmaTestContentPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); - memory_cfg->MmaTestContentSize = - region_device_sz(&mma_cfg->test_content); - memory_cfg->MmaTestConfigPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); - memory_cfg->MmaTestConfigSize = - region_device_sz(&mma_cfg->test_param); - memory_cfg->MrcFastBoot = 0x00; - memory_cfg->SaGv = 0x02; -} - -__weak void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - /* Do nothing */ -} diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 089dd5d572..54dfd31ebe 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -48,20 +48,6 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { .icc_max = VR_CFG_AMP(34), .voltage_limit = 1520, }, -#if CONFIG(PLATFORM_USES_FSP1_1) - [VR_RING] = { - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 0, - .psi4enable = 0, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), - .voltage_limit = 1520, - }, -#endif [VR_GT_UNSLICED] = { .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -92,109 +78,141 @@ static uint16_t get_sku_icc_max(int domain) { const uint16_t tdp = cpu_get_power_max(); - static uint16_t mch_id = 0, igd_id = 0, lpc_id = 0; + static uint16_t mch_id = 0, igd_id = 0; if (!mch_id) { struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - mch_id = pci_read_config16(dev, PCI_DEVICE_ID); + mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; } if (!igd_id) { struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (dev) - igd_id = pci_read_config16(dev, PCI_DEVICE_ID); - else - igd_id = 0xffff; - } - if (!lpc_id) { - struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); - lpc_id = pci_read_config16(dev, PCI_DEVICE_ID); + igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; } /* * Iccmax table from Doc #559100 Section 7.2 DC Specifications, the * Iccmax is the same among KBL-Y but KBL-U/R. * Addendum for AML-Y #594883, IccMax for IA core is 28A. - * KBL-S #335195, KBL-H #335190 - * +----------------+-------------+---------------+------+-----+ - * | Domain/Setting | SA | IA | GTUS | GTS | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-S) | 11.1A | 100A | 45A | 45A | - * | | | ... | | | - * | | | 40A | | | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-H) | 11.1A(45W) | 68A | 55A | 55A | - * | | 6.6A(Others)| 60A | | | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A | - * | | 4.5A(Others)| 29A(P/C) | | | - * | | | 32A(i3/i5) | | | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(AML-Y) | 4.1A | 28A | 24A | 24A | - * +----------------+-------------+---------------+------+-----+ + * KBL-S #335195, KBL-H #335190, SKL-S #332687, SKL-H #332986, + * SKL-U/Y #332990 + * + * Platform Segment SA IA GT (GT/GTx) + * --------------------------------------------------------------------- + * KBL/SKL-S (95W) quad 11.1 100 45 + * SKL-S (80W) quad 11.1 82 45 + * KBL/SKL-S (65W) quad 11.1 79 45 + * SKL-S (45W) quad 11.1 70 0 + * KBL/SKL-S (35W) quad 11.1 66 35 + * SKL-S (25W) quad 11.1 55 35 + * + * KBL/SKL-S (54W) dual 11.1 58 48 + * KBL/SKL-S (51W) dual 11.1 45 48 + * KBL/SKL-S (35W) dual 11.1 40 48 + * + * SKL-H + OPC (65W) GT4 quad 8 74 105/24 + * SKL-H + OPC (45W) GT4 quad 8 74 94/20 + * SKL-H + OPC (35W) GT4 quad 8 66 94/20 + * + * SKL-H (35W) GT2 dual 11.1 60 55 + * + * KBL/SKL-H (45W) GT2 quad 11.1 68 55 + * KBL-H (18W) GT2 quad 6.6 60 55 + * + * SKL-U + OPC (28W) GT3 dual 5.1 32 57/19 + * SKL-U + OPC (15W) GT3 dual 5.1 29 57/19 + * SKL-U (15W) GT2 dual 4.5 29 31 + * + * KBL-U + OPC (28W) GT3 dual 5.1 32 57/19 + * KBL-U + OPC (15W) GT3 dual 5.1 32 57/19 + * KBL-U (15W) GT1/2 dual 4.5 32 31 + * KBL-U [*] (15W) GT1 quad 4.5 29 31 + * + * KBL-U/R (15W) GT2 quad 6 64 31 + * + * SKL/KBL-Y (6W) 4.1 24 24 + * SKL/KBL-Y (4.5W) 4.1 24 24 + * + * [*] Pentium/Celeron CPUs with HD Graphics 610 */ switch (mch_id) { + case PCI_DEVICE_ID_INTEL_SKL_ID_S_2: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_S: { - uint16_t icc_max[NUM_VR_DOMAINS] = { - VR_CFG_AMP(11.1), - VR_CFG_AMP(40), - VR_CFG_AMP(45), - VR_CFG_AMP(45), - }; + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 40, 48, 48); if (tdp >= 54) icc_max[VR_IA_CORE] = VR_CFG_AMP(58); else if (tdp >= 51) icc_max[VR_IA_CORE] = VR_CFG_AMP(45); return icc_max[domain]; - } + case PCI_DEVICE_ID_INTEL_SKL_ID_S_4: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_DT: { - uint16_t icc_max[NUM_VR_DOMAINS] = { - VR_CFG_AMP(11.1), - VR_CFG_AMP(66), - VR_CFG_AMP(55), - VR_CFG_AMP(55), - }; + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 55, 45, 45); if (tdp >= 91) icc_max[VR_IA_CORE] = VR_CFG_AMP(100); + else if (tdp >= 80) + icc_max[VR_IA_CORE] = VR_CFG_AMP(82); else if (tdp >= 65) icc_max[VR_IA_CORE] = VR_CFG_AMP(79); + else if (tdp >= 45) { + icc_max[VR_IA_CORE] = VR_CFG_AMP(70); + icc_max[VR_GT_SLICED] = 0; + icc_max[VR_GT_UNSLICED] = 0; + } else if (tdp >= 25) { + if (tdp >= 35) + icc_max[VR_IA_CORE] = VR_CFG_AMP(66); - return icc_max[domain]; - } - case PCI_DEVICE_ID_INTEL_KBL_ID_H: { - uint16_t icc_max[NUM_VR_DOMAINS] = { - VR_CFG_AMP(6.6), - VR_CFG_AMP(60), - VR_CFG_AMP(55), - VR_CFG_AMP(55), - }; - if (tdp >= 45) { - icc_max[VR_SYSTEM_AGENT] = VR_CFG_AMP(11.1); - icc_max[VR_IA_CORE] = VR_CFG_AMP(68); + icc_max[VR_GT_SLICED] = VR_CFG_AMP(35); + icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(35); } return icc_max[domain]; } - case PCI_DEVICE_ID_INTEL_KBL_U_R: { - static const uint16_t icc_max[NUM_VR_DOMAINS] = { - VR_CFG_AMP(6), - VR_CFG_AMP(64), - VR_CFG_AMP(31), - VR_CFG_AMP(31), - }; + case PCI_DEVICE_ID_INTEL_SKL_ID_H_4: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 60, 94, 20); + if (tdp >= 45) { + icc_max[VR_IA_CORE] = VR_CFG_AMP(74); + if (tdp >= 65) { + icc_max[VR_GT_SLICED] = VR_CFG_AMP(105); + icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(24); + } + } return icc_max[domain]; } + case PCI_DEVICE_ID_INTEL_SKL_ID_H_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_SKL_ID_H_EM: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_ID_H: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6.6, 60, 55, 55); + if (tdp >= 35) { + if (tdp >= 45) + icc_max[VR_IA_CORE] = VR_CFG_AMP(68); + + icc_max[VR_SYSTEM_AGENT] = VR_CFG_AMP(11.1); + } + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_SKL_ID_U: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(5.1, 29, 57, 19); + if (tdp >= 28) + icc_max[VR_IA_CORE] = VR_CFG_AMP(32); + else if (igd_id != PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_1) { + const uint16_t icc_max_gt2[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_ICC(4.5, 29, 31, 31); + + return icc_max_gt2[domain]; + } + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_KBL_U_R: { + const uint16_t icc_max[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_ICC(6, 64, 31, 31); + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_SKL_ID_Y: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_Y: { - uint16_t icc_max[NUM_VR_DOMAINS] = { - VR_CFG_AMP(4.1), - VR_CFG_AMP(24), - VR_CFG_AMP(24), - VR_CFG_AMP(24), - }; + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(4.1, 24, 24, 24); if (igd_id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX) icc_max[VR_IA_CORE] = VR_CFG_AMP(28); @@ -202,98 +220,96 @@ static uint16_t get_sku_icc_max(int domain) return icc_max[domain]; } case PCI_DEVICE_ID_INTEL_KBL_ID_U: { - uint16_t icc_max[NUM_VR_DOMAINS] = { - VR_CFG_AMP(4.5), - VR_CFG_AMP(32), - VR_CFG_AMP(31), - VR_CFG_AMP(31), - }; + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(4.5, 32, 31, 31); - if (igd_id == PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22) + if (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM) icc_max[VR_IA_CORE] = VR_CFG_AMP(29); + else if ((igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) || + (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2)) { + const uint16_t icc_max_gt3[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_ICC(5.1, 32, 57, 19); + + return icc_max_gt3[domain]; + } + return icc_max[domain]; } default: - printk(BIOS_ERR, "ERROR: Unknown MCH in VR-config\n"); + printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); } return 0; } -#if CONFIG(PLATFORM_USES_FSP2_0) static uint16_t get_sku_ac_dc_loadline(const int domain) { static uint16_t mch_id = 0, igd_id = 0; if (!mch_id) { struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - mch_id = pci_read_config16(dev, PCI_DEVICE_ID); + mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; } if (!igd_id) { struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (dev) - igd_id = pci_read_config16(dev, PCI_DEVICE_ID); - else - igd_id = 0xffff; + igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; } switch (mch_id) { - case PCI_DEVICE_ID_INTEL_KBL_ID_S: /* fallthrough */ - case PCI_DEVICE_ID_INTEL_KBL_ID_DT: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_SKL_ID_S_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_SKL_ID_S_4: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_ID_S: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_ID_DT: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: { - static const uint16_t loadline[NUM_VR_DOMAINS] = { - VR_CFG_MOHMS(0), /* Not specified */ - VR_CFG_MOHMS(2.1), - VR_CFG_MOHMS(3.1), - VR_CFG_MOHMS(3.1), - }; - + /* SA Loadline is not specified */ + const uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(0, 2.1, 3.1, 3.1); return loadline[domain]; } + case PCI_DEVICE_ID_INTEL_SKL_ID_H_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_SKL_ID_H_EM: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_SKL_ID_H_4: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_H: { - static const uint16_t loadline[NUM_VR_DOMAINS] = { - VR_CFG_MOHMS(10), - VR_CFG_MOHMS(1.8), - VR_CFG_MOHMS(2.65), - VR_CFG_MOHMS(2.65), - }; + const uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10, 1.8, 2.65, 2.65); + + if (igd_id == PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM) { + const uint16_t loadline_gt4[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(6, 1.6, 1.4, 6); + return loadline_gt4[domain]; + } return loadline[domain]; } + case PCI_DEVICE_ID_INTEL_SKL_ID_Y: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_Y: { - uint16_t loadline[NUM_VR_DOMAINS] = { - VR_CFG_MOHMS(18), - VR_CFG_MOHMS(5.9), - VR_CFG_MOHMS(5.7), - VR_CFG_MOHMS(5.7), - }; + uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(18, 5.9, 5.7, 5.7); if (igd_id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX) loadline[VR_IA_CORE] = VR_CFG_MOHMS(4); return loadline[domain]; } - case PCI_DEVICE_ID_INTEL_KBL_U_R: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_SKL_ID_U: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_U_R: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_U: { - uint16_t loadline[NUM_VR_DOMAINS] = { - VR_CFG_MOHMS(10.3), - VR_CFG_MOHMS(2.4), - VR_CFG_MOHMS(3.1), - VR_CFG_MOHMS(3.1), - }; + uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 3.1, 3.1); - if (igd_id == PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22) { - loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(6); + if ((igd_id == PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_1) || + (igd_id == PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_2) || + (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) || + (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2)) { + loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(2); loadline[VR_GT_SLICED] = VR_CFG_MOHMS(6); } return loadline[domain]; } default: - printk(BIOS_ERR, "ERROR: Unknown MCH in VR-config\n"); + printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); } return 0; } -#endif void fill_vr_domain_config(void *params, int domain, const struct vr_config *chip_cfg) @@ -325,7 +341,6 @@ void fill_vr_domain_config(void *params, vr_params->IccMax[domain] = get_sku_icc_max(domain); vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; -#if CONFIG(PLATFORM_USES_FSP2_0) if (cfg->ac_loadline) vr_params->AcLoadline[domain] = cfg->ac_loadline; else @@ -334,5 +349,4 @@ void fill_vr_domain_config(void *params, vr_params->DcLoadline[domain] = cfg->dc_loadline; else vr_params->DcLoadline[domain] = get_sku_ac_dc_loadline(domain); -#endif } diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index 8906565bd5..1a55d0113e 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -21,7 +21,7 @@ #define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB) -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); } diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 679bec8d75..d60abdb964 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -81,9 +81,9 @@ static void mtk_dsi_phy_timing(int data_rate, struct mtk_phy_timing *phy_timing) memset(phy_timing, 0, sizeof(*phy_timing)); phy_timing->lpx = DIV_ROUND_UP(60, cycle_time); - phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time); + phy_timing->da_hs_prepare = DIV_ROUND_UP((50 + 5 * ui), cycle_time); phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time); - phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time); + phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 77), cycle_time); phy_timing->ta_go = 4U * phy_timing->lpx; phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; @@ -392,6 +392,12 @@ static void mtk_dsi_send_init_commands(const u8 *buf) } } +static void mtk_dsi_reset_dphy(void) +{ + setbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET); + clrbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET); +} + int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid, const u8 *init_commands) { @@ -407,6 +413,8 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid, struct mtk_phy_timing phy_timing; mtk_dsi_phy_timing(data_rate, &phy_timing); mtk_dsi_rxtx_control(mode_flags, lanes); + mdelay(1); + mtk_dsi_reset_dphy(); mtk_dsi_clk_hs_mode_disable(); mtk_dsi_config_vdo_timing(mode_flags, format, lanes, edid, &phy_timing); mtk_dsi_clk_hs_mode_enable(); diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index 9a00d1d149..3052689c90 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -115,6 +115,7 @@ enum { enum { DSI_RESET = BIT(0), DSI_EN = BIT(1), + DPHY_RESET = BIT(2), DSI_DUAL = BIT(4), }; diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 8632affc7e..d0c6ee9302 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -64,7 +64,7 @@ romstage-y += ../common/rtc.c rtc.c ################################################################################ -ramstage-y += ../common/cbmem.c emi.c +ramstage-y += emi.c ramstage-y += ../common/spi.c spi.c ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c ramstage-y += soc.c ../common/mtcmos.c diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 6dda1026be..f9bd5073ca 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index 67de335ebf..22702d31b0 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index 5ded0d3801..46249be038 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -30,6 +30,13 @@ config MT8183_DRAM_EMCP The eMCP platform should select this option to run at different DRAM frequencies. +config MT8183_DRAM_DVFS + bool + default y + help + This options enables DRAM calibration with multiple frequencies (low, + medium and high) for DVFS feature. + config MEMORY_TEST bool default y diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index d1171ef379..b0dd48f7a4 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -27,6 +27,7 @@ verstage-y += ../common/wdt.c romstage-y += auxadc.c romstage-y += ../common/cbmem.c emi.c romstage-y += dramc_init_setting.c +romstage-y += dramc_param.c romstage-y += dramc_pi_basic_api.c romstage-y += dramc_pi_calibration_api.c romstage-y += memory.c @@ -44,7 +45,7 @@ romstage-y += ../common/uart.c romstage-y += ../common/wdt.c ramstage-y += auxadc.c -ramstage-y += ../common/cbmem.c emi.c +ramstage-y += emi.c ramstage-y += ../common/ddp.c ddp.c ramstage-y += ../common/dsi.c dsi.c ramstage-y += ../common/gpio.c gpio.c @@ -80,6 +81,14 @@ sspm.bin-file := $(MT8183_BLOB_DIR)/sspm.bin sspm.bin-type := raw sspm.bin-compression := $(CBFS_COMPRESS_FLAG) +DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram +$(DRAM_CBFS)-file := $(MT8183_BLOB_DIR)/dram.elf +$(DRAM_CBFS)-type := stage +$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +ifneq ($(wildcard $($(DRAM_CBFS)-file)),) + cbfs-files-y += $(DRAM_CBFS) +endif + BL31_MAKEARGS += PLAT=mt8183 CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index 0ae0be1815..3c2b0fd662 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index b8491d3360..2a36b48d5d 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -43,6 +43,40 @@ static void cke_fix_onoff(int option, u8 chn) (0x1 << 6) | (0x1 << 7), (on << 6) | (off << 7)); } +static void dvfs_settings(u8 freq_group) +{ + u8 dll_idle; + + switch (freq_group) { + case LP4X_DDR1600: + dll_idle = 0x18; + break; + case LP4X_DDR2400: + dll_idle = 0x10; + break; + case LP4X_DDR3200: + dll_idle = 0xc; + break; + case LP4X_DDR3600: + dll_idle = 0xa; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + dll_idle = dll_idle << 1; + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 5); + setbits_le32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 29); + clrsetbits_le32(&ch[0].ao.shuctrl2, 0x7f, dll_idle); + + setbits_le32(&ch[0].phy.misc_ctrl0, 0x3 << 19); + setbits_le32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24); + setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 7); + } +} + static void ddr_phy_pll_setting(u8 chn, u8 freq_group) { u8 cap_sel, mid_cap_sel; @@ -67,13 +101,13 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) mid_cap_sel = 0x2; cap_sel = 0x0; sdm_pcw = 0x7b00; - delta = 0xC03; + delta = 0xc03; break; case LP4X_DDR3600: mid_cap_sel = 0x1; cap_sel = 0x0; sdm_pcw = 0x8a00; - delta = 0xD96; + delta = 0xd96; break; default: die("Invalid DDR frequency group %u\n", freq_group); @@ -86,16 +120,14 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) ca_dll_mode[CHANNEL_A] = DLL_MASTER; ca_dll_mode[CHANNEL_B] = DLL_SLAVE; - clrbits_le32(&ch[chn].phy.shu[0].pll[4], 0xFFFF); - clrbits_le32(&ch[chn].phy.shu[0].pll[6], 0xFFFF); + clrbits_le32(&ch[chn].phy.shu[0].pll[4], 0xffff); + clrbits_le32(&ch[chn].phy.shu[0].pll[6], 0xffff); setbits_le32(&ch[chn].phy.misc_shu_opt, (chn + 1) << 18); clrsetbits_le32(&ch[chn].phy.ckmux_sel, 0x3 << 18 | 0x3 << 16, 0x0); clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[0], 0x3 << 18, 0x1 << 18); - if (ca_dll_mode[chn] == DLL_SLAVE) - clrsetbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1, 0x1 << 1); - else - clrsetbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1, 0x0 << 1); + SET32_BITFIELDS(&ch[chn].ao.dvfsdll, DVFSDLL_R_BYPASS_1ST_DLL_SHU1, + ca_dll_mode[chn] == DLL_SLAVE); bool is_master = (ca_dll_mode[chn] == DLL_MASTER); u8 phdet_out = is_master ? 0x0 : 0x1; @@ -120,8 +152,7 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) (pd_ck_sel << 2) | (fastpj_ck_sel << 0)); clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], - 0x1 << 7, - (is_master ? 0x1 : 0x0) << 7); + 0x1 << 7, (is_master ? 0x1 : 0x0) << 7); struct reg_value regs_bak[] = { {&ch[chn].phy.b[0].dq[7]}, @@ -132,15 +163,14 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) regs_bak[i].value = read32(regs_bak[i].addr); - for (size_t b = 0; b < 2; b++) { + for (size_t b = 0; b < 2; b++) setbits_le32(&ch[chn].phy.b[b].dq[7], 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0); - } setbits_le32(&ch[chn].phy.ca_cmd[7], 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0); setbits_le32(&ch[chn].phy.ca_cmd[2], 0x1 << 21); /* 26M */ - clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl0, 0x3 << 4, 0x0 << 4); + SET32_BITFIELDS(&ch[chn].phy.misc_cg_ctrl0, MISC_CG_CTRL0_CLK_MEM_SEL, 0); /* MID FINE_TUNE */ clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], (0x1 << 26) | (0x1 << 27)); @@ -245,11 +275,11 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[3], (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17)); + clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], (0x1 << 10) | (0x1 << 13) | (0x1 << 15) | (0x1 << 16) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); - clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], (0x1 << 10) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17) | @@ -323,7 +353,7 @@ static void dramc_gating_mode(u8 mode) static void update_initial_settings(u8 freq_group) { - u8 chn = 0, operate_fsp = get_freq_fsq(freq_group); + u8 operate_fsp = get_freq_fsq(freq_group); u16 rx_vref = 0x16; if (operate_fsp == FSP_1) @@ -380,11 +410,9 @@ static void update_initial_settings(u8 freq_group) clrsetbits_le32(&ch[0].phy.b[b].dq[5], 0x3f << 8, rx_vref << 8); } - for (chn = 0; chn < CHANNEL_MAX; chn++) { - setbits_le32(&ch[chn].phy.b[0].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); - setbits_le32(&ch[chn].phy.b[1].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); - setbits_le32(&ch[chn].phy.ca_cmd[9], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); - } + setbits_le32(&ch[0].phy.b[0].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); + setbits_le32(&ch[0].phy.b[1].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); + setbits_le32(&ch[0].phy.ca_cmd[9], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); dramc_gating_mode(1); setbits_le32(&ch[0].phy.ca_cmd[8], 0x1 << 19); @@ -398,7 +426,7 @@ static void update_initial_settings(u8 freq_group) clrbits_le32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 8); dramc_set_broadcast(DRAMC_BROADCAST_OFF); - for (chn = 0; chn < CHANNEL_MAX; chn++) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], 0x3f << 0); clrbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], 0x3f << 0); clrbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0x3f << 0); @@ -504,13 +532,8 @@ static void update_initial_settings(u8 freq_group) setbits_le32(&ch[0].ao.ckectrl, 0x1 << 22); clrsetbits_le32(&ch[0].phy.ca_tx_mck, (0x1 << 31) | (0x1f << 21) | (0x1f << 26), (0x1 << 31) | (0xa << 21) | (0xa << 26)); - setbits_le32(&ch[0].ao.ckectrl, 0x1 << 23); - - /* Gating error problem happened in M17 - * has been solved by setting this RG as 0 */ clrbits_le32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 31); - } static void dramc_power_on_sequence(void) @@ -548,7 +571,7 @@ static void ddr_phy_reserved_rg_setting(u8 freq_group) /* fine tune */ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) - clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0xFFFF << 6, + clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0xffff << 6, (0x1 << 6) | ((!chn) << 7) | (hyst_sel << 8) | (midpi_cap_sel << 9) | (0x1 << 10) | (0x3 << 17) | (lp3_sel << 20)); @@ -612,6 +635,22 @@ static void dramc_duty_set_dqs_delay(u8 chn, const s8 *s_dqsDelay) static void dramc_duty_calibration(const struct sdram_params *params, u8 freq_group) { + switch (params->source) { + case DRAMC_PARAM_SOURCE_SDRAM_CONFIG: + break; + case DRAMC_PARAM_SOURCE_FLASH: + dramc_dbg("bypass duty calibration\n"); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + dramc_duty_set_clk_delay(chn, params->duty_clk_delay[chn]); + dramc_duty_set_dqs_delay(chn, params->duty_dqs_delay[chn]); + } + return; + default: + die("Invalid DRAM param source %u\n", params->source); + return; + } + s8 clkDelay[CHANNEL_MAX] = {0x0}; s8 dqsDelay[CHANNEL_MAX][DQS_NUMBER] = {0x0}; @@ -662,9 +701,9 @@ static u8 dramc_zq_calibration(u8 chn, u8 rank) const u32 TIMEOUT_US = 100; struct reg_value regs_bak[] = { - {&ch[chn].ao.mrs, 0x0}, - {&ch[chn].ao.dramc_pd_ctrl, 0x0}, - {&ch[chn].ao.ckectrl, 0x0}, + {&ch[chn].ao.mrs}, + {&ch[chn].ao.dramc_pd_ctrl}, + {&ch[chn].ao.ckectrl}, }; for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) @@ -673,26 +712,26 @@ static u8 dramc_zq_calibration(u8 chn, u8 rank) setbits_le32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); dramc_cke_fix_onoff(chn, true, false); - clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT); - setbits_le32(&ch[chn].ao.mpc_option, 0x1 << MPC_OPTION_MPCRKEN_SHIFT); - setbits_le32(&ch[chn].ao.spcmd, 0x1 << SPCMD_ZQCEN_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank); + SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPCRKEN, 1); + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_ZQCEN, 1); if (!wait_us(TIMEOUT_US, read32(&ch[chn].nao.spcmdresp) & 0x1 << 4)) { dramc_dbg("ZQCAL Start fail (time out)\n"); return 1; } - clrbits_le32(&ch[chn].ao.spcmd, 0x1 << SPCMD_ZQCEN_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_ZQCEN, 0); udelay(1); - setbits_le32(&ch[chn].ao.spcmd, 0x1 << SPCMD_ZQLATEN_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_ZQLATEN, 1); if (!wait_us(TIMEOUT_US, read32(&ch[chn].nao.spcmdresp) & 0x1 << 6)) { dramc_dbg("ZQCAL Latch fail (time out)\n"); return 1; } - clrbits_le32(&ch[chn].ao.spcmd, 0x1 << SPCMD_ZQLATEN_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_ZQLATEN, 0); udelay(1); for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) write32(regs_bak[i].addr, regs_bak[i].value); @@ -700,24 +739,24 @@ static u8 dramc_zq_calibration(u8 chn, u8 rank) return 0; } -u8 MR01Value[FSP_MAX] = {0x26, 0x56}; -u8 MR13Value = (1 << 4) | (1 << 3); -static void dramc_mode_reg_init(u8 freq_group) +static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr) { + u8 *MR01Value = mr->MR01Value; u8 MR02Value[FSP_MAX] = {0x12, 0x12}; u8 MR03Value = 0x30; u8 MR11Value[FSP_MAX] = {0x0, 0x23}; u8 MR12Value[CHANNEL_MAX][RANK_MAX][FSP_MAX] = { {{0x5d, 0x5d}, {0x5d, 0x5d} }, {{0x5d, 0x5d}, {0x5d, 0x5d} }, }; + u8 MR13Value; u8 MR14Value[CHANNEL_MAX][RANK_MAX][FSP_MAX] = { {{0x5d, 0x10}, {0x5d, 0x10} }, {{0x5d, 0x10}, {0x5d, 0x10} }, }; u8 MR22Value[FSP_MAX] = {0x38, 0x34}; - MR01Value[FSP_0] &= 0x8F; - MR01Value[FSP_1] &= 0x8F; + MR01Value[FSP_0] = 0x6; + MR01Value[FSP_1] = 0x6; if (freq_group == LP4X_DDR1600) { MR02Value[0] = 0x12; @@ -738,7 +777,7 @@ static void dramc_mode_reg_init(u8 freq_group) MR01Value[FSP_0] |= (0x5 << 4); MR01Value[FSP_1] |= (0x5 << 4); } else if (freq_group == LP4X_DDR3600) { - MR02Value[0] = 0x1A; + MR02Value[0] = 0x1a; MR02Value[1] = 0x36; MR01Value[FSP_0] |= (0x6 << 4); @@ -799,6 +838,8 @@ static void dramc_mode_reg_init(u8 freq_group) (2 << 0) | (MR02Value[operate_fsp] << 16)); } + mr->MR13Value = MR13Value; + clrsetbits_le32(&ch[0].ao.mrs, 0x3 << 24, RANK_0 << 24); clrsetbits_le32(&ch[1].ao.mrs, 0x3 << 24, RANK_0 << 24); dramc_set_broadcast(broadcast_bak); @@ -854,13 +895,9 @@ static void dramc_setting_DDR1600(void) (0x2 << 8) | (0x2 << 12) | (0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28)); clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], - 0x77777777, - (0x1 << 0) | (0x1 << 4) | (0x1 << 8) | (0x1 << 12) | - (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); + 0x77777777, _SELPH_DQS_BITS(0x1, 0x7)); clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], - 0x77777777, - (0x1 << 0) | (0x1 << 4) | (0x1 << 8) | (0x1 << 12) | - (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); + 0x77777777, _SELPH_DQS_BITS(0x1, 0x7)); } clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), @@ -870,7 +907,7 @@ static void dramc_setting_DDR1600(void) clrsetbits_le32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x2 << 4) | (0x0 << 7) | (0x0 << 13)); clrsetbits_le32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x4 << 20); - clrbits_le32(&ch[0].phy.b[0].dq[7], (0x1 << 7) | (0x1 << 13)); + clrbits_le32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { int value = ((r == 0) ? 0x1a : 0x26); @@ -917,13 +954,9 @@ static void dramc_setting_DDR2400(void) (0x3 << 8) | (0x3 << 12) | (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], - 0x77777777, - (0x2 << 0) | (0x2 << 4) | (0x2 << 8) | (0x2 << 12) | - (0x0 << 16) | (0x0 << 20) | (0x0 << 24) | (0x0 << 28)); + 0x77777777, _SELPH_DQS_BITS(0x2, 0x0)); clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], - 0x77777777, - (0x2 << 0) | (0x2 << 4) | (0x2 << 8) | (0x2 << 12) | - (0x0 << 16) | (0x0 << 20) | (0x0 << 24) | (0x0 << 28)); + 0x77777777, _SELPH_DQS_BITS(0x2, 0x0)); } clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, @@ -932,7 +965,7 @@ static void dramc_setting_DDR2400(void) clrsetbits_le32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x1 << 4) | (0x1 << 7) | (0x1 << 13)); clrsetbits_le32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits_le32(&ch[0].phy.b[0].dq[7], + clrsetbits_le32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13), (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { @@ -948,7 +981,8 @@ static void dramc_setting_DDR3600(void) clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3600); } -static void dramc_setting(const struct sdram_params *params, u8 freq_group) +static void dramc_setting(const struct sdram_params *params, u8 freq_group, + const struct dram_impedance *impedance) { u8 chn; @@ -1066,11 +1100,7 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group) for (size_t b = 0; b < 2; b++) setbits_le32(&ch[0].phy.b[b].dq[3], (0x3 << 1) | (0x1 << 10)); - - dramc_set_broadcast(DRAMC_BROADCAST_OFF); setbits_le32(&ch[0].phy.shu[0].ca_dll[0], 0x1 << 0); - setbits_le32(&ch[1].phy.shu[0].ca_dll[0], 0x1 << 0); - dramc_set_broadcast(DRAMC_BROADCAST_ON); for (size_t b = 0; b < 2; b++) clrsetbits_le32(&ch[0].phy.shu[0].b[b].dll[0], @@ -1093,26 +1123,25 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group) clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[6], 0xffff << 6, 0x1 << 6); dramc_set_broadcast(DRAMC_BROADCAST_OFF); - for (size_t chan = 0; chan < 2; chan++) - clrsetbits_le32(&ch[chan].phy.misc_shu_opt, + for (chn = 0; chn < CHANNEL_MAX; chn++) + clrsetbits_le32(&ch[chn].phy.misc_shu_opt, (0x1 << 0) | (0x3 << 2) | (0x1 << 8) | (0x3 << 10) | (0x1 << 16) | (0x3 << 18), (0x1 << 0) | (0x2 << 2) | (0x1 << 8) | - (0x2 << 10) | (0x1 << 16) | ((0x1+chan) << 18)); + (0x2 << 10) | (0x1 << 16) | ((0x1 + chn) << 18)); udelay(9); clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 2); clrsetbits_le32(&ch[1].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 0); dramc_set_broadcast(DRAMC_BROADCAST_ON); - for (size_t b = 0; b < 2; b++) { + for (size_t b = 0; b < 2; b++) clrsetbits_le32(&ch[0].phy.shu[0].b[b].dll[1], (0x1 << 0) | (0x1 << 2), (0x1 << 0) | (0x0 << 2)); - } udelay(1); clrbits_le32(&ch[0].phy.pll2, 0x1 << 31); - clrsetbits_le32(&ch[0].phy.misc_cg_ctrl0, 0xffffffff, 0xF); + clrsetbits_le32(&ch[0].phy.misc_cg_ctrl0, 0xffffffff, 0xf); udelay(1); dramc_set_broadcast(DRAMC_BROADCAST_OFF); @@ -1168,9 +1197,8 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group) setbits_le32(&ch[0].phy.misc_ctrl0, (0xf << 0) | (0x1 << 9) | (0x1 << 24) | (0x1 << 31)); - for (chn = 0; chn < CHANNEL_MAX; chn++) - setbits_le32(&ch[chn].phy.misc_ctrl1, - (0x1 << 2) | (0x1 << 3) | (0x1 << 15) | (0x1 << 24)); + setbits_le32(&ch[0].phy.misc_ctrl1, + (0x1 << 2) | (0x1 << 3) | (0x1 << 15) | (0x1 << 24)); clrsetbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 24, 0x1 << 24); clrsetbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 24, 0x1 << 24); clrsetbits_le32(&ch[0].phy.ca_rxdvs0, 0x1 << 24, 0x0 << 24); @@ -1208,21 +1236,13 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group) for (size_t rank = 0; rank < 2; rank++) { clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], - 0x77777777, - (0x3 << 0) | (0x3 << 4) | (0x3 << 8) | (0x3 << 12) | - (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); + 0x77777777, _SELPH_DQS_BITS(0x3, 0x3)); clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], - 0x77777777, - (0x3 << 0) | (0x3 << 4) | (0x3 << 8) | (0x3 << 12) | - (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); + 0x77777777, _SELPH_DQS_BITS(0x3, 0x3)); clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], - 0x77777777, - (0x6 << 0) | (0x6 << 4) | (0x6 << 8) | (0x6 << 12) | - (0x2 << 16) | (0x2 << 20) | (0x2 << 24) | (0x2 << 28)); + 0x77777777, _SELPH_DQS_BITS(0x6, 0x2)); clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], - 0x77777777, - (0x6 << 0) | (0x6 << 4) | (0x6 << 8) | (0x6 << 12) | - (0x2 << 16) | (0x2 << 20) | (0x2 << 24) | (0x2 << 28)); + 0x77777777, _SELPH_DQS_BITS(0x6, 0x2)); } for (int b = 0; b < 2; b++) { @@ -1285,6 +1305,8 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group) setbits_le32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 0); clrsetbits_le32(&ch[0].ao.eyescan, (0x1 << 1) | (0xf << 16), (0x0 << 1) | (0x1 << 16)); setbits_le32(&ch[0].ao.stbcal1, (0x1 << 10) | (0x1 << 11)); + clrsetbits_le32(&ch[0].ao.test2_1, 0xfffffff << 4, 0x10000 << 4); + clrsetbits_le32(&ch[0].ao.test2_2, 0xfffffff << 4, 0x400 << 4); clrsetbits_le32(&ch[0].ao.test2_3, (0x1 << 7) | (0x7 << 8) | (0x1 << 28), (0x1 << 7) | (0x4 << 8) | (0x1 << 28)); @@ -1294,15 +1316,14 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group) udelay(1); clrsetbits_le32(&ch[0].ao.hw_mrr_fun, (0xf << 0) | (0xf << 4), (0x8 << 0) | (0x6 << 4)); + clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 0); clrsetbits_le32(&ch[0].ao.perfctl0, (0x1 << 18) | (0x1 << 19), (0x0 << 18) | (0x1 << 19)); + setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 28); clrbits_le32(&ch[0].ao.rstmask, 0x1 << 28); setbits_le32(&ch[0].ao.rkcfg, 0x1 << 11); - setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 28); - setbits_le32(&ch[0].ao.eyescan, 0x1 << 2); - - clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 0); setbits_le32(&ch[0].ao.mpc_option, 0x1 << 17); + setbits_le32(&ch[0].ao.eyescan, 0x1 << 2); setbits_le32(&ch[0].ao.shu[0].wodt, 0x1 << 29); setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 7); setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 7); @@ -1332,7 +1353,7 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group) clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x7 << 4, 0x1 << 4); if (freq_group == LP4X_DDR1600) - clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, (0x0 << 0)); + clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x0 << 0); else clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x2 << 0); setbits_le32(&ch[0].ao.refctrl1, (0x1 << 0) | (0x1 << 5)); @@ -1381,11 +1402,10 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group) default: die("Invalid DDR frequency group %u\n", freq_group); return; - break; } update_initial_settings(freq_group); - dramc_sw_impedance_save_reg(freq_group); + dramc_sw_impedance_save_reg(freq_group, impedance); clrbits_le32(&ch[0].ao.test2_4, 0x1 << 17); clrsetbits_le32(&ch[0].ao.shu[0].conf[3], 0x1ff << 0, 0x5 << 0); @@ -1711,12 +1731,14 @@ static void ddr_update_ac_timing(u8 freq_group) clrsetbits_le32(&ch[0].ao.arbctl, 0x1 << 13, dram_cbt_mode); } -void dramc_init(const struct sdram_params *params, u8 freq_group) +void dramc_init(const struct sdram_params *params, u8 freq_group, + struct dram_shared_data *shared) { - dramc_setting(params, freq_group); + dramc_setting(params, freq_group, &shared->impedance); dramc_duty_calibration(params, freq_group); + dvfs_settings(freq_group); - dramc_mode_reg_init(freq_group); + dramc_mode_reg_init(freq_group, &shared->mr); ddr_update_ac_timing(freq_group); } diff --git a/src/soc/mediatek/mt8183/dramc_param.c b/src/soc/mediatek/mt8183/dramc_param.c new file mode 100644 index 0000000000..bf1fee43a2 --- /dev/null +++ b/src/soc/mediatek/mt8183/dramc_param.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "soc/dramc_param.h" + +struct dramc_param *get_dramc_param_from_blob(void *blob) +{ + return (struct dramc_param *)blob; +} + +int validate_dramc_param(const void *blob) +{ + const struct dramc_param *param = blob; + const struct dramc_param_header *hdr = ¶m->header; + + if (hdr->magic != DRAMC_PARAM_HEADER_MAGIC) + return DRAMC_ERR_INVALID_MAGIC; + + if (hdr->version != DRAMC_PARAM_HEADER_VERSION) + return DRAMC_ERR_INVALID_VERSION; + + if (hdr->size != sizeof(*param)) + return DRAMC_ERR_INVALID_SIZE; + + return DRAMC_SUCCESS; +} + +int is_valid_dramc_param(const void *blob) +{ + return validate_dramc_param(blob) == DRAMC_SUCCESS; +} + +int initialize_dramc_param(void *blob, u16 config) +{ + struct dramc_param *param = blob; + struct dramc_param_header *hdr = ¶m->header; + + memset(blob, 0, sizeof(*param)); + hdr->magic = DRAMC_PARAM_HEADER_MAGIC; + hdr->size = sizeof(*param); + hdr->version = DRAMC_PARAM_HEADER_VERSION; + hdr->config = config; + return 0; +} diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index a194d7a3dd..eb30381953 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -20,8 +20,6 @@ #include #include -static u32 impedance[2][4]; - u8 get_freq_fsq(u8 freq) { if (freq == LP4X_DDR1600 || freq == LP4X_DDR2400) @@ -53,7 +51,8 @@ static void dramc_sw_imp_cal_vref_sel(u8 term_option, u8 impcal_stage) clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x3f << 8, vref_sel << 8); } -void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term) +void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term, + struct dram_impedance *impedance) { u32 broadcast_bak, impcal_bak, imp_cal_result; u32 DRVP_result = 0xff, ODTN_result = 0xff, DRVN_result = 0x9; @@ -73,7 +72,7 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term) clrsetbits_le32(&ch[0].phy.misc_imp_ctrl0, 0x7 << 4, 0x3 << 4); udelay(1); - dramc_show("K DRVP\n"); + dramc_dbg("impedance: K DRVP\n"); setbits_le32(&ch[0].ao.impcal, 0x1 << 23); setbits_le32(&ch[0].ao.impcal, 0x1 << 22); clrbits_le32(&ch[0].ao.impcal, 0x1 << 21); @@ -88,18 +87,18 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term) udelay(1); imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> 24) & 0x1; - dramc_show("1. OCD DRVP=%d CALOUT=%d\n", - impx_drv, imp_cal_result); + dramc_dbg("1. OCD DRVP=%d CALOUT=%d\n", + impx_drv, imp_cal_result); if (imp_cal_result == 1 && DRVP_result == 0xff) { DRVP_result = impx_drv; - dramc_show("1. OCD DRVP calibration OK! DRVP=%d\n", - DRVP_result); + dramc_dbg("1. OCD DRVP calibration OK! DRVP=%d\n", + DRVP_result); break; } } - dramc_show("K ODTN\n"); + dramc_dbg("impedance: K ODTN\n"); dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVN); clrbits_le32(&ch[0].ao.impcal, 0x1 << 22); if (term == ODT_ON) @@ -116,41 +115,40 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term) udelay(1); imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> 24) & 0x1; - dramc_show("3. OCD ODTN=%d CALOUT=%d\n", - impx_drv, imp_cal_result); + dramc_dbg("3. OCD ODTN=%d CALOUT=%d\n", + impx_drv, imp_cal_result); if (imp_cal_result == 0 && ODTN_result == 0xff) { ODTN_result = impx_drv; - dramc_show("3. OCD ODTN calibration OK! ODTN=%d\n", - ODTN_result); + dramc_dbg("3. OCD ODTN calibration OK! ODTN=%d\n", + ODTN_result); break; } } write32(&ch[0].ao.impcal, impcal_bak); - dramc_show("term:%d, DRVP=%d, DRVN=%d, ODTN=%d\n", - term, DRVP_result, DRVN_result, ODTN_result); + dramc_dbg("impedance: term=%d, DRVP=%d, DRVN=%d, ODTN=%d\n", + term, DRVP_result, DRVN_result, ODTN_result); + u32 *imp = impedance->data[term]; if (term == ODT_OFF) { - impedance[term][0] = DRVP_result; - impedance[term][1] = ODTN_result; - impedance[term][2] = 0; - impedance[term][3] = 15; + imp[0] = DRVP_result; + imp[1] = ODTN_result; + imp[2] = 0; + imp[3] = 15; } else { - impedance[term][0] = (DRVP_result <= 3) ? - (DRVP_result * 3) : DRVP_result; - impedance[term][1] = (DRVN_result <= 3) ? - (DRVN_result * 3) : DRVN_result; - impedance[term][2] = 0; - impedance[term][3] = (ODTN_result <= 3) ? - (ODTN_result * 3) : ODTN_result; + imp[0] = (DRVP_result <= 3) ? (DRVP_result * 3) : DRVP_result; + imp[1] = (DRVN_result <= 3) ? (DRVN_result * 3) : DRVN_result; + imp[2] = 0; + imp[3] = (ODTN_result <= 3) ? (ODTN_result * 3) : ODTN_result; } dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_TRACKING); dramc_set_broadcast(broadcast_bak); } -void dramc_sw_impedance_save_reg(u8 freq_group) +void dramc_sw_impedance_save_reg(u8 freq_group, + const struct dram_impedance *impedance) { u8 ca_term = ODT_OFF, dq_term = ODT_ON; u32 sw_impedance[2][4] = {0}; @@ -160,7 +158,7 @@ void dramc_sw_impedance_save_reg(u8 freq_group) for (u8 term = 0; term < 2; term++) for (u8 i = 0; i < 4; i++) - sw_impedance[term][i] = impedance[term][i]; + sw_impedance[term][i] = impedance->data[term][i]; sw_impedance[ODT_OFF][2] = sw_impedance[ODT_ON][2]; sw_impedance[ODT_OFF][3] = sw_impedance[ODT_ON][3]; @@ -212,11 +210,10 @@ void dramc_sw_impedance_save_reg(u8 freq_group) clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 22, sw_impedance[ca_term][1] << 22); - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[3], - SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_MASK, - 1 << SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_SHIFT); - clrbits_le32(&ch[0].phy.shu[0].ca_cmd[0], - SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE_MASK); + SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[3], + SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE, 1); + SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[0], + SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE, 0); clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); } diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index f8b1f091ed..16f28785d3 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -84,29 +84,25 @@ struct per_byte_dly { u16 final_dly; }; -extern u8 MR01Value[FSP_MAX]; -extern u8 MR13Value; - static void dramc_auto_refresh_switch(u8 chn, bool option) { - clrsetbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_REFDIS_SHIFT, - (option ? 0 : 1) << REFCTRL0_REFDIS_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, option ? 0 : 1); if (!option) { /* * Because HW will actually disable autorefresh after * refresh_queue empty, we need to wait until queue empty. */ - udelay(((read32(&ch[chn].nao.misc_statusa) & - MISC_STATUSA_REFRESH_QUEUE_CNT_MASK) >> - MISC_STATUSA_REFRESH_QUEUE_CNT_SHIFT) * 4); + udelay(READ32_BITFIELD(&ch[chn].nao.misc_statusa, + MISC_STATUSA_REFRESH_QUEUE_CNT) * 4); } } void dramc_cke_fix_onoff(u8 chn, bool cke_on, bool cke_off) { - clrsetbits_le32(&ch[chn].ao.ckectrl, (0x1 << 6) | (0x1 << 7), - ((cke_on ? 1 : 0) << 6) | ((cke_off ? 1 : 0) << 7)); + SET32_BITFIELDS(&ch[chn].ao.ckectrl, + CKECTRL_CKEFIXON, cke_on, + CKECTRL_CKEFIXOFF, cke_off); } void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) @@ -114,17 +110,16 @@ void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) u32 ckectrl_bak = read32(&ch[chn].ao.ckectrl); dramc_cke_fix_onoff(chn, true, false); - clrsetbits_le32(&ch[chn].ao.mrs, - MRS_MRSMA_MASK, mr_idx << MRS_MRSMA_SHIFT); - clrsetbits_le32(&ch[chn].ao.mrs, - MRS_MRSOP_MASK, value << MRS_MRSOP_SHIFT); - setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_MRWEN_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSMA, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSOP, value); + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRWEN, 1); /* Wait MRW command fired */ - while ((read32(&ch[chn].nao.spcmdresp) & 1) == 0) + while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRW_RESPONSE) + == 0) ; - clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_MRWEN_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRWEN, 0); write32(&ch[chn].ao.ckectrl, ckectrl_bak); dramc_dbg("Write MR%d =0x%x\n", mr_idx, value); } @@ -132,13 +127,12 @@ void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value) { - u32 mrs_back = read32(&ch[chn].ao.mrs) & MRS_MRSRK_MASK; + u32 mrs_bak = READ32_BITFIELD(&ch[chn].ao.mrs, MRS_MRSRK); dramc_dbg("Mode reg write rank%d MR%d = 0x%x\n", rank, mr_idx, value); - clrsetbits_le32(&ch[chn].ao.mrs, - MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank); dramc_mode_reg_write(chn, mr_idx, value); - clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, mrs_back); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, mrs_bak); } static void move_dramc_delay(u32 *reg_0, u32 *reg_1, u8 shift, s8 shift_coarse_tune) @@ -204,7 +198,6 @@ static void move_dramc_tx_dq_oen(u8 chn, u8 rank, static void write_leveling_move_dqs_instead_of_clk(u8 chn) { - dramc_dbg("%s do ch:%d k\n", __func__, chn); for (u8 byte = 0; byte < DQS_NUMBER; byte++) { move_dramc_tx_dqs(chn, byte, -WRITE_LEVELING_MOVD_DQS); move_dramc_tx_dqs_oen(chn, byte, -WRITE_LEVELING_MOVD_DQS); @@ -226,58 +219,62 @@ static void dramc_write_leveling(u8 chn, u8 rank, u8 freq_group, freq_group == LP4X_DDR2400)) write_leveling_move_dqs_instead_of_clk(chn); - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], - SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_MASK, 0); + SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], + SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK, 0); for (size_t byte = 0; byte < DQS_NUMBER; byte++) { u32 wrlevel_dq_delay = wr_level[chn][rank][byte] + 0x10; - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7], - FINE_TUNE_PBYTE_MASK, - wr_level[chn][rank][byte] << FINE_TUNE_PBYTE_SHIFT); + SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7], + FINE_TUNE_PBYTE, wr_level[chn][rank][byte]); if (wrlevel_dq_delay >= 0x40) { wrlevel_dq_delay -= 0x40; move_dramc_tx_dq(chn, rank, byte, 2); move_dramc_tx_dq_oen(chn, rank, byte, 2); } - - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7], - FINE_TUNE_DQM_MASK | FINE_TUNE_DQ_MASK, - (wrlevel_dq_delay << FINE_TUNE_DQM_SHIFT) | - (wrlevel_dq_delay << FINE_TUNE_DQ_SHIFT)); + SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7], + FINE_TUNE_DQM, wrlevel_dq_delay, + FINE_TUNE_DQ, wrlevel_dq_delay); } } static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group, - const struct sdram_params *params) + const struct sdram_params *params, const bool fast_calib) { - u32 cbt_cs, mr12_value; + u32 final_vref, clk_dly, cmd_dly, cs_dly; - cbt_cs = params->cbt_cs_dly[chn][rank]; - mr12_value = params->cbt_final_vref[chn][rank]; + clk_dly = params->cbt_clk_dly[chn][rank]; + cmd_dly = params->cbt_cmd_dly[chn][rank]; + cs_dly = params->cbt_cs_dly[chn][rank]; + final_vref = params->cbt_final_vref[chn][rank]; - /* CBT adjust cs */ - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], - SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CS_MASK, cbt_cs << 0); + if (fast_calib) { + /* Set CLK and CA delay */ + SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], + SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD, cmd_dly, + SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK, clk_dly); + udelay(1); + } + + /* Set CLK and CS delay */ + SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], + SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, cs_dly); /* CBT set vref */ - dramc_mode_reg_write_by_rank(chn, rank, 12, mr12_value); + dramc_mode_reg_write_by_rank(chn, rank, 12, final_vref); } static void dramc_read_dbi_onoff(bool on) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], - 0x1 << SHU1_BX_DQ7_R_DMDQMDBI_SHIFT, - (on ? 1 : 0) << SHU1_BX_DQ7_R_DMDQMDBI_SHIFT); + SET32_BITFIELDS(&ch[chn].phy.shu[0].b[b].dq[7], + SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0, on); } -static void dramc_write_dbi_onoff(bool on) +static void dramc_write_dbi_onoff(bool onoff) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - clrsetbits_le32(&ch[chn].ao.shu[0].wodt, - 0x1 << SHU1_WODT_DBIWR_SHIFT, - (on ? 1 : 0) << SHU1_WODT_DBIWR_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.shu[0].wodt, SHU1_WODT_DBIWR, onoff); } static void dramc_phy_dcm_2_channel(u8 chn, bool en) @@ -385,7 +382,7 @@ void dramc_apply_config_before_calibration(u8 freq_group) setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 24); clrsetbits_le32(&ch[0].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1); - for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++) setbits_le32(&ch[0].ao.shu[shu].conf[3], 0x1ff << 0); clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 18); @@ -400,29 +397,29 @@ void dramc_apply_config_before_calibration(u8 freq_group) for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { setbits_le32(&ch[chn].ao.spcmdctrl, 0x1 << 29); setbits_le32(&ch[chn].ao.dqsoscr, 0x1 << 24); - for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++) setbits_le32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30); clrbits_le32(&ch[chn].ao.dummy_rd, (0x1 << 7) | (0x7 << 20)); dramc_hw_gating_onoff(chn, false); clrbits_le32(&ch[chn].ao.stbcal2, 0x1 << 28); - setbits_le32(&ch[chn].phy.misc_ctrl1, - (0x1 << 7) | (0x1 << 11)); + setbits_le32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11)); clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18); clrbits_le32(&ch[chn].ao.mrs, 0x3 << 24); setbits_le32(&ch[chn].ao.mpc_option, 0x1 << 17); clrsetbits_le32(&ch[chn].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0); clrsetbits_le32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0); clrsetbits_le32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0); + + dramc_rx_input_delay_tracking_init_by_freq(chn); + setbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25); setbits_le32(&ch[chn].ao.drsctrl, 0x1 << 0); if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) clrbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); else setbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); - - dramc_rx_input_delay_tracking_init_by_freq(chn); } for (size_t r = 0; r < 2; r++) { @@ -433,24 +430,24 @@ void dramc_apply_config_before_calibration(u8 freq_group) } } -static void dramc_set_mr13_vrcg_to_Normal(u8 chn) +static void dramc_set_mr13_vrcg_to_Normal(u8 chn, const struct mr_value *mr) { - MR13Value &= ~(0x1 << 3); for (u8 rank = 0; rank < RANK_MAX; rank++) - dramc_mode_reg_write_by_rank(chn, rank, 13, MR13Value); + dramc_mode_reg_write_by_rank(chn, rank, 13, + mr->MR13Value & ~(0x1 << 3)); for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) clrbits_le32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19); } -void dramc_apply_config_after_calibration(void) +void dramc_apply_config_after_calibration(const struct mr_value *mr) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { write32(&ch[chn].phy.misc_cg_ctrl4, 0x11400000); clrbits_le32(&ch[chn].ao.refctrl1, 0x1 << 7); clrbits_le32(&ch[chn].ao.shuctrl, 0x1 << 2); clrbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 6); - dramc_set_mr13_vrcg_to_Normal(chn); + dramc_set_mr13_vrcg_to_Normal(chn, mr); clrbits_le32(&ch[chn].phy.b[0].dq[6], 0x3); clrbits_le32(&ch[chn].phy.b[1].dq[6], 0x3); @@ -490,59 +487,59 @@ static void dramc_rx_dqs_isi_pulse_cg_switch(u8 chn, bool flag) static void dramc_set_rank_engine2(u8 chn, u8 rank) { - setbits_le32(&ch[chn].ao.dramctrl, 0x1 << 1); - clrbits_le32(&ch[chn].ao.test2_4, TEST2_4_TESTAGENTRKSEL_MASK); - clrsetbits_le32(&ch[chn].ao.test2_4, TEST2_4_TESTAGENTRK_MASK, - rank << TEST2_4_TESTAGENTRK_SHIFT); + /* Select CTO_AGENT1_RANK */ + SET32_BITFIELDS(&ch[chn].ao.dramctrl, DRAMCTRL_ADRDECEN_TARKMODE, 1); + SET32_BITFIELDS(&ch[chn].ao.test2_4, TEST2_4_TESTAGENTRKSEL, 0); + SET32_BITFIELDS(&ch[chn].ao.test2_4, TEST2_4_TESTAGENTRK, rank); } static void dramc_engine2_setpat(u8 chn, bool test_pat) { - clrbits_le32(&ch[chn].ao.test2_4, - (0x1 << TEST2_4_TEST_REQ_LEN1_SHIFT) | - (0x1 << TEST2_4_TESTXTALKPAT_SHIFT) | - (0x1 << TEST2_4_TESTAUDMODE_SHIFT) | - (0x1 << TEST2_4_TESTAUDBITINV_SHIFT)); + SET32_BITFIELDS(&ch[chn].ao.test2_4, + TEST2_4_TEST_REQ_LEN1, 0, + TEST2_4_TESTXTALKPAT, 0, + TEST2_4_TESTAUDMODE, 0, + TEST2_4_TESTAUDBITINV, 0); if (!test_pat) { - setbits_le32(&ch[chn].ao.perfctl0, 1 << PERFCTL0_RWOFOEN_SHIFT); - - clrsetbits_le32(&ch[chn].ao.test2_4, - (0x1 << TEST2_4_TESTSSOPAT_SHIFT) | - (0x1 << TEST2_4_TESTSSOXTALKPAT_SHIFT), - (0x1 << TEST2_4_TESTXTALKPAT_SHIFT)); + SET32_BITFIELDS(&ch[chn].ao.perfctl0, PERFCTL0_RWOFOEN, 1); + SET32_BITFIELDS(&ch[chn].ao.test2_4, + TEST2_4_TESTSSOPAT, 0, + TEST2_4_TESTSSOXTALKPAT, 0, + TEST2_4_TESTXTALKPAT, 1); } else { - clrsetbits_le32(&ch[chn].ao.test2_4, - TEST2_4_TESTAUDINIT_MASK | TEST2_4_TESTAUDINC_MASK, - (0x11 << 8) | (0xd << 0) | (0x1 << 14)); + SET32_BITFIELDS(&ch[chn].ao.test2_4, + TEST2_4_TESTAUDINIT, 0x11, + TEST2_4_TESTAUDINC, 0xd, + TEST2_4_TESTAUDBITINV, 1); } - clrsetbits_le32(&ch[chn].ao.test2_3, - (0x1 << TEST2_3_TESTAUDPAT_SHIFT) | TEST2_3_TESTCNT_MASK, - (test_pat ? 1 : 0) << TEST2_3_TESTAUDPAT_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.test2_3, + TEST2_3_TESTAUDPAT, test_pat, TEST2_3_TESTCNT, 0); } static void dramc_engine2_init(u8 chn, u8 rank, u32 t2_1, u32 t2_2, bool test_pat) { dramc_set_rank_engine2(chn, rank); - clrbits_le32(&ch[chn].ao.dummy_rd, - (0x1 << DUMMY_RD_DQSG_DMYRD_EN_SHIFT) | - (0x1 << DUMMY_RD_DQSG_DMYWR_EN_SHIFT) | - (0x1 << DUMMY_RD_DUMMY_RD_EN_SHIFT) | - (0x1 << DUMMY_RD_SREF_DMYRD_EN_SHIFT) | - (0x1 << DUMMY_RD_DMY_RD_DBG_SHIFT) | - (0x1 << DUMMY_RD_DMY_WR_DBG_SHIFT)); - clrbits_le32(&ch[chn].nao.testchip_dma1, 0x1 << 12); - clrbits_le32(&ch[chn].ao.test2_3, - (0x1 << TEST2_3_TEST2W_SHIFT) | - (0x1 << TEST2_3_TEST2R_SHIFT) | - (0x1 << TEST2_3_TEST1_SHIFT)); - clrsetbits_le32(&ch[chn].ao.test2_0, - TEST2_0_PAT0_MASK | TEST2_0_PAT1_MASK, - ((t2_1 >> 24) << TEST2_0_PAT0_SHIFT) | - ((t2_2 >> 24) << TEST2_0_PAT1_SHIFT)); - clrsetbits_le32(&ch[chn].ao.test2_1, 0xfffffff0, (t2_1 & 0x00ffffff) << 4); - clrsetbits_le32(&ch[chn].ao.test2_2, 0xfffffff0, (t2_2 & 0x00ffffff) << 4); + SET32_BITFIELDS(&ch[chn].ao.dummy_rd, + DUMMY_RD_DQSG_DMYRD_EN, 0, + DUMMY_RD_DQSG_DMYWR_EN, 0, + DUMMY_RD_DUMMY_RD_EN, 0, + DUMMY_RD_SREF_DMYRD_EN, 0, + DUMMY_RD_DMY_RD_DBG, 0, + DUMMY_RD_DMY_WR_DBG, 0); + SET32_BITFIELDS(&ch[chn].nao.testchip_dma1, + TESTCHIP_DMA1_DMA_LP4MATAB_OPT, 0); + SET32_BITFIELDS(&ch[chn].ao.test2_3, + TEST2_3_TEST2W, 0, + TEST2_3_TEST2R, 0, + TEST2_3_TEST1, 0); + SET32_BITFIELDS(&ch[chn].ao.test2_0, TEST2_0_PAT0, t2_1 >> 24, + TEST2_0_PAT1, t2_2 >> 24); + SET32_BITFIELDS(&ch[chn].ao.test2_1, TEST2_1_TEST2_BASE, + t2_1 & 0xffffff); + SET32_BITFIELDS(&ch[chn].ao.test2_2, TEST2_2_TEST2_OFF, + t2_2 & 0xffffff); dramc_engine2_setpat(chn, test_pat); } @@ -569,10 +566,10 @@ static void dramc_engine2_compare(u8 chn, enum dram_te_op wr) if (wr == TE_OP_WRITE_READ_CHECK) { dramc_engine2_check_complete(chn, rank_status); - clrbits_le32(&ch[chn].ao.test2_3, (0x1 << TEST2_3_TEST2W_SHIFT) | - (0x1 << TEST2_3_TEST2R_SHIFT) | (0x1 << TEST2_3_TEST1_SHIFT)); + SET32_BITFIELDS(&ch[chn].ao.test2_3, TEST2_3_TEST2W, 0, + TEST2_3_TEST2R, 0, TEST2_3_TEST1, 0); udelay(1); - setbits_le32(&ch[chn].ao.test2_3, 0x1 << TEST2_3_TEST2W_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.test2_3, TEST2_3_TEST2W, 1); } dramc_engine2_check_complete(chn, rank_status); @@ -583,33 +580,28 @@ static u32 dramc_engine2_run(u8 chn, enum dram_te_op wr) u32 result; if (wr == TE_OP_READ_CHECK) { - clrbits_le32(&ch[chn].ao.test2_4, - 0x1 << TEST2_4_TESTAUDMODE_SHIFT); - - clrsetbits_le32(&ch[chn].ao.test2_3, - (0x1 << TEST2_3_TEST2W_SHIFT) | (0x1 << TEST2_3_TEST2R_SHIFT) | - (0x1 << TEST2_3_TEST1_SHIFT), 0x1 << TEST2_3_TEST2R_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.test2_4, TEST2_4_TESTAUDMODE, 0); + SET32_BITFIELDS(&ch[chn].ao.test2_3, + TEST2_3_TEST2W, 0, TEST2_3_TEST2R, 1, TEST2_3_TEST1, 0); } else if (wr == TE_OP_WRITE_READ_CHECK) { - clrsetbits_le32(&ch[chn].ao.test2_3, - (0x1 << TEST2_3_TEST2W_SHIFT) | (0x1 << TEST2_3_TEST2R_SHIFT) | - (0x1 << TEST2_3_TEST1_SHIFT), 0x1 << TEST2_3_TEST2W_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.test2_3, + TEST2_3_TEST2W, 1, TEST2_3_TEST2R, 0, TEST2_3_TEST1, 0); } dramc_engine2_compare(chn, wr); udelay(1); result = read32(&ch[chn].nao.cmp_err); - clrbits_le32(&ch[chn].ao.test2_3, - (0x1 << TEST2_3_TEST2W_SHIFT) | - (0x1 << TEST2_3_TEST2R_SHIFT) | - (0x1 << TEST2_3_TEST1_SHIFT)); + SET32_BITFIELDS(&ch[chn].ao.test2_3, + TEST2_3_TEST2W, 0, TEST2_3_TEST2R, 0, TEST2_3_TEST1, 0); return result; } -static void dramc_engine2_end(u8 chn) +static void dramc_engine2_end(u8 chn, u32 dummy_rd) { clrbits_le32(&ch[chn].ao.test2_4, 0x1 << 17); + write32(&ch[chn].ao.dummy_rd, dummy_rd); } static bool dramc_find_gating_window(u32 result_r, u32 result_f, u32 *debug_cnt, @@ -723,16 +715,16 @@ static void dramc_find_dly_tune(u8 chn, u8 dly_coarse_large, u8 dly_coarse_0p5t, static void dram_phy_reset(u8 chn) { - setbits_le32(&ch[chn].ao.ddrconf0, 1 << DDRCONF0_RDATRST_SHIFT); - setbits_le32(&ch[chn].phy.misc_ctrl1, 1 << MISC_CTRL1_R_DMPHYRST_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.ddrconf0, DDRCONF0_RDATRST, 1); + SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 1); clrbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0)); clrbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0)); udelay(1); setbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0)); setbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0)); - clrbits_le32(&ch[chn].phy.misc_ctrl1, 1 << MISC_CTRL1_R_DMPHYRST_SHIFT); - clrbits_le32(&ch[chn].ao.ddrconf0, 1 << DDRCONF0_RDATRST_SHIFT); + SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 0); + SET32_BITFIELDS(&ch[chn].ao.ddrconf0, DDRCONF0_RDATRST, 0); } static void dramc_set_gating_mode(u8 chn, bool mode) @@ -761,25 +753,31 @@ static void dramc_set_gating_mode(u8 chn, bool mode) static void dramc_rx_dqs_gating_cal_pre(u8 chn, u8 rank) { - clrbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_PBREFEN_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_PBREFEN, 0); dramc_hw_gating_onoff(chn, false); - setbits_le32(&ch[chn].ao.stbcal1, 1 << STBCAL1_STBENCMPEN_SHIFT); - setbits_le32(&ch[chn].ao.stbcal1, 1 << STBCAL1_STBCNT_LATCH_EN_SHIFT); - clrbits_le32(&ch[chn].ao.ddrconf0, 1 << DDRCONF0_DM4TO1MODE_SHIFT); - setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTEN_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.stbcal1, STBCAL1_STBENCMPEN, 1); + SET32_BITFIELDS(&ch[chn].ao.stbcal1, STBCAL1_STBCNT_LATCH_EN, 1); + SET32_BITFIELDS(&ch[chn].ao.ddrconf0, DDRCONF0_DM4TO1MODE, 0); + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSGCNTEN, 1); udelay(4); - setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSGCNTRST, 1); udelay(1); - clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); - clrsetbits_le32(&ch[chn].phy.misc_ctrl1, - 1 << MISC_CTRL1_R_DMSTBENCMP_RK_OPT_SHIFT, - rank << MISC_CTRL1_R_DMSTBENCMP_RK_OPT_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSGCNTRST, 0); + SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMSTBENCMP_RK, + rank); } +static void set_selph_gating_value(uint32_t *addr, u8 dly, u8 dly_p1) +{ + clrsetbits_le32(addr, 0x77777777, + (dly << 0) | (dly << 8) | (dly << 16) | (dly << 24) | + (dly_p1 << 4) | (dly_p1 << 12) | (dly_p1 << 20) | (dly_p1 << 28)); +} + static void dramc_write_dqs_gating_result(u8 chn, u8 rank, u8 *best_coarse_tune2t, u8 *best_coarse_tune0p5t, u8 *best_coarse_tune2t_p1, u8 *best_coarse_tune0p5t_p1) @@ -839,66 +837,17 @@ static void dramc_write_dqs_gating_result(u8 chn, u8 rank, (best_coarse_0p5t_rodt_p1[0] << 4) | (best_coarse_0p5t_rodt_p1[1] << 12)); } -static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group, - const struct sdram_params *params) +static void dramc_rx_dqs_gating_cal_partial(u8 chn, u8 rank, + u32 coarse_start, u32 coarse_end, u8 freqDiv, + u8 *pass_begin, u8 *pass_count, u8 *pass_count_1, u8 *dqs_done, + u8 *dqs_high, u8 *dqs_transition, u8 *dly_coarse_large_cnt, + u8 *dly_coarse_0p5t_cnt, u8 *dly_fine_tune_cnt) { - u8 dqs, fsp, freqDiv = 4; - u8 pass_begin[DQS_NUMBER] = {0}, pass_count[DQS_NUMBER] = {0}, - pass_count_1[DQS_NUMBER] = {0}, dqs_done[DQS_NUMBER] = {0}; - u8 min_coarse_tune2t[DQS_NUMBER], min_coarse_tune0p5t[DQS_NUMBER], - min_fine_tune[DQS_NUMBER]; - u8 best_fine_tune[DQS_NUMBER], best_coarse_tune0p5t[DQS_NUMBER], - best_coarse_tune2t[DQS_NUMBER]; - u8 best_coarse_tune0p5t_p1[DQS_NUMBER], best_coarse_tune2t_p1[DQS_NUMBER]; - u8 dqs_high[DQS_NUMBER] = {0}, dqs_transition[DQS_NUMBER] = {0}; - u8 dly_coarse_large_cnt[DQS_NUMBER] = {0}, dly_coarse_0p5t_cnt[DQS_NUMBER] = {0}, - dly_fine_tune_cnt[DQS_NUMBER] = {0}; - u32 coarse_start, coarse_end; + u8 dqs; u32 debug_cnt[DQS_NUMBER]; - struct reg_value regs_bak[] = { - {&ch[chn].ao.stbcal, 0x0}, - {&ch[chn].ao.stbcal1, 0x0}, - {&ch[chn].ao.ddrconf0, 0x0}, - {&ch[chn].ao.spcmd, 0x0}, - {&ch[chn].ao.refctrl0, 0x0}, - {&ch[chn].phy.b[0].dq[6], 0x0}, - {&ch[chn].phy.b[1].dq[6], 0x0}, - }; - for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) - regs_bak[i].value = read32(regs_bak[i].addr); - - fsp = get_freq_fsq(freq_group); - dramc_rx_dqs_isi_pulse_cg_switch(chn, false); - - MR01Value[fsp] |= 0x80; - dramc_mode_reg_write_by_rank(chn, rank, 0x1, MR01Value[fsp]); - dramc_rx_dqs_gating_cal_pre(chn, rank); - - u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); - dramc_engine2_init(chn, rank, TEST2_1_CAL, 0xaa000023, true); - - switch (freq_group) { - case LP4X_DDR1600: - coarse_start = 18; - break; - case LP4X_DDR2400: - coarse_start = 25; - break; - case LP4X_DDR3200: - coarse_start = 25; - break; - case LP4X_DDR3600: - coarse_start = 21; - break; - default: - die("Invalid DDR frequency group %u\n", freq_group); - return; - } - coarse_end = coarse_start + 12; - - dramc_dbg("[Gating]\n"); - for (u32 coarse_tune = coarse_start; coarse_tune < coarse_end; coarse_tune++) { + for (u32 coarse_tune = coarse_start; coarse_tune < coarse_end; + coarse_tune++) { u32 dly_coarse_large_rodt = 0, dly_coarse_0p5t_rodt = 0; u32 dly_coarse_large_rodt_p1 = 4, dly_coarse_0p5t_rodt_p1 = 4; @@ -913,56 +862,42 @@ static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group, dly_coarse_large_rodt = value >> 3; dly_coarse_0p5t_rodt = value - (dly_coarse_large_rodt << 3); - value = (dly_coarse_large << 3) + dly_coarse_0p5t - 11; dly_coarse_large_rodt_p1 = value >> 3; dly_coarse_0p5t_rodt_p1 = value - (dly_coarse_large_rodt_p1 << 3); } - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, - 0x77777777, - (dly_coarse_large << 0) | (dly_coarse_large << 8) | - (dly_coarse_large << 16) | (dly_coarse_large << 24) | - (dly_coarse_large_p1 << 4) | (dly_coarse_large_p1 << 12) | - (dly_coarse_large_p1 << 20) | (dly_coarse_large_p1 << 28)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, - 0x77777777, - (dly_coarse_0p5t << 0) | (dly_coarse_0p5t << 8) | - (dly_coarse_0p5t << 16) | (dly_coarse_0p5t << 24) | - (dly_coarse_0p5t_p1 << 4) | (dly_coarse_0p5t_p1 << 12) | - (dly_coarse_0p5t_p1 << 20) | (dly_coarse_0p5t_p1 << 28)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, - 0x77777777, - (dly_coarse_large_rodt << 0) | (dly_coarse_large_rodt << 8) | - (dly_coarse_large_rodt << 16) | (dly_coarse_large_rodt << 24) | - (dly_coarse_large_rodt_p1 << 4) | (dly_coarse_large_rodt_p1 << 12) | - (dly_coarse_large_rodt_p1 << 20) | (dly_coarse_large_rodt_p1 << 28)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, - 0x77777777, - (dly_coarse_0p5t_rodt << 0) | (dly_coarse_0p5t_rodt << 8) | - (dly_coarse_0p5t_rodt << 16) | (dly_coarse_0p5t_rodt << 24) | - (dly_coarse_0p5t_rodt_p1 << 4) | (dly_coarse_0p5t_rodt_p1 << 12) | - (dly_coarse_0p5t_rodt_p1 << 20) | (dly_coarse_0p5t_rodt_p1 << 28)); + set_selph_gating_value(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + dly_coarse_large, dly_coarse_large_p1); + set_selph_gating_value(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, + dly_coarse_0p5t, dly_coarse_0p5t_p1); + set_selph_gating_value(&ch[chn].ao.shu[0].rk[rank].selph_odten0, + dly_coarse_large_rodt, dly_coarse_large_rodt_p1); + set_selph_gating_value(&ch[chn].ao.shu[0].rk[rank].selph_odten1, + dly_coarse_0p5t_rodt, dly_coarse_0p5t_rodt_p1); - for (u8 dly_fine_xt = 0; dly_fine_xt < DQS_GW_FINE_END; dly_fine_xt += 4) { + for (u8 dly_fine_xt = 0; dly_fine_xt < DQS_GW_FINE_END; + dly_fine_xt += 4) { dramc_set_gating_mode(chn, 0); - write32(&ch[chn].ao.shu[0].rk[rank].dqsien, - dly_fine_xt | (dly_fine_xt << 8)); + WRITE32_BITFIELDS(&ch[chn].ao.shu[0].rk[rank].dqsien, + SHURK_DQSIEN_DQS0IEN, dly_fine_xt, + SHURK_DQSIEN_DQS1IEN, dly_fine_xt); dram_phy_reset(chn); - setbits_le32(&ch[chn].ao.spcmd, - 1 << SPCMD_DQSGCNTRST_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSGCNTRST, 1); udelay(1); - clrbits_le32(&ch[chn].ao.spcmd, - 1 << SPCMD_DQSGCNTRST_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSGCNTRST, 0); dramc_engine2_run(chn, TE_OP_READ_CHECK); - u32 result_r = read32(&ch[chn].phy.misc_stberr_rk0_r) & - MISC_STBERR_RK_R_STBERR_RK_R_MASK; - u32 result_f = read32(&ch[chn].phy.misc_stberr_rk0_f) & - MISC_STBERR_RK_F_STBERR_RK_F_MASK; + u32 result_r = READ32_BITFIELD( + &ch[chn].phy.misc_stberr_rk0_r, + MISC_STBERR_RK_R_STBERR_RK_R); + u32 result_f = READ32_BITFIELD( + &ch[chn].phy.misc_stberr_rk0_f, + MISC_STBERR_RK_F_STBERR_RK_F); + debug_cnt[0] = read32(&ch[chn].nao.dqsgnwcnt[0]); debug_cnt[1] = (debug_cnt[0] >> 16) & 0xffff; debug_cnt[0] &= 0xffff; @@ -989,21 +924,95 @@ static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group, dramc_dbg("\n"); if (dramc_find_gating_window(result_r, result_f, debug_cnt, - dly_coarse_large, dly_coarse_0p5t, pass_begin, pass_count, - pass_count_1, &dly_fine_xt, dqs_high, dqs_done)) + dly_coarse_large, dly_coarse_0p5t, pass_begin, + pass_count, pass_count_1, &dly_fine_xt, + dqs_high, dqs_done)) coarse_tune = coarse_end; } } +} - dramc_engine2_end(chn); - write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); +static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group, + const struct sdram_params *params, const bool fast_calib, + const struct mr_value *mr) +{ + u8 dqs, fsp, freqDiv = 4; + u8 pass_begin[DQS_NUMBER] = {0}, pass_count[DQS_NUMBER] = {0}, + pass_count_1[DQS_NUMBER] = {0}, dqs_done[DQS_NUMBER] = {0}; + u8 min_coarse_tune2t[DQS_NUMBER], min_coarse_tune0p5t[DQS_NUMBER], + min_fine_tune[DQS_NUMBER]; + u8 best_fine_tune[DQS_NUMBER], best_coarse_tune0p5t[DQS_NUMBER], + best_coarse_tune2t[DQS_NUMBER]; + u8 best_coarse_tune0p5t_p1[DQS_NUMBER], best_coarse_tune2t_p1[DQS_NUMBER]; + u8 dqs_high[DQS_NUMBER] = {0}, dqs_transition[DQS_NUMBER] = {0}; + u8 dly_coarse_large_cnt[DQS_NUMBER] = {0}, dly_coarse_0p5t_cnt[DQS_NUMBER] = {0}, + dly_fine_tune_cnt[DQS_NUMBER] = {0}; + u32 coarse_start, coarse_end; + + struct reg_value regs_bak[] = { + {&ch[chn].ao.stbcal}, + {&ch[chn].ao.stbcal1}, + {&ch[chn].ao.ddrconf0}, + {&ch[chn].ao.spcmd}, + {&ch[chn].ao.refctrl0}, + {&ch[chn].phy.b[0].dq[6]}, + {&ch[chn].phy.b[1].dq[6]}, + }; + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + fsp = get_freq_fsq(freq_group); + dramc_rx_dqs_isi_pulse_cg_switch(chn, false); + + dramc_mode_reg_write_by_rank(chn, rank, 0x1, mr->MR01Value[fsp] | 0x80); + dramc_rx_dqs_gating_cal_pre(chn, rank); + + u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); + dramc_engine2_init(chn, rank, TEST2_1_CAL, 0xaa000023, true); + + switch (freq_group) { + case LP4X_DDR1600: + coarse_start = 18; + break; + case LP4X_DDR2400: + coarse_start = 25; + break; + case LP4X_DDR3200: + coarse_start = 25; + break; + case LP4X_DDR3600: + coarse_start = 21; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + coarse_end = coarse_start + 12; + + dramc_dbg("[Gating]\n"); + + if (!fast_calib) { + dramc_rx_dqs_gating_cal_partial(chn, rank, + coarse_start, coarse_end, + freqDiv, pass_begin, pass_count, pass_count_1, dqs_done, + dqs_high, dqs_transition, dly_coarse_large_cnt, + dly_coarse_0p5t_cnt, dly_fine_tune_cnt); + dramc_engine2_end(chn, dummy_rd_backup); + } for (dqs = 0; dqs < DQS_NUMBER; dqs++) { - pass_count[dqs] = dqs_transition[dqs]; - min_fine_tune[dqs] = dly_fine_tune_cnt[dqs]; - min_coarse_tune0p5t[dqs] = dly_coarse_0p5t_cnt[dqs]; - min_coarse_tune2t[dqs] = dly_coarse_large_cnt[dqs]; - + if (fast_calib) { + dramc_dbg("[bypass Gating params] dqs: %d\n", dqs); + pass_count[dqs] = params->gating_pass_count[chn][rank][dqs]; + min_fine_tune[dqs] = params->gating_fine_tune[chn][rank][dqs]; + min_coarse_tune0p5t[dqs] = params->gating05T[chn][rank][dqs]; + min_coarse_tune2t[dqs] = params->gating2T[chn][rank][dqs]; + } else { + pass_count[dqs] = dqs_transition[dqs]; + min_fine_tune[dqs] = dly_fine_tune_cnt[dqs]; + min_coarse_tune0p5t[dqs] = dly_coarse_0p5t_cnt[dqs]; + min_coarse_tune2t[dqs] = dly_coarse_large_cnt[dqs]; + } u8 tmp_offset = pass_count[dqs] * DQS_GW_FINE_STEP / 2; u8 tmp_value = min_fine_tune[dqs] + tmp_offset; best_fine_tune[dqs] = tmp_value % RX_DLY_DQSIENSTB_LOOP; @@ -1024,26 +1033,26 @@ static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group, } for (dqs = 0; dqs < DQS_NUMBER; dqs++) - dramc_show("Best DQS%d dly(2T, 0.5T, fine tune)" - " = (%d, %d, %d)\n", dqs, best_coarse_tune2t[dqs], - best_coarse_tune0p5t[dqs], best_fine_tune[dqs]); + dramc_dbg("Best DQS%d dly(2T, 0.5T, fine tune)" + " = (%d, %d, %d)\n", dqs, best_coarse_tune2t[dqs], + best_coarse_tune0p5t[dqs], best_fine_tune[dqs]); for (dqs = 0; dqs < DQS_NUMBER; dqs++) - dramc_show("Best DQS%d P1 dly(2T, 0.5T, fine tune)" - " = (%d, %d, %d)\n", dqs, best_coarse_tune2t_p1[dqs], - best_coarse_tune0p5t_p1[dqs], best_fine_tune[dqs]); + dramc_dbg("Best DQS%d P1 dly(2T, 0.5T, fine tune)" + " = (%d, %d, %d)\n", dqs, best_coarse_tune2t_p1[dqs], + best_coarse_tune0p5t_p1[dqs], best_fine_tune[dqs]); for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) write32(regs_bak[i].addr, regs_bak[i].value); - MR01Value[fsp] &= 0x7f; - dramc_mode_reg_write_by_rank(chn, rank, 0x1, MR01Value[fsp]); + dramc_mode_reg_write_by_rank(chn, rank, 0x1, mr->MR01Value[fsp]); dramc_write_dqs_gating_result(chn, rank, best_coarse_tune2t, best_coarse_tune0p5t, best_coarse_tune2t_p1, best_coarse_tune0p5t_p1); - write32(&ch[chn].ao.shu[0].rk[rank].dqsien, - best_fine_tune[0] | (best_fine_tune[1] << 8)); + WRITE32_BITFIELDS(&ch[chn].ao.shu[0].rk[rank].dqsien, + SHURK_DQSIEN_DQS0IEN, best_fine_tune[0], + SHURK_DQSIEN_DQS1IEN, best_fine_tune[1]); dram_phy_reset(chn); } @@ -1056,26 +1065,24 @@ static void dramc_rx_rd_dqc_init(u8 chn, u8 rank) for (size_t b = 0; b < 2; b++) clrbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], 0x1 << 7); - clrsetbits_le32(&ch[chn].ao.mrs, - MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT); - setbits_le32(&ch[chn].ao.mpc_option, - 0x1 << MPC_OPTION_MPCRKEN_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank); + SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPCRKEN, 1); for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) temp_value |= ((0x5555 >> bit) & 0x1) << lpddr_phy_mapping[bit]; u16 mr15_golden_value = temp_value & 0xff; u16 mr20_golden_value = (temp_value >> 8) & 0xff; - clrsetbits_le32(&ch[chn].ao.mr_golden, - MR_GOLDEN_MR15_GOLDEN_MASK | MR_GOLDEN_MR20_GOLDEN_MASK, - (mr15_golden_value << 8) | mr20_golden_value); + SET32_BITFIELDS(&ch[chn].ao.mr_golden, + MR_GOLDEN_MR15_GOLDEN, mr15_golden_value, + MR_GOLDEN_MR20_GOLDEN, mr20_golden_value); } static u32 dramc_rx_rd_dqc_run(u8 chn) { u32 loop = 0; - setbits_le32(&ch[chn].ao.spcmdctrl, 1 << SPCMDCTRL_RDDQCDIS_SHIFT); - setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_RDDQCEN_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.spcmdctrl, SPCMDCTRL_RDDQCDIS, 1); + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_RDDQCEN, 1); while (!wait_us(10, read32(&ch[chn].nao.spcmdresp) & (0x1 << 7))) { if (loop++ > 10) @@ -1083,27 +1090,28 @@ static u32 dramc_rx_rd_dqc_run(u8 chn) } u32 result = read32(&ch[chn].nao.rdqc_cmp); - clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_RDDQCEN_SHIFT); - clrbits_le32(&ch[chn].ao.spcmdctrl, 1 << SPCMDCTRL_RDDQCDIS_SHIFT); + SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_RDDQCEN, 0); + SET32_BITFIELDS(&ch[chn].ao.spcmdctrl, SPCMDCTRL_RDDQCDIS, 0); return result; } static void dramc_rx_rd_dqc_end(u8 chn) { - clrbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, 0); } static void dramc_rx_vref_pre_setting(u8 chn) { - setbits_le32(&ch[chn].phy.b[0].dq[5], 0x1 << 16); - setbits_le32(&ch[chn].phy.b[1].dq[5], 0x1 << 16); + SET32_BITFIELDS(&ch[chn].phy.b[0].dq[5], B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy.b[1].dq[5], B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1); } static void dramc_set_rx_vref(u8 chn, u8 vref) { for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[5], 0x3f, vref << 0); + SET32_BITFIELDS(&ch[chn].phy.shu[0].b[b].dq[5], + SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0, vref); dramc_dbg("set rx vref :%d\n", vref); } @@ -1150,38 +1158,34 @@ static void dramc_transfer_dly_tune(u8 chn, u32 dly, u32 adjust_center, static void dramc_set_rx_dly_factor(u8 chn, u8 rank, enum RX_TYPE type, u32 val) { - u32 tmp, mask; + int b, dq; switch (type) { case RX_DQ: - tmp = (val << 24 | val << 16 | val << 8 | val); - for (size_t dq = 2; dq < 6; dq++) { - write32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[dq], tmp); - write32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[dq], tmp); - } + for (dq = 2; dq < 6; dq++) + for (b = 0; b < 2; b++) + WRITE32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].b[b].dq[dq], + SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0, val, + SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0, val, + SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0, val, + SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0, val); break; case RX_DQM: - tmp = (val << 8 | val); - mask = SHU1_B0_DQ6_RK_RX_ARDQM0_F_DLY_B0_MASK | - SHU1_B0_DQ6_RK_RX_ARDQM0_R_DLY_B0_MASK; - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[6], - mask, tmp); - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[6], - mask, tmp); + for (b = 0; b < 2; b++) + SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].b[b].dq[6], + SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0, val, + SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0, val); break; case RX_DQS: - tmp = (val << 24 | val << 16); - mask = SHU1_B0_DQ6_RK_RX_ARDQS0_F_DLY_B0_MASK | - SHU1_B0_DQ6_RK_RX_ARDQS0_R_DLY_B0_MASK; - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[6], - mask, tmp); - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[6], - mask, tmp); + for (b = 0; b < 2; b++) + SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].b[b].dq[6], + SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0, val, + SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0, val); break; default: - dramc_show("error calibration type:%d\n", type); + dramc_err("error calibration type: %d\n", type); break; } } @@ -1227,13 +1231,13 @@ static void dramc_set_tx_dly_factor(u8 chn, u8 rk, if (type == TX_WIN_DQ_DQM || type == TX_WIN_DQ_ONLY) { for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rk].b[b].dq[7], - FINE_TUNE_DQ_MASK, dly_tune.fine_tune << 8); + SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rk].b[b].dq[7], + FINE_TUNE_DQ, dly_tune.fine_tune); } if (type == TX_WIN_DQ_DQM) { for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rk].b[b].dq[7], - FINE_TUNE_DQM_MASK, dly_tune.fine_tune << 16); + SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rk].b[b].dq[7], + FINE_TUNE_DQM, dly_tune.fine_tune); } } @@ -1294,7 +1298,7 @@ static void dramc_get_dly_range(u8 chn, u8 rank, enum CAL_TYPE type, *end = *begin + 64; break; default: - dramc_show("error calibration type:%d\n", type); + dramc_err("error calibration type: %d\n", type); break; } } @@ -1421,7 +1425,7 @@ static bool dramk_calc_best_vref(enum CAL_TYPE type, u8 vref, break; default: - dramc_show("error calibration type:%d\n", type); + dramc_err("error calibration type: %d\n", type); break; } @@ -1486,10 +1490,10 @@ static void dramc_set_tx_best_dly_factor(u8 chn, u8 rank_start, u8 type, 0x77777777, dqm_small | (dqm_small_oen << 16)); for (size_t byte = 0; byte < 2; byte++) - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7], - FINE_TUNE_DQ_MASK | FINE_TUNE_DQM_MASK, - (dqdly_tune[byte].fine_tune << 8) | - (dqmdly_tune[byte].fine_tune << 16)); + SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7], + FINE_TUNE_DQ, dqdly_tune[byte].fine_tune, + FINE_TUNE_DQM, dqmdly_tune[byte].fine_tune); + if (use_delay_cell == 1) { for (size_t byte = 0; byte < DQS_NUMBER; byte++) write32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[0], @@ -1548,9 +1552,35 @@ static void dramc_set_dqdqs_dly(u8 chn, u8 rank, enum CAL_TYPE type, u8 *small_v dramc_set_tx_dly_factor(chn, rank, type, small_value, dly); } +static void dramc_set_tx_dly_center(struct per_byte_dly *center_dly, + const struct win_perbit_dly *vref_dly) +{ + int index; + struct per_byte_dly *dly; + + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + dly = ¢er_dly[byte]; + dly->min_center = 0xffff; + dly->max_center = 0; + + for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit++) { + index = bit + 8 * byte; + if (vref_dly[index].win_center < dly->min_center) + dly->min_center = vref_dly[index].win_center; + if (vref_dly[index].win_center > dly->max_center) + dly->max_center = vref_dly[index].win_center; + } + dramc_dbg("center_dly[%d].min_center = %d, " + "center_dly[%d].max_center = %d\n", + byte, center_dly[byte].min_center, + byte, center_dly[byte].max_center); + } +} + static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx, struct win_perbit_dly *vref_dly, enum CAL_TYPE type, u8 freq_group, - u16 *tx_dq_precal_result, u16 dly_cell_unit, const struct sdram_params *params) + u16 *tx_dq_precal_result, u16 dly_cell_unit, const struct sdram_params *params, + const bool fast_calib) { int index, clock_rate; u8 use_delay_cell; @@ -1581,20 +1611,23 @@ static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx, else use_delay_cell = 0; - for (u8 byte = 0; byte < DQS_NUMBER; byte++) { - center_dly[byte].min_center = 0xffff; - center_dly[byte].max_center = 0; - - for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit++) { - index = bit + 8 * byte; - if (vref_dly[index].win_center < center_dly[byte].min_center) - center_dly[byte].min_center = vref_dly[index].win_center; - if (vref_dly[index].win_center > center_dly[byte].max_center) - center_dly[byte].max_center = vref_dly[index].win_center; + if (fast_calib && bypass_tx) { + dramc_dbg("bypass TX\n"); + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + center_dly[byte].min_center = params->tx_center_min[chn][rank][byte]; + center_dly[byte].max_center = params->tx_center_max[chn][rank][byte]; + for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit++) { + index = bit + 8 * byte; + vref_dly[index].win_center = + params->tx_win_center[chn][rank][index]; + vref_dly[index].best_first = + params->tx_first_pass[chn][rank][index]; + vref_dly[index].best_last = + params->tx_last_pass[chn][rank][index]; + } } - dramc_dbg("[channel %d] [rank %d] byte:%d, center_dly[byte].min_center:%d, center_dly[byte].max_center:%d\n", - chn, rank, byte, center_dly[byte].min_center, - center_dly[byte].max_center); + } else { + dramc_set_tx_dly_center(center_dly, vref_dly); } for (u8 byte = 0; byte < DQS_NUMBER; byte++) { @@ -1697,13 +1730,57 @@ static u32 dram_k_perbit(u8 chn, enum CAL_TYPE type) return err_value; } +static void dramc_window_perbit_cal_partial(u8 chn, u8 rank, + s16 dly_begin, s16 dly_end, s16 dly_step, + enum CAL_TYPE type, u8 *small_value, u8 vref_scan_enable, + struct win_perbit_dly *win_perbit) +{ + u32 finish_bit = 0; + + for (s16 dly = dly_begin; dly < dly_end; dly += dly_step) { + dramc_set_dqdqs_dly(chn, rank, type, small_value, dly); + + u32 err_value = dram_k_perbit(chn, type); + if (!vref_scan_enable) + dramc_dbg("%d ", dly); + + for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { + bool bit_fail = (err_value & ((u32) 1 << bit)) != 0; + + /* pass window bigger than 7, + * consider as real pass window. + */ + if (dramc_check_dqdqs_win(&(win_perbit[bit]), + dly, dly_end, bit_fail) > 7) + finish_bit |= (1 << bit); + + if (vref_scan_enable) + continue; + + dramc_dbg("%s", bit_fail ? "x" : "o"); + if (bit % DQS_BIT_NUMBER == 7) + dramc_dbg(" "); + } + + if (!vref_scan_enable) + dramc_dbg(" [MSB]\n"); + + if (finish_bit == 0xffff && (err_value & 0xffff) == 0xffff) { + dramc_dbg("all bits window found, " + "early break! delay=%#x\n", dly); + break; + } + } +} + static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group, - enum CAL_TYPE type, const struct sdram_params *params) + enum CAL_TYPE type, const struct sdram_params *params, + const bool fast_calib) { u8 vref = 0, vref_begin = 0, vref_end = 1, vref_step = 1, vref_use = 0; u8 vref_scan_enable = 0, small_reg_value = 0xff; - s16 dly, dly_begin = 0, dly_end = 0, dly_step = 1; - u32 dummy_rd_bak_engine2 = 0, err_value, finish_bit, win_min_max = 0; + s16 dly_begin = 0, dly_end = 0, dly_step = 1; + u32 dummy_rd_bak_engine2 = 0, finish_bit, win_min_max = 0; static u16 dq_precal_result[DQS_NUMBER]; struct vref_perbit_dly vref_dly; struct win_perbit_dly win_perbit[DQ_DATA_WIDTH]; @@ -1711,16 +1788,30 @@ static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group, u8 fsp = get_freq_fsq(freq_group); u8 vref_range = !fsp; + bool bypass_tx = !fsp; dramc_get_vref_prop(rank, type, fsp, &vref_scan_enable, &vref_begin, &vref_end); dramc_get_dly_range(chn, rank, type, freq_group, dq_precal_result, &dly_begin, &dly_end, params); + if (fast_calib) { + if (type == RX_WIN_TEST_ENG && vref_scan_enable == 1) { + vref_begin = params->rx_vref[chn]; + vref_end = vref_begin + 1; + dramc_dbg("bypass RX vref: %d\n", vref_begin); + } else if (type == TX_WIN_DQ_ONLY) { + vref_begin = params->tx_vref[chn][rank]; + vref_end = vref_begin + 1; + dramc_dbg("bypass TX vref: %d\n", vref_begin); + } + vref_dly.best_vref = vref_begin; + } + if ((type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) && fsp == FSP_0) dly_step = 2; - dramc_dbg("[channel %d] [rank %d] type:%d, vref_enable:%d, vref range[%d:%d]\n", + dramc_dbg("[channel %d] [rank %d] type: %d, vref_enable: %d, vref range[%d : %d]\n", chn, rank, type, vref_scan_enable, vref_begin, vref_end); if (type == TX_WIN_DQ_ONLY || type == TX_WIN_DQ_DQM) { @@ -1735,6 +1826,17 @@ static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group, vref_step = 2; } + if (fast_calib && bypass_tx && + (type == TX_WIN_DQ_ONLY || type == TX_WIN_DQ_DQM)) { + dramc_set_tx_best_dly(chn, rank, true, vref_dly.perbit_dly, + type, freq_group, dq_precal_result, dly_cell_unit, + params, fast_calib); + + if (vref_scan_enable) + dramc_set_vref(chn, rank, type, vref_dly.best_vref); + return 0; + } + if (type == RX_WIN_RD_DQC) { dramc_rx_rd_dqc_init(chn, rank); } else { @@ -1770,36 +1872,20 @@ static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group, RX_DQ, FIRST_DQ_DELAY); } - for (dly = dly_begin; dly < dly_end; dly += dly_step) { - dramc_set_dqdqs_dly(chn, rank, type, &small_reg_value, dly); - - err_value = dram_k_perbit(chn, type); - if (!vref_scan_enable) - dramc_dbg("%d ", dly); - + if (fast_calib && + (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG)) { + dramc_dbg("bypass RX params\n"); for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { - bool bit_fail = (err_value & ((u32) 1 << bit)) != 0; - - /* pass window bigger than 7, consider as real pass window */ - if (dramc_check_dqdqs_win(&(win_perbit[bit]), - dly, dly_end, bit_fail) > 7) - finish_bit |= (1 << bit); - - if (vref_scan_enable) - continue; - dramc_dbg("%s", bit_fail ? "x" : "o"); - if (bit % DQS_BIT_NUMBER == 7) - dramc_dbg(" "); - } - - if (!vref_scan_enable) - dramc_dbg(" [MSB]\n"); - - if (finish_bit == 0xffff && (err_value & 0xffff) == 0xffff) { - dramc_dbg("all bits window found, early break! delay=0x%x\n", - dly); - break; + win_perbit[bit].best_first = + params->rx_firspass[chn][rank][bit]; + win_perbit[bit].best_last = + params->rx_lastpass[chn][rank][bit]; } + } else { + dramc_window_perbit_cal_partial(chn, rank, + dly_begin, dly_end, dly_step, + type, &small_reg_value, + vref_scan_enable, win_perbit); } for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) @@ -1807,16 +1893,15 @@ static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group, win_perbit[bit].best_first, win_perbit[bit].best_last, win_perbit[bit].best_last - win_perbit[bit].best_first); - if (dramk_calc_best_vref(type, vref_use, &vref_dly, win_perbit, &win_min_max)) + if (dramk_calc_best_vref(type, vref_use, &vref_dly, + win_perbit, &win_min_max)) break; } - if (type == RX_WIN_RD_DQC) { + if (type == RX_WIN_RD_DQC) dramc_rx_rd_dqc_end(chn); - } else { - dramc_engine2_end(chn); - write32(&ch[chn].ao.dummy_rd, dummy_rd_bak_engine2); - } + else + dramc_engine2_end(chn, dummy_rd_bak_engine2); if (vref_scan_enable && type == RX_WIN_TEST_ENG) dramc_set_vref(chn, rank, type, vref_dly.best_vref); @@ -1824,8 +1909,9 @@ static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group, if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) dramc_set_rx_best_dly(chn, rank, vref_dly.perbit_dly); else - dramc_set_tx_best_dly(chn, rank, false, vref_dly.perbit_dly, type, - freq_group, dq_precal_result, dly_cell_unit, params); + dramc_set_tx_best_dly(chn, rank, false, + vref_dly.perbit_dly, type, freq_group, + dq_precal_result, dly_cell_unit, params, fast_calib); if (vref_scan_enable && type == TX_WIN_DQ_ONLY) dramc_set_vref(chn, rank, type, vref_dly.best_vref); @@ -1838,12 +1924,10 @@ static void dramc_dle_factor_handler(u8 chn, u8 val, u8 freq_group) u8 start_ext2 = 0, start_ext3 = 0, last_ext2 = 0, last_ext3 = 0; val = MAX(val, 2); - clrsetbits_le32(&ch[chn].ao.shu[0].conf[1], - SHU_CONF1_DATLAT_MASK | SHU_CONF1_DATLAT_DSEL_MASK | - SHU_CONF1_DATLAT_DSEL_PHY_MASK, - (val << SHU_CONF1_DATLAT_SHIFT) | - ((val - 2) << SHU_CONF1_DATLAT_DSEL_SHIFT) | - ((val - 2) << SHU_CONF1_DATLAT_DSEL_PHY_SHIFT)); + SET32_BITFIELDS(&ch[chn].ao.shu[0].conf[1], + SHU_CONF1_DATLAT, val, + SHU_CONF1_DATLAT_DSEL, val - 2, + SHU_CONF1_DATLAT_DSEL_PHY, val - 2); if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) start_ext2 = 1; @@ -1853,19 +1937,25 @@ static void dramc_dle_factor_handler(u8 chn, u8 val, u8 freq_group) else if (val >= 18) last_ext2 = 1; - clrsetbits_le32(&ch[chn].ao.shu[0].pipe, (0x1 << 31) | (0x1 << 30) | (0x1 << 29) | - (0x1 << 28) | (0x1 << 27) | (0x1 << 26), - (0x1 << 31) | (0x1 << 30) | (start_ext2 << 29) | - (last_ext2 << 28) | (start_ext3 << 27) | (last_ext3 << 26)); + SET32_BITFIELDS(&ch[chn].ao.shu[0].pipe, + SHU_PIPE_READ_START_EXTEND1, 1, + SHU_PIPE_DLE_LAST_EXTEND1, 1, + SHU_PIPE_READ_START_EXTEND2, start_ext2, + SHU_PIPE_DLE_LAST_EXTEND2, last_ext2, + SHU_PIPE_READ_START_EXTEND3, start_ext3, + SHU_PIPE_DLE_LAST_EXTEND3, last_ext3); dram_phy_reset(chn); } -static u8 dramc_rx_datlat_cal(u8 chn, u8 rank, u8 freq_group, const struct sdram_params *params) +static u8 dramc_rx_datlat_cal(u8 chn, u8 rank, u8 freq_group, + const struct sdram_params *params, const bool fast_calib, + bool *test_passed) { - u32 datlat, begin = 0, first = 0, sum = 0, best_step; + u32 datlat, begin = 0, first = 0, sum = 0, best_step; u32 datlat_start = 7; - best_step = read32(&ch[chn].ao.shu[0].conf[1]) & SHU_CONF1_DATLAT_MASK; + *test_passed = true; + best_step = READ32_BITFIELD(&ch[chn].ao.shu[0].conf[1], SHU_CONF1_DATLAT); dramc_dbg("[DATLAT] start. CH%d RK%d DATLAT Default: 0x%x\n", chn, rank, best_step); @@ -1873,45 +1963,52 @@ static u8 dramc_rx_datlat_cal(u8 chn, u8 rank, u8 freq_group, const struct sdram u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); dramc_engine2_init(chn, rank, TEST2_1_CAL, TEST2_2_CAL, false); - for (datlat = datlat_start; datlat < DATLAT_TAP_NUMBER; datlat++) { - dramc_dle_factor_handler(chn, datlat, freq_group); + if (fast_calib) { + best_step = params->rx_datlat[chn][rank]; + dramc_dbg("bypass DATLAT, best_step: %d\n", best_step); + } else { + for (datlat = datlat_start; datlat < DATLAT_TAP_NUMBER; datlat++) { + dramc_dle_factor_handler(chn, datlat, freq_group); - u32 err = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); - if (err == 0) { - if (begin == 0) { - first = datlat; - begin = 1; + u32 err = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); + if (err == 0) { + if (begin == 0) { + first = datlat; + begin = 1; + } + if (begin == 1) { + sum++; + if (sum > 4) + break; + } + } else { + if (begin == 1) + begin = 0xff; } - if (begin == 1) { - sum++; - if (sum > 4) - break; - } - } else { - if (begin == 1) - begin = 0xff; + + dramc_dbg("Datlat=%2d, err_value=0x%4x, sum=%d\n", datlat, err, sum); } - dramc_dbg("Datlat=%2d, err_value=0x%4x, sum=%d\n", datlat, err, sum); + dramc_engine2_end(chn, dummy_rd_backup); + + *test_passed = (sum != 0); + if (!*test_passed) { + dramc_err("DRAM memory test failed\n"); + return 0; + } + + if (sum <= 3) + best_step = first + (sum >> 1); + else + best_step = first + 2; + dramc_dbg("First_step=%d, total pass=%d, best_step=%d\n", + begin, sum, best_step); } - dramc_engine2_end(chn); - write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); - - assert(sum != 0); - - if (sum <= 3) - best_step = first + (sum >> 1); - else - best_step = first + 2; - dramc_dbg("First_step=%d, total pass=%d, best_step=%d\n", - begin, sum, best_step); - dramc_dle_factor_handler(chn, best_step, freq_group); - clrsetbits_le32(&ch[chn].ao.padctrl, 0x3 | (0x1 << 3), - (0x1 << PADCTRL_DQIENQKEND_SHIFT) | - (0x1 << PADCTRL_DQIENLATEBEGIN_SHIFT)); + SET32_BITFIELDS(&ch[chn].ao.padctrl, + PADCTRL_DQIENQKEND, 1, PADCTRL_DQIENLATEBEGIN, 1); return (u8) best_step; } @@ -1982,12 +2079,12 @@ static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group) } } - read_dqsinctl = (read32(&ch[chn].ao.shu[0].rk[0].dqsctl) & - SHURK_DQSCTL_DQSINCTL_MASK) - dqsinctl; + read_dqsinctl = READ32_BITFIELD(&ch[chn].ao.shu[0].rk[0].dqsctl, + SHURK_DQSCTL_DQSINCTL) - dqsinctl; rankinctl_root = (read_dqsinctl >= 2) ? (read_dqsinctl - 2) : 0; - clrsetbits_le32(&ch[chn].ao.shu[0].rk[0].dqsctl, 0xf, read_dqsinctl << 0); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[1].dqsctl, 0xf, read_dqsinctl << 0); + SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[0].dqsctl, SHURK_DQSCTL_DQSINCTL, read_dqsinctl); + SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[1].dqsctl, SHURK_DQSCTL_DQSINCTL, read_dqsinctl); clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, (0xf << 28) | (0xf << 20) | (0xf << 24) | 0xf, (read_dqsinctl << 28) | (rankinctl_root << 20) | @@ -1998,25 +2095,52 @@ static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group) (0xff << 8) | (0x9 << 2) | ROEN); } -void dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group) +int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group, + const struct mr_value *mr) { + bool fast_calib; + switch (pams->source) { + case DRAMC_PARAM_SOURCE_SDRAM_CONFIG: + fast_calib = false; + break; + case DRAMC_PARAM_SOURCE_FLASH: + fast_calib = true; + break; + default: + die("Invalid DRAM param source %u\n", pams->source); + return -1; + } + + bool test_passed; u8 rx_datlat[RANK_MAX] = {0}; for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { - dramc_show("Start K ch:%d, rank:%d\n", chn, rk); - dramc_auto_refresh_switch(chn, false); - dramc_cmd_bus_training(chn, rk, freq_group, pams); + dramc_dbg("Start K: freq=%d, ch=%d, rank=%d\n", + freq_group, chn, rk); + dramc_cmd_bus_training(chn, rk, freq_group, pams, + fast_calib); dramc_write_leveling(chn, rk, freq_group, pams->wr_level); dramc_auto_refresh_switch(chn, true); - dramc_rx_dqs_gating_cal(chn, rk, freq_group, pams); - dramc_window_perbit_cal(chn, rk, freq_group, RX_WIN_RD_DQC, pams); - dramc_window_perbit_cal(chn, rk, freq_group, TX_WIN_DQ_DQM, pams); - dramc_window_perbit_cal(chn, rk, freq_group, TX_WIN_DQ_ONLY, pams); - rx_datlat[rk] = dramc_rx_datlat_cal(chn, rk, freq_group, pams); - dramc_window_perbit_cal(chn, rk, freq_group, RX_WIN_TEST_ENG, pams); + + dramc_rx_dqs_gating_cal(chn, rk, freq_group, pams, + fast_calib, mr); + dramc_window_perbit_cal(chn, rk, freq_group, + RX_WIN_RD_DQC, pams, fast_calib); + dramc_window_perbit_cal(chn, rk, freq_group, + TX_WIN_DQ_DQM, pams, fast_calib); + dramc_window_perbit_cal(chn, rk, freq_group, + TX_WIN_DQ_ONLY, pams, fast_calib); + rx_datlat[rk] = dramc_rx_datlat_cal(chn, rk, freq_group, + pams, fast_calib, &test_passed); + if (!test_passed) + return -2; + dramc_window_perbit_cal(chn, rk, freq_group, + RX_WIN_TEST_ENG, pams, fast_calib); + dramc_auto_refresh_switch(chn, false); } dramc_rx_dqs_gating_post_process(chn, freq_group); dramc_dual_rank_rx_datlat_cal(chn, freq_group, rx_datlat[0], rx_datlat[1]); } + return 0; } diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c index daa06caeae..604592f5cb 100644 --- a/src/soc/mediatek/mt8183/dsi.c +++ b/src/soc/mediatek/mt8183/dsi.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 8bd8a39a35..7cd631ca0b 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -14,10 +14,13 @@ */ #include -#include -#include +#include #include #include +#include +#include +#include +#include static const u8 freq_shuffle[DRAM_DFS_SHUFFLE_MAX] = { [DRAM_DFS_SHUFFLE_1] = LP4X_DDR3200, @@ -38,6 +41,13 @@ u32 frequency_table[LP4X_DDRFREQ_MAX] = { [LP4X_DDR3600] = 3600, }; +static const u32 vcore_lp4x[LP4X_DDRFREQ_MAX] = { + [LP4X_DDR1600] = 725000, + [LP4X_DDR2400] = 725000, + [LP4X_DDR3200] = 762500, + [LP4X_DDR3600] = 800000, +}; + struct emi_regs *emi_regs = (void *)EMI_BASE; const u8 phy_mapping[CHANNEL_MAX][16] = { [CHANNEL_A] = { @@ -179,6 +189,24 @@ static void global_option_init(const struct sdram_params *params) set_MRR_pinmux_mapping(); } +static void set_vcore_voltage(u8 freq_group) +{ + const u32 vcore = vcore_lp4x[freq_group]; + dramc_dbg("Set DRAM voltage (freq %d): vcore = %u\n", + frequency_table[freq_group], vcore); + pmic_set_vcore_vol(vcore); +} + +static void set_vdram1_vddq_voltage(void) +{ + const u32 vdram1 = 1125000; + const u32 vddq = 600000; + dramc_dbg("Set DRAM voltage: vdram1 = %u, vddq = %u\n", + vdram1, vddq); + pmic_set_vdram1_vol(vdram1); + pmic_set_vddq_vol(vddq); +} + static void emi_esl_setting1(void) { dramc_set_broadcast(DRAMC_BROADCAST_ON); @@ -312,23 +340,38 @@ static void dramc_ac_timing_optimize(u8 freq_group) } } -static void dfs_init_for_calibration(const struct sdram_params *params, u8 freq_group) +static void spm_pinmux_setting(void) { - dramc_init(params, freq_group); + clrsetbits_le32(&mtk_spm->poweron_config_set, + (0xffff << 16) | (0x1 << 0), (0xb16 << 16) | (0x1 << 0)); + clrbits_le32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16)); + write32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff); + write32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff); +} + +static void dfs_init_for_calibration(const struct sdram_params *params, + u8 freq_group, + struct dram_shared_data *shared) +{ + dramc_init(params, freq_group, shared); dramc_apply_config_before_calibration(freq_group); } -static void init_dram(const struct sdram_params *params, u8 freq_group) +static void init_dram(const struct sdram_params *params, u8 freq_group, + struct dram_shared_data *shared) { global_option_init(params); emi_init(params); dramc_set_broadcast(DRAMC_BROADCAST_ON); dramc_init_pre_settings(); - dramc_sw_impedance_cal(params, ODT_OFF); - dramc_sw_impedance_cal(params, ODT_ON); + spm_pinmux_setting(); - dfs_init_for_calibration(params, freq_group); + dramc_sw_impedance_cal(params, ODT_OFF, &shared->impedance); + dramc_sw_impedance_cal(params, ODT_ON, &shared->impedance); + + dramc_init(params, freq_group, shared); + dramc_apply_config_before_calibration(freq_group); emi_init2(params); } @@ -341,32 +384,165 @@ void enable_emi_dcm(void) clrbits_le32(&ch[chn].emi.chn_conb, 0xff << 24); } -static void do_calib(const struct sdram_params *params, u8 freq_group) +struct shuffle_reg_addr { + u32 start; + u32 end; +}; + +#define AO_SHU_ADDR(s, e) \ + { \ + .start = offsetof(struct dramc_ao_regs_shu, s), \ + .end = offsetof(struct dramc_ao_regs_shu, e), \ + } + +static const struct shuffle_reg_addr dramc_regs[] = { + AO_SHU_ADDR(actim, hwset_vrcg), + AO_SHU_ADDR(rk[0], rk[0].dqs2dq_cal5), + AO_SHU_ADDR(rk[1], rk[1].dqs2dq_cal5), + AO_SHU_ADDR(rk[2], rk[2].dqs2dq_cal5), + AO_SHU_ADDR(dqsg_retry, dqsg_retry), +}; + +#define PHY_SHU_ADDR(s, e) \ + { \ + .start = offsetof(struct ddrphy_ao_shu, s), \ + .end = offsetof(struct ddrphy_ao_shu, e), \ + } + +static const struct shuffle_reg_addr phy_regs[] = { + PHY_SHU_ADDR(b[0], b[0].dll[1]), + PHY_SHU_ADDR(b[1], b[1].dll[1]), + PHY_SHU_ADDR(ca_cmd, ca_dll[1]), + PHY_SHU_ADDR(pll[0], pll[15]), + PHY_SHU_ADDR(pll20, misc0), + PHY_SHU_ADDR(rk[0].b[0], rk[0].b[0].rsvd_20[3]), + PHY_SHU_ADDR(rk[0].b[1], rk[0].b[1].rsvd_20[3]), + PHY_SHU_ADDR(rk[0].ca_cmd, rk[0].rsvd_22[1]), + PHY_SHU_ADDR(rk[1].b[0], rk[1].b[0].rsvd_20[3]), + PHY_SHU_ADDR(rk[1].b[1], rk[1].b[1].rsvd_20[3]), + PHY_SHU_ADDR(rk[1].ca_cmd, rk[1].rsvd_22[1]), + PHY_SHU_ADDR(rk[2].b[0], rk[2].b[0].rsvd_20[3]), + PHY_SHU_ADDR(rk[2].b[1], rk[2].b[1].rsvd_20[3]), + PHY_SHU_ADDR(rk[2].ca_cmd, rk[2].rsvd_22[1]), +}; + +static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle) { - dramc_show("Start K freq group:%d\n", frequency_table[freq_group]); - dramc_calibrate_all_channels(params, freq_group); - dramc_ac_timing_optimize(freq_group); - dramc_show("%s K freq group:%d finish!\n", __func__, frequency_table[freq_group]); + u32 offset, chn, index, value; + u8 *src_addr, *dst_addr; + + if (src_shuffle == dst_shuffle) + return; + + dramc_dbg("Save shuffle %u to shuffle %u\n", src_shuffle, dst_shuffle); + + for (chn = 0; chn < CHANNEL_MAX; chn++) { + /* DRAMC */ + for (index = 0; index < ARRAY_SIZE(dramc_regs); index++) { + for (offset = dramc_regs[index].start; + offset <= dramc_regs[index].end; offset += 4) { + src_addr = (u8 *)&ch[chn].ao.shu[src_shuffle] + + offset; + dst_addr = (u8 *)&ch[chn].ao.shu[dst_shuffle] + + offset; + write32(dst_addr, read32(src_addr)); + + } + } + + /* DRAMC-exception-1 */ + src_addr = (u8 *)&ch[chn].ao.shuctrl2; + dst_addr = (u8 *)&ch[chn].ao.dvfsdll; + value = read32(src_addr) & 0x7f; + + if (dst_shuffle == DRAM_DFS_SHUFFLE_2) + clrsetbits_le32(dst_addr, 0x7f << 0x8, value << 0x8); + else if (dst_shuffle == DRAM_DFS_SHUFFLE_3) + clrsetbits_le32(dst_addr, 0x7f << 0x16, value << 0x16); + + /* DRAMC-exception-2 */ + src_addr = (u8 *)&ch[chn].ao.dvfsdll; + value = (read32(src_addr) >> 1) & 0x1; + + if (dst_shuffle == DRAM_DFS_SHUFFLE_2) + clrsetbits_le32(src_addr, 0x1 << 2, value << 2); + else if (dst_shuffle == DRAM_DFS_SHUFFLE_3) + clrsetbits_le32(src_addr, 0x1 << 3, value << 3); + + /* PHY */ + for (index = 0; index < ARRAY_SIZE(phy_regs); index++) { + for (offset = phy_regs[index].start; + offset <= phy_regs[index].end; offset += 4) { + src_addr = (u8 *)&ch[chn].phy.shu[src_shuffle] + + offset; + dst_addr = (u8 *)&ch[chn].phy.shu[dst_shuffle] + + offset; + write32(dst_addr, read32(src_addr)); + + } + } + } } -static void after_calib(void) -{ - dramc_apply_config_after_calibration(); - dramc_runtime_config(); -} - -void mt_set_emi(const struct sdram_params *params) +static int run_calib(const struct dramc_param *dparam, + struct dram_shared_data *shared, + const int shuffle, bool *first_run) { const u8 *freq_tbl; - u8 current_freqsel; if (CONFIG(MT8183_DRAM_EMCP)) freq_tbl = freq_shuffle_emcp; else freq_tbl = freq_shuffle; - current_freqsel = freq_tbl[DRAM_DFS_SHUFFLE_1]; - init_dram(params, current_freqsel); - do_calib(params, current_freqsel); - after_calib(); + const u8 freq_group = freq_tbl[shuffle]; + const struct sdram_params *params = &dparam->freq_params[shuffle]; + + set_vcore_voltage(freq_group); + + dramc_show("Run calibration (freq: %u, first: %d)\n", + frequency_table[freq_group], *first_run); + + if (*first_run) + init_dram(params, freq_group, shared); + else + dfs_init_for_calibration(params, freq_group, shared); + *first_run = false; + + dramc_dbg("Start K (current clock: %u\n", params->frequency); + if (dramc_calibrate_all_channels(params, freq_group, &shared->mr) != 0) + return -1; + dramc_ac_timing_optimize(freq_group); + dramc_dbg("K finished (current clock: %u\n", params->frequency); + + dramc_save_result_to_shuffle(DRAM_DFS_SHUFFLE_1, shuffle); + return 0; +} + +static void after_calib(const struct mr_value *mr) +{ + dramc_apply_config_after_calibration(mr); + dramc_runtime_config(); +} + +int mt_set_emi(const struct dramc_param *dparam) +{ + struct dram_shared_data shared; + bool first_run = true; + set_vdram1_vddq_voltage(); + + if (dparam->header.config & DRAMC_CONFIG_DVFS) { + if (run_calib(dparam, &shared, DRAM_DFS_SHUFFLE_3, + &first_run) != 0) + return -1; + if (run_calib(dparam, &shared, DRAM_DFS_SHUFFLE_2, + &first_run) != 0) + return -1; + } + + if (run_calib(dparam, &shared, DRAM_DFS_SHUFFLE_1, &first_run) != 0) + return -1; + + after_calib(&shared.mr); + return 0; } diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h index ef6eaf162c..4da948ec4a 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h @@ -37,7 +37,8 @@ enum { enum dram_odt_type { ODT_OFF = 0, - ODT_ON + ODT_ON, + ODT_MAX }; enum { @@ -58,4 +59,10 @@ enum { CBT_BYTE_MODE1 }; +enum { + FSP_0 = 0, + FSP_1, + FSP_MAX +}; + #endif /* _DRAMC_COMMON_MT8183_H_ */ diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_param.h b/src/soc/mediatek/mt8183/include/soc/dramc_param.h new file mode 100644 index 0000000000..1f4148bc8d --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/dramc_param.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_DRAMC_PARAM_H +#define SOC_MEDIATEK_MT8183_DRAMC_PARAM_H + +#include +#include + +#include "emi.h" + +enum { + DRAMC_PARAM_HEADER_MAGIC = 0x44524d4b, + DRAMC_PARAM_HEADER_VERSION = 2, +}; + +enum DRAMC_PARAM_STATUS_CODES { + DRAMC_SUCCESS = 0, + DRAMC_ERR_INVALID_MAGIC, + DRAMC_ERR_INVALID_VERSION, + DRAMC_ERR_INVALID_SIZE, + DRAMC_ERR_INVALID_CHECKSUM, + DRAMC_ERR_INVALID_FLAGS, + DRAMC_ERR_RECALIBRATE, + DRAMC_ERR_INIT_DRAM, + DRAMC_ERR_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_1ST_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_2ND_COMPLEX_RW_MEM_TEST, +}; + +/* Bit flags */ +enum DRAMC_PARAM_CONFIG { + DRAMC_CONFIG_EMCP = 0x0001, + DRAMC_CONFIG_DVFS = 0x0002, +}; + +enum DRAMC_PARAM_FLAGS { + DRAMC_FLAG_HAS_SAVED_DATA = 0x0001, +}; + +struct dramc_param_header { + u32 status; /* DRAMC_PARAM_STATUS_CODES */ + u32 magic; + u32 version; + u32 size; /* size of whole dramc_param */ + u16 config; /* DRAMC_PARAM_CONFIG */ + u16 flags; /* DRAMC_PARAM_FLAGS */ + u32 checksum; +}; + +struct dramc_param { + struct dramc_param_header header; + void (*do_putc)(unsigned char c); + struct sdram_params freq_params[DRAM_DFS_SHUFFLE_MAX]; +}; + +struct dramc_param_ops { + struct dramc_param *param; + bool (*read_from_flash)(struct dramc_param *dparam); + bool (*write_to_flash)(const struct dramc_param *dparam); +}; + +struct dramc_param *get_dramc_param_from_blob(void *blob); +int validate_dramc_param(const void *blob); +int is_valid_dramc_param(const void *blob); +int initialize_dramc_param(void *blob, u16 config); + +#endif /* SOC_MEDIATEK_MT8183_DRAMC_PARAM_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 1ce5f67470..54f009e9f0 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -20,6 +20,7 @@ #include #include +#define dramc_err(_x_...) printk(BIOS_ERR, _x_) #define dramc_show(_x_...) printk(BIOS_INFO, _x_) #if CONFIG(DEBUG_DRAM) #define dramc_dbg(_x_...) printk(BIOS_DEBUG, _x_) @@ -43,12 +44,6 @@ enum dram_te_op { TE_OP_READ_CHECK }; -enum { - FSP_0 = 0, - FSP_1, - FSP_MAX -}; - enum { PASS_RANGE_NA = 0x7fff }; @@ -105,13 +100,16 @@ void dramc_runtime_config(void); void dramc_set_broadcast(u32 onoff); u32 dramc_get_broadcast(void); u8 get_freq_fsq(u8 freq_group); -void dramc_init(const struct sdram_params *params, u8 freq_group); -void dramc_sw_impedance_save_reg(u8 freq_group); -void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term_option); +void dramc_init(const struct sdram_params *params, u8 freq_group, + struct dram_shared_data *shared); +void dramc_sw_impedance_save_reg(u8 freq_group, + const struct dram_impedance *impedance); +void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term_option, + struct dram_impedance *impedance); void dramc_apply_config_before_calibration(u8 freq_group); -void dramc_apply_config_after_calibration(void); -void dramc_calibrate_all_channels(const struct sdram_params *pams, - u8 freq_group); +void dramc_apply_config_after_calibration(const struct mr_value *mr); +int dramc_calibrate_all_channels(const struct sdram_params *pams, + u8 freq_group, const struct mr_value *mr); void dramc_hw_gating_onoff(u8 chn, bool onoff); void dramc_enable_phy_dcm(bool bEn); void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value); diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index fb8d7d78f9..b3ee6af4c7 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -16,6 +16,7 @@ #ifndef _DRAMC_REGISTER_H_ #define _DRAMC_REGISTER_H_ +#include #include #include @@ -178,88 +179,6 @@ struct dramc_nao_regs { }; check_member(dramc_nao_regs, testmode, 0x0000); -check_member(dramc_nao_regs, lbwdat0, 0x0004); -check_member(dramc_nao_regs, lbwdat1, 0x0008); -check_member(dramc_nao_regs, lbwdat2, 0x000c); -check_member(dramc_nao_regs, lbwdat3, 0x0010); -check_member(dramc_nao_regs, ckphchk, 0x0020); -check_member(dramc_nao_regs, dmmonitor, 0x0024); -check_member(dramc_nao_regs, testchip_dma1, 0x0030); -check_member(dramc_nao_regs, misc_statusa, 0x0080); -check_member(dramc_nao_regs, special_status, 0x0084); -check_member(dramc_nao_regs, spcmdresp, 0x0088); -check_member(dramc_nao_regs, mrr_status, 0x008c); -check_member(dramc_nao_regs, mrr_status2, 0x0090); -check_member(dramc_nao_regs, mrrdata0, 0x0094); -check_member(dramc_nao_regs, mrrdata1, 0x0098); -check_member(dramc_nao_regs, mrrdata2, 0x009c); -check_member(dramc_nao_regs, mrrdata3, 0x00a0); -check_member(dramc_nao_regs, drs_status, 0x00a8); -check_member(dramc_nao_regs, jmeter_st, 0x00bc); -check_member(dramc_nao_regs, tcmdo1lat, 0x00c0); -check_member(dramc_nao_regs, rdqc_cmp, 0x00c4); -check_member(dramc_nao_regs, ckphchk_status, 0x00c8); -check_member(dramc_nao_regs, hwmrr_push2pop_cnt, 0x010c); -check_member(dramc_nao_regs, hwmrr_status, 0x0110); -check_member(dramc_nao_regs, testrpt, 0x0120); -check_member(dramc_nao_regs, cmp_err, 0x0124); -check_member(dramc_nao_regs, test_abit_status1, 0x0128); -check_member(dramc_nao_regs, test_abit_status2, 0x012c); -check_member(dramc_nao_regs, test_abit_status3, 0x0130); -check_member(dramc_nao_regs, test_abit_status4, 0x0134); -check_member(dramc_nao_regs, dqsdly0, 0x0150); -check_member(dramc_nao_regs, dq_cal_max[0], 0x0154); -check_member(dramc_nao_regs, dqs_cal_min[0], 0x0174); -check_member(dramc_nao_regs, dqs_cal_max[0], 0x0194); -check_member(dramc_nao_regs, dqical0, 0x01b4); -check_member(dramc_nao_regs, dqical1, 0x01b8); -check_member(dramc_nao_regs, dqical2, 0x01bc); -check_member(dramc_nao_regs, dqical3, 0x01c0); -check_member(dramc_nao_regs, testchip_dma_status[0], 0x0200); -check_member(dramc_nao_regs, refresh_pop_counter, 0x0300); -check_member(dramc_nao_regs, freerun_26m_counter, 0x0304); -check_member(dramc_nao_regs, dramc_idle_counter, 0x0308); -check_member(dramc_nao_regs, r2r_page_hit_counter, 0x030c); -check_member(dramc_nao_regs, r2r_page_miss_counter, 0x0310); -check_member(dramc_nao_regs, r2r_interbank_counter, 0x0314); -check_member(dramc_nao_regs, r2w_page_hit_counter, 0x0318); -check_member(dramc_nao_regs, r2w_page_miss_counter, 0x031c); -check_member(dramc_nao_regs, r2w_interbank_counter, 0x0320); -check_member(dramc_nao_regs, w2r_page_hit_counter, 0x0324); -check_member(dramc_nao_regs, w2r_page_miss_counter, 0x0328); -check_member(dramc_nao_regs, w2r_interbank_counter, 0x032c); -check_member(dramc_nao_regs, w2w_page_hit_counter, 0x0330); -check_member(dramc_nao_regs, w2w_page_miss_counter, 0x0334); -check_member(dramc_nao_regs, w2w_interbank_counter, 0x0338); -check_member(dramc_nao_regs, dq0_toggle_counter, 0x036c); -check_member(dramc_nao_regs, dq1_toggle_counter, 0x0370); -check_member(dramc_nao_regs, dq2_toggle_counter, 0x0374); -check_member(dramc_nao_regs, dq3_toggle_counter, 0x0378); -check_member(dramc_nao_regs, dq0_toggle_counter_r, 0x037c); -check_member(dramc_nao_regs, dq1_toggle_counter_r, 0x0380); -check_member(dramc_nao_regs, dq2_toggle_counter_r, 0x0384); -check_member(dramc_nao_regs, dq3_toggle_counter_r, 0x0388); -check_member(dramc_nao_regs, read_bytes_counter, 0x038c); -check_member(dramc_nao_regs, write_bytes_counter, 0x0390); -check_member(dramc_nao_regs, dqssamplev, 0x0400); -check_member(dramc_nao_regs, dqsgnwcnt[0], 0x0408); -check_member(dramc_nao_regs, toggle_cnt, 0x0420); -check_member(dramc_nao_regs, dqs0_err_cnt, 0x0424); -check_member(dramc_nao_regs, dq_err_cnt0, 0x0428); -check_member(dramc_nao_regs, dqs1_err_cnt, 0x042c); -check_member(dramc_nao_regs, dq_err_cnt1, 0x0430); -check_member(dramc_nao_regs, dqs2_err_cnt, 0x0434); -check_member(dramc_nao_regs, dq_err_cnt2, 0x0438); -check_member(dramc_nao_regs, dqs3_err_cnt, 0x043c); -check_member(dramc_nao_regs, dq_err_cnt3, 0x0440); -check_member(dramc_nao_regs, iorgcnt, 0x0450); -check_member(dramc_nao_regs, dqsg_retry_state, 0x0454); -check_member(dramc_nao_regs, dqsg_retry_state1, 0x0458); -check_member(dramc_nao_regs, impcal_status1, 0x0460); -check_member(dramc_nao_regs, impcal_status2, 0x0464); -check_member(dramc_nao_regs, dqdrv_status, 0x0468); -check_member(dramc_nao_regs, cmddrv_status, 0x046c); -check_member(dramc_nao_regs, cmddrv1, 0x0470); check_member(dramc_nao_regs, cmddrv2, 0x0474); struct dramc_ao_regs_rk { @@ -369,7 +288,7 @@ struct dramc_ao_regs { uint32_t rsvd_10[46]; struct dramc_ao_regs_rk rk[3]; uint32_t rsvd_16[64]; - struct { + struct dramc_ao_regs_shu { uint32_t rsvd0[64]; uint32_t actim[7]; uint32_t actim_xrt; @@ -424,104 +343,6 @@ struct dramc_ao_regs { }; check_member(dramc_ao_regs, ddrconf0, 0x0000); -check_member(dramc_ao_regs, dramctrl, 0x0004); -check_member(dramc_ao_regs, misctl0, 0x0008); -check_member(dramc_ao_regs, perfctl0, 0x000c); -check_member(dramc_ao_regs, arbctl, 0x0010); -check_member(dramc_ao_regs, rstmask, 0x001c); -check_member(dramc_ao_regs, padctrl, 0x0020); -check_member(dramc_ao_regs, ckectrl, 0x0024); -check_member(dramc_ao_regs, drsctrl, 0x0028); -check_member(dramc_ao_regs, rkcfg, 0x0034); -check_member(dramc_ao_regs, dramc_pd_ctrl, 0x0038); -check_member(dramc_ao_regs, clkar, 0x003c); -check_member(dramc_ao_regs, clkctrl, 0x0040); -check_member(dramc_ao_regs, selfref_hwsave_flag, 0x0044); -check_member(dramc_ao_regs, srefctrl, 0x0048); -check_member(dramc_ao_regs, refctrl0, 0x004c); -check_member(dramc_ao_regs, refctrl1, 0x0050); -check_member(dramc_ao_regs, refratre_filter, 0x0054); -check_member(dramc_ao_regs, zqcs, 0x0058); -check_member(dramc_ao_regs, mrs, 0x005c); -check_member(dramc_ao_regs, spcmd, 0x0060); -check_member(dramc_ao_regs, spcmdctrl, 0x0064); -check_member(dramc_ao_regs, ppr_ctrl, 0x0068); -check_member(dramc_ao_regs, mpc_option, 0x006c); -check_member(dramc_ao_regs, refque_cnt, 0x0070); -check_member(dramc_ao_regs, hw_mrr_fun, 0x0074); -check_member(dramc_ao_regs, mrr_bit_mux1, 0x0078); -check_member(dramc_ao_regs, mrr_bit_mux2, 0x007c); -check_member(dramc_ao_regs, mrr_bit_mux3, 0x0080); -check_member(dramc_ao_regs, mrr_bit_mux4, 0x0084); -check_member(dramc_ao_regs, test2_5, 0x008c); -check_member(dramc_ao_regs, test2_0, 0x0090); -check_member(dramc_ao_regs, test2_1, 0x0094); -check_member(dramc_ao_regs, test2_2, 0x0098); -check_member(dramc_ao_regs, test2_3, 0x009c); -check_member(dramc_ao_regs, test2_4, 0x00a0); -check_member(dramc_ao_regs, wdt_dbg_signal, 0x00a4); -check_member(dramc_ao_regs, lbtest, 0x00ac); -check_member(dramc_ao_regs, catraining1, 0x00b0); -check_member(dramc_ao_regs, catraining2, 0x00b4); -check_member(dramc_ao_regs, write_lev, 0x00bc); -check_member(dramc_ao_regs, mr_golden, 0x00c0); -check_member(dramc_ao_regs, slp4_testmode, 0x00c4); -check_member(dramc_ao_regs, dqsoscr, 0x00c8); -check_member(dramc_ao_regs, dummy_rd, 0x00d0); -check_member(dramc_ao_regs, shuctrl, 0x00d4); -check_member(dramc_ao_regs, shuctrl1, 0x00d8); -check_member(dramc_ao_regs, shuctrl2, 0x00dc); -check_member(dramc_ao_regs, shuctrl3, 0x00e0); -check_member(dramc_ao_regs, shustatus, 0x00e4); -check_member(dramc_ao_regs, stbcal, 0x0200); -check_member(dramc_ao_regs, stbcal1, 0x0204); -check_member(dramc_ao_regs, stbcal2, 0x0208); -check_member(dramc_ao_regs, eyescan, 0x020c); -check_member(dramc_ao_regs, dvfsdll, 0x0210); -check_member(dramc_ao_regs, pre_tdqsck[0], 0x0218); -check_member(dramc_ao_regs, pre_tdqsck[1], 0x021c); -check_member(dramc_ao_regs, pre_tdqsck[2], 0x0220); -check_member(dramc_ao_regs, pre_tdqsck[3], 0x0224); -check_member(dramc_ao_regs, impcal, 0x022c); -check_member(dramc_ao_regs, impedamce_ctrl1, 0x0230); -check_member(dramc_ao_regs, impedamce_ctrl2, 0x0234); -check_member(dramc_ao_regs, impedamce_ctrl3, 0x0238); -check_member(dramc_ao_regs, impedamce_ctrl4, 0x023c); -check_member(dramc_ao_regs, dramc_dbg_sel1, 0x0240); -check_member(dramc_ao_regs, dramc_dbg_sel2, 0x0244); -check_member(dramc_ao_regs, shu[0].actim[0], 0x0800); -check_member(dramc_ao_regs, shu[0].actim_xrt, 0x081c); -check_member(dramc_ao_regs, shu[0].ac_time_05t, 0x0820); -check_member(dramc_ao_regs, shu[0].ac_derating0, 0x0824); -check_member(dramc_ao_regs, shu[0].ac_derating1, 0x0828); -check_member(dramc_ao_regs, shu[0].ac_derating_05t, 0x0830); -check_member(dramc_ao_regs, shu[0].conf[0], 0x0840); -check_member(dramc_ao_regs, shu[0].rankctl, 0x0858); -check_member(dramc_ao_regs, shu[0].ckectrl, 0x085c); -check_member(dramc_ao_regs, shu[0].odtctrl, 0x0860); -check_member(dramc_ao_regs, shu[0].impcal1, 0x0864); -check_member(dramc_ao_regs, shu[0].dqsosc_prd, 0x0868); -check_member(dramc_ao_regs, shu[0].dqsoscr, 0x086c); -check_member(dramc_ao_regs, shu[0].dqsoscr2, 0x0870); -check_member(dramc_ao_regs, shu[0].rodtenstb, 0x0874); -check_member(dramc_ao_regs, shu[0].pipe, 0x0878); -check_member(dramc_ao_regs, shu[0].test1, 0x087c); -check_member(dramc_ao_regs, shu[0].selph_ca1, 0x0880); -check_member(dramc_ao_regs, shu[0].selph_dqs0, 0x08a0); -check_member(dramc_ao_regs, shu[0].selph_dqs1, 0x08a4); -check_member(dramc_ao_regs, shu[0].drving[0], 0x08a8); -check_member(dramc_ao_regs, shu[0].wodt, 0x08c0); -check_member(dramc_ao_regs, shu[0].dqsg, 0x08c4); -check_member(dramc_ao_regs, shu[0].scintv, 0x08c8); -check_member(dramc_ao_regs, shu[0].misc, 0x08cc); -check_member(dramc_ao_regs, shu[0].dqs2dq_tx, 0x08d0); -check_member(dramc_ao_regs, shu[0].hwset_mr2, 0x08d4); -check_member(dramc_ao_regs, shu[0].hwset_mr13, 0x08d8); -check_member(dramc_ao_regs, shu[0].hwset_vrcg, 0x08dc); -check_member(dramc_ao_regs, shu[0].rk[0].dqsctl, 0x0A00); -check_member(dramc_ao_regs, shu[0].dqsg_retry, 0x0c54); -check_member(dramc_ao_regs, shu[1].dqsg_retry, 0x1254); -check_member(dramc_ao_regs, shu[2].dqsg_retry, 0x1854); check_member(dramc_ao_regs, shu[3].dqsg_retry, 0x1e54); struct dramc_ddrphy_regs_misc_stberr_rk { @@ -648,78 +469,6 @@ struct dramc_ddrphy_ao_regs { }; check_member(dramc_ddrphy_ao_regs, pll1, 0x0000); -check_member(dramc_ddrphy_ao_regs, b[0].dll_fine_tune[0], 0x0080); -check_member(dramc_ddrphy_ao_regs, b[0].dq[0], 0x0098); -check_member(dramc_ddrphy_ao_regs, b[0].tx_mck, 0x00d0); -check_member(dramc_ddrphy_ao_regs, ca_dll_fine_tune[0], 0x0180); -check_member(dramc_ddrphy_ao_regs, ca_cmd[0], 0x0198); -check_member(dramc_ddrphy_ao_regs, ca_tx_mck, 0x01d0); -check_member(dramc_ddrphy_ao_regs, misc_extlb[0], 0x0200); -check_member(dramc_ddrphy_ao_regs, dvfs_emi_clk, 0x0260); -check_member(dramc_ddrphy_ao_regs, misc_vref_ctrl, 0x0264); -check_member(dramc_ddrphy_ao_regs, misc_imp_ctrl0, 0x0268); -check_member(dramc_ddrphy_ao_regs, misc_imp_ctrl1, 0x026c); -check_member(dramc_ddrphy_ao_regs, misc_shu_opt, 0x0270); -check_member(dramc_ddrphy_ao_regs, misc_spm_ctrl0, 0x0274); -check_member(dramc_ddrphy_ao_regs, misc_spm_ctrl1, 0x0278); -check_member(dramc_ddrphy_ao_regs, misc_spm_ctrl2, 0x027c); -check_member(dramc_ddrphy_ao_regs, misc_spm_ctrl3, 0x0280); -check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl0, 0x0284); -check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl1, 0x0288); -check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl2, 0x028c); -check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl3, 0x0290); -check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl4, 0x0294); -check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl5, 0x0298); -check_member(dramc_ddrphy_ao_regs, misc_ctrl0, 0x029c); -check_member(dramc_ddrphy_ao_regs, misc_ctrl1, 0x02a0); -check_member(dramc_ddrphy_ao_regs, misc_ctrl2, 0x02a4); -check_member(dramc_ddrphy_ao_regs, misc_ctrl3, 0x02a8); -check_member(dramc_ddrphy_ao_regs, misc_ctrl4, 0x02ac); -check_member(dramc_ddrphy_ao_regs, misc_ctrl5, 0x02b0); -check_member(dramc_ddrphy_ao_regs, misc_extlb_rx[0], 0x02b4); -check_member(dramc_ddrphy_ao_regs, ckmux_sel, 0x0308); -check_member(dramc_ddrphy_ao_regs, misc_rxdvs[0], 0x05e0); -check_member(dramc_ddrphy_ao_regs, misc_rxdvs[1], 0x05e4); -check_member(dramc_ddrphy_ao_regs, misc_rxdvs[2], 0x05e8); -check_member(dramc_ddrphy_ao_regs, rfu_0x5ec, 0x05ec); -check_member(dramc_ddrphy_ao_regs, b0_rxdvs[0], 0x05f0); -check_member(dramc_ddrphy_ao_regs, r[0].b[0].rxdvs[0], 0x0600); -check_member(dramc_ddrphy_ao_regs, b1_rxdvs[0], 0x0670); -check_member(dramc_ddrphy_ao_regs, r[0].b[1].rxdvs[0], 0x0680); -check_member(dramc_ddrphy_ao_regs, ca_rxdvs0, 0x06F0); -check_member(dramc_ddrphy_ao_regs, r0_ca_rxdvs[0], 0x0700); -check_member(dramc_ddrphy_ao_regs, r[1].b[1].rxdvs[0], 0x0880); -check_member(dramc_ddrphy_ao_regs, r[1].rxdvs[0], 0x0900); -check_member(dramc_ddrphy_ao_regs, shu[0].b[0].dq[0], 0x0c00); -check_member(dramc_ddrphy_ao_regs, shu[0].b[1].dq[6], 0x0C98); -check_member(dramc_ddrphy_ao_regs, shu[0].ca_cmd[0], 0x0d00); -check_member(dramc_ddrphy_ao_regs, shu[0].ca_dll[0], 0x0d34); -check_member(dramc_ddrphy_ao_regs, shu[0].pll[0], 0x0d80); -check_member(dramc_ddrphy_ao_regs, shu[0].misc0, 0x0DF0); -check_member(dramc_ddrphy_ao_regs, shu[0].rk[0].b[0].dq[0], 0x0e00); -check_member(dramc_ddrphy_ao_regs, shu[0].rk[0].ca_cmd[9], 0x0ec4); -check_member(dramc_ddrphy_ao_regs, shu[0].rk[1].b[0].dq[0], 0x0f00); -check_member(dramc_ddrphy_ao_regs, shu[0].rk[1].ca_cmd[9], 0x0fc4); -check_member(dramc_ddrphy_ao_regs, shu[0].rk[2].b[0].dq[0], 0x1000); -check_member(dramc_ddrphy_ao_regs, shu[0].rk[2].ca_cmd[9], 0x10c4); -check_member(dramc_ddrphy_ao_regs, shu[2].b[0].dq[0], 0x1600); -check_member(dramc_ddrphy_ao_regs, shu[2].b[1].dq[0], 0x1680); -check_member(dramc_ddrphy_ao_regs, shu[2].ca_cmd[0], 0x1700); -check_member(dramc_ddrphy_ao_regs, shu[2].ca_dll[0], 0x1734); -check_member(dramc_ddrphy_ao_regs, shu[2].pll[0], 0x1780); -check_member(dramc_ddrphy_ao_regs, shu[2].misc0, 0x17F0); -check_member(dramc_ddrphy_ao_regs, shu[2].rk[0].b[0].dq[0], 0x1800); -check_member(dramc_ddrphy_ao_regs, shu[2].rk[0].ca_cmd[0], 0x18A0); -check_member(dramc_ddrphy_ao_regs, shu[2].rk[1].b[0].dq[0], 0x1900); -check_member(dramc_ddrphy_ao_regs, shu[2].rk[1].ca_cmd[0], 0x19A0); -check_member(dramc_ddrphy_ao_regs, shu[2].rk[2].b[0].dq[0], 0x1A00); -check_member(dramc_ddrphy_ao_regs, shu[2].rk[2].ca_cmd[0], 0x1AA0); -check_member(dramc_ddrphy_ao_regs, shu[3].ca_cmd[0], 0x1C00); -check_member(dramc_ddrphy_ao_regs, shu[3].pll[0], 0x1C80); -check_member(dramc_ddrphy_ao_regs, shu[3].pll20, 0x1CD0); -check_member(dramc_ddrphy_ao_regs, shu[3].misc0, 0x1CF0); -check_member(dramc_ddrphy_ao_regs, shu[3].rk[0].ca_cmd[9], 0x1DC4); -check_member(dramc_ddrphy_ao_regs, shu[3].rk[1].ca_cmd[9], 0x1EC4); check_member(dramc_ddrphy_ao_regs, shu[3].rk[2].ca_cmd[9], 0x1FC4); struct dramc_ddrphy_nao_regs { @@ -739,12 +488,6 @@ struct dramc_ddrphy_nao_regs { }; check_member(dramc_ddrphy_nao_regs, misc_sta_extlb[0], 0x0); -check_member(dramc_ddrphy_nao_regs, misc_dq_rxdly_trro[0], 0x080); -check_member(dramc_ddrphy_nao_regs, misc_dqo1, 0x0180); -check_member(dramc_ddrphy_nao_regs, misc_cao1, 0x0184); -check_member(dramc_ddrphy_nao_regs, misc_phy_rgs_dq, 0x0190); -check_member(dramc_ddrphy_nao_regs, misc_phy_rgs_cmd, 0x0194); -check_member(dramc_ddrphy_nao_regs, misc_phy_stben_b[0], 0x0198); check_member(dramc_ddrphy_nao_regs, misc_phy_rgs_stben_cmd, 0x01A0); struct emi_regs { @@ -830,43 +573,6 @@ struct emi_regs { }; check_member(emi_regs, cona, 0x0000); -check_member(emi_regs, conb, 0x0008); -check_member(emi_regs, conc, 0x0010); -check_member(emi_regs, cond, 0x0018); -check_member(emi_regs, cone, 0x0020); -check_member(emi_regs, conf, 0x0028); -check_member(emi_regs, cong, 0x0030); -check_member(emi_regs, conh, 0x0038); -check_member(emi_regs, conh_2nd, 0x003c); -check_member(emi_regs, coni, 0x0040); -check_member(emi_regs, conj, 0x0048); -check_member(emi_regs, conm, 0x0060); -check_member(emi_regs, conn, 0x0068); -check_member(emi_regs, cono, 0x0070); -check_member(emi_regs, mdct, 0x0078); -check_member(emi_regs, mdct_2nd, 0x007c); -check_member(emi_regs, iocl, 0x00d0); -check_member(emi_regs, iocl_2nd, 0x00d4); -check_member(emi_regs, iocm, 0x00d8); -check_member(emi_regs, iocm_2nd, 0x00dc); -check_member(emi_regs, testb, 0x00e8); -check_member(emi_regs, testc, 0x00f0); -check_member(emi_regs, testd, 0x00f8); -check_member(emi_regs, arba, 0x0100); -check_member(emi_regs, arbb, 0x0108); -check_member(emi_regs, arbc, 0x0110); -check_member(emi_regs, arbd, 0x0118); -check_member(emi_regs, arbe, 0x0120); -check_member(emi_regs, arbf, 0x0128); -check_member(emi_regs, arbg, 0x0130); -check_member(emi_regs, arbh, 0x0138); -check_member(emi_regs, arbi, 0x0140); -check_member(emi_regs, arbi_2nd, 0x0144); -check_member(emi_regs, slct, 0x0158); -check_member(emi_regs, bwct0, 0x05B0); -check_member(emi_regs, bwct0_2nd, 0x06A0); -check_member(emi_regs, bwct0_3rd, 0x0770); -check_member(emi_regs, bwct0_4th, 0x0780); check_member(emi_regs, bwct0_5th, 0x07B0); struct chn_emi_regs { @@ -909,26 +615,6 @@ struct chn_emi_regs { }; check_member(chn_emi_regs, chn_cona, 0x0000); -check_member(chn_emi_regs, chn_conb, 0x0008); -check_member(chn_emi_regs, chn_conc, 0x0010); -check_member(chn_emi_regs, chn_mdct, 0x0018); -check_member(chn_emi_regs, chn_testb, 0x0048); -check_member(chn_emi_regs, chn_testc, 0x0050); -check_member(chn_emi_regs, chn_testd, 0x0058); -check_member(chn_emi_regs, chn_md_pre_mask, 0x0080); -check_member(chn_emi_regs, chn_md_pre_mask_shf, 0x0088); -check_member(chn_emi_regs, chn_arbi, 0x0140); -check_member(chn_emi_regs, chn_arbi_2nd, 0x0144); -check_member(chn_emi_regs, chn_arbj, 0x0148); -check_member(chn_emi_regs, chn_arbj_2nd, 0x014c); -check_member(chn_emi_regs, chn_arbk, 0x0150); -check_member(chn_emi_regs, chn_arbk_2nd, 0x0154); -check_member(chn_emi_regs, chn_slct, 0x0158); -check_member(chn_emi_regs, chn_arb_ref, 0x015c); -check_member(chn_emi_regs, chn_rkarb0, 0x01b0); -check_member(chn_emi_regs, chn_rkarb1, 0x01b4); -check_member(chn_emi_regs, chn_rkarb2, 0x01b8); -check_member(chn_emi_regs, chn_eco3, 0x03fc); check_member(chn_emi_regs, chn_emi_shf0, 0x0710); struct emi_mpu_regs { @@ -940,245 +626,148 @@ struct emi_mpu_regs { check_member(emi_mpu_regs, mpu_ctrl, 0x0000); check_member(emi_mpu_regs, mpu_ctrl_d[0], 0x0800); -enum { - TESTCHIP_DMA1_DMA_LP4MATAB_OPT_SHIFT = 12, -}; +DEFINE_BITFIELD(MISC_STATUSA_REFRESH_QUEUE_CNT, 27, 24) +DEFINE_BIT(SPCMDRESP_MRW_RESPONSE, 0) -enum { - MISC_STATUSA_SREF_STATE = 16, - MISC_STATUSA_REFRESH_QUEUE_CNT_SHIFT = 24, - MISC_STATUSA_REFRESH_QUEUE_CNT_MASK = 0x0f000000, -}; +DEFINE_BIT(DDRCONF0_DM4TO1MODE, 22) +DEFINE_BIT(DDRCONF0_RDATRST, 0) +DEFINE_BIT(PERFCTL0_RWOFOEN, 4) -enum { - DDRCONF0_DM4TO1MODE_SHIFT = 22, - DDRCONF0_RDATRST_SHIFT = 0, -}; +DEFINE_BIT(PADCTRL_DQIENLATEBEGIN, 3) +DEFINE_BITFIELD(PADCTRL_DQIENQKEND, 1, 0) -enum { - PERFCTL0_RWOFOEN_SHIFT = 4, -}; +DEFINE_BITFIELD(SHURK_DQSIEN_DQS0IEN, 6, 0) +DEFINE_BITFIELD(SHURK_DQSIEN_DQS1IEN, 14, 8) +DEFINE_BITFIELD(SHURK_DQSIEN_DQS2IEN, 22, 16) +DEFINE_BITFIELD(SHURK_DQSIEN_DQS3IEN, 30, 24) -enum { - PADCTRL_DQIENLATEBEGIN_SHIFT = 3, - PADCTRL_DQIENQKEND_SHIFT = 0, - PADCTRL_DQIENQKEND_MASK = 0x00000003, -}; +DEFINE_BIT(REFCTRL0_REFDIS, 29) +DEFINE_BIT(REFCTRL0_PBREFEN, 18) -enum { - REFCTRL0_REFDIS_SHIFT = 29, - REFCTRL0_PBREFEN_SHIFT = 18, -}; +DEFINE_BIT(CKECTRL_CKEFIXON, 6) +DEFINE_BIT(CKECTRL_CKEFIXOFF, 7) -enum { - MRS_MPCRK_SHIFT = 28, - MRS_MPCRK_MASK = 0x30000000, - MRS_MRSRK_SHIFT = 24, - MRS_MRSRK_MASK = 0x03000000, - MRS_MRSMA_SHIFT = 8, - MRS_MRSMA_MASK = 0x001fff00, - MRS_MRSOP_SHIFT = 0, - MRS_MRSOP_MASK = 0x000000ff, -}; +DEFINE_BITFIELD(MRS_MRSBG, 31, 30) +DEFINE_BITFIELD(MRS_MPCRK, 29, 28) +DEFINE_BITFIELD(MRS_MRRRK, 27, 26) +DEFINE_BITFIELD(MRS_MRSRK, 25, 24) +DEFINE_BITFIELD(MRS_MRSBA, 23, 21) +DEFINE_BITFIELD(MRS_MRSMA, 20, 8) +DEFINE_BITFIELD(MRS_MRSOP, 7, 0) -enum { - SPCMD_DQSGCNTRST_SHIFT = 9, - SPCMD_DQSGCNTEN_SHIFT = 8, - SPCMD_RDDQCEN_SHIFT = 7, - SPCMD_ZQLATEN_SHIFT = 6, - SPCMD_ZQCEN_SHIFT = 4, - SPCMD_MRWEN_SHIFT = 0, -}; +DEFINE_BIT(SPCMD_DQSGCNTRST, 9) +DEFINE_BIT(SPCMD_DQSGCNTEN, 8) +DEFINE_BIT(SPCMD_ZQLATEN, 6) +DEFINE_BIT(SPCMD_RDDQCEN, 7) +DEFINE_BIT(SPCMD_ZQCEN, 4) +DEFINE_BIT(SPCMD_MRWEN, 0) -enum { - SPCMDCTRL_RDDQCDIS_SHIFT = 11, -}; +DEFINE_BIT(SPCMDCTRL_RDDQCDIS, 11) -enum { - MPC_OPTION_MPCRKEN_SHIFT = 17, -}; +DEFINE_BIT(MPC_OPTION_MPCRKEN, 17) -enum { - TEST2_0_PAT0_SHIFT = 8, - TEST2_0_PAT0_MASK = 0x0000ff00, - TEST2_0_PAT1_SHIFT = 0, - TEST2_0_PAT1_MASK = 0x000000ff, -}; +DEFINE_BIT(DVFSDLL_R_BYPASS_1ST_DLL_SHU1, 1) -enum { - TEST2_3_TEST2W_SHIFT = 31, - TEST2_3_TEST2R_SHIFT = 30, - TEST2_3_TEST1_SHIFT = 29, - TEST2_3_TESTAUDPAT_SHIFT = 7, - TEST2_3_TESTCNT_SHIFT = 0, - TEST2_3_TESTCNT_MASK = 0x0000000f, -}; +DEFINE_BITFIELD(MISC_CG_CTRL0_CLK_MEM_SEL, 5, 4) -enum { - TEST2_4_TESTAGENTRKSEL_MASK = 0x70000000, - TEST2_4_TESTAGENTRK_SHIFT = 24, - TEST2_4_TESTAGENTRK_MASK = 0x03000000, - TEST2_4_TEST_REQ_LEN1_SHIFT = 17, - TEST2_4_TESTXTALKPAT_SHIFT = 16, - TEST2_4_TESTAUDMODE_SHIFT = 15, - TEST2_4_TESTAUDBITINV_SHIFT = 14, - TEST2_4_TESTAUDINIT_SHIFT = 8, - TEST2_4_TESTAUDINIT_MASK = 0x00001f00, - TEST2_4_TESTSSOXTALKPAT_SHIFT = 7, - TEST2_4_TESTSSOPAT_SHIFT = 6, - TEST2_4_TESTAUDINC_SHIFT = 0, - TEST2_4_TESTAUDINC_MASK = 0x0000001f, -}; +DEFINE_BIT(DRAMCTRL_ADRDECEN_TARKMODE, 1) -enum { - MR_GOLDEN_MR15_GOLDEN_MASK = 0x0000ff00, - MR_GOLDEN_MR20_GOLDEN_MASK = 0x000000ff, -}; +DEFINE_BIT(TESTCHIP_DMA1_DMA_LP4MATAB_OPT, 12) +DEFINE_BITFIELD(TEST2_0_PAT0, 15, 8) +DEFINE_BITFIELD(TEST2_0_PAT1, 7, 0) -enum { - DQSOSCR_AR_COARSE_TUNE_DQ_SW_SHIFT = 7, -}; +DEFINE_BITFIELD(TEST2_1_TEST2_BASE, 31, 4) +DEFINE_BITFIELD(TEST2_2_TEST2_OFF, 31, 4) -enum { - DUMMY_RD_DQSG_DMYWR_EN_SHIFT = 23, - DUMMY_RD_DQSG_DMYRD_EN_SHIFT = 22, - DUMMY_RD_SREF_DMYRD_EN_SHIFT = 21, - DUMMY_RD_DUMMY_RD_EN_SHIFT = 20, - DUMMY_RD_DMY_RD_DBG_SHIFT = 7, - DUMMY_RD_DMY_WR_DBG_SHIFT = 6, -}; +DEFINE_BIT(TEST2_3_TEST2W, 31) +DEFINE_BIT(TEST2_3_TEST2R, 30) +DEFINE_BIT(TEST2_3_TEST1, 29) +DEFINE_BIT(TEST2_3_TESTAUDPAT, 7) +DEFINE_BITFIELD(TEST2_3_TESTCNT, 3, 0) -enum { - STBCAL1_STBCNT_LATCH_EN_SHIFT = 11, - STBCAL1_STBENCMPEN_SHIFT = 10, -}; +DEFINE_BITFIELD(TEST2_4_TESTAGENTRKSEL, 30, 28) +DEFINE_BITFIELD(TEST2_4_TESTAGENTRK, 25, 24) +DEFINE_BIT(TEST2_4_TEST_REQ_LEN1, 17) +DEFINE_BIT(TEST2_4_TESTXTALKPAT, 16) +DEFINE_BIT(TEST2_4_TESTAUDMODE, 15) +DEFINE_BIT(TEST2_4_TESTAUDBITINV, 14) +DEFINE_BITFIELD(TEST2_4_TESTAUDINIT, 12, 8) +DEFINE_BIT(TEST2_4_TESTSSOXTALKPAT, 7) +DEFINE_BIT(TEST2_4_TESTSSOPAT, 6) +DEFINE_BITFIELD(TEST2_4_TESTAUDINC, 4, 0) -enum { - SHU_ACTIM_XRT_XRTR2R_SHIFT = 0, - SHU_ACTIM_XRT_XRTR2R_MASK = 0x0000000f, -}; +DEFINE_BITFIELD(MR_GOLDEN_MR15_GOLDEN, 15, 8) +DEFINE_BITFIELD(MR_GOLDEN_MR20_GOLDEN, 7, 0) -enum { - SHU_CONF1_DATLAT_DSEL_PHY_SHIFT = 26, - SHU_CONF1_DATLAT_DSEL_PHY_MASK = 0x7c000000, - SHU_CONF1_DATLAT_DSEL_SHIFT = 8, - SHU_CONF1_DATLAT_DSEL_MASK = 0x00001f00, - SHU_CONF1_DATLAT_SHIFT = 0, - SHU_CONF1_DATLAT_MASK = 0x0000001f, -}; +DEFINE_BIT(DUMMY_RD_DQSG_DMYWR_EN, 23) +DEFINE_BIT(DUMMY_RD_DQSG_DMYRD_EN, 22) +DEFINE_BIT(DUMMY_RD_SREF_DMYRD_EN, 21) +DEFINE_BIT(DUMMY_RD_DUMMY_RD_EN, 20) +DEFINE_BIT(DUMMY_RD_DMY_RD_DBG, 7) +DEFINE_BIT(DUMMY_RD_DMY_WR_DBG, 6) -enum { - SHU_RANKCTL_RANKINCTL_PHY_SHIFT = 28, - SHU_RANKCTL_RANKINCTL_PHY_MASK = 0xf0000000, - SHU_RANKCTL_RANKINCTL_ROOT1_SHIFT = 24, - SHU_RANKCTL_RANKINCTL_ROOT1_MASK = 0x0f000000, - SHU_RANKCTL_RANKINCTL_SHIFT = 20, - SHU_RANKCTL_RANKINCTL_MASK = 0x00f00000, -}; +DEFINE_BIT(STBCAL1_STBCNT_LATCH_EN, 11) +DEFINE_BIT(STBCAL1_STBENCMPEN, 10) -enum { - SHU1_WODT_DBIWR_SHIFT = 29, -}; +DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTR2R, 3, 0) -enum { - SHURK_DQSCTL_DQSINCTL_SHIFT = 0, - SHURK_DQSCTL_DQSINCTL_MASK = 0x0000000f, -}; +DEFINE_BITFIELD(SHU_CONF1_DATLAT_DSEL_PHY, 30, 26) +DEFINE_BITFIELD(SHU_CONF1_DATLAT_DSEL, 12, 8) +DEFINE_BITFIELD(SHU_CONF1_DATLAT, 4, 0) -enum { - SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1_SHIFT = 12, - SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_SHIFT = 8, - SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1_SHIFT = 4, - SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_SHIFT = 0, -}; +DEFINE_BIT(SHU_PIPE_READ_START_EXTEND1, 31) +DEFINE_BIT(SHU_PIPE_DLE_LAST_EXTEND1, 30) +DEFINE_BIT(SHU_PIPE_READ_START_EXTEND2, 29) +DEFINE_BIT(SHU_PIPE_DLE_LAST_EXTEND2, 28) +DEFINE_BIT(SHU_PIPE_READ_START_EXTEND3, 27) +DEFINE_BIT(SHU_PIPE_DLE_LAST_EXTEND3, 26) -enum { - SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_P1_SHIFT = 12, - SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_SHIFT = 8, - SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_P1_SHIFT = 4, - SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_SHIFT = 0, -}; +DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL_PHY, 31, 28) +DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL_ROOT1, 27, 24) +DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL, 23, 20) -enum { - SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1_SHIFT = 12, - SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_SHIFT = 8, - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT = 4, - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_MASK = 0x00000070, - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_SHIFT = 0, - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_MASK = 0x00000007, -}; +DEFINE_BIT(SHU1_WODT_DBIWR, 29) +DEFINE_BITFIELD(SHURK_DQSCTL_DQSINCTL, 3, 0) -enum { - SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1_SHIFT = 12, - SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_SHIFT = 8, - SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1_SHIFT = 4, - SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_SHIFT = 0, -}; +DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1, 14, 12) +DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1, 6, 4) +DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED, 2, 0) -enum { - B0_DQ5_RG_RX_ARDQ_VREF_EN_B0_SHIFT = 16, -}; +DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS1_GATED_P1, 14, 12) +DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED_P1, 6, 4) +DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED, 2, 0) -enum { - B1_DQ5_RG_RX_ARDQ_VREF_EN_B1_SHIFT = 16, -}; +DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 16) +DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 16) -enum { - MISC_CTRL1_R_DMSTBENCMP_RK_OPT_SHIFT = 25, - MISC_CTRL1_R_DMAR_FINE_TUNE_DQ_SW_SHIFT = 7, - MISC_CTRL1_R_DMPHYRST_SHIFT = 1, -}; +DEFINE_BIT(MISC_CTRL1_R_DMSTBENCMP_RK, 25) +DEFINE_BIT(MISC_CTRL1_R_DMARPIDQ_SW, 7) +DEFINE_BIT(MISC_CTRL1_R_DMPHYRST, 1) -enum { - MISC_STBERR_RK_R_STBERR_RK_R_MASK = 0x0000ffff, -}; +DEFINE_BITFIELD(MISC_STBERR_RK_R_STBERR_RK_R, 15, 0) +DEFINE_BITFIELD(MISC_STBERR_RK_F_STBERR_RK_F, 15, 0) -enum { - MISC_STBERR_RK_F_STBERR_RK_F_MASK = 0x0000ffff, -}; +DEFINE_BITFIELD(SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 5, 0) -enum { - SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0_SHIFT = 0, - SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0_MASK = 0x0000003f, -}; +DEFINE_BIT(SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0, 7) +DEFINE_BITFIELD(SHU1_B0_DQ7_R_DMRANKRXDVS, 3, 0) -enum { - SHU1_BX_DQ7_R_DMDQMDBI_SHIFT = 7, - SHU1_BX_DQ7_R_DMRANKRXDVS_SHIFT = 0, - SHU1_BX_DQ7_R_DMRANKRXDVS_MASK = 0x0000000f, -}; +DEFINE_BITFIELD(SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE, 14, 12) -enum { - SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE_SHIFT = 12, - SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE_MASK = 0x00007000, -}; +DEFINE_BITFIELD(SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE, 11, 10) -enum { - SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_SHIFT = 10, - SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_MASK = 0x00000c00, -}; +DEFINE_BITFIELD(SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0, 30, 24) +DEFINE_BITFIELD(SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0, 22, 16) +DEFINE_BITFIELD(SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0, 13, 8) +DEFINE_BITFIELD(SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0, 5, 0) -enum { - SHU1_B0_DQ6_RK_RX_ARDQS0_F_DLY_B0_MASK = 0x7f000000, - SHU1_B0_DQ6_RK_RX_ARDQS0_R_DLY_B0_MASK = 0x007f0000, - SHU1_B0_DQ6_RK_RX_ARDQM0_F_DLY_B0_MASK = 0x00003f00, - SHU1_B0_DQ6_RK_RX_ARDQM0_R_DLY_B0_MASK = 0x0000003f, -}; +DEFINE_BITFIELD(FINE_TUNE_PBYTE, 29, 24) +DEFINE_BITFIELD(FINE_TUNE_DQM, 21, 16) +DEFINE_BITFIELD(FINE_TUNE_DQ, 13, 8) -enum { - FINE_TUNE_PBYTE_SHIFT = 24, - FINE_TUNE_PBYTE_MASK = 0x3f000000, - FINE_TUNE_DQM_SHIFT = 16, - FINE_TUNE_DQM_MASK = 0x003f0000, - FINE_TUNE_DQ_SHIFT = 8, - FINE_TUNE_DQ_MASK = 0x00003f00, -}; - -enum { - SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_SHIFT = 24, - SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_MASK = 0x3f000000, - SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CS_MASK = 0x0000003f, -}; +DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK, 29, 24) +DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD, 13, 8) +DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, 5, 0) struct dramc_channel_regs { union { diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 15889eeca4..255a323d1a 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -20,10 +20,49 @@ #include #include +enum DRAMC_PARAM_SOURCE { + DRAMC_PARAM_SOURCE_SDRAM_INVALID = 0, + DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + DRAMC_PARAM_SOURCE_FLASH, +}; + struct sdram_params { + u16 source; /* DRAMC_PARAM_SOURCE */ + u16 frequency; u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; - u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]; + + /* DUTY */ + s8 duty_clk_delay[CHANNEL_MAX]; + s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER]; + + /* CBT */ u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; + u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]; + + /* Gating */ + u8 gating2T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + u8 gating05T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + u8 gating_fine_tune[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + + /* TX perbit */ + u8 tx_vref[CHANNEL_MAX][RANK_MAX]; + u16 tx_center_min[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + u16 tx_center_max[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + u16 tx_win_center[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; + u16 tx_first_pass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; + u16 tx_last_pass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; + + /* datlat */ + u8 rx_datlat[CHANNEL_MAX][RANK_MAX]; + + /* RX perbit */ + u8 rx_vref[CHANNEL_MAX]; + s16 rx_firspass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; + u8 rx_lastpass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; + u32 emi_cona_val; u32 emi_conh_val; u32 emi_conf_val; @@ -32,6 +71,9 @@ struct sdram_params { u16 delay_cell_unit; }; +struct dramc_param; +struct dramc_param_ops; + enum { LP4X_DDR1600, LP4X_DDR2400, @@ -40,13 +82,27 @@ enum { LP4X_DDRFREQ_MAX, }; +struct dram_impedance { + u32 data[ODT_MAX][4]; +}; + +struct mr_value { + u8 MR01Value[FSP_MAX]; + u8 MR13Value; +}; + +struct dram_shared_data { + struct dram_impedance impedance; + struct mr_value mr; +}; + extern const u8 phy_mapping[CHANNEL_MAX][16]; int complex_mem_test(u8 *start, unsigned int len); size_t sdram_size(void); const struct sdram_params *get_sdram_config(void); void enable_emi_dcm(void); -void mt_set_emi(const struct sdram_params *params); -void mt_mem_init(const struct sdram_params *params); +int mt_set_emi(const struct dramc_param *dparam); +void mt_mem_init(struct dramc_param_ops *dparam_ops); #endif /* SOC_MEDIATEK_MT8183_EMI_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index 73c880afbf..82e404f790 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -24,6 +24,8 @@ */ #define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) #define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) +#define DRAM_INIT_CODE(addr, size) \ + REGION(dram_init_code, addr, size, 4) SECTIONS { @@ -42,6 +44,7 @@ SECTIONS SRAM_L2C_START(0x00200000) OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K) BOOTBLOCK(0x00230000, 64K) + DRAM_INIT_CODE(0x00240000, 256K) SRAM_L2C_END(0x00280000) DRAM_START(0x40000000) diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index bb5f019433..6b74695bab 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -19,9 +19,18 @@ enum { PMIC_SWCID = 0x000a, PMIC_VM_MODE = 0x004e, + PMIC_TOP_CKPDN_CON0_SET = 0x010e, + PMIC_TOP_CKPDN_CON0_CLR = 0x0110, + PMIC_TOP_CKHWEN_CON0_SET = 0x012c, + PMIC_TOP_CKHWEN_CON0_CLR = 0x012e, PMIC_TOP_RST_MISC = 0x014c, PMIC_TOP_RST_MISC_SET = 0x014e, PMIC_TOP_RST_MISC_CLR = 0x0150, + PMIC_OTP_CON0 = 0x038a, + PMIC_OTP_CON8 = 0x039a, + PMIC_OTP_CON11 = 0x03a0, + PMIC_OTP_CON12 = 0x03a2, + PMIC_OTP_CON13 = 0x03a4, PMIC_TOP_TMA_KEY = 0x03a8, PMIC_PWRHOLD = 0x0a08, PMIC_CPSDSA4 = 0x0a2e, @@ -29,8 +38,13 @@ enum { PMIC_VCORE_DBG0 = 0x149e, PMIC_VCORE_VOSEL = 0x14aa, PMIC_VDRAM1_VOSEL_SLEEP = 0x160a, + PMIC_VDRAM1_OP_EN = 0x1610, + PMIC_VDRAM1_DBG0 = 0x161e, + PMIC_VDRAM1_VOSEL = 0x1626, PMIC_SMPS_ANA_CON0 = 0x1808, + PMIC_VDDQ_OP_EN = 0x1b16, PMIC_VSIM2_ANA_CON0 = 0x1e30, + PMIC_VDDQ_ELR_0 = 0x1ec4, }; struct pmic_setting { @@ -46,5 +60,9 @@ void pmic_set_vsim2_cali(unsigned int vsim2_mv); void pmic_init_scp_voltage(void); unsigned int pmic_get_vcore_vol(void); void pmic_set_vcore_vol(unsigned int vcore_uv); +unsigned int pmic_get_vdram1_vol(void); +void pmic_set_vdram1_vol(unsigned int vdram_uv); +unsigned int pmic_get_vddq_vol(void); +void pmic_set_vddq_vol(unsigned int vddq_uv); #endif /* __SOC_MEDIATEK_MT6358_H__ */ diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h index 4ca72b632a..d0a7aa7608 100644 --- a/src/soc/mediatek/mt8183/include/soc/spm.h +++ b/src/soc/mediatek/mt8183/include/soc/spm.h @@ -16,10 +16,7 @@ #ifndef SOC_MEDIATEK_MT8183_SPM_H #define SOC_MEDIATEK_MT8183_SPM_H -#include -#include #include -#include #include #include diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index b2c744198b..13c3d9ad36 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -14,18 +14,19 @@ */ #include +#include #include +#include +#include +#include #include #include #include -void mt_mem_init(const struct sdram_params *params) +static int mt_mem_test(void) { u64 rank_size[RANK_MAX]; - /* memory calibration */ - mt_set_emi(params); - if (CONFIG(MEMORY_TEST)) { size_t r; u8 *addr = _dram; @@ -43,9 +44,187 @@ void mt_mem_init(const struct sdram_params *params) printk(BIOS_DEBUG, "[MEM] complex R/W mem test %s : %d\n", (i == 0) ? "pass" : "fail", i); - ASSERT(i == 0); + if (i != 0) { + printk(BIOS_ERR, "DRAM memory test failed\n"); + return -1; + } addr += rank_size[r]; } } + + return 0; +} + +static void dump_param_header(const struct dramc_param *dparam) +{ + const struct dramc_param_header *header = &dparam->header; + + printk(BIOS_DEBUG, "header.status = %#x\n", header->status); + printk(BIOS_DEBUG, "header.magic = %#x (expected: %#x)\n", + header->magic, DRAMC_PARAM_HEADER_MAGIC); + printk(BIOS_DEBUG, "header.version = %#x (expected: %#x)\n", + header->version, DRAMC_PARAM_HEADER_VERSION); + printk(BIOS_DEBUG, "header.size = %#x (expected: %#lx)\n", + header->size, sizeof(*dparam)); + printk(BIOS_DEBUG, "header.config = %#x\n", header->config); + printk(BIOS_DEBUG, "header.flags = %#x\n", header->flags); + printk(BIOS_DEBUG, "header.checksum = %#x\n", header->checksum); +} + +static u32 compute_checksum(const struct dramc_param *dparam) +{ + return (u32)compute_ip_checksum(dparam->freq_params, + sizeof(dparam->freq_params)); +} + +static int dram_run_fast_calibration(const struct dramc_param *dparam, + u16 config) +{ + if (!is_valid_dramc_param(dparam)) { + printk(BIOS_WARNING, + "Invalid DRAM calibration data from flash\n"); + dump_param_header(dparam); + return -1; + } + + if (dparam->header.config != config) { + printk(BIOS_WARNING, + "Incompatible config for calibration data from flash " + "(expected: %#x, saved: %#x)\n", + config, dparam->header.config); + return -1; + } + + const u32 checksum = compute_checksum(dparam); + if (dparam->header.checksum != checksum) { + printk(BIOS_ERR, + "Invalid DRAM calibration checksum from flash " + "(expected: %#x, saved: %#x)\n", + checksum, dparam->header.checksum); + return -1; + } + + return 0; +} + +static int dram_run_full_calibration(struct dramc_param *dparam, u16 config) +{ + initialize_dramc_param(dparam, config); + + /* Load and run the provided blob for full-calibration if available */ + struct prog dram = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/dram"); + + if (prog_locate(&dram)) + return -1; + + if (cbfs_prog_stage_load(&dram)) + return -2; + + dparam->do_putc = do_putchar; + prog_set_entry(&dram, prog_entry(&dram), dparam); + prog_run(&dram); + + if (dparam->header.status != DRAMC_SUCCESS) { + printk(BIOS_ERR, "Full calibration failed: status = %d\n", + dparam->header.status); + return -3; + } + + if (!(dparam->header.flags & DRAMC_FLAG_HAS_SAVED_DATA)) { + printk(BIOS_ERR, + "Full calibration executed without saving parameters. " + "Please ensure the blob is built properly.\n"); + return -4; + } + + return 0; +} + +static void set_source_to_flash(struct sdram_params *freq_params) +{ + for (u8 shuffle = DRAM_DFS_SHUFFLE_1; shuffle < DRAM_DFS_SHUFFLE_MAX; + shuffle++) + freq_params[shuffle].source = DRAMC_PARAM_SOURCE_FLASH; +} + +static void init_sdram_params(struct sdram_params *dst, + const struct sdram_params *src) +{ + for (u8 shuffle = DRAM_DFS_SHUFFLE_1; shuffle < DRAM_DFS_SHUFFLE_MAX; + shuffle++) + memcpy(&dst[shuffle], src, sizeof(*dst)); +} + +void mt_mem_init(struct dramc_param_ops *dparam_ops) +{ + struct dramc_param *dparam = dparam_ops->param; + + u16 config = 0; + if (CONFIG(MT8183_DRAM_EMCP)) + config |= DRAMC_CONFIG_EMCP; + + const bool recovery_mode = vboot_recovery_mode_enabled(); + + /* DRAM DVFS is disabled in recovery mode */ + if (CONFIG(MT8183_DRAM_DVFS) && !recovery_mode) + config |= DRAMC_CONFIG_DVFS; + + /* Load calibration params from flash and run fast calibration */ + if (recovery_mode) { + printk(BIOS_WARNING, "Skip loading cached calibration data\n"); + if (vboot_recovery_mode_memory_retrain() || + vboot_check_recovery_request() == VB2_RECOVERY_TRAIN_AND_REBOOT) { + printk(BIOS_WARNING, "Retrain memory in next boot\n"); + /* Use 0xFF as erased flash data. */ + memset(dparam, 0xff, sizeof(*dparam)); + dparam_ops->write_to_flash(dparam); + } + } else if (dparam_ops->read_from_flash(dparam)) { + printk(BIOS_INFO, "DRAM-K: Fast Calibration\n"); + if (dram_run_fast_calibration(dparam, config) == 0) { + printk(BIOS_INFO, + "Calibration params loaded from flash\n"); + if (mt_set_emi(dparam) == 0 && mt_mem_test() == 0) + return; + } else { + printk(BIOS_ERR, + "Failed to apply cached calibration data\n"); + } + } else { + printk(BIOS_WARNING, + "Failed to read calibration data from flash\n"); + } + + /* Run full calibration */ + printk(BIOS_INFO, "DRAM-K: Full Calibration\n"); + int err = dram_run_full_calibration(dparam, config); + if (err == 0) { + printk(BIOS_INFO, "Successfully loaded DRAM blobs and " + "ran DRAM calibration\n"); + /* + * In recovery mode the system boots in RO but the flash params + * should be calibrated for RW so we can't mix them up. + */ + if (!recovery_mode) { + set_source_to_flash(dparam->freq_params); + dparam->header.checksum = compute_checksum(dparam); + dparam_ops->write_to_flash(dparam); + printk(BIOS_DEBUG, "Calibration params saved to flash: " + "version=%#x, size=%#x\n", + dparam->header.version, dparam->header.size); + } + return; + } + + printk(BIOS_ERR, "Failed to do full calibration (%d), " + "falling back to load default sdram param\n", err); + + /* Init params from sdram configs and run partial calibration */ + printk(BIOS_INFO, "DRAM-K: Partial Calibration\n"); + init_sdram_params(dparam->freq_params, get_sdram_config()); + if (mt_set_emi(dparam) != 0) + die("Set emi failed with params from sdram config\n"); + if (mt_mem_test() != 0) + die("Memory test failed with params from sdram config\n"); } diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 3600b6a3de..4ab0e7ed76 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -752,6 +753,55 @@ static struct pmic_setting scp_setting[] = { /* [4:4]: RG_SRCVOLTEN_LP_EN */ {0x134, 0x1, 0x1, 4}, }; + +static const int vddq_votrim[] = { + 0, -10000, -20000, -30000, -40000, -50000, -60000, -70000, + 80000, 70000, 60000, 50000, 40000, 30000, 20000, 10000, +}; + +static unsigned int pmic_read_efuse(int i) +{ + unsigned int efuse_data = 0; + + /* 1. Enable efuse ctrl engine clock */ + pwrap_write_field(PMIC_TOP_CKHWEN_CON0_CLR, 0x1, 0x1, 2); + pwrap_write_field(PMIC_TOP_CKPDN_CON0_CLR, 0x1, 0x1, 4); + + /* 2. */ + pwrap_write_field(PMIC_OTP_CON11, 0x1, 0x1, 0); + + /* 3. Set row to read */ + pwrap_write_field(PMIC_OTP_CON0, i * 2, 0xFF, 0); + + /* 4. Toggle RG_OTP_RD_TRIG */ + if (pwrap_read_field(PMIC_OTP_CON8, 0x1, 0) == 0) + pwrap_write_field(PMIC_OTP_CON8, 0x1, 0x1, 0); + else + pwrap_write_field(PMIC_OTP_CON8, 0, 0x1, 0); + + /* 5. Polling RG_OTP_RD_BUSY = 0 */ + udelay(300); + while (pwrap_read_field(PMIC_OTP_CON13, 0x1, 0) == 1) + ; + + /* 6. Read RG_OTP_DOUT_SW */ + udelay(100); + efuse_data = pwrap_read_field(PMIC_OTP_CON12, 0xFFFF, 0); + + /* 7. Disable efuse ctrl engine clock */ + pwrap_write_field(PMIC_TOP_CKHWEN_CON0_SET, 0x1, 0x1, 2); + pwrap_write_field(PMIC_TOP_CKPDN_CON0_SET, 0x1, 0x1, 4); + + return efuse_data; +} + +static int pmic_get_efuse_votrim(void) +{ + const unsigned int cali_efuse = pmic_read_efuse(104) & 0xF; + assert(cali_efuse < ARRAY_SIZE(vddq_votrim)); + return vddq_votrim[cali_efuse]; +} + void pmic_set_power_hold(bool enable) { pwrap_write_field(PMIC_PWRHOLD, (enable) ? 1 : 0, 0x1, 0); @@ -824,6 +874,74 @@ void pmic_set_vcore_vol(unsigned int vcore_uv) pwrap_write_field(PMIC_VCORE_OP_EN, 1, 0x7F, 0); pwrap_write_field(PMIC_VCORE_VOSEL, vol_reg, 0x7F, 0); + udelay(1); +} + +unsigned int pmic_get_vdram1_vol(void) +{ + unsigned int vol_reg; + + vol_reg = pwrap_read_field(PMIC_VDRAM1_DBG0, 0x7F, 0); + return 500000 + vol_reg * 12500; +} + +void pmic_set_vdram1_vol(unsigned int vdram_uv) +{ + unsigned int vol_reg; + + assert(vdram_uv >= 500000); + assert(vdram_uv <= 1300000); + + vol_reg = (vdram_uv - 500000) / 12500; + + pwrap_write_field(PMIC_VDRAM1_OP_EN, 1, 0x7F, 0); + pwrap_write_field(PMIC_VDRAM1_VOSEL, vol_reg, 0x7F, 0); + udelay(1); +} + +unsigned int pmic_get_vddq_vol(void) +{ + int efuse_votrim; + unsigned int cali_trim; + + if (!pwrap_read_field(PMIC_VDDQ_OP_EN, 0x1, 15)) + return 0; + + efuse_votrim = pmic_get_efuse_votrim(); + cali_trim = pwrap_read_field(PMIC_VDDQ_ELR_0, 0xF, 0); + assert(cali_trim < ARRAY_SIZE(vddq_votrim)); + return 600 * 1000 - efuse_votrim + vddq_votrim[cali_trim]; +} + +void pmic_set_vddq_vol(unsigned int vddq_uv) +{ + int target_mv, dram2_ori_mv, cali_offset_uv, cali_trim; + + assert(vddq_uv >= 530000); + assert(vddq_uv <= 680000); + + /* Round down to multiple of 10 */ + target_mv = (vddq_uv / 1000) / 10 * 10; + + dram2_ori_mv = 600 - pmic_get_efuse_votrim() / 1000; + cali_offset_uv = 1000 * (target_mv - dram2_ori_mv); + + if (cali_offset_uv >= 80000) + cali_trim = 8; + else if (cali_offset_uv <= -70000) + cali_trim = 7; + else { + cali_trim = 0; + while (cali_trim < ARRAY_SIZE(vddq_votrim) && + vddq_votrim[cali_trim] != cali_offset_uv) + ++cali_trim; + assert(cali_trim < ARRAY_SIZE(vddq_votrim)); + } + + pwrap_write_field(PMIC_TOP_TMA_KEY, 0x9CA7, 0xFFFF, 0); + pwrap_write_field(PMIC_VDDQ_ELR_0, cali_trim, 0xF, 0); + pwrap_write_field(PMIC_TOP_TMA_KEY, 0, 0xFFFF, 0); + udelay(1); } static void pmic_wdt_set(void) diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index c28cd0b1de..0e9553c8ed 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -138,7 +138,7 @@ static int tegra_i2c_send_recv(int bus, int read, return 0; } -static int tegra_i2c_request(int bus, unsigned chip, int cont, int restart, +static int tegra_i2c_request(int bus, unsigned int chip, int cont, int restart, int read, void *data, int data_len) { uint32_t headers[3]; @@ -170,7 +170,7 @@ static int tegra_i2c_request(int bus, unsigned chip, int cont, int restart, data, data_len); } -static int i2c_transfer_segment(unsigned bus, unsigned chip, int restart, +static int i2c_transfer_segment(unsigned int bus, unsigned int chip, int restart, int read, void *buf, int len) { const uint32_t max_payload = @@ -188,7 +188,7 @@ static int i2c_transfer_segment(unsigned bus, unsigned chip, int restart, return 0; } -int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, int count) +int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int count) { struct i2c_msg *seg = segments; int i; @@ -208,7 +208,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, int count) return 0; } -void i2c_init(unsigned bus) +void i2c_init(unsigned int bus) { struct tegra_i2c_regs *regs; diff --git a/src/soc/nvidia/tegra/i2c.h b/src/soc/nvidia/tegra/i2c.h index 07480c15ca..a2bf9508be 100644 --- a/src/soc/nvidia/tegra/i2c.h +++ b/src/soc/nvidia/tegra/i2c.h @@ -18,9 +18,9 @@ #include -void i2c_init(unsigned bus); -void tegra_software_i2c_init(unsigned bus); -void tegra_software_i2c_disable(unsigned bus); +void i2c_init(unsigned int bus); +void tegra_software_i2c_init(unsigned int bus); +void tegra_software_i2c_disable(unsigned int bus); enum { /* Word 0 */ @@ -168,6 +168,6 @@ struct tegra_i2c_regs { }; check_member(tegra_i2c_regs, config_load, 0x8C); -extern unsigned g_num_i2c_buses; +extern unsigned int g_num_i2c_buses; #endif /* __SOC_NVIDIA_TEGRA_I2C_H__ */ diff --git a/src/soc/nvidia/tegra/software_i2c.c b/src/soc/nvidia/tegra/software_i2c.c index 50aac8c45a..e215c0275d 100644 --- a/src/soc/nvidia/tegra/software_i2c.c +++ b/src/soc/nvidia/tegra/software_i2c.c @@ -36,7 +36,7 @@ static struct { .sda = GPIO(Z7), .scl = GPIO(Z6)}, }; -static void tegra_set_sda(unsigned bus, int high) +static void tegra_set_sda(unsigned int bus, int high) { if (high) gpio_input_pullup(pins[bus].sda); @@ -44,7 +44,7 @@ static void tegra_set_sda(unsigned bus, int high) gpio_output(pins[bus].sda, 0); } -static void tegra_set_scl(unsigned bus, int high) +static void tegra_set_scl(unsigned int bus, int high) { if (high) gpio_input_pullup(pins[bus].scl); @@ -52,12 +52,12 @@ static void tegra_set_scl(unsigned bus, int high) gpio_output(pins[bus].scl, 0); } -static int tegra_get_sda(unsigned bus) +static int tegra_get_sda(unsigned int bus) { return gpio_get(pins[bus].sda); } -static int tegra_get_scl(unsigned bus) +static int tegra_get_scl(unsigned int bus) { return gpio_get(pins[bus].scl); } @@ -69,7 +69,7 @@ static struct software_i2c_ops tegra_ops = { .get_scl = tegra_get_scl, }; -void tegra_software_i2c_init(unsigned bus) +void tegra_software_i2c_init(unsigned int bus) { software_i2c[bus] = &tegra_ops; @@ -78,7 +78,7 @@ void tegra_software_i2c_init(unsigned bus) tegra_set_scl(bus, 1); } -void tegra_software_i2c_disable(unsigned bus) +void tegra_software_i2c_disable(unsigned int bus) { software_i2c[bus] = NULL; diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index fb5389fa2f..e80125e953 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -46,7 +46,6 @@ romstage-y += ../tegra/pinmux.c romstage-y += cache.c romstage-y += uart.c -ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += display.c ramstage-y += dma.c diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index 4b52a519bd..ac2a92e39d 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -17,7 +17,7 @@ #include #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); } diff --git a/src/soc/nvidia/tegra124/i2c.c b/src/soc/nvidia/tegra124/i2c.c index 76b8f138f9..ee339bbe48 100644 --- a/src/soc/nvidia/tegra124/i2c.c +++ b/src/soc/nvidia/tegra124/i2c.c @@ -50,4 +50,4 @@ struct tegra_i2c_bus_info tegra_i2c_info[] = { } }; -unsigned g_num_i2c_buses = ARRAY_SIZE(tegra_i2c_info); +unsigned int g_num_i2c_buses = ARRAY_SIZE(tegra_i2c_info); diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index e00dbd1039..0ebe8e7056 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -292,7 +292,7 @@ static void __noreturn reset(void) halt(); } -static void udelay(unsigned usecs) +static void udelay(unsigned int usecs) { uint32_t start = read32(timer_us_ptr); while (read32(timer_us_ptr) - start < usecs) @@ -313,7 +313,7 @@ static uint32_t get_wakeup_vector(void) return read32(pmc_ctlr_scratch41_ptr); } -static unsigned get_osc_freq(void) +static unsigned int get_osc_freq(void) { return (read32(clk_rst_osc_ctrl_ptr) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; } @@ -507,7 +507,7 @@ void ram_repair(void) /* Power. */ -static void power_on_partition(unsigned id) +static void power_on_partition(unsigned int id) { uint32_t bit = 0x1 << id; if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) { diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index 1c151f50df..9554ce9173 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -18,7 +18,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 2d6469cc3f..27ae1faf22 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -288,6 +288,9 @@ static void dump_spi_regs(struct tegra_spi_channel *spi) static void dump_dma_regs(struct apb_dma_channel *dma) { + if (dma == NULL) + return; + printk(BIOS_INFO, "DMA regs:\n" "\tahb_ptr: 0x%08x\n" "\tapb_ptr: 0x%08x\n" @@ -545,9 +548,9 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) int ret; unsigned int todo; - todo = read32(&spi->dma_in->regs->wcount); - if (spi->dma_in) { + todo = read32(&spi->dma_in->regs->wcount); + while ((read32(&spi->dma_in->regs->dma_byte_sta) < todo) || dma_busy(spi->dma_in)) ; /* this shouldn't take long, no udelay */ @@ -557,9 +560,12 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) } if (spi->dma_out) { + todo = read32(&spi->dma_out->regs->wcount); + while ((read32(&spi->dma_out->regs->dma_byte_sta) < todo) || - dma_busy(spi->dma_out)) + dma_busy(spi->dma_out)) { spi_delay(spi, todo - spi_byte_count(spi)); + } clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); dma_stop(spi->dma_out); dma_release(spi->dma_out); diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index f5f72aff4b..9bebc72afb 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -45,7 +45,7 @@ static int tegra124_uart_tst_byte(struct tegra124_uart *uart_ptr); static void tegra124_uart_init(struct tegra124_uart *uart_ptr) { // Use a hardcoded divisor for now. - const unsigned divisor = 221; + const unsigned int divisor = 221; const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1 tegra124_uart_tx_flush(uart_ptr); diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index 2495351f6c..7ecf31a84e 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -45,7 +45,7 @@ void verstage_mainboard_init(void) early_mainboard_init(); } -void stage_entry(void) +void stage_entry(uintptr_t unused) { asm volatile ("bl arm_init_caches" : : : "r0", "r1", "r2", "r3", "r4", "r5", "ip"); diff --git a/src/soc/nvidia/tegra210/cbmem.c b/src/soc/nvidia/tegra210/cbmem.c index 63ae497ebb..7fdde9e6ea 100644 --- a/src/soc/nvidia/tegra210/cbmem.c +++ b/src/soc/nvidia/tegra210/cbmem.c @@ -16,7 +16,7 @@ #include #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { static uintptr_t addr; diff --git a/src/soc/nvidia/tegra210/i2c.c b/src/soc/nvidia/tegra210/i2c.c index 35ee77712e..34aae5a639 100644 --- a/src/soc/nvidia/tegra210/i2c.c +++ b/src/soc/nvidia/tegra210/i2c.c @@ -50,4 +50,4 @@ struct tegra_i2c_bus_info tegra_i2c_info[] = { } }; -unsigned g_num_i2c_buses = ARRAY_SIZE(tegra_i2c_info); +unsigned int g_num_i2c_buses = ARRAY_SIZE(tegra_i2c_info); diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index c6a8393905..6ff95b8ac1 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -456,7 +456,7 @@ static void __noreturn reset(void) halt(); } -static void udelay(unsigned usecs) +static void udelay(unsigned int usecs) { uint32_t start = read32(timer_us_ptr); while (read32(timer_us_ptr) - start < usecs) @@ -638,7 +638,7 @@ void ram_repair(void) /* Power. */ -static void power_on_partition(unsigned id) +static void power_on_partition(unsigned int id) { uint32_t bit = 0x1 << id; if (!(read32(pmc_pwrgate_status_ptr) & bit)) { diff --git a/src/soc/nvidia/tegra210/mtc.c b/src/soc/nvidia/tegra210/mtc.c index 97eb3dee14..2973518441 100644 --- a/src/soc/nvidia/tegra210/mtc.c +++ b/src/soc/nvidia/tegra210/mtc.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index 13fa1c6a02..2e01523060 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -72,6 +73,11 @@ void ramstage_entry(void) if (tegra210_run_mtc() != 0) printk(BIOS_ERR, "MTC: No training data.\n"); + /* Ramstage is run on a different core, so passing cbmem_top + via calling arguments is not an option, but it is not a problem + to call cbmem_top_chipset() again here to populate _cbmem_top_ptr. */ + _cbmem_top_ptr = (uintptr_t)cbmem_top_chipset(); + /* Jump to boot state machine in common code. */ main(); } diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c index 904aafa076..b5cf5d5a40 100644 --- a/src/soc/nvidia/tegra210/uart.c +++ b/src/soc/nvidia/tegra210/uart.c @@ -49,7 +49,7 @@ static int tegra210_uart_tst_byte(void); static void tegra210_uart_init(void) { // Use a hardcoded divisor for now. - const unsigned divisor = 221; + const unsigned int divisor = 221; const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1 tegra210_uart_tx_flush(); diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 05325cceb9..972c6258c9 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -23,7 +23,7 @@ void ipq_cbmem_backing_store_ready(void) cbmem_backing_store_ready = 1; } -void *cbmem_top(void) +void *cbmem_top_chipset(void) { /* * In romstage, make sure that cbmem backing store is ready before diff --git a/src/soc/qualcomm/ipq40xx/gpio.c b/src/soc/qualcomm/ipq40xx/gpio.c index a4b06c2c76..41352419d9 100644 --- a/src/soc/qualcomm/ipq40xx/gpio.c +++ b/src/soc/qualcomm/ipq40xx/gpio.c @@ -58,11 +58,11 @@ Return : None *******************************************************/ -void gpio_tlmm_config_set(gpio_t gpio, unsigned func, - unsigned pull, unsigned drvstr, - unsigned enable) +void gpio_tlmm_config_set(gpio_t gpio, unsigned int func, + unsigned int pull, unsigned int drvstr, + unsigned int enable) { - unsigned val = 0; + unsigned int val = 0; if (gpio_not_valid(gpio)) return; @@ -88,11 +88,11 @@ Return : None *******************************************************/ -void gpio_tlmm_config_get(gpio_t gpio, unsigned *func, - unsigned *pull, unsigned *drvstr, - unsigned *enable) +void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func, + unsigned int *pull, unsigned int *drvstr, + unsigned int *enable) { - unsigned val; + unsigned int val; void *addr = GPIO_CONFIG_ADDR(gpio); if (gpio_not_valid(gpio)) diff --git a/src/soc/qualcomm/ipq40xx/i2c.c b/src/soc/qualcomm/ipq40xx/i2c.c index f20dada0b0..17d772a974 100644 --- a/src/soc/qualcomm/ipq40xx/i2c.c +++ b/src/soc/qualcomm/ipq40xx/i2c.c @@ -152,7 +152,7 @@ static int i2c_init(blsp_qup_id_t id) return 0; } -int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, +int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int seg_count) { struct i2c_msg *seg = segments; diff --git a/src/soc/qualcomm/ipq40xx/include/soc/cdp.h b/src/soc/qualcomm/ipq40xx/include/soc/cdp.h index 05a17c2e73..1e26dcde52 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/cdp.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/cdp.h @@ -33,7 +33,7 @@ #include -unsigned smem_get_board_machtype(void); +unsigned int smem_get_board_machtype(void); typedef enum { PHY_INTERFACE_MODE_MII, @@ -116,17 +116,17 @@ typedef struct { } spinorflash_params_t; typedef struct { - unsigned count; + unsigned int count; uint8_t addr[7]; } ipq_gmac_phy_addr_t; typedef struct { - unsigned base; + unsigned int base; int unit; - unsigned is_macsec; - unsigned mac_pwr0; - unsigned mac_pwr1; - unsigned mac_conn_to_phy; + unsigned int is_macsec; + unsigned int mac_pwr0; + unsigned int mac_pwr1; + unsigned int mac_conn_to_phy; phy_interface_t phy; ipq_gmac_phy_addr_t phy_addr; } ipq_gmac_board_cfg_t; @@ -169,7 +169,7 @@ static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg) } #endif -unsigned int get_board_index(unsigned machid); -void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); +unsigned int get_board_index(unsigned int machid); +void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count); #endif /* _IPQ40XX_CDP_H_ */ diff --git a/src/soc/qualcomm/ipq40xx/include/soc/clock.h b/src/soc/qualcomm/ipq40xx/include/soc/clock.h index 8544c4382d..c79c50badc 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/clock.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/clock.h @@ -209,7 +209,7 @@ void uart_clock_config(unsigned int blsp_uart, unsigned int m, unsigned int n, unsigned int d); void nand_clock_config(void); void usb_clock_config(void); -int audio_clock_config(unsigned frequency); +int audio_clock_config(unsigned int frequency); int blsp_i2c_clock_config(blsp_qup_id_t id); diff --git a/src/soc/qualcomm/ipq40xx/include/soc/qup.h b/src/soc/qualcomm/ipq40xx/include/soc/qup.h index e55989a591..7b775433b1 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/qup.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/qup.h @@ -159,10 +159,10 @@ typedef enum { typedef struct { qup_protocol_t protocol; - unsigned clk_frequency; - unsigned src_frequency; + unsigned int clk_frequency; + unsigned int src_frequency; qup_mode_t mode; - unsigned initialized; + unsigned int initialized; } qup_config_t; typedef struct { @@ -171,12 +171,12 @@ typedef struct { struct { uint8_t addr; uint8_t *data; - unsigned data_len; + unsigned int data_len; } iic; struct { void *in; void *out; - unsigned size; + unsigned int size; } spi; } p; } qup_data_t; diff --git a/src/soc/qualcomm/ipq40xx/lcc.c b/src/soc/qualcomm/ipq40xx/lcc.c index 9a6c9116ec..392bd9c714 100644 --- a/src/soc/qualcomm/ipq40xx/lcc.c +++ b/src/soc/qualcomm/ipq40xx/lcc.c @@ -76,11 +76,11 @@ typedef struct __packed { } IpqLccPllRegs; struct lcc_freq_tbl { - unsigned freq; - unsigned pd; - unsigned m; - unsigned n; - unsigned d; + unsigned int freq; + unsigned int pd; + unsigned int m; + unsigned int n; + unsigned int d; }; static const struct lcc_freq_tbl lcc_mi2s_freq_tbl[] = { @@ -205,12 +205,12 @@ static int lcc_init_enable_ahbix(IpqLccClocks *bus) return 1; } -static int lcc_init_mi2s(IpqLccClocks *bus, unsigned freq) +static int lcc_init_mi2s(IpqLccClocks *bus, unsigned int freq) { IpqLccMi2sRegs *mi2s_regs = bus->lcc_mi2s_regs; uint32_t regval; uint8_t pd, m, n, d; - unsigned i; + unsigned int i; i = 0; while (lcc_mi2s_freq_tbl[i].freq != 0) { @@ -285,7 +285,7 @@ static int lcc_enable_mi2s(IpqLccClocks *bus) return 1; } -int audio_clock_config(unsigned frequency) +int audio_clock_config(unsigned int frequency) { IpqLccClocks bus = { .gcc_apcs_regs = (void *)(MSM_GCC_BASE + GCC_PLL_APCS_REG), diff --git a/src/soc/qualcomm/ipq40xx/qup.c b/src/soc/qualcomm/ipq40xx/qup.c index 438bd14757..9a206fc6a9 100644 --- a/src/soc/qualcomm/ipq40xx/qup.c +++ b/src/soc/qualcomm/ipq40xx/qup.c @@ -100,7 +100,7 @@ static int check_bit_state(uint32_t *reg, int wait_for) /* * Check whether GSBIn_QUP State is valid */ -static qup_return_t qup_wait_for_state(blsp_qup_id_t id, unsigned wait_for) +static qup_return_t qup_wait_for_state(blsp_qup_id_t id, unsigned int wait_for) { return check_bit_state(QUP_ADDR(id, QUP_STATE), wait_for); } @@ -195,8 +195,8 @@ static qup_return_t qup_i2c_write_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj, qup_return_t ret = QUP_ERR_UNDEFINED; uint8_t addr = p_tx_obj->p.iic.addr; uint8_t *data_ptr = p_tx_obj->p.iic.data; - unsigned data_len = p_tx_obj->p.iic.data_len; - unsigned idx = 0; + unsigned int data_len = p_tx_obj->p.iic.data_len; + unsigned int idx = 0; uint32_t tag, *fifo = QUP_ADDR(id, QUP_OUTPUT_FIFO); qup_reset_master_status(id); @@ -312,8 +312,8 @@ static qup_return_t qup_i2c_read_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj) qup_return_t ret = QUP_ERR_UNDEFINED; uint8_t addr = p_tx_obj->p.iic.addr; uint8_t *data_ptr = p_tx_obj->p.iic.data; - unsigned data_len = p_tx_obj->p.iic.data_len; - unsigned idx = 0; + unsigned int data_len = p_tx_obj->p.iic.data_len; + unsigned int idx = 0; uint32_t *fifo = QUP_ADDR(id, QUP_OUTPUT_FIFO); qup_reset_master_status(id); @@ -476,7 +476,7 @@ bailout: qup_return_t qup_set_state(blsp_qup_id_t id, uint32_t state) { qup_return_t ret = QUP_ERR_UNDEFINED; - unsigned curr_state = read32(QUP_ADDR(id, QUP_STATE)); + unsigned int curr_state = read32(QUP_ADDR(id, QUP_STATE)); if (state <= QUP_STATE_PAUSE && (curr_state & QUP_STATE_VALID_MASK)) { /* diff --git a/src/soc/qualcomm/ipq40xx/timer.c b/src/soc/qualcomm/ipq40xx/timer.c index a08f1fbf86..1401730558 100644 --- a/src/soc/qualcomm/ipq40xx/timer.c +++ b/src/soc/qualcomm/ipq40xx/timer.c @@ -70,7 +70,7 @@ static inline uint64_t read_gcnt_val(void) * udelay - generates micro second delay. * @param usec: delay duration in microseconds */ -void udelay(unsigned usec) +void udelay(unsigned int usec) { uint64_t expire; diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index 6e5bac624b..9548bf0c16 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -44,7 +44,7 @@ typedef struct { void *uart_dm_base; uart_clk_mnd_t mnd_value; - unsigned blsp_uart; + unsigned int blsp_uart; gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS]; } uart_params_t; diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 9674db65da..6dc92a0c11 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -23,7 +23,7 @@ void ipq_cbmem_backing_store_ready(void) cbmem_backing_store_ready = 1; } -void *cbmem_top(void) +void *cbmem_top_chipset(void) { /* * In romstage, make sure that cbmem backing store is ready before diff --git a/src/soc/qualcomm/ipq806x/gpio.c b/src/soc/qualcomm/ipq806x/gpio.c index 2b27e6d2e0..019635110a 100644 --- a/src/soc/qualcomm/ipq806x/gpio.c +++ b/src/soc/qualcomm/ipq806x/gpio.c @@ -59,11 +59,11 @@ Return : None *******************************************************/ -void gpio_tlmm_config_set(gpio_t gpio, unsigned func, - unsigned pull, unsigned drvstr, - unsigned enable) +void gpio_tlmm_config_set(gpio_t gpio, unsigned int func, + unsigned int pull, unsigned int drvstr, + unsigned int enable) { - unsigned val = 0; + unsigned int val = 0; if (gpio_not_valid(gpio)) return; @@ -89,11 +89,11 @@ Return : None *******************************************************/ -void gpio_tlmm_config_get(gpio_t gpio, unsigned *func, - unsigned *pull, unsigned *drvstr, - unsigned *enable) +void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func, + unsigned int *pull, unsigned int *drvstr, + unsigned int *enable) { - unsigned val; + unsigned int val; void *addr = GPIO_CONFIG_ADDR(gpio); if (gpio_not_valid(gpio)) diff --git a/src/soc/qualcomm/ipq806x/gsbi.c b/src/soc/qualcomm/ipq806x/gsbi.c index 4e3c780925..18b1876933 100644 --- a/src/soc/qualcomm/ipq806x/gsbi.c +++ b/src/soc/qualcomm/ipq806x/gsbi.c @@ -57,12 +57,12 @@ static inline void *gsbi_ctl_reg_addr(gsbi_id_t gsbi_id) gsbi_return_t gsbi_init(gsbi_id_t gsbi_id, gsbi_protocol_t protocol) { - unsigned reg_val; - unsigned m = 1; - unsigned n = 4; - unsigned pre_div = 4; - unsigned src = 3; - unsigned mnctr_mode = 2; + unsigned int reg_val; + unsigned int m = 1; + unsigned int n = 4; + unsigned int pre_div = 4; + unsigned int src = 3; + unsigned int mnctr_mode = 2; void *gsbi_ctl = gsbi_ctl_reg_addr(gsbi_id); if (!gsbi_ctl) diff --git a/src/soc/qualcomm/ipq806x/i2c.c b/src/soc/qualcomm/ipq806x/i2c.c index c81373fade..e24e76d51d 100644 --- a/src/soc/qualcomm/ipq806x/i2c.c +++ b/src/soc/qualcomm/ipq806x/i2c.c @@ -96,9 +96,9 @@ static int i2c_write(uint32_t gsbi_id, uint8_t slave, return 0; } -static int i2c_init(unsigned bus) +static int i2c_init(unsigned int bus) { - unsigned gsbi_id = bus; + unsigned int gsbi_id = bus; qup_config_t *qup_config; switch (gsbi_id) { @@ -139,7 +139,7 @@ static int i2c_init(unsigned bus) return 0; } -int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, +int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int seg_count) { struct i2c_msg *seg = segments; diff --git a/src/soc/qualcomm/ipq806x/include/soc/cdp.h b/src/soc/qualcomm/ipq806x/include/soc/cdp.h index 89636ace18..35659a7fcc 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/cdp.h +++ b/src/soc/qualcomm/ipq806x/include/soc/cdp.h @@ -18,7 +18,7 @@ #include -unsigned smem_get_board_machtype(void); +unsigned int smem_get_board_machtype(void); typedef enum { PHY_INTERFACE_MODE_MII, @@ -101,17 +101,17 @@ typedef struct { } spinorflash_params_t; typedef struct { - unsigned count; + unsigned int count; uint8_t addr[7]; } ipq_gmac_phy_addr_t; typedef struct { - unsigned base; + unsigned int base; int unit; - unsigned is_macsec; - unsigned mac_pwr0; - unsigned mac_pwr1; - unsigned mac_conn_to_phy; + unsigned int is_macsec; + unsigned int mac_pwr0; + unsigned int mac_pwr1; + unsigned int mac_conn_to_phy; phy_interface_t phy; ipq_gmac_phy_addr_t phy_addr; } ipq_gmac_board_cfg_t; @@ -154,8 +154,8 @@ static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg) } #endif -unsigned int get_board_index(unsigned machid); -void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); +unsigned int get_board_index(unsigned int machid); +void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count); void board_nand_init(void); diff --git a/src/soc/qualcomm/ipq806x/include/soc/clock.h b/src/soc/qualcomm/ipq806x/include/soc/clock.h index 7ecc1eee16..47d7d49ce7 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/clock.h +++ b/src/soc/qualcomm/ipq806x/include/soc/clock.h @@ -193,6 +193,6 @@ void uart_clock_config(unsigned int gsbi_port, unsigned int m, unsigned int n, unsigned int d, unsigned int clk_dummy); void nand_clock_config(void); void usb_clock_config(void); -int audio_clock_config(unsigned frequency); +int audio_clock_config(unsigned int frequency); #endif /* __IPQ860X_CLOCK_H_ */ diff --git a/src/soc/qualcomm/ipq806x/include/soc/qup.h b/src/soc/qualcomm/ipq806x/include/soc/qup.h index 5168b19cc0..2b0cff3914 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/qup.h +++ b/src/soc/qualcomm/ipq806x/include/soc/qup.h @@ -145,10 +145,10 @@ typedef enum { typedef struct { qup_protocol_t protocol; - unsigned clk_frequency; - unsigned src_frequency; + unsigned int clk_frequency; + unsigned int src_frequency; qup_mode_t mode; - unsigned initialized; + unsigned int initialized; } qup_config_t; typedef struct { @@ -157,12 +157,12 @@ typedef struct { struct { uint8_t addr; uint8_t *data; - unsigned data_len; + unsigned int data_len; } iic; struct { void *in; void *out; - unsigned size; + unsigned int size; } spi; } p; } qup_data_t; diff --git a/src/soc/qualcomm/ipq806x/lcc.c b/src/soc/qualcomm/ipq806x/lcc.c index 8f862b4d49..7d8d7bf4d2 100644 --- a/src/soc/qualcomm/ipq806x/lcc.c +++ b/src/soc/qualcomm/ipq806x/lcc.c @@ -76,11 +76,11 @@ typedef struct __packed { } Ipq806xLccPllRegs; struct lcc_freq_tbl { - unsigned freq; - unsigned pd; - unsigned m; - unsigned n; - unsigned d; + unsigned int freq; + unsigned int pd; + unsigned int m; + unsigned int n; + unsigned int d; }; static const struct lcc_freq_tbl lcc_mi2s_freq_tbl[] = { @@ -205,12 +205,12 @@ static int lcc_init_enable_ahbix(Ipq806xLccClocks *bus) return 1; } -static int lcc_init_mi2s(Ipq806xLccClocks *bus, unsigned freq) +static int lcc_init_mi2s(Ipq806xLccClocks *bus, unsigned int freq) { Ipq806xLccMi2sRegs *mi2s_regs = bus->lcc_mi2s_regs; uint32_t regval; uint8_t pd, m, n, d; - unsigned i; + unsigned int i; i = 0; while (lcc_mi2s_freq_tbl[i].freq != 0) { @@ -285,7 +285,7 @@ static int lcc_enable_mi2s(Ipq806xLccClocks *bus) return 1; } -int audio_clock_config(unsigned frequency) +int audio_clock_config(unsigned int frequency) { Ipq806xLccClocks bus = { .gcc_apcs_regs = (void *)(MSM_GCC_BASE + GCC_PLL_APCS_REG), diff --git a/src/soc/qualcomm/ipq806x/qup.c b/src/soc/qualcomm/ipq806x/qup.c index 3ceb84d881..dcfc00cb84 100644 --- a/src/soc/qualcomm/ipq806x/qup.c +++ b/src/soc/qualcomm/ipq806x/qup.c @@ -37,14 +37,14 @@ #define TIMEOUT_CNT 100000 //TODO: refactor the following array to iomap driver. -static unsigned gsbi_qup_base[] = { - (unsigned)GSBI_QUP1_BASE, - (unsigned)GSBI_QUP2_BASE, - (unsigned)GSBI_QUP3_BASE, - (unsigned)GSBI_QUP4_BASE, - (unsigned)GSBI_QUP5_BASE, - (unsigned)GSBI_QUP6_BASE, - (unsigned)GSBI_QUP7_BASE, +static unsigned int gsbi_qup_base[] = { + (unsigned int)GSBI_QUP1_BASE, + (unsigned int)GSBI_QUP2_BASE, + (unsigned int)GSBI_QUP3_BASE, + (unsigned int)GSBI_QUP4_BASE, + (unsigned int)GSBI_QUP5_BASE, + (unsigned int)GSBI_QUP6_BASE, + (unsigned int)GSBI_QUP7_BASE, }; #define QUP_ADDR(gsbi_num, reg) ((void *)((gsbi_qup_base[gsbi_num-1]) + (reg))) @@ -91,7 +91,7 @@ static int check_bit_state(uint32_t *reg, int wait_for) /* * Check whether GSBIn_QUP State is valid */ -static qup_return_t qup_wait_for_state(gsbi_id_t gsbi_id, unsigned wait_for) +static qup_return_t qup_wait_for_state(gsbi_id_t gsbi_id, unsigned int wait_for) { return check_bit_state(QUP_ADDR(gsbi_id, QUP_STATE), wait_for); } @@ -155,8 +155,8 @@ static qup_return_t qup_i2c_write_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj, qup_return_t ret = QUP_ERR_UNDEFINED; uint8_t addr = p_tx_obj->p.iic.addr; uint8_t *data_ptr = p_tx_obj->p.iic.data; - unsigned data_len = p_tx_obj->p.iic.data_len; - unsigned idx = 0; + unsigned int data_len = p_tx_obj->p.iic.data_len; + unsigned int idx = 0; qup_reset_master_status(gsbi_id); qup_set_state(gsbi_id, QUP_STATE_RUN); @@ -228,8 +228,8 @@ static qup_return_t qup_i2c_read_fifo(gsbi_id_t gsbi_id, qup_data_t *p_tx_obj) qup_return_t ret = QUP_ERR_UNDEFINED; uint8_t addr = p_tx_obj->p.iic.addr; uint8_t *data_ptr = p_tx_obj->p.iic.data; - unsigned data_len = p_tx_obj->p.iic.data_len; - unsigned idx = 0; + unsigned int data_len = p_tx_obj->p.iic.data_len; + unsigned int idx = 0; qup_reset_master_status(gsbi_id); qup_set_state(gsbi_id, QUP_STATE_RUN); @@ -377,7 +377,7 @@ bailout: qup_return_t qup_set_state(gsbi_id_t gsbi_id, uint32_t state) { qup_return_t ret = QUP_ERR_UNDEFINED; - unsigned curr_state = read32(QUP_ADDR(gsbi_id, QUP_STATE)); + unsigned int curr_state = read32(QUP_ADDR(gsbi_id, QUP_STATE)); if (state <= QUP_STATE_PAUSE && (curr_state & QUP_STATE_VALID_MASK)) { /* diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 64a98d5123..183b33c20a 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -632,7 +632,7 @@ static void spi_ctrlr_release_bus(const struct spi_slave *slave) } static int spi_xfer_tx_packet(struct ipq_spi_slave *ds, - const uint8_t *dout, unsigned out_bytes) + const uint8_t *dout, unsigned int out_bytes) { int ret; @@ -660,7 +660,7 @@ static int spi_xfer_tx_packet(struct ipq_spi_slave *ds, } static int spi_xfer_rx_packet(struct ipq_spi_slave *ds, - uint8_t *din, unsigned in_bytes) + uint8_t *din, unsigned int in_bytes) { int ret; @@ -711,7 +711,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, SPI_QUP_CONF_OUTPUT_ENA); while (out_bytes) { - unsigned todo = MIN(out_bytes, MAX_PACKET_COUNT); + unsigned int todo = MIN(out_bytes, MAX_PACKET_COUNT); ret = spi_xfer_tx_packet(ds, dout, todo); if (ret) @@ -733,7 +733,7 @@ spi_receive: SPI_QUP_CONF_INPUT_ENA); while (in_bytes) { - unsigned todo = MIN(in_bytes, MAX_PACKET_COUNT); + unsigned int todo = MIN(in_bytes, MAX_PACKET_COUNT); ret = spi_xfer_rx_packet(ds, din, todo); if (ret) diff --git a/src/soc/qualcomm/ipq806x/timer.c b/src/soc/qualcomm/ipq806x/timer.c index f52f2efdc8..25eebf4eb9 100644 --- a/src/soc/qualcomm/ipq806x/timer.c +++ b/src/soc/qualcomm/ipq806x/timer.c @@ -72,7 +72,7 @@ void init_timer(void) * udelay - generates micro second delay. * @param usec: delay duration in microseconds */ -void udelay(unsigned usec) +void udelay(unsigned int usec) { uint32_t now; uint32_t last; diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index f3e7de5910..36084f7806 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -47,7 +47,7 @@ typedef struct { void *uart_dm_base; void *uart_gsbi_base; - unsigned uart_gsbi; + unsigned int uart_gsbi; uart_clk_mnd_t mnd_value; gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS]; } uart_params_t; @@ -194,7 +194,7 @@ msm_boot_uart_dm_read(unsigned int *data, int *count, int wait) void uart_tx_byte(int idx, unsigned char data) { int num_of_chars = 1; - unsigned tx_data = 0; + unsigned int tx_data = 0; void *base = uart_board_param.uart_dm_base; /* Wait until transmit FIFO is empty. */ diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 0ebfcaef78..0766d2f181 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -39,7 +39,6 @@ romstage-y += blsp.c ramstage-y += soc.c ramstage-y += timer.c ramstage-y += spi.c -ramstage-y += cbmem.c ramstage-y += gpio.c ramstage-y += clock.c ramstage-y += i2c.c @@ -52,8 +51,4 @@ ramstage-$(CONFIG_DRIVERS_UART) += uart.c CPPFLAGS_common += -Isrc/soc/qualcomm/qcs405/include -$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin - @printf "Generating: $(subst $(obj)/,,$(@))\n" - cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin - endif diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c index e065409622..a780c6bcf1 100644 --- a/src/soc/qualcomm/qcs405/cbmem.c +++ b/src/soc/qualcomm/qcs405/cbmem.c @@ -15,7 +15,7 @@ #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return (void *)((uintptr_t)3 * GiB); } diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index b7dd51b2a6..37fd2c2098 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #define DIV(div) (div ? (2*div - 1) : 0) diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index 13b9daef9d..827448ce91 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c index 3e980887db..24045cd388 100644 --- a/src/soc/qualcomm/qcs405/uart.c +++ b/src/soc/qualcomm/qcs405/uart.c @@ -30,7 +30,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig new file mode 100644 index 0000000000..70737e9379 --- /dev/null +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -0,0 +1,25 @@ + +config SOC_QUALCOMM_SC7180 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER + select ARM64_USE_ARCH_TIMER + select SOC_QUALCOMM_COMMON + select HAVE_UART_SPECIAL + select BOOTBLOCK_CONSOLE + +if SOC_QUALCOMM_SC7180 + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + +endif diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc new file mode 100644 index 0000000000..6d2a3e7c08 --- /dev/null +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -0,0 +1,43 @@ + +ifeq ($(CONFIG_SOC_QUALCOMM_SC7180),y) + +################################################################################ +bootblock-y += bootblock.c +bootblock-y += mmu.c +bootblock-y += timer.c +bootblock-y += spi.c +bootblock-y += gpio.c +bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c + +################################################################################ +verstage-y += timer.c +verstage-y += spi.c +verstage-y += gpio.c +verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c + +################################################################################ +romstage-y += cbmem.c +romstage-y += timer.c +romstage-y += ../common/qclib.c +romstage-y += qclib.c +romstage-y += ../common/mmu.c +romstage-y += mmu.c +romstage-y += spi.c +romstage-y += gpio.c +romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c + +################################################################################ +ramstage-y += soc.c +ramstage-y += timer.c +ramstage-y += spi.c +ramstage-y += gpio.c +ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/sc7180/include +CPPFLAGS_common += -Isrc/soc/qualcomm/common/include + +################################################################################ + +endif diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c new file mode 100644 index 0000000000..b9b86609ad --- /dev/null +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +void bootblock_soc_init(void) +{ + sc7180_mmu_init(); +} diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c new file mode 100644 index 0000000000..fe81309c7a --- /dev/null +++ b/src/soc/qualcomm/sc7180/cbmem.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +void *cbmem_top_chipset(void) +{ + return (void *)((uintptr_t)4 * GiB); +} diff --git a/src/soc/qualcomm/sc7180/gpio.c b/src/soc/qualcomm/sc7180/gpio.c new file mode 100644 index 0000000000..9f3b722e31 --- /dev/null +++ b/src/soc/qualcomm/sc7180/gpio.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable) +{ + uint32_t reg_val; + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + /* gpio pull only PULLNONE, PULLUP, KEEPER, PULLDOWN status */ + assert(pull <= GPIO_PULL_UP); + + reg_val = ((enable & GPIO_CFG_OE_BMSK) << GPIO_CFG_OE_SHFT) | + ((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) | + ((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) | + ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT); + + write32(®s->cfg, reg_val); +} + +void gpio_set(gpio_t gpio, int value) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + write32(®s->in_out, (!!value) << GPIO_IO_OUT_SHFT); +} + +int gpio_get(gpio_t gpio) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + return ((read32(®s->in_out) >> GPIO_IO_IN_SHFT) & + GPIO_IO_IN_BMSK); +} + +void gpio_input_pulldown(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_PULL_DOWN, GPIO_2MA, GPIO_OUTPUT_DISABLE); +} + +void gpio_input_pullup(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_PULL_UP, GPIO_2MA, GPIO_OUTPUT_DISABLE); +} + +void gpio_input(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_DISABLE); +} + +void gpio_output(gpio_t gpio, int value) +{ + gpio_set(gpio, value); + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); +} + +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + gpio_configure(gpio, GPIO_FUNC_GPIO, + pull, GPIO_2MA, GPIO_OUTPUT_DISABLE); + + clrsetbits_le32(®s->intr_cfg, GPIO_INTR_DECT_CTL_MASK << + GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT); + clrsetbits_le32(®s->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE + << GPIO_INTR_RAW_STATUS_EN_SHIFT, GPIO_INTR_RAW_STATUS_ENABLE + << GPIO_INTR_RAW_STATUS_EN_SHIFT); +} + +int gpio_irq_status(gpio_t gpio) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + if (!(read32(®s->intr_status) & GPIO_INTR_STATUS_MASK)) + return 0; + + write32(®s->intr_status, GPIO_INTR_STATUS_DISABLE); + return 1; +} diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h new file mode 100644 index 0000000000..ffacf55681 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018-2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ +#define _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ + +#include + +#define AOSS_CC_BASE 0x0C2A0000 +#define GCC_BASE 0x00100000 +#define QSPI_BASE 0x088DC000 +#define TLMM_NORTH_TILE_BASE 0x03900000 +#define TLMM_SOUTH_TILE_BASE 0x03D00000 +#define TLMM_WEST_TILE_BASE 0x03500000 + +#endif /* __SOC_QUALCOMM_SC7180_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/gpio.h b/src/soc/qualcomm/sc7180/include/soc/gpio.h new file mode 100644 index 0000000000..56ff1ab3ed --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/gpio.h @@ -0,0 +1,301 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_GPIO_H_ +#define _SOC_QUALCOMM_SC7180_GPIO_H_ + +#include +#include + +typedef struct { + u32 addr; +} gpio_t; + +#define TLMM_TILE_SIZE 0x00400000 +#define TLMM_GPIO_OFF_DELTA 0x00001000 +#define TLMM_GPIO_TILE_NUM 3 + +#define TLMM_GPIO_IN_OUT_OFF 0x4 +#define TLMM_GPIO_ID_STATUS_OFF 0x10 + +#define GPIO_FUNC_GPIO 0 + +/* GPIO INTR CFG MASK */ +#define GPIO_INTR_DECT_CTL_MASK 0x3 +#define GPIO_INTR_RAW_STATUS_EN_MASK 0x1 + +/* GPIO INTR CFG SHIFT */ +#define GPIO_INTR_DECT_CTL_SHIFT 2 +#define GPIO_INTR_RAW_STATUS_EN_SHIFT 4 + +/* GPIO INTR STATUS MASK */ +#define GPIO_INTR_STATUS_MASK 0x1 + +/* GPIO INTR RAW STATUS */ +#define GPIO_INTR_RAW_STATUS_ENABLE 1 +#define GPIO_INTR_RAW_STATUS_DISABLE 0 + +/* GPIO INTR STATUS */ +#define GPIO_INTR_STATUS_ENABLE 1 +#define GPIO_INTR_STATUS_DISABLE 0 + +/* GPIO INTR CFG MASK */ +#define GPIO_INTR_DECT_CTL_MASK 0x3 +#define GPIO_INTR_RAW_STATUS_EN_MASK 0x1 + +/* GPIO INTR CFG SHIFT */ +#define GPIO_INTR_DECT_CTL_SHIFT 2 +#define GPIO_INTR_RAW_STATUS_EN_SHIFT 4 + +/* GPIO INTR STATUS MASK */ +#define GPIO_INTR_STATUS_MASK 0x1 + +/* GPIO INTR RAW STATUS */ +#define GPIO_INTR_RAW_STATUS_ENABLE 1 +#define GPIO_INTR_RAW_STATUS_DISABLE 0 + +/* GPIO INTR STATUS */ +#define GPIO_INTR_STATUS_ENABLE 1 +#define GPIO_INTR_STATUS_DISABLE 0 + +/* GPIO TLMM: Direction */ +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +/* GPIO TLMM: Pullup/Pulldown */ +#define GPIO_NO_PULL 0 +#define GPIO_PULL_DOWN 1 +#define GPIO_KEEPER 2 +#define GPIO_PULL_UP 3 + +/* GPIO TLMM: Drive Strength */ +#define GPIO_2MA 0 +#define GPIO_4MA 1 +#define GPIO_6MA 2 +#define GPIO_8MA 3 +#define GPIO_10MA 4 +#define GPIO_12MA 5 +#define GPIO_14MA 6 +#define GPIO_16MA 7 + +/* GPIO TLMM: Status */ +#define GPIO_OUTPUT_DISABLE 0 +#define GPIO_OUTPUT_ENABLE 1 + +/* GPIO TLMM: Mask */ +#define GPIO_CFG_PULL_BMSK 0x3 +#define GPIO_CFG_FUNC_BMSK 0xF +#define GPIO_CFG_DRV_BMSK 0x7 +#define GPIO_CFG_OE_BMSK 0x1 + +/* GPIO TLMM: Shift */ +#define GPIO_CFG_PULL_SHFT 0 +#define GPIO_CFG_FUNC_SHFT 2 +#define GPIO_CFG_DRV_SHFT 6 +#define GPIO_CFG_OE_SHFT 9 + +/* GPIO IO: Mask */ +#define GPIO_IO_IN_BMSK 0x1 +#define GPIO_IO_OUT_BMSK 0x1 + +/* GPIO IO: Shift */ +#define GPIO_IO_IN_SHFT 0 +#define GPIO_IO_OUT_SHFT 1 + +/* GPIO ID STATUS: Mask */ +#define GPIO_ID_STATUS_BMSK 0x1 + +/* GPIO MAX Valid # */ +#define GPIO_NUM_MAX 118 + +#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR}) + +#define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \ +GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \ +GPIO##index##_FUNC_##func1 = 1, \ +GPIO##index##_FUNC_##func2 = 2, \ +GPIO##index##_FUNC_##func3 = 3, \ +GPIO##index##_FUNC_##func4 = 4, \ +GPIO##index##_FUNC_##func5 = 5, \ +GPIO##index##_FUNC_##func6 = 6, \ +GPIO##index##_FUNC_##func7 = 7 + +enum { + PIN(0, SOUTH, QUP0_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(1, SOUTH, QUP0_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(2, SOUTH, QUP0_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(3, SOUTH, QUP0_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(4, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(5, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(6, NORTH, QUP1_L0, QUP1_L2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(7, NORTH, QUP1_L1, QUP1_L3, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(8, NORTH, GP_PDM_MIRB, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(9, NORTH, RES1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(10, NORTH, MDP_VSYNC_P_MIRA, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(11, NORTH, MDP_VSYNC_S_MIRA, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(12, SOUTH, MDP_VSYNC_E, RES_2, QUP0_L4, RES_4, RES_5, RES_6, RES_7), + PIN(13, SOUTH, CAM_MCLK0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(14, SOUTH, CAM_MCLK1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(15, SOUTH, CAM_MCLK2, QUP0_L0, QUP0_L2, RES_4, RES_5, RES_6, RES_7), + PIN(16, SOUTH, CAM_MCLK3, QUP0_L1, QUP0_L3, RES_4, RES_5, RES_6, RES_7), + PIN(17, SOUTH, CCI_I2C_SDA0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(18, SOUTH, CCI_I2C_SCL0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(19, SOUTH, CCI_I2C_SDA1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(20, SOUTH, CCI_I2C_SCL1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(21, NORTH, CCI_TIMER0, GCC_GP2_CLK_MIRB, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(22, NORTH, CCI_TIMER1, GCC_GP3_CLK_MIRB, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(23, SOUTH, CCI_TIMER2, CAM_MCLK4, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(24, SOUTH, CCI_TIMER3, CCI_ASYNC_IN1, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(25, SOUTH, CCI_TIMER4, CCI_ASYNC_IN2, QUP0_L0, RES_4, RES_5, RES_6, + RES_7), + PIN(26, SOUTH, CCI_ASYNC_IN0, QUP0_L1, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(27, SOUTH, CCI_I2C_SDA2, QUP0_L2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(28, SOUTH, CCI_I2C_SCL2, QUP0_L3, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(29, SOUTH, GP_MN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(30, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(31, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(32, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(33, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(34, SOUTH, QUP0_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(35, SOUTH, QUP0_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(36, SOUTH, QUP0_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(37, SOUTH, QUP0_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(38, SOUTH, QUP0_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(39, SOUTH, QUP0_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(40, SOUTH, QUP0_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(41, SOUTH, QUP0_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(42, NORTH, QUP1_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(43, NORTH, QUP1_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(44, NORTH, QUP1_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(45, NORTH, QUP1_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(46, NORTH, QUP1_L0, QUP1_L2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(47, NORTH, QUP1_L1, QUP1_L3, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(48, NORTH, GCC_GP1_CLK_MIRA, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(49, WEST, MI2S_1_SCK, BTFM_SLIMBUS_CLK, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(50, WEST, MI2S_1_WS, BTFM_SLIMBUS_DATA0, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(51, WEST, MI2S_1_DATA0, BTFM_SLIMBUS_DATA1, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(52, WEST, MI2S_1_DATA1, BTFM_SLIMBUS_DATA2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(53, WEST, MI2S_0_SCK, QUP1_L0, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(54, WEST, MI2S_0_WS, QUP1_L1, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(55, WEST, MI2S_0_DATA0, QUP1_L2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(56, WEST, MI2S_0_DATA1, QUP1_L3, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(57, WEST, LPASS_EXT_MCLK0, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(58, WEST, LPASS_EXT_MCLK1, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(59, NORTH, QUP1_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(60, NORTH, QUP1_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(61, NORTH, QUP1_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(62, NORTH, QUP1_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(63, NORTH, QSPI_CLK, MDP_VSYNC0_OUT, MI2S_2_SCK, MDP_VSYNC1_OUT, + MDP_VSYNC2_OUT, MDP_VSYNC3_OUT, RES_7), + PIN(64, NORTH, QSPI_DATA_0, MI2S_2_WS, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(65, NORTH, QSPI_DATA_1, MI2S_2_DATA0, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(66, NORTH, QSPI_DATA_2, MI2S_2_DATA1, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(67, NORTH, QSPI_DATA_3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(68, NORTH, QSPI_CS_N_0, QUP1_L4, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(69, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(70, NORTH, RES_1, RES_2, MDP_VSYNC_P_MIRB, LDO_EN, RES_5, RES_6, + RES_7), + PIN(71, NORTH, RES_1, MDP_VSYNC_S_MIRB, LDO_UPDATE, RES_4, RES_5, RES_6, + RES_7), + PIN(72, NORTH, QSPI_CS_N_1, QUP1_L5, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(73, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(74, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(75, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(76, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(77, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(78, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(79, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(80, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(81, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(82, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(83, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(84, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(85, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(86, NORTH, QUP1_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(87, NORTH, QUP1_L1, ADSP_EXT_VFR_IRQ, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(88, NORTH, QUP1_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(89, NORTH, QUP1_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(90, NORTH, QUP1_L4, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(91, NORTH, QUP1_L5, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(92, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(93, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(94, SOUTH, QUP0_L5, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(95, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(96, WEST, QLINK_REQUEST, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(97, WEST, QLINK_ENABLE, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(98, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(99, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(100, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(101, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(102, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(103, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(104, WEST, USB_PHY_PS, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(105, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(106, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(107, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(108, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(109, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(110, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(111, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(112, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(113, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(114, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(115, WEST, QUP0_L0, QUP0_L2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(116, WEST, QUP0_L1, QUP0_L3, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(117, WEST, DP_HOT_PLUG_DETECT_MIRB, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(118, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), +}; + +enum gpio_irq_type { + IRQ_TYPE_LEVEL = 0, + IRQ_TYPE_RISING_EDGE = 1, + IRQ_TYPE_FALLING_EDGE = 2, + IRQ_TYPE_DUAL_EDGE = 3, +}; + +struct tlmm_gpio { + uint32_t cfg; + uint32_t in_out; + uint32_t intr_cfg; + uint32_t intr_status; +}; + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable); +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull); +int gpio_irq_status(gpio_t gpio); + +#endif /* _SOC_QUALCOMM_SC7180_GPIO_H_ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld new file mode 100644 index 0000000000..b2ee3b20a0 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +/* SYSTEM_IMEM : 0x14680000 - 0x146AE000 */ +#define SSRAM_START(addr) SYMBOL(ssram, addr) +#define SSRAM_END(addr) SYMBOL(essram, addr) + +/* BOOT_IMEM : 0x14800000 - 0x14980000 */ +#define BSRAM_START(addr) SYMBOL(bsram, addr) +#define BSRAM_END(addr) SYMBOL(ebsram, addr) + +SECTIONS +{ + SSRAM_START(0x14680000) + OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) + REGION(qcsdi, 0x14699000, 52K, 4K) + SSRAM_END(0x146AE000) + + BSRAM_START(0x14800000) + BOOTBLOCK(0x14815000, 40K) + PRERAM_CBFS_CACHE(0x1481F000, 70K) + PRERAM_CBMEM_CONSOLE(0x14830800, 32K) + TIMESTAMP(0x14838800, 1K) + TTB(0x14839000, 56K) + STACK(0x14847000, 16K) + VBOOT2_WORK(0x1484B000, 12K) + DMA_COHERENT(0x1484E000, 8K) + REGION(ddr_training, 0x14850000, 8K, 4K) + REGION(qclib_serial_log, 0x14852000, 4K, 4K) + REGION(ddr_information, 0x14853000, 1K, 1K) + REGION(dcb, 0x14870000, 16K, 4K) + REGION(pmic, 0x14874000, 44K, 4K) + REGION(limits_cfg, 0x1487F000, 4K, 4K) + REGION(qclib, 0x14880000, 512K, 4K) + BSRAM_END(0x14900000) + + DRAM_START(0x80000000) + /* Various hardware/software subsystems make use of this area */ + REGION(dram_soc, 0x80900000, 0x300000, 0x1000) + BL31(0x80C00000, 0x1A800000) + POSTRAM_CBFS_CACHE(0x9F800000, 16M) + RAMSTAGE(0xA0800000, 16M) +} diff --git a/src/soc/qualcomm/sc7180/include/soc/mmu.h b/src/soc/qualcomm/sc7180/include/soc/mmu.h new file mode 100644 index 0000000000..735ce17936 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/mmu.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_MMU_H_ +#define _SOC_QUALCOMM_SC7180_MMU_H_ + +void sc7180_mmu_init(void); + +#endif /* _SOC_QUALCOMM_SC7180_MMU_H_ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h new file mode 100644 index 0000000000..f379bb98e3 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_SYMBOLS_H_ +#define _SOC_QUALCOMM_SC7180_SYMBOLS_H_ + +#include + +DECLARE_REGION(ssram) +DECLARE_REGION(bsram) +DECLARE_REGION(dram_aop) +DECLARE_REGION(dram_soc) +DECLARE_REGION(dcb) +DECLARE_REGION(pmic) +DECLARE_REGION(limits_cfg) + +#endif /* _SOC_QUALCOMM_SC7180_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c new file mode 100644 index 0000000000..231b06f819 --- /dev/null +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +void sc7180_mmu_init(void) +{ + mmu_init(); + + mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM); + mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); + mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); + mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), + UNCACHED_RAM); + + mmu_enable(); +} diff --git a/src/soc/qualcomm/sc7180/qclib.c b/src/soc/qualcomm/sc7180/qclib.c new file mode 100644 index 0000000000..9c05452c9e --- /dev/null +++ b/src/soc/qualcomm/sc7180/qclib.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +int qclib_soc_blob_load(void) +{ + size_t size; + ssize_t ssize; + + /* Attempt to load PMICCFG Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); + + /* Attempt to load DCB Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", + _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); + + /* Attempt to load Limits Config Blob */ + ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, + REGION_SIZE(limits_cfg)); + if (ssize < 0) + return -1; + qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, + _limits_cfg, ssize, 0); + + return 0; +} diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c new file mode 100644 index 0000000000..7003b39a75 --- /dev/null +++ b/src/soc/qualcomm/sc7180/soc.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, + ddr_region->size / KiB); + reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB, + REGION_SIZE(dram_soc) / KiB); +} + +static void soc_init(struct device *dev) +{ + +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_sc7180_ops = { + CHIP_NAME("SOC Qualcomm SC7180") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/qualcomm/sc7180/spi.c b/src/soc/qualcomm/sc7180/spi.c new file mode 100644 index 0000000000..5abb81ac0a --- /dev/null +++ b/src/soc/qualcomm/sc7180/spi.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +static const struct spi_ctrlr spi_ctrlr; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/sc7180/timer.c b/src/soc/qualcomm/sc7180/timer.c new file mode 100644 index 0000000000..5b78c1d047 --- /dev/null +++ b/src/soc/qualcomm/sc7180/timer.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void init_timer(void) +{ + raw_write_cntfrq_el0(19200*KHz); +} diff --git a/src/soc/qualcomm/sc7180/uart_bitbang.c b/src/soc/qualcomm/sc7180/uart_bitbang.c new file mode 100644 index 0000000000..fa0eac8fa7 --- /dev/null +++ b/src/soc/qualcomm/sc7180/uart_bitbang.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * Copyright 2019 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#define UART_TX_PIN GPIO(44) + +void uart_fill_lb(void *data) +{ + +} + +static void set_tx(int line_state) +{ + gpio_set(UART_TX_PIN, line_state); +} + +void uart_init(int idx) +{ + gpio_output(UART_TX_PIN, 1); +} + +void uart_tx_byte(int idx, unsigned char data) +{ + uart_bitbang_tx_byte(data, set_tx); +} + +void uart_tx_flush(int idx) +{ + /* unnecessary, PIO Tx means transaction is over when tx_byte returns */ +} + +unsigned char uart_rx_byte(int idx) +{ + return 0; /* not implemented */ +} diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc index c20be142b6..4449a69023 100644 --- a/src/soc/qualcomm/sdm845/Makefile.inc +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -33,7 +33,6 @@ romstage-y += mmu.c ################################################################################ ramstage-y += soc.c ramstage-y += spi.c -ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += clock.c @@ -48,8 +47,4 @@ ramstage-y += aop_load_reset.c CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include CPPFLAGS_common += -Isrc/soc/qualcomm/common/include -$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin - @printf "Generating: $(subst $(obj)/,,$(@))\n" - cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin - endif diff --git a/src/soc/qualcomm/sdm845/aop_load_reset.c b/src/soc/qualcomm/sdm845/aop_load_reset.c index 02217f9bd3..c1cf0579cc 100644 --- a/src/soc/qualcomm/sdm845/aop_load_reset.c +++ b/src/soc/qualcomm/sdm845/aop_load_reset.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c index 3b9ad4a617..b092a1a610 100644 --- a/src/soc/qualcomm/sdm845/cbmem.c +++ b/src/soc/qualcomm/sdm845/cbmem.c @@ -15,7 +15,7 @@ #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return (void *)((uintptr_t)4 * GiB); } diff --git a/src/soc/qualcomm/sdm845/qclib.c b/src/soc/qualcomm/sdm845/qclib.c index 9c05452c9e..ae7251a12c 100644 --- a/src/soc/qualcomm/sdm845/qclib.c +++ b/src/soc/qualcomm/sdm845/qclib.c @@ -15,7 +15,6 @@ #include #include -#include #include #include diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index 401f8b2a65..6e3aabb81c 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -19,7 +19,7 @@ #include #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, MAX_DRAM_ADDRESS); diff --git a/src/soc/rockchip/common/i2c.c b/src/soc/rockchip/common/i2c.c index cd0ed9b94f..953928ed92 100644 --- a/src/soc/rockchip/common/i2c.c +++ b/src/soc/rockchip/common/i2c.c @@ -231,7 +231,7 @@ static int i2c_do_xfer(void *reg_addr, struct i2c_msg segment) return i2c_send_stop(reg_addr) || res; } -int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, +int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int seg_count) { int i; diff --git a/src/soc/rockchip/common/include/soc/i2c.h b/src/soc/rockchip/common/include/soc/i2c.h index 4cdcbe04d1..56ad73256e 100644 --- a/src/soc/rockchip/common/include/soc/i2c.h +++ b/src/soc/rockchip/common/include/soc/i2c.h @@ -17,7 +17,7 @@ #define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_I2C_H void i2c_init(unsigned int bus, unsigned int hz); -void software_i2c_attach(unsigned bus); -void software_i2c_detach(unsigned bus); +void software_i2c_attach(unsigned int bus); +void software_i2c_detach(unsigned int bus); #endif /* ! __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_I2C_H */ diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index 7e4c5b48ad..e7982f7492 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -18,7 +18,6 @@ ifeq ($(CONFIG_SOC_ROCKCHIP_RK3288),y) IDBTOOL = util/rockchip/make_idb.py bootblock-y += bootblock.c -bootblock-y += ../common/cbmem.c bootblock-y += ../common/uart.c bootblock-y += timer.c bootblock-y += clock.c @@ -55,7 +54,6 @@ romstage-y += tsadc.c romstage-y += ../common/i2c.c ramstage-y += soc.c -ramstage-y += ../common/cbmem.c ramstage-y += timer.c ramstage-y += ../common/i2c.c ramstage-$(CONFIG_SOFTWARE_I2C) += software_i2c.c diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index cee1ee2b56..f025d30d4e 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -669,7 +669,7 @@ int rkclk_was_watchdog_reset(void) return read32(&cru_ptr->cru_glb_rst_st) & 0x30; } -unsigned rkclk_i2c_clock_for_bus(unsigned bus) +unsigned int rkclk_i2c_clock_for_bus(unsigned int bus) { /*i2c0,i2c2 src clk from pd_bus_pclk other i2c src clk from peri_pclk diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h index b3c6302b3a..40152d7e91 100644 --- a/src/soc/rockchip/rk3288/include/soc/clock.h +++ b/src/soc/rockchip/rk3288/include/soc/clock.h @@ -56,6 +56,6 @@ int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz); void rkclk_configure_edp(void); void rkclk_configure_hdmi(void); int rkclk_was_watchdog_reset(void); -unsigned rkclk_i2c_clock_for_bus(unsigned bus); +unsigned int rkclk_i2c_clock_for_bus(unsigned int bus); #endif /* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */ diff --git a/src/soc/rockchip/rk3288/software_i2c.c b/src/soc/rockchip/rk3288/software_i2c.c index ae1249ec52..8c439842c1 100644 --- a/src/soc/rockchip/rk3288/software_i2c.c +++ b/src/soc/rockchip/rk3288/software_i2c.c @@ -33,17 +33,17 @@ static struct { [5]{.scl = GPIO(7, C, 4), .sda = GPIO(7, C, 3)}, }; -static int get_scl(unsigned bus) +static int get_scl(unsigned int bus) { return gpio_get(pins[bus].scl); } -static int get_sda(unsigned bus) +static int get_sda(unsigned int bus) { return gpio_get(pins[bus].sda); } -static void set_scl(unsigned bus, int high) +static void set_scl(unsigned int bus, int high) { if (high) gpio_input_pullup(pins[bus].scl); @@ -51,7 +51,7 @@ static void set_scl(unsigned bus, int high) gpio_output(pins[bus].scl, 0); } -static void set_sda(unsigned bus, int high) +static void set_sda(unsigned int bus, int high) { if (high) gpio_input_pullup(pins[bus].sda); @@ -66,7 +66,7 @@ static struct software_i2c_ops rk_ops = { .set_sda = set_sda, }; -void software_i2c_attach(unsigned bus) +void software_i2c_attach(unsigned int bus) { software_i2c[bus] = &rk_ops; @@ -101,7 +101,7 @@ void software_i2c_attach(unsigned bus) set_sda(bus, 1); } -void software_i2c_detach(unsigned bus) +void software_i2c_detach(unsigned int bus) { software_i2c[bus] = NULL; diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 3b66247868..7f6ad8cac1 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -31,7 +31,6 @@ bootblock-y += gpio.c bootblock-y += saradc.c bootblock-y += timer.c -verstage-y += ../common/cbmem.c verstage-y += ../common/gpio.c verstage-y += gpio.c verstage-y += sdram.c @@ -59,7 +58,6 @@ romstage-y += ../common/i2c.c ################################################################################ -ramstage-y += ../common/cbmem.c ramstage-y += sdram.c ramstage-y += ../common/spi.c ramstage-y += ../common/uart.c diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 37a4c09012..e2aeaeaa7a 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -118,7 +118,7 @@ void rkclk_configure_tsadc(unsigned int hz); void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz); void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); int rkclk_was_watchdog_reset(void); -uint32_t rkclk_i2c_clock_for_bus(unsigned bus); +uint32_t rkclk_i2c_clock_for_bus(unsigned int bus); void rkclk_configure_edp(unsigned int hz); void rkclk_configure_mipi(void); diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc index a6eb9eea9b..6a595f4b82 100644 --- a/src/soc/samsung/exynos5250/Makefile.inc +++ b/src/soc/samsung/exynos5250/Makefile.inc @@ -40,7 +40,6 @@ ramstage-y += i2c.c ramstage-y += dp-reg.c ramstage-y += fb.c ramstage-y += usb.c -ramstage-y += cbmem.c CPPFLAGS_common += -Isrc/soc/samsung/exynos5250/include/ diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c index 1874495396..31463b19b5 100644 --- a/src/soc/samsung/exynos5250/cbmem.c +++ b/src/soc/samsung/exynos5250/cbmem.c @@ -17,7 +17,7 @@ #include #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return (void *)(get_fb_base_kb() * KiB); } diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c index 7e7fe97d18..efb0de31f3 100644 --- a/src/soc/samsung/exynos5250/clock.c +++ b/src/soc/samsung/exynos5250/clock.c @@ -385,10 +385,10 @@ void set_mmc_clk(int dev_index, unsigned int div) write32(addr, val); } -void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) +void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor) { - unsigned shift; - unsigned mask = 0xff; + unsigned int shift; + unsigned int mask = 0xff; u32 *reg; /* @@ -428,10 +428,10 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); } -void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor) +void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor) { - unsigned shift; - unsigned mask = 0xff; + unsigned int shift; + unsigned int mask = 0xff; u32 *reg; switch (periph_id) { diff --git a/src/soc/samsung/exynos5250/gpio.c b/src/soc/samsung/exynos5250/gpio.c index 96cfef6528..0ae2d2a87a 100644 --- a/src/soc/samsung/exynos5250/gpio.c +++ b/src/soc/samsung/exynos5250/gpio.c @@ -154,14 +154,14 @@ void gpio_set_rate(int gpio, int mode) write32(&bank->drv, value); } -int gpio_direction_input(unsigned gpio) +int gpio_direction_input(unsigned int gpio) { gpio_cfg_pin(gpio, GPIO_INPUT); return 0; } -int gpio_direction_output(unsigned gpio, int value) +int gpio_direction_output(unsigned int gpio, int value) { unsigned int val; struct gpio_bank *bank = gpio_get_bank(gpio); @@ -177,7 +177,7 @@ int gpio_direction_output(unsigned gpio, int value) return 0; } -int gpio_get_value(unsigned gpio) +int gpio_get_value(unsigned int gpio) { unsigned int value; struct gpio_bank *bank = gpio_get_bank(gpio); @@ -186,7 +186,7 @@ int gpio_get_value(unsigned gpio) return !!(value & DAT_MASK(GPIO_BIT(gpio))); } -int gpio_set_value(unsigned gpio, int value) +int gpio_set_value(unsigned int gpio, int value) { unsigned int val; struct gpio_bank *bank = gpio_get_bank(gpio); @@ -207,7 +207,7 @@ int gpio_set_value(unsigned gpio, int value) */ #define GPIO_DELAY_US 5 -int gpio_read_mvl3(unsigned gpio) +int gpio_read_mvl3(unsigned int gpio) { int high, low; enum mvl3 value; @@ -248,7 +248,7 @@ int gpio_read_mvl3(unsigned gpio) */ void gpio_info(void) { - unsigned gpio; + unsigned int gpio; for (gpio = 0; gpio < GPIO_MAX_PORT; gpio++) { int cfg = gpio_get_cfg(gpio); diff --git a/src/soc/samsung/exynos5250/i2c.c b/src/soc/samsung/exynos5250/i2c.c index 0efd25c62d..e9aabf81bf 100644 --- a/src/soc/samsung/exynos5250/i2c.c +++ b/src/soc/samsung/exynos5250/i2c.c @@ -233,7 +233,7 @@ static int i2c_recv_buf(struct i2c_regs *regs, uint8_t *data, int len) return 0; } -int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, +int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int seg_count) { struct s3c24x0_i2c_bus *i2c = &i2c_busses[bus]; @@ -263,7 +263,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, return i2c_send_stop(regs) || res; } -void i2c_init(unsigned bus, int speed, int slaveadd) +void i2c_init(unsigned int bus, int speed, int slaveadd) { struct s3c24x0_i2c_bus *i2c = &i2c_busses[bus]; diff --git a/src/soc/samsung/exynos5250/include/soc/clk.h b/src/soc/samsung/exynos5250/include/soc/clk.h index 971bfc291c..fab0444e11 100644 --- a/src/soc/samsung/exynos5250/include/soc/clk.h +++ b/src/soc/samsung/exynos5250/include/soc/clk.h @@ -561,7 +561,7 @@ struct st_epll_con_val { * @param periph_id Peripheral ID of peripheral to change * @param divisor New divisor for this peripheral's clock */ -void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor); +void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor); /** * Low-level function to set the clock ratio for a peripheral @@ -569,7 +569,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor); * @param periph_id Peripheral ID of peripheral to change * @param divisor New divisor for this peripheral's clock */ -void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor); +void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor); /** * Low-level function that selects the best clock scalars for a given rate and diff --git a/src/soc/samsung/exynos5250/include/soc/gpio.h b/src/soc/samsung/exynos5250/include/soc/gpio.h index 959fbd199d..a521bea791 100644 --- a/src/soc/samsung/exynos5250/include/soc/gpio.h +++ b/src/soc/samsung/exynos5250/include/soc/gpio.h @@ -482,7 +482,7 @@ void gpio_set_rate(int gpio, int mode); * @return -1 if the value cannot be determined. Otherwise returns * the corresponding MVL3 enum value. */ -int gpio_read_mvl3(unsigned gpio); +int gpio_read_mvl3(unsigned int gpio); void gpio_info(void); @@ -510,7 +510,7 @@ void gpio_info(void); * @param gpio GPIO number * @return 0 if ok, -1 on error */ -int gpio_direction_input(unsigned gpio); +int gpio_direction_input(unsigned int gpio); /** * Make a GPIO an output, and set its value. @@ -519,7 +519,7 @@ int gpio_direction_input(unsigned gpio); * @param value GPIO value (0 for low or 1 for high) * @return 0 if ok, -1 on error */ -int gpio_direction_output(unsigned gpio, int value); +int gpio_direction_output(unsigned int gpio, int value); /** * Get a GPIO's value. This will work whether the GPIO is an input @@ -528,7 +528,7 @@ int gpio_direction_output(unsigned gpio, int value); * @param gpio GPIO number * @return 0 if low, 1 if high, -1 on error */ -int gpio_get_value(unsigned gpio); +int gpio_get_value(unsigned int gpio); /** * Set an output GPIO's value. The GPIO must already be an output or @@ -538,7 +538,7 @@ int gpio_get_value(unsigned gpio); * @param value GPIO value (0 for low or 1 for high) * @return 0 if ok, -1 on error */ -int gpio_set_value(unsigned gpio, int value); +int gpio_set_value(unsigned int gpio, int value); /* * Many-value logic (3 states). This can be used for inputs whereby presence diff --git a/src/soc/samsung/exynos5250/include/soc/i2c.h b/src/soc/samsung/exynos5250/include/soc/i2c.h index d58237c039..aa458838c4 100644 --- a/src/soc/samsung/exynos5250/include/soc/i2c.h +++ b/src/soc/samsung/exynos5250/include/soc/i2c.h @@ -16,6 +16,6 @@ #ifndef CPU_SAMSUNG_EXYNOS5250_I2C_H #define CPU_SAMSUNG_EXYNOS5250_I2C_H -void i2c_init(unsigned bus, int speed, int slaveadd); +void i2c_init(unsigned int bus, int speed, int slaveadd); #endif /* CPU_SAMSUNG_EXYNOS5250_I2C_H */ diff --git a/src/soc/samsung/exynos5250/include/soc/tmu.h b/src/soc/samsung/exynos5250/include/soc/tmu.h index bd15a209a5..cb92c16e48 100644 --- a/src/soc/samsung/exynos5250/include/soc/tmu.h +++ b/src/soc/samsung/exynos5250/include/soc/tmu.h @@ -19,39 +19,39 @@ #define CPU_SAMSUNG_EXYNOS5250_TMU_H struct tmu_reg { - unsigned triminfo; - unsigned rsvd1; - unsigned rsvd2; - unsigned rsvd3; - unsigned rsvd4; - unsigned triminfo_control; - unsigned rsvd5; - unsigned rsvd6; - unsigned tmu_control; - unsigned rsvd7; - unsigned tmu_status; - unsigned sampling_internal; - unsigned counter_value0; - unsigned counter_value1; - unsigned rsvd8; - unsigned rsvd9; - unsigned current_temp; - unsigned rsvd10; - unsigned rsvd11; - unsigned rsvd12; - unsigned threshold_temp_rise; - unsigned threshold_temp_fall; - unsigned rsvd13; - unsigned rsvd14; - unsigned past_temp3_0; - unsigned past_temp7_4; - unsigned past_temp11_8; - unsigned past_temp15_12; - unsigned inten; - unsigned intstat; - unsigned intclear; - unsigned rsvd15; - unsigned emul_con; + unsigned int triminfo; + unsigned int rsvd1; + unsigned int rsvd2; + unsigned int rsvd3; + unsigned int rsvd4; + unsigned int triminfo_control; + unsigned int rsvd5; + unsigned int rsvd6; + unsigned int tmu_control; + unsigned int rsvd7; + unsigned int tmu_status; + unsigned int sampling_internal; + unsigned int counter_value0; + unsigned int counter_value1; + unsigned int rsvd8; + unsigned int rsvd9; + unsigned int current_temp; + unsigned int rsvd10; + unsigned int rsvd11; + unsigned int rsvd12; + unsigned int threshold_temp_rise; + unsigned int threshold_temp_fall; + unsigned int rsvd13; + unsigned int rsvd14; + unsigned int past_temp3_0; + unsigned int past_temp7_4; + unsigned int past_temp11_8; + unsigned int past_temp15_12; + unsigned int inten; + unsigned int intstat; + unsigned int intclear; + unsigned int rsvd15; + unsigned int emul_con; }; check_member(tmu_reg, emul_con, 0x80); @@ -93,7 +93,7 @@ struct tmu_data { /* TMU device specific details and status */ struct tmu_info { /* base Address for the TMU */ - unsigned tmu_base; + unsigned int tmu_base; /* mux Address for the TMU */ int tmu_mux; /* pre-defined values for calibration and thresholds */ diff --git a/src/soc/samsung/exynos5420/Makefile.inc b/src/soc/samsung/exynos5420/Makefile.inc index b41e9f96f3..dc25919ff6 100644 --- a/src/soc/samsung/exynos5420/Makefile.inc +++ b/src/soc/samsung/exynos5420/Makefile.inc @@ -40,7 +40,6 @@ ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += dp.c dp_lowlevel.c fimd.c ramstage-y += usb.c -ramstage-y += cbmem.c rmodules_$(ARCH-ROMSTAGE-y)-y += timer.c diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c index e1999e888e..ffed589ee1 100644 --- a/src/soc/samsung/exynos5420/cbmem.c +++ b/src/soc/samsung/exynos5420/cbmem.c @@ -17,7 +17,7 @@ #include #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return (void *)(get_fb_base_kb() * KiB); } diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index 720506c8d5..b578133ea4 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -350,10 +350,10 @@ int clock_set_dwmci(enum periph_id peripheral) return 0; } -void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) +void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor) { - unsigned shift; - unsigned mask = 0xff; + unsigned int shift; + unsigned int mask = 0xff; u32 *reg; /* @@ -393,10 +393,10 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); } -void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor) +void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor) { - unsigned shift; - unsigned mask = 0xf; + unsigned int shift; + unsigned int mask = 0xf; u32 *reg; switch (periph_id) { diff --git a/src/soc/samsung/exynos5420/gpio.c b/src/soc/samsung/exynos5420/gpio.c index 1462c2928c..97331a0222 100644 --- a/src/soc/samsung/exynos5420/gpio.c +++ b/src/soc/samsung/exynos5420/gpio.c @@ -154,14 +154,14 @@ void gpio_set_rate(int gpio, int mode) write32(&bank->drv, value); } -int gpio_direction_input(unsigned gpio) +int gpio_direction_input(unsigned int gpio) { gpio_cfg_pin(gpio, GPIO_INPUT); return 0; } -int gpio_direction_output(unsigned gpio, int value) +int gpio_direction_output(unsigned int gpio, int value) { unsigned int val; struct gpio_bank *bank = gpio_get_bank(gpio); @@ -177,7 +177,7 @@ int gpio_direction_output(unsigned gpio, int value) return 0; } -int gpio_get_value(unsigned gpio) +int gpio_get_value(unsigned int gpio) { unsigned int value; struct gpio_bank *bank = gpio_get_bank(gpio); @@ -186,7 +186,7 @@ int gpio_get_value(unsigned gpio) return !!(value & DAT_MASK(GPIO_BIT(gpio))); } -int gpio_set_value(unsigned gpio, int value) +int gpio_set_value(unsigned int gpio, int value) { unsigned int val; struct gpio_bank *bank = gpio_get_bank(gpio); @@ -207,7 +207,7 @@ int gpio_set_value(unsigned gpio, int value) */ #define GPIO_DELAY_US 15 -int gpio_read_mvl3(unsigned gpio) +int gpio_read_mvl3(unsigned int gpio) { int high, low; enum mvl3 value; @@ -248,7 +248,7 @@ int gpio_read_mvl3(unsigned gpio) */ void gpio_info(void) { - unsigned gpio; + unsigned int gpio; for (gpio = 0; gpio < GPIO_MAX_PORT; gpio++) { int cfg = gpio_get_cfg(gpio); diff --git a/src/soc/samsung/exynos5420/i2c.c b/src/soc/samsung/exynos5420/i2c.c index 00ad12f715..4dd9caa16a 100644 --- a/src/soc/samsung/exynos5420/i2c.c +++ b/src/soc/samsung/exynos5420/i2c.c @@ -82,8 +82,8 @@ struct i2c_bus struct hsi2c_regs *hsregs; int is_highspeed; /* High speed type, rather than I2C */ int id; - unsigned clk_cycle; - unsigned clk_div; + unsigned int clk_cycle; + unsigned int clk_div; }; @@ -255,7 +255,7 @@ enum { static int hsi2c_get_clk_details(struct i2c_bus *i2c, int *div, int *cycle, - unsigned op_clk) + unsigned int op_clk) { struct hsi2c_regs *regs = i2c->hsregs; unsigned long clkin = clock_get_periph_rate(i2c->periph_id); @@ -361,7 +361,7 @@ static void i2c_ch_init(struct i2c_bus *i2c, int speed) write32(®s->stat, I2cStatMasterXmit | I2cStatEnable); } -void i2c_init(unsigned bus, int speed, int slaveadd) +void i2c_init(unsigned int bus, int speed, int slaveadd) { struct i2c_bus *i2c = &i2c_busses[bus]; @@ -627,7 +627,7 @@ static int i2c_recv_buf(struct i2c_regs *regs, uint8_t *data, int len) return 0; } -int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, int count) +int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int count) { struct i2c_bus *i2c = &i2c_busses[bus]; if (i2c->is_highspeed) diff --git a/src/soc/samsung/exynos5420/include/soc/clk.h b/src/soc/samsung/exynos5420/include/soc/clk.h index 262d6fb969..08663ff307 100644 --- a/src/soc/samsung/exynos5420/include/soc/clk.h +++ b/src/soc/samsung/exynos5420/include/soc/clk.h @@ -697,7 +697,7 @@ struct st_epll_con_val { * @param periph_id Peripheral ID of peripheral to change * @param divisor New divisor for this peripheral's clock */ -void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor); +void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor); /** * Low-level function to set the clock ratio for a peripheral @@ -705,7 +705,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor); * @param periph_id Peripheral ID of peripheral to change * @param divisor New divisor for this peripheral's clock */ -void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor); +void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor); /** * Low-level function that selects the best clock scalars for a given rate and diff --git a/src/soc/samsung/exynos5420/include/soc/gpio.h b/src/soc/samsung/exynos5420/include/soc/gpio.h index 69ef046e13..6a40554003 100644 --- a/src/soc/samsung/exynos5420/include/soc/gpio.h +++ b/src/soc/samsung/exynos5420/include/soc/gpio.h @@ -465,7 +465,7 @@ void gpio_set_rate(int gpio, int mode); * @return -1 if the value cannot be determined. Otherwise returns * the corresponding MVL3 enum value. */ -int gpio_read_mvl3(unsigned gpio); +int gpio_read_mvl3(unsigned int gpio); void gpio_info(void); @@ -493,7 +493,7 @@ void gpio_info(void); * @param gpio GPIO number * @return 0 if ok, -1 on error */ -int gpio_direction_input(unsigned gpio); +int gpio_direction_input(unsigned int gpio); /** * Make a GPIO an output, and set its value. @@ -502,7 +502,7 @@ int gpio_direction_input(unsigned gpio); * @param value GPIO value (0 for low or 1 for high) * @return 0 if ok, -1 on error */ -int gpio_direction_output(unsigned gpio, int value); +int gpio_direction_output(unsigned int gpio, int value); /** * Get a GPIO's value. This will work whether the GPIO is an input @@ -511,7 +511,7 @@ int gpio_direction_output(unsigned gpio, int value); * @param gpio GPIO number * @return 0 if low, 1 if high, -1 on error */ -int gpio_get_value(unsigned gpio); +int gpio_get_value(unsigned int gpio); /** * Set an output GPIO's value. The GPIO must already be an output or @@ -521,7 +521,7 @@ int gpio_get_value(unsigned gpio); * @param value GPIO value (0 for low or 1 for high) * @return 0 if ok, -1 on error */ -int gpio_set_value(unsigned gpio, int value); +int gpio_set_value(unsigned int gpio, int value); /* * Many-value logic (3 states). This can be used for inputs whereby presence diff --git a/src/soc/samsung/exynos5420/include/soc/i2c.h b/src/soc/samsung/exynos5420/include/soc/i2c.h index dc894f56d8..ab936985fe 100644 --- a/src/soc/samsung/exynos5420/include/soc/i2c.h +++ b/src/soc/samsung/exynos5420/include/soc/i2c.h @@ -16,6 +16,6 @@ #ifndef CPU_SAMSUNG_EXYNOS5420_I2C_H #define CPU_SAMSUNG_EXYNOS5420_I2C_H -void i2c_init(unsigned bus, int speed, int slaveadd); +void i2c_init(unsigned int bus, int speed, int slaveadd); #endif /* CPU_SAMSUNG_EXYNOS5420_I2C_H */ diff --git a/src/soc/samsung/exynos5420/include/soc/tmu.h b/src/soc/samsung/exynos5420/include/soc/tmu.h index 9f75131af8..eade11f0ec 100644 --- a/src/soc/samsung/exynos5420/include/soc/tmu.h +++ b/src/soc/samsung/exynos5420/include/soc/tmu.h @@ -19,39 +19,39 @@ #define CPU_SAMSUNG_EXYNOS5420_TMU_H struct tmu_reg { - unsigned triminfo; - unsigned rsvd1; - unsigned rsvd2; - unsigned rsvd3; - unsigned rsvd4; - unsigned triminfo_control; - unsigned rsvd5; - unsigned rsvd6; - unsigned tmu_control; - unsigned rsvd7; - unsigned tmu_status; - unsigned sampling_internal; - unsigned counter_value0; - unsigned counter_value1; - unsigned rsvd8; - unsigned rsvd9; - unsigned current_temp; - unsigned rsvd10; - unsigned rsvd11; - unsigned rsvd12; - unsigned threshold_temp_rise; - unsigned threshold_temp_fall; - unsigned rsvd13; - unsigned rsvd14; - unsigned past_temp3_0; - unsigned past_temp7_4; - unsigned past_temp11_8; - unsigned past_temp15_12; - unsigned inten; - unsigned intstat; - unsigned intclear; - unsigned rsvd15; - unsigned emul_con; + unsigned int triminfo; + unsigned int rsvd1; + unsigned int rsvd2; + unsigned int rsvd3; + unsigned int rsvd4; + unsigned int triminfo_control; + unsigned int rsvd5; + unsigned int rsvd6; + unsigned int tmu_control; + unsigned int rsvd7; + unsigned int tmu_status; + unsigned int sampling_internal; + unsigned int counter_value0; + unsigned int counter_value1; + unsigned int rsvd8; + unsigned int rsvd9; + unsigned int current_temp; + unsigned int rsvd10; + unsigned int rsvd11; + unsigned int rsvd12; + unsigned int threshold_temp_rise; + unsigned int threshold_temp_fall; + unsigned int rsvd13; + unsigned int rsvd14; + unsigned int past_temp3_0; + unsigned int past_temp7_4; + unsigned int past_temp11_8; + unsigned int past_temp15_12; + unsigned int inten; + unsigned int intstat; + unsigned int intclear; + unsigned int rsvd15; + unsigned int emul_con; }; check_member(tmu_reg, emul_con, 0x80); @@ -93,7 +93,7 @@ struct tmu_data { /* TMU device specific details and status */ struct tmu_info { /* base Address for the TMU */ - unsigned tmu_base; + unsigned int tmu_base; /* mux Address for the TMU */ int tmu_mux; /* pre-defined values for calibration and thresholds */ diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index 1c68de894b..a7de16c56a 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -19,7 +19,7 @@ #include #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, FU540_MAXDRAM); diff --git a/src/soc/sifive/fu540/otp.c b/src/soc/sifive/fu540/otp.c index dfdd960403..10647f4a1a 100644 --- a/src/soc/sifive/fu540/otp.c +++ b/src/soc/sifive/fu540/otp.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c index 6bf1700767..5e30e77939 100644 --- a/src/soc/sifive/fu540/spi.c +++ b/src/soc/sifive/fu540/spi.c @@ -61,6 +61,25 @@ static uint8_t spi_rx(volatile struct spi_ctrl *spictrl) return (uint8_t) out; } +static int spi_claim_bus_(const struct spi_slave *slave) +{ + struct spi_ctrl *spictrl = spictrls[slave->bus]; + spi_reg_csmode csmode; + csmode.raw_bits = 0; + csmode.mode = FU540_SPI_CSMODE_HOLD; + write32(&spictrl->csmode.raw_bits, csmode.raw_bits); + return 0; +} + +static void spi_release_bus_(const struct spi_slave *slave) +{ + struct spi_ctrl *spictrl = spictrls[slave->bus]; + spi_reg_csmode csmode; + csmode.raw_bits = 0; + csmode.mode = FU540_SPI_CSMODE_OFF; + write32(&spictrl->csmode.raw_bits, csmode.raw_bits); +} + static int spi_xfer_(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) @@ -126,6 +145,8 @@ static int spi_setup_(const struct spi_slave *slave) sckmode.pol = FU540_SPI_POL_LEADING; write32(&spictrl->sckmode.raw_bits, sckmode.raw_bits); + write32(&spictrl->csdef, 0xffffffff); + csmode.raw_bits = 0; csmode.mode = FU540_SPI_CSMODE_AUTO; write32(&spictrl->csmode.raw_bits, csmode.raw_bits); @@ -133,7 +154,7 @@ static int spi_setup_(const struct spi_slave *slave) fmt.raw_bits = 0; fmt.proto = FU540_SPI_PROTO_S; fmt.endian = FU540_SPI_ENDIAN_BIG; - fmt.dir = 1; + fmt.dir = 0; fmt.len = 8; write32(&spictrl->fmt.raw_bits, fmt.raw_bits); @@ -143,6 +164,8 @@ static int spi_setup_(const struct spi_slave *slave) struct spi_ctrlr fu540_spi_ctrlr = { .xfer = spi_xfer_, .setup = spi_setup_, + .claim_bus = spi_claim_bus_, + .release_bus = spi_release_bus_, }; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { @@ -187,6 +210,8 @@ int fu540_spi_setup(unsigned int bus, unsigned int cs, sckmode.pol = config->pol; write32(&spictrl->sckmode.raw_bits, sckmode.raw_bits); + write32(&spictrl->csdef, 0xffffffff); + csmode.raw_bits = 0; csmode.mode = FU540_SPI_CSMODE_AUTO; write32(&spictrl->csmode.raw_bits, csmode.raw_bits); @@ -194,7 +219,7 @@ int fu540_spi_setup(unsigned int bus, unsigned int cs, fmt.raw_bits = 0; fmt.proto = config->protocol; fmt.endian = config->endianness; - fmt.dir = 1; + fmt.dir = 0; fmt.len = config->bits_per_frame; write32(&spictrl->fmt.raw_bits, fmt.raw_bits); diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 542e08d05e..143e11b88c 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -15,7 +15,7 @@ #include #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 9b18315c5a..4cfbb6487e 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -347,7 +347,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &lops_pci, .acpi_name = lpc_acpi_name, }; diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index b5739f9e39..07646c862c 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -19,7 +19,7 @@ #include #include #include -#include + #include "hudson.h" #include "smbus.c" diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index ab48833247..a735ff9bf9 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -100,7 +100,7 @@ static int lsmbus_block_write(struct device *dev, uint8_t cmd, u8 bytes, #if CONFIG(HAVE_ACPI_TABLES) -unsigned pm_base; +unsigned int pm_base; #endif static void acpi_init(struct device *dev) diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c index cbf0d30859..0180f45653 100644 --- a/src/southbridge/amd/amd8111/amd8111.c +++ b/src/southbridge/amd/amd8111/amd8111.c @@ -21,15 +21,15 @@ void amd8111_enable(struct device *dev) { struct device *lpc_dev; struct device *bus_dev; - unsigned index; - unsigned reg_old, reg; + unsigned int index; + unsigned int reg_old, reg; /* See if we are on the bus behind the amd8111 pci bridge */ bus_dev = dev->bus->dev; if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) && (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) { - unsigned devfn; + unsigned int devfn; devfn = bus_dev->path.pci.devfn + (1 << 3); lpc_dev = pcidev_path_behind(bus_dev->bus, devfn); index = ((dev->path.pci.devfn & ~7) >> 3) + 8; @@ -37,7 +37,7 @@ void amd8111_enable(struct device *dev) index = 16; } } else { - unsigned devfn; + unsigned int devfn; devfn = (dev->path.pci.devfn) & ~7; lpc_dev = pcidev_path_behind(dev->bus, devfn); index = dev->path.pci.devfn & 7; diff --git a/src/southbridge/amd/amd8111/amd8111.h b/src/southbridge/amd/amd8111/amd8111.h index 447edf9b4c..fc57936908 100644 --- a/src/southbridge/amd/amd8111/amd8111.h +++ b/src/southbridge/amd/amd8111/amd8111.h @@ -17,6 +17,6 @@ #include void amd8111_enable(struct device *dev); -void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); +void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn); #endif /* AMD8111_H */ diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h index 738696509a..894fcd0a61 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ b/src/southbridge/amd/amd8111/amd8111_smbus.h @@ -29,7 +29,7 @@ static inline void smbus_delay(void) outb(0x80, 0x80); } -static int smbus_wait_until_ready(unsigned smbus_io_base) +static int smbus_wait_until_ready(unsigned int smbus_io_base) { unsigned long loops; loops = SMBUS_TIMEOUT; @@ -48,7 +48,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base) return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; } -static int smbus_wait_until_done(unsigned smbus_io_base) +static int smbus_wait_until_done(unsigned int smbus_io_base) { unsigned long loops; loops = SMBUS_TIMEOUT; @@ -64,10 +64,10 @@ static int smbus_wait_until_done(unsigned smbus_io_base) return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT; } -static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned int device) +static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device) { - unsigned global_status_register; - unsigned byte; + unsigned int global_status_register; + unsigned int byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; @@ -110,10 +110,10 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned int device) return byte; } -static int do_smbus_send_byte(unsigned smbus_io_base, unsigned int device, - unsigned value) +static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device, + unsigned int value) { - unsigned global_status_register; + unsigned int global_status_register; if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; @@ -153,11 +153,11 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned int device, } -static int do_smbus_read_byte(unsigned smbus_io_base, unsigned int device, +static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address) { - unsigned global_status_register; - unsigned byte; + unsigned int global_status_register; + unsigned int byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; @@ -200,10 +200,10 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned int device, return byte; } -static int do_smbus_write_byte(unsigned smbus_io_base, unsigned int device, +static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address, unsigned char val) { - unsigned global_status_register; + unsigned int global_status_register; if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; @@ -239,11 +239,11 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned int device, return 0; } -static int do_smbus_block_read(unsigned smbus_io_base, unsigned int device, - unsigned cmd, u8 bytes, u8 *buf) +static int do_smbus_block_read(unsigned int smbus_io_base, unsigned int device, + unsigned int cmd, u8 bytes, u8 *buf) { - unsigned global_status_register; - unsigned i; + unsigned int global_status_register; + unsigned int i; u8 msglen; if (smbus_wait_until_ready(smbus_io_base) < 0) { @@ -296,11 +296,11 @@ static int do_smbus_block_read(unsigned smbus_io_base, unsigned int device, return i; } -static int do_smbus_block_write(unsigned smbus_io_base, unsigned int device, - unsigned cmd, u8 bytes, const u8 *buf) +static int do_smbus_block_write(unsigned int smbus_io_base, unsigned int device, + unsigned int cmd, u8 bytes, const u8 *buf) { - unsigned global_status_register; - unsigned i; + unsigned int global_status_register; + unsigned int i; if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c index 8b12d83499..e9676ebc08 100644 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ b/src/southbridge/amd/amd8111/early_ctrl.c @@ -19,7 +19,7 @@ #include #include "amd8111.h" -unsigned get_sbdn(unsigned bus) +unsigned int get_sbdn(unsigned int bus) { pci_devfn_t dev; @@ -34,7 +34,7 @@ unsigned get_sbdn(unsigned bus) } -static void enable_cf9_x(unsigned sbbusn, unsigned sbdn) +static void enable_cf9_x(unsigned int sbbusn, unsigned int sbdn) { pci_devfn_t dev; uint8_t byte; @@ -48,9 +48,9 @@ static void enable_cf9_x(unsigned sbbusn, unsigned sbdn) static void enable_cf9(void) { - unsigned sblk = get_sblk(); - unsigned sbbusn = get_sbbusn(sblk); - unsigned sbdn = get_sbdn(sbbusn); + unsigned int sblk = get_sblk(); + unsigned int sbbusn = get_sbbusn(sblk); + unsigned int sbdn = get_sbdn(sbbusn); enable_cf9_x(sbbusn, sbdn); } @@ -63,7 +63,7 @@ void do_board_reset(void) outb(0x0e, 0x0cf9); // make sure cf9 is enabled } -void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn) { pci_devfn_t dev; @@ -76,7 +76,7 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) } -static void soft_reset_x(unsigned sbbusn, unsigned sbdn) +static void soft_reset_x(unsigned int sbbusn, unsigned int sbdn) { pci_devfn_t dev; @@ -91,9 +91,9 @@ static void soft_reset_x(unsigned sbbusn, unsigned sbdn) void do_soft_reset(void) { - unsigned sblk = get_sblk(); - unsigned sbbusn = get_sbbusn(sblk); - unsigned sbdn = get_sbdn(sbbusn); + unsigned int sblk = get_sblk(); + unsigned int sbbusn = get_sbbusn(sblk); + unsigned int sbdn = get_sbdn(sbbusn); return soft_reset_x(sbbusn, sbdn); diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c index cabb31b52b..c82190223d 100644 --- a/src/southbridge/amd/amd8111/early_smbus.c +++ b/src/southbridge/amd/amd8111/early_smbus.c @@ -64,13 +64,13 @@ static inline int smbus_write_byte(unsigned int device, unsigned int address, return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); } -static inline int smbus_block_read(unsigned int device, unsigned cmd, u8 bytes, +static inline int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) { return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); } -static inline int smbus_block_write(unsigned int device, unsigned cmd, u8 bytes, +static inline int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf) { return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index c4a7896ca7..b4a92a0f03 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -164,7 +164,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .enable = amd8111_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index f4907c53da..b175be2727 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -21,7 +21,7 @@ #define PCI_DEV_INVALID (0xffffffffU) -static pci_devfn_t pci_io_locate_device_on_bus(unsigned pci_id, unsigned bus) +static pci_devfn_t pci_io_locate_device_on_bus(unsigned int pci_id, unsigned int bus) { pci_devfn_t dev, last; dev = PCI_DEV(bus, 0, 0); @@ -41,9 +41,9 @@ static pci_devfn_t pci_io_locate_device_on_bus(unsigned pci_id, unsigned bus) void do_board_reset(void) { pci_devfn_t dev; - unsigned bus; - unsigned node = 0; - unsigned link = get_sblk(); + unsigned int bus; + unsigned int node = 0; + unsigned int link = get_sblk(); /* Find the device. * There can only be one 8111 on a hypertransport chain/bus. diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c index 527a736f5f..1088dda79c 100644 --- a/src/southbridge/amd/amd8132/bridge.c +++ b/src/southbridge/amd/amd8132/bridge.c @@ -43,8 +43,8 @@ static void amd8132_walk_children(struct bus *bus, } struct amd8132_bus_info { - unsigned sstatus; - unsigned rev; + unsigned int sstatus; + unsigned int rev; int master_devices; int max_func; }; @@ -65,9 +65,9 @@ static void amd8132_count_dev(struct device *dev, void *ptr) static void amd8132_pcix_tune_dev(struct device *dev, void *ptr) { struct amd8132_bus_info *info = ptr; - unsigned cap; - unsigned status, cmd, orig_cmd; - unsigned max_read, max_tran; + unsigned int cap; + unsigned int status, cmd, orig_cmd; + unsigned int max_read, max_tran; int sibs; if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) { @@ -133,10 +133,10 @@ static void amd8132_pcix_tune_dev(struct device *dev, void *ptr) } static void amd8132_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn) + unsigned int min_devfn, unsigned int max_devfn) { struct amd8132_bus_info info; - unsigned pos; + unsigned int pos; /* Find the children on the bus */ pci_scan_bus(bus, min_devfn, max_devfn); @@ -162,7 +162,7 @@ static void amd8132_scan_bus(struct bus *bus, */ if (!bus->children) { - unsigned pcix_misc; + unsigned int pcix_misc; /* Disable all of my children */ disable_children(bus); @@ -198,7 +198,7 @@ static void amd8132_pcix_init(struct device *dev) { uint32_t dword; uint8_t byte; - unsigned chip_rev; + unsigned int chip_rev; /* Find the revision of the 8132 */ chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION); @@ -368,7 +368,7 @@ static void ioapic_enable(struct device *dev) static void amd8132_ioapic_init(struct device *dev) { uint32_t dword; - unsigned chip_rev; + unsigned int chip_rev; /* Find the revision of the 8132 */ chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION); diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 7d93c81dd8..48829578e1 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -14,7 +14,6 @@ */ #include -#include #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 1e1cfe0537..4233a6ff0d 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -167,7 +167,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &lops_pci, .acpi_name = lpc_acpi_name, }; diff --git a/src/southbridge/amd/cimx/sb800/smbus_spd.c b/src/southbridge/amd/cimx/sb800/smbus_spd.c index a6881bbe1e..a574072388 100644 --- a/src/southbridge/amd/cimx/sb800/smbus_spd.c +++ b/src/southbridge/amd/cimx/sb800/smbus_spd.c @@ -15,7 +15,7 @@ #include #include -#include +#include #include /* SMBUS0_BASE_ADDRESS */ /* warning: Porting.h includes an open #pragma pack(1) */ diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index ffda0a8ea4..fcb4fa1111 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -12,8 +12,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include -#include + #include #include #include @@ -21,6 +20,7 @@ #include #include #include +#include #include "SBPLATFORM.h" #include diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index 1aa9a5a4ba..ccada12dc3 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -17,7 +17,6 @@ #define __SIMPLE_DEVICE__ #include -#include #include #include "SbPlatform.h" #include "sb_cimx.h" diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index fc321f8b6b..3a65e33804 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -116,7 +116,7 @@ static struct device_operations lpc_ops = { #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index bdda5edbcc..f12cec8602 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -15,7 +15,6 @@ #include #include -#include /* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 02123a10b2..1e080a0e8e 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -363,7 +363,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &lops_pci, .acpi_name = lpc_acpi_name, }; diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 58f5113fa5..7ecb8df2ab 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -19,7 +19,7 @@ #include #include #include -#include + #include "hudson.h" #include "smbus.c" diff --git a/src/southbridge/amd/sb700/fadt.c b/src/southbridge/amd/sb700/fadt.c index 4a5746ccd7..c81e644aa7 100644 --- a/src/southbridge/amd/sb700/fadt.c +++ b/src/southbridge/amd/sb700/fadt.c @@ -36,7 +36,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) /* Prepare the header */ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); - header->length = 244; + header->length = sizeof(acpi_fadt_t); header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index eb171e605a..5d6d1cd85a 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -282,7 +282,7 @@ static struct device_operations lpc_ops = { .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 66316828ba..535e5e4135 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -24,7 +24,7 @@ #include #include #include -#include + #include "sb700.h" #include "smbus.h" diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c index ee031e927f..f772f755ba 100644 --- a/src/southbridge/amd/sb700/spi.c +++ b/src/southbridge/amd/sb700/spi.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include -#include #include #include #include @@ -23,6 +21,7 @@ #include #include #include +#include #define AMD_SB_SPI_TX_LEN 8 diff --git a/src/southbridge/amd/sb800/fadt.c b/src/southbridge/amd/sb800/fadt.c index 71bdf2313b..acda6dbd52 100644 --- a/src/southbridge/amd/sb800/fadt.c +++ b/src/southbridge/amd/sb800/fadt.c @@ -36,7 +36,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) /* Prepare the header */ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); - header->length = 244; + header->length = sizeof(acpi_fadt_t); header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 580138a470..0ca50cce74 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -251,7 +251,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c index 1d2daed81c..e1cf05ce09 100644 --- a/src/southbridge/amd/sb800/sm.c +++ b/src/southbridge/amd/sb800/sm.c @@ -23,7 +23,7 @@ #include #include #include -#include + #include "sb800.h" #include "smbus.c" diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index 50d13b030b..ea77359257 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -31,21 +31,21 @@ void bcm5785_enable(struct device *dev) if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && (bus_dev->device == 0x0036)) // device under PCI-X Bridge { - unsigned devfn; + unsigned int devfn; devfn = bus_dev->path.pci.devfn + (1 << 3); sb_pci_main_dev = pcidev_path_behind(bus_dev->bus, devfn); // index = ((dev->path.pci.devfn & ~7) >> 3) + 8; } else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && (bus_dev->device == 0x0104)) // device under PCI Bridge (under PCI-X) { - unsigned devfn; + unsigned int devfn; devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3); sb_pci_main_dev = pcidev_path_behind(bus_dev->bus->dev->bus, devfn); // index = ((dev->path.pci.devfn & ~7) >> 3) + 8; } else { // same bus - unsigned devfn; + unsigned int devfn; devfn = (dev->path.pci.devfn) & ~7; if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS) { if (dev->device == 0x0036) //PCI-X Bridge @@ -62,7 +62,7 @@ void bcm5785_enable(struct device *dev) // get index now #if 0 - unsigned reg_old, reg; + unsigned int reg_old, reg; if (index < 16) { reg = reg_old = pci_read_config16(sb_pci_main_dev, 0x48); reg &= ~(1 << index); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h index e1c6f66191..db723dd8b3 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.h +++ b/src/southbridge/broadcom/bcm5785/bcm5785.h @@ -21,7 +21,7 @@ #include "chip.h" void bcm5785_enable(struct device *dev); -void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); +void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn); void bcm5785_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device); diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 8ea776f76e..b4d623b98c 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -64,7 +64,7 @@ static void bcm5785_enable_wdt_port_cf9(void) pci_write_config8(dev, 0x40, 1 << 2); } -unsigned get_sbdn(unsigned bus) +unsigned int get_sbdn(unsigned int bus) { pci_devfn_t dev; @@ -81,7 +81,7 @@ unsigned get_sbdn(unsigned bus) #define SB_VFSMAF 0 -void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn) { //ACPI Decode Enable outb(0x0e, 0xcd6); diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index 5aa6ee2ad1..05e401dae1 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -40,22 +40,22 @@ static void enable_smbus(void) outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); } -static inline int smbus_recv_byte(unsigned device) +static inline int smbus_recv_byte(unsigned int device) { return do_smbus_recv_byte(SMBUS_IO_BASE, device); } -static inline int smbus_send_byte(unsigned device, unsigned char val) +static inline int smbus_send_byte(unsigned int device, unsigned char val) { return do_smbus_send_byte(SMBUS_IO_BASE, device, val); } -static inline int smbus_read_byte(unsigned device, unsigned address) +static inline int smbus_read_byte(unsigned int device, unsigned int address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val) +static inline int smbus_write_byte(unsigned int device, unsigned int address, unsigned char val) { return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); } diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index 17bc8bce88..5ac15e0fd0 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -124,7 +124,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = bcm5785_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, // .enable = bcm5785_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index 318086e7bf..837ce42b4b 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -72,7 +72,7 @@ static void bcm5785_sb_read_resources(struct device *dev) static int lsmbus_recv_byte(struct device *dev) { - unsigned device; + unsigned int device; struct resource *res; struct bus *pbus; @@ -86,7 +86,7 @@ static int lsmbus_recv_byte(struct device *dev) static int lsmbus_send_byte(struct device *dev, uint8_t val) { - unsigned device; + unsigned int device; struct resource *res; struct bus *pbus; @@ -100,7 +100,7 @@ static int lsmbus_send_byte(struct device *dev, uint8_t val) static int lsmbus_read_byte(struct device *dev, uint8_t address) { - unsigned device; + unsigned int device; struct resource *res; struct bus *pbus; @@ -114,7 +114,7 @@ static int lsmbus_read_byte(struct device *dev, uint8_t address) static int lsmbus_write_byte(struct device *dev, uint8_t address, uint8_t val) { - unsigned device; + unsigned int device; struct resource *res; struct bus *pbus; diff --git a/src/southbridge/broadcom/bcm5785/smbus.h b/src/southbridge/broadcom/bcm5785/smbus.h index 657d97d858..40ed774b72 100644 --- a/src/southbridge/broadcom/bcm5785/smbus.h +++ b/src/southbridge/broadcom/bcm5785/smbus.h @@ -42,7 +42,7 @@ static inline void smbus_delay(void) outb(0x80, 0x80); } -static int smbus_wait_until_ready(unsigned smbus_io_base) +static int smbus_wait_until_ready(unsigned int smbus_io_base) { unsigned long loops; loops = SMBUS_TIMEOUT; @@ -58,7 +58,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base) return -2; // time out } -static int smbus_wait_until_done(unsigned smbus_io_base) +static int smbus_wait_until_done(unsigned int smbus_io_base) { unsigned long loops; loops = SMBUS_TIMEOUT; @@ -78,7 +78,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base) return -3; // timeout } -static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) +static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device) { uint8_t byte; @@ -105,7 +105,7 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) return byte; } -static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) +static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device, unsigned char val) { uint8_t byte; @@ -132,7 +132,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned return 0; } -static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) +static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address) { uint8_t byte; @@ -162,7 +162,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned return byte; } -static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) +static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address, unsigned char val) { uint8_t byte; diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index fc3e9fcadb..f5b8b36a35 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -30,6 +30,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_PMCLIB + select SOUTHBRIDGE_INTEL_COMMON_PMBASE select IOAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/bd82x6x/acpi/lpc.asl b/src/southbridge/intel/bd82x6x/acpi/lpc.asl index 5204b29d48..06c9ada15b 100644 --- a/src/southbridge/intel/bd82x6x/acpi/lpc.asl +++ b/src/southbridge/intel/bd82x6x/acpi/lpc.asl @@ -97,7 +97,7 @@ Device (LPCB) Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -120,15 +120,15 @@ Device (LPCB) If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) } If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) } If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } } diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 20182192f2..8dae5fff2a 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -251,7 +251,7 @@ Scope(\) #include "sata.asl" // SMBus 0:1f.3 -#include "smbus.asl" +#include Method (_OSC, 4) { diff --git a/src/southbridge/intel/bd82x6x/acpi/platform.asl b/src/southbridge/intel/bd82x6x/acpi/platform.asl deleted file mode 100644 index e37066887b..0000000000 --- a/src/southbridge/intel/bd82x6x/acpi/platform.asl +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} diff --git a/src/southbridge/intel/bd82x6x/acpi/sleepstates.asl b/src/southbridge/intel/bd82x6x/acpi/sleepstates.asl deleted file mode 100644 index 4d1d0b3ea2..0000000000 --- a/src/southbridge/intel/bd82x6x/acpi/sleepstates.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -// Name(\_S1, Package(){0x1,0x1,0x0,0x0}) -Name(\_S3, Package(){0x5,0x5,0x0,0x0}) -Name(\_S4, Package(){0x6,0x6,0x0,0x0}) -Name(\_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 73fce3bf9f..d8fd7ad6a5 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -21,7 +21,6 @@ #include #include #include -#include /* For DMI bar. */ #include @@ -254,8 +253,22 @@ static void pch_generic_setup(void) write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ } -static void pch_enable_lpc_gen_decode(void) +static void pch_enable_lpc_decode(void) { + /* + * Enable some common LPC IO ranges: + * - 0x2e/0x2f, 0x4e/0x4f often SuperIO + * - 0x60/0x64, 0x62/0x66 often KBC/EC + * - 0x3f0-0x3f5/0x3f7 FDD + * - 0x378-0x37f and 0x778-0x77f LPT + * - 0x2f8-0x2ff COMB + * - 0x3f8-0x3ff COMA + */ + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + | MC_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + const struct device *dev = pcidev_on_root(0x1f, 0); const struct southbridge_intel_bd82x6x_config *config = NULL; @@ -275,9 +288,10 @@ static void pch_enable_lpc_gen_decode(void) void early_pch_init(void) { - pch_enable_lpc(); - pch_enable_lpc_gen_decode(); + pch_enable_lpc_decode(); + + pch_enable_lpc(); pch_enable_bars(); diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index d3847a5018..f5700401be 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -51,7 +51,7 @@ void enable_smbus(void) printk(BIOS_DEBUG, "SMBus controller enabled.\n"); } -int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(unsigned int device, unsigned int address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index b8df7aad10..5f0dd8c299 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -460,18 +460,6 @@ static void pch_fixups(struct device *dev) RCBA32_OR(LCTL, 0x3); } -static void pch_decode_init(struct device *dev) -{ - config_t *config = dev->chip_info; - - printk(BIOS_DEBUG, "pch_decode_init\n"); - - pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec); -} - static void pch_spi_init(const struct device *const dev) { const config_t *const config = dev->chip_info; @@ -681,12 +669,6 @@ static void pch_lpc_read_resources(struct device *dev) } } -static void pch_lpc_enable_resources(struct device *dev) -{ - pch_decode_init(dev); - return pci_dev_enable_resources(dev); -} - static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ @@ -910,7 +892,7 @@ static struct pci_operations pci_ops = { static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pch_lpc_enable_resources, + .enable_resources = pci_dev_enable_resources, .write_acpi_tables = acpi_write_hpet, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .acpi_fill_ssdt_generator = southbridge_fill_ssdt, @@ -918,7 +900,7 @@ static struct device_operations device_ops = { .init = lpc_init, .final = lpc_final, .enable = pch_lpc_enable, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 1670091055..ea60085624 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -154,7 +154,7 @@ static inline u32 read_cb(void) static int mei_wait_for_me_ready(void) { struct mei_csr me; - unsigned try = ME_RETRY; + unsigned int try = ME_RETRY; while (try--) { read_me_csr(&me); @@ -195,7 +195,7 @@ static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, void *req_data) { struct mei_csr host; - unsigned ndata, n; + unsigned int ndata, n; u32 *data; /* Number of dwords to write, ignoring MKHI */ @@ -260,8 +260,8 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, struct mei_header mei_rsp; struct mkhi_header mkhi_rsp; struct mei_csr me, host; - unsigned ndata, n; - unsigned expected; + unsigned int ndata, n; + unsigned int expected; u32 *data; /* Total number of dwords to read from circular buffer */ diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 954353698d..54c3fff05c 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -156,7 +156,7 @@ static inline u32 read_cb(void) static int mei_wait_for_me_ready(void) { struct mei_csr me; - unsigned try = ME_RETRY; + unsigned int try = ME_RETRY; while (try--) { read_me_csr(&me); @@ -197,7 +197,7 @@ static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, void *req_data) { struct mei_csr host; - unsigned ndata, n; + unsigned int ndata, n; u32 *data; /* Number of dwords to write, ignoring MKHI */ @@ -262,8 +262,8 @@ static int mei_recv_msg(struct mkhi_header *mkhi, struct mei_header mei_rsp; struct mkhi_header mkhi_rsp; struct mei_csr me, host; - unsigned ndata, n/*, me_data_len*/; - unsigned expected; + unsigned int ndata, n/*, me_data_len*/; + unsigned int expected; u32 *data; /* Total number of dwords to read from circular buffer */ diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 475def33e4..de7fc36ef6 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -87,7 +87,7 @@ int pch_silicon_supported(int type, int rev) #define IOBP_RETRY 1000 static inline int iobp_poll(void) { - unsigned try = IOBP_RETRY; + unsigned int try = IOBP_RETRY; u32 data; while (try--) { @@ -147,7 +147,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) #ifndef __SMM__ /* Set bit in function disable register to hide this device */ -static void pch_hide_devfn(unsigned devfn) +static void pch_hide_devfn(unsigned int devfn) { switch (devfn) { case PCI_DEVFN(20, 0): /* xHCI */ diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 22b91073ce..ac976c2982 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -66,7 +66,7 @@ void enable_smbus(void); void enable_usb_bar(void); #if ENV_ROMSTAGE -int smbus_read_byte(unsigned device, unsigned address); +int smbus_read_byte(unsigned int device, unsigned int address); #endif void early_thermal_init(void); diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 2c2f9d97e9..98a4bdbe60 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -74,8 +74,8 @@ static void usb_ehci_init(struct device *dev) printk(BIOS_DEBUG, "done.\n"); } -static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { u8 access_cntl; diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 31039b68b4..c5aaa80f8c 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -9,6 +9,11 @@ config SOUTHBRIDGE_INTEL_COMMON_RESET config SOUTHBRIDGE_INTEL_COMMON_PMCLIB def_bool n depends on SOUTHBRIDGE_INTEL_COMMON + depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE + +config SOUTHBRIDGE_INTEL_COMMON_PMBASE + def_bool n + depends on SOUTHBRIDGE_INTEL_COMMON config SOUTHBRIDGE_INTEL_COMMON_GPIO def_bool n @@ -36,6 +41,7 @@ config SOUTHBRIDGE_INTEL_COMMON_SMM def_bool n select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select SOUTHBRIDGE_INTEL_COMMON_PMBASE config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT bool @@ -78,6 +84,7 @@ config INTEL_CHIPSET_LOCKDOWN config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG bool depends on SOUTHBRIDGE_INTEL_COMMON + depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE if SOUTHBRIDGE_INTEL_COMMON_FINALIZE diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index deab85ff97..5ca7daf8a5 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -16,11 +16,7 @@ # CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build. subdirs-y += firmware -verstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c -bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c -ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c -postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c @@ -31,11 +27,8 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG) += watchdog.c ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) -verstage-y += pmbase.c -romstage-y += pmbase.c -ramstage-y += pmbase.c -postcar-y += pmbase.c -smm-y += pmbase.c +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c +smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c bootblock-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c @@ -45,10 +38,7 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c -bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c -postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c -ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c ifeq ($(CONFIG_SPI_FLASH_SMM),y) smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c endif @@ -63,10 +53,6 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c -verstage-y += rtc.c -romstage-y += rtc.c -ramstage-y += rtc.c -postcar-y += rtc.c -smm-y += rtc.c +all-y += rtc.c endif diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl index ba8091d73b..03cb625ce6 100644 --- a/src/southbridge/intel/common/acpi/platform.asl +++ b/src/southbridge/intel/common/acpi/platform.asl @@ -71,16 +71,6 @@ Method(GOS, 0) Store (2000, OSYS) If (CondRefOf(_OSI)) { - /* Linux answers _OSI with "True" for a couple of - * Windows version queries. But unlike Windows it - * needs a Video repost, so let's determine whether - * we're running Linux. - */ - - If (_OSI("Linux")) { - Store (1, LINX) - } - If (_OSI("Windows 2001")) { Store (2001, OSYS) } diff --git a/src/southbridge/intel/i82801ix/acpi/sleepstates.asl b/src/southbridge/intel/common/acpi/sleepstates.asl similarity index 100% rename from src/southbridge/intel/i82801ix/acpi/sleepstates.asl rename to src/southbridge/intel/common/acpi/sleepstates.asl diff --git a/src/southbridge/intel/bd82x6x/acpi/smbus.asl b/src/southbridge/intel/common/acpi/smbus.asl similarity index 100% rename from src/southbridge/intel/bd82x6x/acpi/smbus.asl rename to src/southbridge/intel/common/acpi/smbus.asl diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index 0245f4fc2d..0669b5fcca 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -124,11 +124,11 @@ int get_gpio(int gpio_num) * get a number comprised of multiple GPIO values. gpio_num_array points to * the array of gpio pin numbers to scan, terminated by -1. */ -unsigned get_gpios(const int *gpio_num_array) +unsigned int get_gpios(const int *gpio_num_array) { int gpio; - unsigned bitmask = 1; - unsigned vector = 0; + unsigned int bitmask = 1; + unsigned int vector = 0; while (bitmask && ((gpio = *gpio_num_array++) != -1)) { diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h index 019009ef18..eba2d0130f 100644 --- a/src/southbridge/intel/common/gpio.h +++ b/src/southbridge/intel/common/gpio.h @@ -172,7 +172,7 @@ int get_gpio(int gpio_num); * get a number comprised of multiple GPIO values. gpio_num_array points to * the array of gpio pin numbers to scan, terminated by -1. */ -unsigned get_gpios(const int *gpio_num_array); +unsigned int get_gpios(const int *gpio_num_array); void set_gpio(int gpio_num, int value); diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index d61238c865..5582051bc5 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -274,7 +274,7 @@ static void southbridge_smi_store(void) u8 sub_command, ret; em64t101_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_SMMSTORE); - uint32_t reg_ebx; + uintptr_t reg_rbx; if (!io_smi) return; @@ -282,10 +282,10 @@ static void southbridge_smi_store(void) sub_command = (io_smi->rax >> 8) & 0xff; /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; + reg_rbx = (uintptr_t)io_smi->rbx; /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (uintptr_t *)reg_ebx); + ret = smmstore_exec(sub_command, (void *)reg_rbx); io_smi->rax = ret; } diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 73181cfd54..a84a0dfb8f 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -102,7 +102,7 @@ struct ich_spi_controller { uint16_t *optype; uint32_t *addr; uint8_t *data; - unsigned databytes; + unsigned int databytes; uint8_t *status; uint16_t *control; uint32_t *bbar; @@ -169,7 +169,7 @@ static u8 readb_(const void *addr) u8 v = read8(addr); printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned int) addr & 0xffff) - 0xf020); return v; } @@ -178,7 +178,7 @@ static u16 readw_(const void *addr) u16 v = read16(addr); printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned int) addr & 0xffff) - 0xf020); return v; } @@ -187,7 +187,7 @@ static u32 readl_(const void *addr) u32 v = read32(addr); printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned int) addr & 0xffff) - 0xf020); return v; } @@ -195,21 +195,21 @@ static void writeb_(u8 b, void *addr) { write8(addr, b); printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned int) addr & 0xffff) - 0xf020); } static void writew_(u16 b, void *addr) { write16(addr, b); printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned int) addr & 0xffff) - 0xf020); } static void writel_(u32 b, void *addr) { write32(addr, b); printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned int) addr & 0xffff) - 0xf020); } #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ @@ -367,13 +367,13 @@ typedef struct spi_transaction { uint32_t offset; } spi_transaction; -static inline void spi_use_out(spi_transaction *trans, unsigned bytes) +static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) { trans->out += bytes; trans->bytesout -= bytes; } -static inline void spi_use_in(spi_transaction *trans, unsigned bytes) +static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) { trans->in += bytes; trans->bytesin -= bytes; @@ -801,8 +801,8 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, if (addr + len > flash->size) { printk(BIOS_ERR, "Attempt to read %x-%x which is out of chip\n", - (unsigned) addr, - (unsigned) addr+(unsigned) len); + (unsigned int) addr, + (unsigned int) addr+(unsigned int) len); return -1; } @@ -872,7 +872,7 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, if (addr + len > flash->size) { printk(BIOS_ERR, "Attempt to write 0x%x-0x%x which is out of chip\n", - (unsigned)addr, (unsigned) (addr+len)); + (unsigned int)addr, (unsigned int) (addr+len)); return -1; } @@ -906,7 +906,7 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, len -= block_len; } printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n", - (unsigned) (addr - start), start); + (unsigned int) (addr - start), start); return 0; } diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index 4526cb3cf5..3460ea62c5 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -32,6 +32,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_PMBASE config EHCI_BAR hex diff --git a/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl b/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl index b53e98f6ce..a896dadc98 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl +++ b/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl @@ -97,7 +97,7 @@ Device (LPCB) Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -120,15 +120,15 @@ Device (LPCB) If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) } If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) } If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } } diff --git a/src/southbridge/intel/fsp_rangeley/acpi/smbus.asl b/src/southbridge/intel/fsp_rangeley/acpi/smbus.asl deleted file mode 100644 index 268298fb4c..0000000000 --- a/src/southbridge/intel/fsp_rangeley/acpi/smbus.asl +++ /dev/null @@ -1,236 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Intel SMBus Controller 0:1f.3 - -Device (SBUS) -{ - Name (_ADR, 0x001f0003) - -#ifdef ENABLE_SMBUS_METHODS - OperationRegion (SMBP, PCI_Config, 0x00, 0x100) - Field(SMBP, DWordAcc, NoLock, Preserve) - { - Offset(0x40), - , 2, - I2CE, 1 - } - - OperationRegion (SMBI, SystemIO, SMBUS_IO_BASE, 0x20) - Field (SMBI, ByteAcc, NoLock, Preserve) - { - HSTS, 8, // Host Status - , 8, - HCNT, 8, // Host Control - HCMD, 8, // Host Command - TXSA, 8, // Transmit Slave Address - DAT0, 8, // Host Data 0 - DAT1, 8, // Host Data 1 - HBDB, 8, // Host Block Data Byte - PECK, 8, // Packet Error Check - RXSA, 8, // Receive Slave Address - RXDA, 16, // Receive Slave Data - AUXS, 8, // Auxiliary Status - AUXC, 8, // Auxiliary Control - SLPC, 8, // SMLink Pin Control - SBPC, 8, // SMBus Pin Control - SSTS, 8, // Slave Status - SCMD, 8, // Slave Command - NADR, 8, // Notify Device Address - NDLB, 8, // Notify Data Low Byte - NDLH, 8, // Notify Data High Byte - } - - // Kill all SMBus communication - Method (KILL, 0, Serialized) - { - Or (HCNT, 0x02, HCNT) // Send Kill - Or (HSTS, 0xff, HSTS) // Clean Status - } - - // Check if last operation completed - // return Failure = 0, Success = 1 - Method (CMPL, 0, Serialized) - { - Store (4000, Local0) // Timeout 200ms in 50us steps - While (Local0) { - If (And(HSTS, 0x02)) { // Completion Status? - Return (1) // Operation Completed - } Else { - Stall (50) - Decrement (Local0) - If (LEqual(Local0, 0)) { - KILL() - } - } - } - - Return (0) // Failure - } - - - // Wait for SMBus to become ready - Method (SRDY, 0, Serialized) - { - Store (200, Local0) // Timeout 200ms - While (Local0) { - If (And(HSTS, 0x40)) { // IN_USE? - Sleep(1) // Wait 1ms - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - Return (1) - } - } Else { - Store (0, Local0) // We're ready - } - } - - Store (4000, Local0) // Timeout 200ms (50us * 4000) - While (Local0) { - If (And (HSTS, 0x01)) { // Host Busy? - Stall(50) // Wait 50us - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - KILL() - } - } Else { - Return (0) // Success - } - } - - Return (1) // Failure - } - - // SMBus Send Byte - // Arg0: Address - // Arg1: Data - // Return: 1 = Success, 0=Failure - - Method (SSXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Data - - Store (0x48, HCNT) // Start + Byte Data Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Receive Byte - // Arg0: Address - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - - Store (0x44, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } - - - // SMBus Write Byte - // Arg0: Address - // Arg1: Command - // Arg2: Data - // Return: 1 = Success, 0=Failure - - Method (SWRB, 3, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Command - Store (Arg2, DAT0) // Write Data - - Store (0x48, HCNT) // Start + Byte Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Read Byte - // Arg0: Address - // Arg1: Command - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRDB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - Store (Arg1, HCMD) // Command - - Store (0x48, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } -#endif -} diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl index dde6796ed0..f22d48d139 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl +++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl @@ -249,7 +249,7 @@ Scope(\) #include "sata.asl" // SMBus 0:1f.3 -#include "smbus.asl" +#include // IRQ routing for each PCI device #include "irqroute.asl" diff --git a/src/southbridge/intel/fsp_rangeley/early_smbus.c b/src/southbridge/intel/fsp_rangeley/early_smbus.c index 48b7769925..da0c54be3f 100644 --- a/src/southbridge/intel/fsp_rangeley/early_smbus.c +++ b/src/southbridge/intel/fsp_rangeley/early_smbus.c @@ -51,7 +51,7 @@ void enable_smbus(void) printk(BIOS_DEBUG, "SMBus controller enabled.\n"); } -int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(unsigned int device, unsigned int address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } diff --git a/src/southbridge/intel/fsp_rangeley/gpio.h b/src/southbridge/intel/fsp_rangeley/gpio.h index 1a916f4dcc..6a27fea861 100644 --- a/src/southbridge/intel/fsp_rangeley/gpio.h +++ b/src/southbridge/intel/fsp_rangeley/gpio.h @@ -119,6 +119,6 @@ int get_gpio(int gpio_num); * Get a number comprised of multiple GPIO values. gpio_num_array points to * the array of GPIO pin numbers to scan, terminated by -1. */ -unsigned get_gpios(const int *gpio_num_array); +unsigned int get_gpios(const int *gpio_num_array); #endif diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index be7913c06a..d12c379ae6 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -446,7 +446,7 @@ static struct device_operations device_ops = { .write_acpi_tables = acpi_write_hpet, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .enable = soc_lpc_enable, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/fsp_rangeley/pci_devs.h b/src/southbridge/intel/fsp_rangeley/pci_devs.h index 89f3c5c230..c5ef6b8c6f 100644 --- a/src/southbridge/intel/fsp_rangeley/pci_devs.h +++ b/src/southbridge/intel/fsp_rangeley/pci_devs.h @@ -26,72 +26,72 @@ /* Host Bridge */ #define SOC_DEV 0x0 #define SOC_FUNC 0 -# define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC) +# define SOC_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC) /* PCIE Port 1 */ #define PCIE_PORT1_DEV 0x1 #define PCIE_PORT1_FUNC 0 -# define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_PORT1_DEV,PCIE_PORT1_FUNC) +# define SOC_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_PORT1_DEV,PCIE_PORT1_FUNC) /* PCIE Port 2 */ #define PCIE_PORT2_DEV 0x2 #define PCIE_PORT2_FUNC 0 -# define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_PORT2_DEV,PCIE_PORT2_FUNC) +# define SOC_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_PORT2_DEV,PCIE_PORT2_FUNC) /* PCIE Port 3 */ #define PCIE_PORT3_DEV 0x3 #define PCIE_PORT3_FUNC 0 -# define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_PORT3_DEV,PCIE_PORT3_FUNC) +# define SOC_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_PORT3_DEV,PCIE_PORT3_FUNC) /* PCIE Port 4 */ #define PCIE_PORT4_DEV 0x4 #define PCIE_PORT4_FUNC 0 -# define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_PORT4_DEV,PCIE_PORT4_FUNC) +# define SOC_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_PORT4_DEV,PCIE_PORT4_FUNC) /* Host Bridge, Fabric, and RAS Registers */ #define HOST_BRIDGE_DEV 0xe #define HOST_BRIDGE_FUNC 0 -# define HOST_BRIDGE_DEV_FUNC PCI_DEVFN(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC) +# define SOC_DEVFN_HOST_BRIDGE PCI_DEVFN(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC) /* Root Complex Event Collector (RCEC) */ #define RCEC_DEV 0xf #define RCEC_FUNC 0 -# define RCEC_DEV_FUNC PCI_DEVFN(RCEC_DEV,RCEC_FUNC) +# define SOC_DEVFN_RCEC PCI_DEVFN(RCEC_DEV,RCEC_FUNC) /* SMBus 2.0 1 */ #define SMBUS1_DEV 0x13 #define SMBUS1_FUNC 0 -# define SMBUS1_DEV_FUNC PCI_DEVFN(SMBUS1_DEV,SMBUS1_FUNC) +# define SOC_DEVFN_SMBUS1 PCI_DEVFN(SMBUS1_DEV,SMBUS1_FUNC) /* Gigabit Ethernet (GbE) */ #define GBE_DEV 0x14 #define GBE1_DEV GBE_DEV #define GBE1_FUNC 0 -# define GBE1_DEV_FUNC PCI_DEVFN(GBE1_DEV,GBE1_FUNC) +# define SOC_DEVFN_GBE1 PCI_DEVFN(GBE1_DEV,GBE1_FUNC) #define GBE2_DEV GBE_DEV #define GBE2_FUNC 1 -# define GBE2_DEV_FUNC PCI_DEVFN(GBE2_DEV,GBE2_FUNC) +# define SOC_DEVFN_GBE2 PCI_DEVFN(GBE2_DEV,GBE2_FUNC) #define GBE3_DEV GBE_DEV #define GBE3_FUNC 2 -# define GBE3_DEV_FUNC PCI_DEVFN(GBE3_DEV,GBE3_FUNC) +# define SOC_DEVFN_GBE3 PCI_DEVFN(GBE3_DEV,GBE3_FUNC) #define GBE4_DEV GBE_DEV #define GBE4_FUNC 3 -# define GBE4_DEV_FUNC PCI_DEVFN(GBE4_DEV,GBE4_FUNC) +# define SOC_DEVFN_GBE4 PCI_DEVFN(GBE4_DEV,GBE4_FUNC) /* USB 2.0 */ #define USB2_DEV 0x16 #define USB2_FUNC 0 -# define USB2_DEV_FUNC PCI_DEVFN(USB2_DEV,USB2_FUNC) +# define SOC_DEVFN_USB2 PCI_DEVFN(USB2_DEV,USB2_FUNC) /* SATA Gen 2 */ #define SATA2_DEV 0x17 #define SATA2_FUNC 0 -# define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV,SATA2_FUNC) +# define SOC_DEVFN_SATA2 PCI_DEVFN(SATA2_DEV,SATA2_FUNC) /* SATA Gen 3 */ #define SATA3_DEV 0x18 #define SATA3_FUNC 0 -# define SATA3_DEV_FUNC PCI_DEVFN(SATA3_DEV,SATA3_FUNC) +# define SOC_DEVFN_SATA3 PCI_DEVFN(SATA3_DEV,SATA3_FUNC) /* Platform Control Unit (PCU) */ #define PCU_DEV 0x1f @@ -99,18 +99,18 @@ /* Low Pin Count (LPC/ISA) */ #define LPC_DEV PCU_DEV #define LPC_FUNC 0 -# define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC) +# define SOC_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC) # define LPC_BDF PCI_DEV(BUS0, LPC_DEV, LPC_FUNC) /* SMBus 2.0 0 */ #define SMBUS0_DEV PCU_DEV #define SMBUS0_FUNC 3 -# define SMBUS0_DEV_FUNC PCI_DEVFN(SMBUS0_DEV,SMBUS0_FUNC) +# define SOC_DEVFN_SMBUS0 PCI_DEVFN(SMBUS0_DEV,SMBUS0_FUNC) /* Intel QuickAssist Integrated Accelerator (IQIA) */ #define IQAT_DEV 0xb #define IQAT_FUNC 0 -# define IQAT_DEV_FUNC PCI_DEVFN(IQAT_DEV,IQAT_FUNC) +# define SOC_DEVFN_IQAT PCI_DEVFN(IQAT_DEV,IQAT_FUNC) #define SOC_DEVID 0x1f08 #define PCIE_PORT1_DEVID 0x1f10 diff --git a/src/southbridge/intel/fsp_rangeley/soc.c b/src/southbridge/intel/fsp_rangeley/soc.c index ec66c430a9..3512f196d3 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.c +++ b/src/southbridge/intel/fsp_rangeley/soc.c @@ -59,7 +59,7 @@ int soc_silicon_supported(int type, int rev) } /* Set bit in Function Disable register to hide this device */ -static void soc_hide_devfn(unsigned devfn) +static void soc_hide_devfn(unsigned int devfn) { /* TODO Function Disable. */ } diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index d2f2a0bd32..f58677ba27 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -121,7 +121,7 @@ typedef struct ich_spi_controller { uint16_t *optype; uint32_t *addr; uint8_t *data; - unsigned databytes; + unsigned int databytes; uint8_t *status; uint16_t *control; uint32_t *bbar; @@ -199,7 +199,7 @@ static u8 readb_(const void *addr) { u8 v = read8(addr); printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned int) addr & 0xffff) - 0xf020); return v; } @@ -207,7 +207,7 @@ static u16 readw_(const void *addr) { u16 v = read16(addr); printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned int) addr & 0xffff) - 0xf020); return v; } @@ -215,7 +215,7 @@ static u32 readl_(const void *addr) { u32 v = read32(addr); printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned int) addr & 0xffff) - 0xf020); return v; } @@ -223,21 +223,21 @@ static void writeb_(u8 b, const void *addr) { write8(addr, b); printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned int) addr & 0xffff) - 0xf020); } static void writew_(u16 b, const void *addr) { write16(addr, b); printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned int) addr & 0xffff) - 0xf020); } static void writel_(u32 b, const void *addr) { write32((unsigned long)addr, b); printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned int) addr & 0xffff) - 0xf020); } #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ @@ -397,13 +397,13 @@ typedef struct spi_transaction { uint32_t offset; } spi_transaction; -static inline void spi_use_out(spi_transaction *trans, unsigned bytes) +static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) { trans->out += bytes; trans->bytesout -= bytes; } -static inline void spi_use_in(spi_transaction *trans, unsigned bytes) +static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) { trans->in += bytes; trans->bytesin -= bytes; diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 9515c01371..cbfb0af2ee 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include "i82371eb.h" @@ -38,8 +37,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); - header->length = 244; - header->revision = 1; + header->length = sizeof(acpi_fadt_t); + header->revision = ACPI_FADT_REV_ACPI_1_0; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 00b3866665..bb88f7ddc0 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -142,7 +142,7 @@ static const struct device_operations isa_ops = { .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif .init = isa_init, - .scan_bus = scan_lpc_bus, /* TODO: Needed? */ + .scan_bus = scan_static_bus, .enable = 0, .ops_pci = 0, /* No subsystem IDs on 82371EB! */ }; diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 9aa3017b00..50122d830b 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -36,7 +36,7 @@ void i82801dx_enable(struct device *dev); void enable_smbus(void); -int smbus_read_byte(unsigned device, unsigned address); +int smbus_read_byte(unsigned int device, unsigned int address); void aseg_smm_lock(void); #endif diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 2daed4a7ab..031a01a68b 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -339,7 +339,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .enable = i82801dx_enable, }; diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 2d6e938eba..5053a1fb2a 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -26,6 +26,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_PMCLIB + select SOUTHBRIDGE_INTEL_COMMON_PMBASE select HAVE_INTEL_CHIPSET_LOCKDOWN select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select INTEL_HAS_TOP_SWAP diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 237c2d5f8e..2e9d31a3e8 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -35,5 +35,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c smm-y += smihandler.c romstage-y += early_smbus.c +romstage-y += early_cir.c endif diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index d63b00e52b..c3b9687255 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -186,4 +186,4 @@ Scope(\) #include "sata.asl" // SMBus -#include "smbus.asl" +#include diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl index 87eab07288..d5201b2fff 100644 --- a/src/southbridge/intel/i82801gx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl @@ -79,7 +79,7 @@ Device (LPCB) Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -102,15 +102,15 @@ Device (LPCB) If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) } If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) } If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } } diff --git a/src/southbridge/intel/i82801gx/acpi/sleepstates.asl b/src/southbridge/intel/i82801gx/acpi/sleepstates.asl deleted file mode 100644 index 4d1d0b3ea2..0000000000 --- a/src/southbridge/intel/i82801gx/acpi/sleepstates.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -// Name(\_S1, Package(){0x1,0x1,0x0,0x0}) -Name(\_S3, Package(){0x5,0x5,0x0,0x0}) -Name(\_S4, Package(){0x6,0x6,0x0,0x0}) -Name(\_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/southbridge/intel/i82801gx/acpi/smbus.asl b/src/southbridge/intel/i82801gx/acpi/smbus.asl deleted file mode 100644 index 3b314e4054..0000000000 --- a/src/southbridge/intel/i82801gx/acpi/smbus.asl +++ /dev/null @@ -1,236 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Intel SMBus Controller 0:1f.3 - -Device (SBUS) -{ - Name (_ADR, 0x001f0003) - -#ifdef ENABLE_SMBUS_METHODS - OperationRegion (SMBP, PCI_Config, 0x00, 0x100) - Field(SMBP, DWordAcc, NoLock, Preserve) - { - Offset(0x40), - , 2, - I2CE, 1 - } - - OperationRegion (SMBI, SystemIO, 0x400, 0x20) - Field (SMBI, ByteAcc, NoLock, Preserve) - { - HSTS, 8, // Host Status - , 8, - HCNT, 8, // Host Control - HCMD, 8, // Host Command - TXSA, 8, // Transmit Slave Address - DAT0, 8, // Host Data 0 - DAT1, 8, // Host Data 1 - HBDB, 8, // Host Block Data Byte - PECK, 8, // Packet Error Check - RXSA, 8, // Receive Slave Address - RXDA, 16, // Receive Slave Data - AUXS, 8, // Auxiliary Status - AUXC, 8, // Auxiliary Control - SLPC, 8, // SMLink Pin Control - SBPC, 8, // SMBus Pin Control - SSTS, 8, // Slave Status - SCMD, 8, // Slave Command - NADR, 8, // Notify Device Address - NDLB, 8, // Notify Data Low Byte - NDLH, 8, // Notify Data High Byte - } - - // Kill all SMBus communication - Method (KILL, 0, Serialized) - { - Or (HCNT, 0x02, HCNT) // Send Kill - Or (HSTS, 0xff, HSTS) // Clean Status - } - - // Check if last operation completed - // return Failure = 0, Success = 1 - Method (CMPL, 0, Serialized) - { - Store (4000, Local0) // Timeout 200ms in 50us steps - While (Local0) { - If (And(HSTS, 0x02)) { // Completion Status? - Return (1) // Operation Completed - } Else { - Stall (50) - Decrement (Local0) - If (LEqual(Local0, 0)) { - KILL() - } - } - } - - Return (0) // Failure - } - - - // Wait for SMBus to become ready - Method (SRDY, 0, Serialized) - { - Store (200, Local0) // Timeout 200ms - While (Local0) { - If (And(HSTS, 0x40)) { // IN_USE? - Sleep(1) // Wait 1ms - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - Return (1) - } - } Else { - Store (0, Local0) // We're ready - } - } - - Store (4000, Local0) // Timeout 200ms (50us * 4000) - While (Local0) { - If (And (HSTS, 0x01)) { // Host Busy? - Stall(50) // Wait 50us - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - KILL() - } - } Else { - Return (0) // Success - } - } - - Return (1) // Failure - } - - // SMBus Send Byte - // Arg0: Address - // Arg1: Data - // Return: 1 = Success, 0=Failure - - Method (SSXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Data - - Store (0x48, HCNT) // Start + Byte Data Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Receive Byte - // Arg0: Address - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - - Store (0x44, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } - - - // SMBus Write Byte - // Arg0: Address - // Arg1: Command - // Arg2: Data - // Return: 1 = Success, 0=Failure - - Method (SWRB, 3, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Command - Store (Arg2, DAT0) // Write Data - - Store (0x48, HCNT) // Start + Byte Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Read Byte - // Arg0: Address - // Arg1: Command - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRDB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - Store (Arg1, HCMD) // Command - - Store (0x48, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } -#endif -} diff --git a/src/southbridge/intel/i82801gx/early_cir.c b/src/southbridge/intel/i82801gx/early_cir.c new file mode 100644 index 0000000000..7543a777d5 --- /dev/null +++ b/src/southbridge/intel/i82801gx/early_cir.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "i82801gx.h" + +/* Chipset Initialization Registers magic */ +void ich7_setup_cir(void) +{ + uint32_t reg32; + uint8_t revision = pci_read_config8(PCI_DEV(0, 31, 0), PCI_REVISION_ID); + uint16_t pci_id = pci_read_config16(PCI_DEV(0, 31, 0), PCI_DEVICE_ID); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + /* Although bit 6 is set, it is not read back */ + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + RCBA32_AND_OR(0x3430, ~(3 << 0), 1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + /* Only on mobile variants of revision b0 or later */ + switch (pci_id) { + case 0x27b9: + case 0x27bc: + case 0x27bd: + if (revision >= 2) { + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; + } + /* FERR# MUX Enable (FME) */ + reg32 = RCBA32(GCS); + reg32 |= (1 << 6); + RCBA32(GCS) = reg32; + } +} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d615b403ac..8c85331af9 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -48,6 +48,7 @@ int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); +void ich7_setup_cir(void); #endif #define MAINBOARD_POWER_OFF 0 diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 4e2f9f959e..670c2f8ad1 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -310,6 +310,10 @@ static void enable_hpet(void) reg32 |= (1 << 7); // HPET Address Enable reg32 &= ~(3 << 0); RCBA32(HPTC) = reg32; + /* On NM10 this only works if read back */ + RCBA32(HPTC); + + write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1); } static void enable_clock_gating(void) @@ -691,7 +695,7 @@ static struct device_operations device_ops = { .acpi_fill_ssdt_generator = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .enable = i82801gx_enable, .ops_pci = &pci_ops, .final = lpc_final, diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index d493b790a7..5ff9d38192 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 5edb8a1426..1d51f43cfa 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -20,6 +20,7 @@ config SOUTHBRIDGE_INTEL_I82801IX select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ + select SOUTHBRIDGE_INTEL_COMMON_PMBASE select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT @@ -47,8 +48,4 @@ config HPET_MIN_TICKS hex default 0x80 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82801ix/bootblock.c" - endif diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 49db1230b7..41d1b89430 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -35,6 +35,9 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S endif smm-y += smihandler.c +bootblock-y += bootblock.c +bootblock-y += early_init.c + romstage-y += early_init.c romstage-y += early_smbus.c romstage-y += dmi_setup.c diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index d155d15d96..5a9d2994ad 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -183,7 +183,7 @@ Scope(\) #include "sata.asl" // SMBus -#include "smbus.asl" +#include Method (_OSC, 4) { diff --git a/src/southbridge/intel/i82801ix/acpi/lpc.asl b/src/southbridge/intel/i82801ix/acpi/lpc.asl index 9d27b0b482..07ce43aa89 100644 --- a/src/southbridge/intel/i82801ix/acpi/lpc.asl +++ b/src/southbridge/intel/i82801ix/acpi/lpc.asl @@ -79,7 +79,7 @@ Device (LPCB) Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -102,15 +102,15 @@ Device (LPCB) If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) } If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) } If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } } diff --git a/src/southbridge/intel/i82801ix/acpi/smbus.asl b/src/southbridge/intel/i82801ix/acpi/smbus.asl deleted file mode 100644 index 3b314e4054..0000000000 --- a/src/southbridge/intel/i82801ix/acpi/smbus.asl +++ /dev/null @@ -1,236 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Intel SMBus Controller 0:1f.3 - -Device (SBUS) -{ - Name (_ADR, 0x001f0003) - -#ifdef ENABLE_SMBUS_METHODS - OperationRegion (SMBP, PCI_Config, 0x00, 0x100) - Field(SMBP, DWordAcc, NoLock, Preserve) - { - Offset(0x40), - , 2, - I2CE, 1 - } - - OperationRegion (SMBI, SystemIO, 0x400, 0x20) - Field (SMBI, ByteAcc, NoLock, Preserve) - { - HSTS, 8, // Host Status - , 8, - HCNT, 8, // Host Control - HCMD, 8, // Host Command - TXSA, 8, // Transmit Slave Address - DAT0, 8, // Host Data 0 - DAT1, 8, // Host Data 1 - HBDB, 8, // Host Block Data Byte - PECK, 8, // Packet Error Check - RXSA, 8, // Receive Slave Address - RXDA, 16, // Receive Slave Data - AUXS, 8, // Auxiliary Status - AUXC, 8, // Auxiliary Control - SLPC, 8, // SMLink Pin Control - SBPC, 8, // SMBus Pin Control - SSTS, 8, // Slave Status - SCMD, 8, // Slave Command - NADR, 8, // Notify Device Address - NDLB, 8, // Notify Data Low Byte - NDLH, 8, // Notify Data High Byte - } - - // Kill all SMBus communication - Method (KILL, 0, Serialized) - { - Or (HCNT, 0x02, HCNT) // Send Kill - Or (HSTS, 0xff, HSTS) // Clean Status - } - - // Check if last operation completed - // return Failure = 0, Success = 1 - Method (CMPL, 0, Serialized) - { - Store (4000, Local0) // Timeout 200ms in 50us steps - While (Local0) { - If (And(HSTS, 0x02)) { // Completion Status? - Return (1) // Operation Completed - } Else { - Stall (50) - Decrement (Local0) - If (LEqual(Local0, 0)) { - KILL() - } - } - } - - Return (0) // Failure - } - - - // Wait for SMBus to become ready - Method (SRDY, 0, Serialized) - { - Store (200, Local0) // Timeout 200ms - While (Local0) { - If (And(HSTS, 0x40)) { // IN_USE? - Sleep(1) // Wait 1ms - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - Return (1) - } - } Else { - Store (0, Local0) // We're ready - } - } - - Store (4000, Local0) // Timeout 200ms (50us * 4000) - While (Local0) { - If (And (HSTS, 0x01)) { // Host Busy? - Stall(50) // Wait 50us - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - KILL() - } - } Else { - Return (0) // Success - } - } - - Return (1) // Failure - } - - // SMBus Send Byte - // Arg0: Address - // Arg1: Data - // Return: 1 = Success, 0=Failure - - Method (SSXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Data - - Store (0x48, HCNT) // Start + Byte Data Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Receive Byte - // Arg0: Address - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - - Store (0x44, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } - - - // SMBus Write Byte - // Arg0: Address - // Arg1: Command - // Arg2: Data - // Return: 1 = Success, 0=Failure - - Method (SWRB, 3, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Command - Store (Arg2, DAT0) // Write Data - - Store (0x48, HCNT) // Start + Byte Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Read Byte - // Arg0: Address - // Arg1: Command - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRDB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - Store (Arg1, HCMD) // Command - - Store (0x48, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } -#endif -} diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index 1957512cc0..0b50d61fba 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -14,6 +14,9 @@ */ #include +#include +#include "i82801ix.h" + static void enable_spi_prefetch(void) { @@ -28,7 +31,10 @@ static void enable_spi_prefetch(void) pci_write_config8(dev, 0xdc, reg8); } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); + + i82801ix_early_init(); + i82801ix_lpc_decode(); } diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index 0b3e0b5a50..73ee822f74 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -88,6 +88,12 @@ struct southbridge_intel_i82801ix_config { } pcie_power_limits[6]; uint8_t pcie_hotplug_map[8]; + + /* Additional LPC IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; }; #endif /* SOUTHBRIDGE_INTEL_I82801IX_CHIP_H */ diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index da124ff54f..51ce9e859e 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -17,6 +17,7 @@ #include #include #include "i82801ix.h" +#include "chip.h" void i82801ix_early_init(void) { @@ -58,3 +59,34 @@ void i82801ix_early_init(void) /* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2) before they get cleared. */ } + +void i82801ix_lpc_decode(void) +{ + const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + const struct device *dev = pcidev_on_root(0x1f, 0); + const struct southbridge_intel_i82801ix_config *config = NULL; + + /* Configure serial IRQs.*/ + pci_write_config8(d31f0, D31F0_SERIRQ_CNTL, 0xd0); + /* + * Enable some common LPC IO ranges: + * - 0x2e/0x2f, 0x4e/0x4f often SuperIO + * - 0x60/0x64, 0x62/0x66 often KBC/EC + * - 0x3f0-0x3f5/0x3f7 FDD + * - 0x378-0x37f and 0x778-0x77f LPT + * - 0x2f8-0x2ff COMB + * - 0x3f8-0x3ff COMA + */ + pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010); + pci_write_config16(d31f0, D31F0_LPC_EN, 0x3f0f); + + /* Set up generic decode ranges */ + if (!dev || !dev->chip_info) + return; + config = dev->chip_info; + + pci_write_config32(d31f0, D31F0_GEN1_DEC, config->gen1_dec); + pci_write_config32(d31f0, D31F0_GEN2_DEC, config->gen2_dec); + pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec); + pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec); +} diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 6949a309f6..54ad3c369b 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -52,7 +52,7 @@ void enable_smbus(void) printk(BIOS_DEBUG, "SMBus controller enabled.\n"); } -int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(unsigned int device, unsigned int address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 341a98aec4..132b684f30 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -137,7 +137,7 @@ static void i82801ix_ehci_init(void) (1 << 29) | (1 << 17) | (2 << 2)); } -static int i82801ix_function_disabled(const unsigned devfn) +static int i82801ix_function_disabled(const unsigned int devfn) { struct device *const dev = pcidev_path_on_root(devfn); if (!dev) { diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index afaaade82d..906d24e95b 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -210,11 +210,12 @@ void aseg_smm_lock(void); void enable_smbus(void); void i82801ix_early_init(void); +void i82801ix_lpc_decode(void); void i82801ix_dmi_setup(void); void i82801ix_dmi_poll_vc1(void); #if ENV_ROMSTAGE -int smbus_read_byte(unsigned device, unsigned address); +int smbus_read_byte(unsigned int device, unsigned int address); #endif #endif diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index cb964de35f..a79ade7291 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -543,7 +543,7 @@ static struct device_operations device_ops = { .acpi_fill_ssdt_generator = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index 04e62db809..fab74ddcb7 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -13,6 +13,10 @@ * GNU General Public License for more details. */ +#ifndef SOUTHBRIDGE_INTEL_I82801IX_NVS_H +#define SOUTHBRIDGE_INTEL_I82801IX_NVS_H +#include + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -133,3 +137,5 @@ typedef struct { } __packed global_nvs_t; void acpi_create_gnvs(global_nvs_t *gnvs); + +#endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */ diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c index f7d8b87828..47254f94b9 100644 --- a/src/southbridge/intel/i82801ix/usb_ehci.c +++ b/src/southbridge/intel/i82801ix/usb_ehci.c @@ -34,8 +34,8 @@ static void usb_ehci_init(struct device *dev) printk(BIOS_DEBUG, "done.\n"); } -static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { u8 access_cntl; diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index b423ecae40..430adf9ca0 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -21,6 +21,7 @@ config SOUTHBRIDGE_INTEL_I82801JX select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_PMCLIB + select SOUTHBRIDGE_INTEL_COMMON_PMBASE select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index 58220f697c..2c277986ad 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -184,7 +184,7 @@ Scope(\) #include "sata.asl" // SMBus -#include "smbus.asl" +#include Method (_OSC, 4) { diff --git a/src/southbridge/intel/i82801jx/acpi/lpc.asl b/src/southbridge/intel/i82801jx/acpi/lpc.asl index 1d9e54e237..7f16e08fae 100644 --- a/src/southbridge/intel/i82801jx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801jx/acpi/lpc.asl @@ -79,7 +79,7 @@ Device (LPCB) Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -102,15 +102,15 @@ Device (LPCB) If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) } If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) } If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } } diff --git a/src/southbridge/intel/i82801jx/acpi/sleepstates.asl b/src/southbridge/intel/i82801jx/acpi/sleepstates.asl deleted file mode 100644 index 79818a109a..0000000000 --- a/src/southbridge/intel/i82801jx/acpi/sleepstates.asl +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -#if !CONFIG(HAVE_ACPI_RESUME) -Name(\_S1, Package(){0x1,0x0,0x0,0x0}) -#else -Name(\_S3, Package(){0x5,0x0,0x0,0x0}) -#endif -Name(\_S4, Package(){0x6,0x0,0x0,0x0}) -Name(\_S5, Package(){0x7,0x0,0x0,0x0}) diff --git a/src/southbridge/intel/i82801jx/acpi/smbus.asl b/src/southbridge/intel/i82801jx/acpi/smbus.asl deleted file mode 100644 index 3b314e4054..0000000000 --- a/src/southbridge/intel/i82801jx/acpi/smbus.asl +++ /dev/null @@ -1,236 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Intel SMBus Controller 0:1f.3 - -Device (SBUS) -{ - Name (_ADR, 0x001f0003) - -#ifdef ENABLE_SMBUS_METHODS - OperationRegion (SMBP, PCI_Config, 0x00, 0x100) - Field(SMBP, DWordAcc, NoLock, Preserve) - { - Offset(0x40), - , 2, - I2CE, 1 - } - - OperationRegion (SMBI, SystemIO, 0x400, 0x20) - Field (SMBI, ByteAcc, NoLock, Preserve) - { - HSTS, 8, // Host Status - , 8, - HCNT, 8, // Host Control - HCMD, 8, // Host Command - TXSA, 8, // Transmit Slave Address - DAT0, 8, // Host Data 0 - DAT1, 8, // Host Data 1 - HBDB, 8, // Host Block Data Byte - PECK, 8, // Packet Error Check - RXSA, 8, // Receive Slave Address - RXDA, 16, // Receive Slave Data - AUXS, 8, // Auxiliary Status - AUXC, 8, // Auxiliary Control - SLPC, 8, // SMLink Pin Control - SBPC, 8, // SMBus Pin Control - SSTS, 8, // Slave Status - SCMD, 8, // Slave Command - NADR, 8, // Notify Device Address - NDLB, 8, // Notify Data Low Byte - NDLH, 8, // Notify Data High Byte - } - - // Kill all SMBus communication - Method (KILL, 0, Serialized) - { - Or (HCNT, 0x02, HCNT) // Send Kill - Or (HSTS, 0xff, HSTS) // Clean Status - } - - // Check if last operation completed - // return Failure = 0, Success = 1 - Method (CMPL, 0, Serialized) - { - Store (4000, Local0) // Timeout 200ms in 50us steps - While (Local0) { - If (And(HSTS, 0x02)) { // Completion Status? - Return (1) // Operation Completed - } Else { - Stall (50) - Decrement (Local0) - If (LEqual(Local0, 0)) { - KILL() - } - } - } - - Return (0) // Failure - } - - - // Wait for SMBus to become ready - Method (SRDY, 0, Serialized) - { - Store (200, Local0) // Timeout 200ms - While (Local0) { - If (And(HSTS, 0x40)) { // IN_USE? - Sleep(1) // Wait 1ms - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - Return (1) - } - } Else { - Store (0, Local0) // We're ready - } - } - - Store (4000, Local0) // Timeout 200ms (50us * 4000) - While (Local0) { - If (And (HSTS, 0x01)) { // Host Busy? - Stall(50) // Wait 50us - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - KILL() - } - } Else { - Return (0) // Success - } - } - - Return (1) // Failure - } - - // SMBus Send Byte - // Arg0: Address - // Arg1: Data - // Return: 1 = Success, 0=Failure - - Method (SSXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Data - - Store (0x48, HCNT) // Start + Byte Data Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Receive Byte - // Arg0: Address - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - - Store (0x44, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } - - - // SMBus Write Byte - // Arg0: Address - // Arg1: Command - // Arg2: Data - // Return: 1 = Success, 0=Failure - - Method (SWRB, 3, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Command - Store (Arg2, DAT0) // Write Data - - Store (0x48, HCNT) // Start + Byte Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Read Byte - // Arg0: Address - // Arg1: Command - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRDB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - Store (Arg1, HCMD) // Command - - Store (0x48, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } -#endif -} diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c index d2b87d1812..adba27ca71 100644 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ b/src/southbridge/intel/i82801jx/early_smbus.c @@ -47,7 +47,7 @@ void enable_smbus(void) printk(BIOS_DEBUG, "SMBus controller enabled.\n"); } -int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(unsigned int device, unsigned int address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 28c9f68ea2..7b882181ff 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -227,7 +227,7 @@ static inline int lpc_is_mobile(const u16 devid) #if ENV_ROMSTAGE void enable_smbus(void); -int smbus_read_byte(unsigned device, unsigned address); +int smbus_read_byte(unsigned int device, unsigned int address); int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, u8 *buf); int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 6c63186336..a39506976e 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -701,7 +701,7 @@ static struct device_operations device_ops = { .acpi_fill_ssdt_generator = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h index ca66985746..88944c0ebd 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/nvs.h @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c index a4f5a01dc1..a24685a26c 100644 --- a/src/southbridge/intel/i82801jx/usb_ehci.c +++ b/src/southbridge/intel/i82801jx/usb_ehci.c @@ -34,8 +34,8 @@ static void usb_ehci_init(struct device *dev) printk(BIOS_DEBUG, "done.\n"); } -static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { u8 access_cntl; diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c index a375568b71..cb6ace8dab 100644 --- a/src/southbridge/intel/i82870/pcibridge.c +++ b/src/southbridge/intel/i82870/pcibridge.c @@ -47,3 +47,7 @@ static const struct pci_driver pcix_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82870_1F0, }; + +struct chip_operations southbridge_intel_i82870_ops = { + CHIP_NAME("Intel 82870") +}; diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 00eb413d1e..620736c70c 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -33,6 +33,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_SMM + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB + select SOUTHBRIDGE_INTEL_COMMON_PMBASE select HAVE_USBDEBUG_OPTIONS select COMMON_FADT select ACPI_SATA_GENERATOR @@ -51,10 +53,6 @@ config DRAM_RESET_GATE_GPIO int default 60 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/ibexpeak/bootblock.c" - config SERIRQ_CONTINUOUS_MODE bool default n diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 83d083f3ae..dc35de561c 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -15,7 +15,9 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y) -ramstage-y += ../bd82x6x/pch.c +bootblock-y += bootblock.c + +ramstage-y += pch.c ramstage-y += azalia.c ramstage-y += lpc.c ramstage-y += ../bd82x6x/pci.c @@ -35,12 +37,15 @@ ramstage-y += ../bd82x6x/me_status.c ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c ramstage-y += madt.c -smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/pch.c +smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c +romstage-y += early_pch.c romstage-y += early_smbus.c romstage-y +=../bd82x6x/early_me.c romstage-y +=../bd82x6x/me_status.c romstage-y += early_thermal.c romstage-y += ../bd82x6x/early_rcba.c +romstage-y += early_cir.c +romstage-y += early_usb.c endif diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index 0086fe3281..599e182a59 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -14,7 +14,9 @@ */ #include +#include #include "pch.h" +#include "chip.h" /* * Enable Prefetching and Caching. @@ -32,18 +34,7 @@ static void enable_spi_prefetch(void) static void enable_port80_on_lpc(void) { - pci_devfn_t dev = PCH_LPC_DEV; - - /* Enable port 80 POST on LPC */ - pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); -#if 0 - RCBA32(GCS) &= (~0x04); -#else - volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS); - u32 reg32 = *gcs; - reg32 = reg32 & ~0x04; - *gcs = reg32; -#endif + RCBA32(GCS) &= ~4; } static void set_spi_speed(void) @@ -66,12 +57,57 @@ static void set_spi_speed(void) RCBA8(0x3893) = ssfc; } -static void bootblock_southbridge_init(void) +static void early_lpc_init(void) +{ + const struct device *dev = pcidev_on_root(0x1f, 0); + const struct southbridge_intel_ibexpeak_config *config = NULL; + + /* Add some default decode ranges: + - 0x2e/2f, 0x4e/0x4f + - EC/Mouse/KBC 60/64, 62/66 + - 0x3f8 COMA + If more are needed, update in mainboard_lpc_init hook + */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | + COMA_LPC_EN); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + /* Clear PWR_FLR */ + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, + (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); + + pci_write_config32(PCH_LPC_DEV, ETR3, + pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); + + /* Set up generic decode ranges */ + if (!dev) + return; + if (dev->chip_info) + config = dev->chip_info; + if (!config) + return; + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); +} + + +void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); + + /* Enable RCBA */ + pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); + pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + enable_port80_on_lpc(); set_spi_speed(); /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); + + early_lpc_init(); } diff --git a/src/southbridge/intel/ibexpeak/early_cir.c b/src/southbridge/intel/ibexpeak/early_cir.c new file mode 100644 index 0000000000..8d7a918d40 --- /dev/null +++ b/src/southbridge/intel/ibexpeak/early_cir.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include "pch.h" + +/* This sets up magic Chipset Initialization Registers */ +void pch_setup_cir(int chipset_type) +{ + printk(BIOS_DEBUG, "Setting up Chipset Initialization Registers (CIR)\n"); + + uint16_t lpc_id = pci_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID); + struct cpuinfo_x86 c; + uint32_t cir22; + + pci_or_config8(PCH_LPC_DEV, GEN_PMCON_3, 0xfb); + + RCBA32_OR(GCS, 0x40); /* FERR# MUX enable */ + + RCBA8(0x3430) |= 0xfc; + + RCBA32(CIR7) = 0xf; + + RCBA32(CIR9) = 0; + + switch (lpc_id) { + case 0x3b01: + case 0x3b03: + case 0x3b05: + case 0x3b07: + case 0x3b09: + case 0x3b0b: + case 0x3b0d: + case 0x3b0f: + RCBA32_AND_OR(CIR6, 0xff1fff7f, 0x600000); + break; + } + + RCBA32_OR(0x3310, 0x31); + + /* Intel 5 Series Chipset and Intel 3400 Series Chipset + External Design Specification (EDS) 13.8.1.1 */ + if (chipset_type == NEHALEM_DESKTOP) + pci_or_config32(PCH_LPC_DEV, GEN_PMCON_1, 1 << 3); + + pci_write_config8(PCH_LPC_DEV, CIR4, 0x45); + + RCBA32(CIR8) = 0x4000000; + pci_write_config32(PCH_LPC_DEV, PMIR, 0xc0000300); + RCBA32(0x3318) = 0x1020000; /* undocumented */ + get_fms(&c, cpuid_eax(1)); + if (c.x86_model == 0x1e) { + /* Lynnfield/Clarksfield */ + RCBA32(CIR13) = 0xfffff; + RCBA32(CIR14) = 0x61080; + RCBA32(CIR16) = 0x7f8f9f80; + RCBA32(CIR18) = 0x3900; + RCBA32(CIR19) = 0x20002; + RCBA32(CIR20) = 0x44b00; + RCBA32(CIR21) = 0x02000; + cir22 = 0x20000; + } else if (c.x86_model == 0x1f || c.x86_model == 0x25) { + /* Auburndale/Havendale + Arrandale/Clarkdale */ + RCBA32(CIR10) = 0xfff80; + RCBA32(CIR15) = 0x7f8f9fff; + RCBA32(CIR17) = 0x2900; + RCBA32(CIR19) = 0x10001; + RCBA32(CIR20) = 0x1004b; + RCBA32(CIR21) = 0x8; + cir22 = 0x10000; + } else { + die("unsupported CPU model: %x!\n", c.x86_model); + } + + /* EDS, 10.1.77: Program this register after all registers in the + 3330-33D3 range and D31:F0:A9h are already programmed */ + RCBA32(CIR22) = cir22; +} diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c new file mode 100644 index 0000000000..b76115bf84 --- /dev/null +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +static void early_gpio_init(void) +{ + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); +} + +static void pch_default_disable(void) +{ + /* Must set BIT0 (hides performance counters PCI device). + coreboot enables the Rate Matching Hub which makes the UHCI PCI + devices disappear, so BIT5-12 and BIT28 can be set to hide those. */ + RCBA32(FD) = (1 << 28) | (0xff << 5) | 1; + + /* Set reserved bit to 1 */ + RCBA32(FD2) = 1; +} + +void early_pch_init(void) +{ + early_gpio_init(); + /* TODO, make this configurable */ + pch_setup_cir(NEHALEM_MOBILE); + southbridge_configure_default_intmap(); + pch_default_disable(); + early_usb_init(mainboard_usb_ports); +} diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index 241584bb49..bd130c0a99 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -51,22 +51,22 @@ void enable_smbus(void) printk(BIOS_DEBUG, "SMBus controller enabled.\n"); } -int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(unsigned int device, unsigned int address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -int smbus_write_byte(unsigned device, unsigned address, u8 data) +int smbus_write_byte(unsigned int device, unsigned int address, u8 data) { return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data); } -int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf) +int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) { return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); } -int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf) +int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf) { return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); } diff --git a/src/southbridge/intel/ibexpeak/early_usb.c b/src/southbridge/intel/ibexpeak/early_usb.c new file mode 100644 index 0000000000..53c4ae7a95 --- /dev/null +++ b/src/southbridge/intel/ibexpeak/early_usb.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include "pch.h" + +#define TOTAL_USB_PORTS 14 + +void early_usb_init(const struct southbridge_usb_port *portmap) +{ + u32 reg32; + const u16 currents[] = { 0xf57, 0xf5f, 0x753, 0x75f, 0x14b, 0x74b, + 0x557, 0x757, 0x55f, 0x54b + }; + int i; + + /* Unlock registers. */ + write_pmbase16(UPRWC, read_pmbase16(UPRWC) | UPRWC_WR_EN); + + for (i = 0; i < TOTAL_USB_PORTS; i++) + RCBA32_AND_OR(USBIR0 + 4 * i, ~0xfff, currents[portmap[i].current]); + + /* USB Initialization Registers. We follow what EDS recommends here. + TODO maybe vendor firmware values are better? */ + RCBA32(USBIRC) &= ~(1 << 8); + RCBA32_OR(USBIRA, (7 << 12) | (7 << 8) | (7 << 4) | (2 << 0)); + RCBA32_AND_OR(USBIRB, ~0x617f0, (3 << 17) | (1 << 12) | (1 << 10) + | (1 << 8) | (4 << 4)); + /* Set to Rate Matching Hub Mode to make PCI devices appear. */ + RCBA32(0x3598) = 0; + + reg32 = 0; + for (i = 0; i < TOTAL_USB_PORTS; i++) + if (!portmap[i].enabled) + reg32 |= (1 << i); + RCBA32(USBPDO) = reg32; + reg32 = 0; + /* The OC pins of the first 8 USB ports are mapped in USBOCM1 */ + for (i = 0; i < 8; i++) + if (portmap[i].enabled && portmap[i].oc_pin >= 0) + reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); + RCBA32(USBOCM1) = reg32; + reg32 = 0; + /* The OC pins of the remainder 6 USB ports are mapped in USBOCM2 */ + for (i = 8; i < TOTAL_USB_PORTS; i++) + if (portmap[i].enabled && portmap[i].oc_pin >= 4) + reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); + RCBA32(USBOCM2) = reg32; + + /* Relock registers. */ + write_pmbase16(UPRWC, 0); +} diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 3e1f4a4350..36576563aa 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -394,6 +394,7 @@ static void enable_hpet(void) reg32 |= (1 << 7); // HPET Address Enable reg32 &= ~(3 << 0); RCBA32(HPTC) = reg32; + RCBA32(HPTC); /* Read back for it to work */ write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1); } @@ -409,11 +410,6 @@ static void enable_clock_gating(struct device *dev) reg16 |= (1 << 2) | (1 << 11); pci_write_config16(dev, GEN_PMCON_1, reg16); - pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); - pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); - reg32 = RCBA32(CG); reg32 |= (1 << 31); reg32 |= (1 << 29) | (1 << 28); @@ -469,18 +465,6 @@ static void pch_fixups(struct device *dev) RCBA32_OR(0x21a8, 0x3); } -static void pch_decode_init(struct device *dev) -{ - config_t *config = dev->chip_info; - - printk(BIOS_DEBUG, "pch_decode_init\n"); - - pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec); -} - static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: lpc_init\n"); @@ -500,13 +484,7 @@ static void lpc_init(struct device *dev) pch_power_options(dev); /* Initialize power management */ - switch (pch_silicon_type()) { - case PCH_TYPE_MOBILE5: - mobile5_pm_init (dev); - break; - default: - printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device); - } + mobile5_pm_init(dev); /* Set the state of the GPIO lines. */ //gpio_init(dev); @@ -597,12 +575,6 @@ static void pch_lpc_read_resources(struct device *dev) } } -static void pch_lpc_enable_resources(struct device *dev) -{ - pch_decode_init(dev); - return pci_dev_enable_resources(dev); -} - static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ @@ -804,7 +776,7 @@ static struct pci_operations pci_ops = { static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pch_lpc_enable_resources, + .enable_resources = pci_dev_enable_resources, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .acpi_fill_ssdt_generator = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, @@ -812,7 +784,7 @@ static struct device_operations device_ops = { .init = lpc_init, .final = lpc_final, .enable = pch_lpc_enable, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 8d3ae02179..f804126654 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -155,7 +155,7 @@ static inline u32 read_cb(void) static int mei_wait_for_me_ready(void) { struct mei_csr me; - unsigned try = ME_RETRY; + unsigned int try = ME_RETRY; while (try--) { read_me_csr(&me); @@ -196,7 +196,7 @@ static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, void *req_data) { struct mei_csr host; - unsigned ndata, n; + unsigned int ndata, n; u32 *data; /* Number of dwords to write, ignoring MKHI */ @@ -261,8 +261,8 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, struct mei_header mei_rsp; struct mkhi_header mkhi_rsp; struct mei_csr me, host; - unsigned ndata, n; - unsigned expected; + unsigned int ndata, n; + unsigned int expected; u32 *data; /* Total number of dwords to read from circular buffer */ diff --git a/src/southbridge/intel/ibexpeak/pch.c b/src/southbridge/intel/ibexpeak/pch.c new file mode 100644 index 0000000000..9148b44a8e --- /dev/null +++ b/src/southbridge/intel/ibexpeak/pch.c @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include "pch.h" + +/* Set bit in function disable register to hide this device */ +static void pch_disable_devfn(struct device *dev) +{ + switch (dev->path.pci.devfn) { + case PCI_DEVFN(22, 0): /* MEI #1 */ + RCBA32_OR(FD2, PCH_DISABLE_MEI1); + break; + case PCI_DEVFN(22, 1): /* MEI #2 */ + RCBA32_OR(FD2, PCH_DISABLE_MEI2); + break; + case PCI_DEVFN(22, 2): /* IDE-R */ + RCBA32_OR(FD2, PCH_DISABLE_IDER); + break; + case PCI_DEVFN(22, 3): /* KT */ + RCBA32_OR(FD2, PCH_DISABLE_KT); + break; + case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ + RCBA32_OR(BUC, PCH_DISABLE_GBE); + break; + case PCI_DEVFN(26, 0): /* EHCI #2 */ + RCBA32_OR(FD, PCH_DISABLE_EHCI2); + break; + case PCI_DEVFN(27, 0): /* HD Audio Controller */ + RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); + break; + case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ + case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ + case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ + case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ + case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ + case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ + case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ + case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ + RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn))); + break; + case PCI_DEVFN(29, 0): /* EHCI #1 */ + RCBA32_OR(FD, PCH_DISABLE_EHCI1); + break; + case PCI_DEVFN(31, 0): /* LPC */ + RCBA32_OR(FD, PCH_DISABLE_LPC); + break; + case PCI_DEVFN(31, 2): /* SATA #1 */ + RCBA32_OR(FD, PCH_DISABLE_SATA1); + break; + case PCI_DEVFN(31, 3): /* SMBUS */ + RCBA32_OR(FD, PCH_DISABLE_SMBUS); + break; + case PCI_DEVFN(31, 5): /* SATA #22 */ + RCBA32_OR(FD, PCH_DISABLE_SATA2); + break; + case PCI_DEVFN(31, 6): /* Thermal Subsystem */ + RCBA32_OR(FD, PCH_DISABLE_THERMAL); + break; + } +} + +void pch_enable(struct device *dev) +{ + u32 reg32; + + if (!dev->enabled) { + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + + /* Ensure memory, io, and bus master are all disabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Disable this device if possible */ + pch_disable_devfn(dev); + } else { + /* Enable SERR */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SERR; + pci_write_config32(dev, PCI_COMMAND, reg32); + } +} + +struct chip_operations southbridge_intel_ibexpeak_ops = { + CHIP_NAME("Intel Series 5 (Ibexpeak) Southbridge") + .enable_dev = pch_enable, +}; diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index f7b29291db..9ee76f22f4 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -51,24 +51,46 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -int pch_silicon_revision(void); -int pch_silicon_type(void); -int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_smbus(void); void enable_usb_bar(void); #if ENV_ROMSTAGE -int smbus_read_byte(unsigned device, unsigned address); -int smbus_write_byte(unsigned device, unsigned address, u8 data); -int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf); -int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); +int smbus_read_byte(unsigned int device, unsigned int address); +int smbus_write_byte(unsigned int device, unsigned int address, u8 data); +int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); +int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); #endif +void early_pch_init(void); + void early_thermal_init(void); void southbridge_configure_default_intmap(void); +void pch_setup_cir(int chipset_type); + +enum current_lookup_idx { + IF1_F57 = 0, + IF1_F5F, + IF1_753, + IF1_75F, + IF1_14B, + IF1_74B, + IF1_557, + IF1_757, + IF1_55F, + IF1_54B, +}; + +struct southbridge_usb_port { + int enabled; + enum current_lookup_idx current; + int oc_pin; +}; + +void early_usb_init(const struct southbridge_usb_port *portmap); #ifndef __ROMCC__ +extern const struct southbridge_usb_port mainboard_usb_ports[14]; #include void pch_enable(struct device *dev); #endif @@ -77,6 +99,10 @@ void pch_enable(struct device *dev); #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 +/* PM I/O Space */ +#define UPRWC 0x3c +#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ + /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b @@ -100,6 +126,9 @@ void pch_enable(struct device *dev); #define ETR3_CWORWRE (1 << 18) #define ETR3_CF9GR (1 << 20) +#define CIR4 0xa9 +#define PMIR 0xac + /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) #define RTC_POWER_FAILED (1 << 1) @@ -349,6 +378,21 @@ void pch_enable(struct device *dev); #define SOFT_RESET_DATA 0x38f8 #define PRSTS 0x3310 +#define CIR6 0x2024 +#define CIR7 0x3314 +#define CIR8 0x3324 +#define CIR9 0x3330 +#define CIR10 0x3340 +#define CIR13 0x3350 +#define CIR14 0x3368 +#define CIR15 0x3378 +#define CIR16 0x3388 +#define CIR17 0x33a0 +#define CIR18 0x33a8 +#define CIR19 0x33c0 +#define CIR20 0x33cc +#define CIR21 0x33d0 +#define CIR22 0x33d4 #define DIR_ROUTE(x,a,b,c,d) \ RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ @@ -385,6 +429,36 @@ void pch_enable(struct device *dev); #define PCH_DISABLE_MEI1 (1 << 1) #define PCH_ENABLE_DBDF (1 << 0) +/* USB Initialization Registers[13:0] */ +#define USBIR0 0x3500 /* 32bit */ +#define USBIR1 0x3504 /* 32bit */ +#define USBIR2 0x3508 /* 32bit */ +#define USBIR3 0x350c /* 32bit */ +#define USBIR4 0x3510 /* 32bit */ +#define USBIR5 0x3514 /* 32bit */ +#define USBIR6 0x3518 /* 32bit */ +#define USBIR7 0x351c /* 32bit */ +#define USBIR8 0x3520 /* 32bit */ +#define USBIR9 0x3524 /* 32bit */ +#define USBIR10 0x3528 /* 32bit */ +#define USBIR11 0x352c /* 32bit */ +#define USBIR12 0x3530 /* 32bit */ +#define USBIR13 0x3534 /* 32bit */ + +#define USBIRC 0x3564 /* 32bit */ +#define USBIRA 0x3570 /* 32bit */ +#define USBIRB 0x357c /* 32bit */ + +/* Miscellaneous Control Register */ +#define MISCCTL 0x3590 /* 32bit */ +/* USB Port Disable Override */ +#define USBPDO 0x359c /* 32bit */ +/* USB Overcurrent MAP Register */ +#define USBOCM1 0x35a0 /* 32bit */ +#define USBOCM2 0x35a4 /* 32bit */ +/* Rate Matching Hub Wake Control Register */ +#define RMHWKCTL 0x35b0 /* 32bit */ + /* ICH7 PMBASE */ #define PM1_STS 0x00 #define WAK_STS (1 << 15) diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index c99e944513..2d9412ad64 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -176,15 +176,6 @@ static void sata_init(struct device *dev) sata_port_map ^ 0x3f) << 24) | 0x183); } - /* Set Gen3 Transmitter settings if needed */ - if (config->sata_port0_gen3_tx) - pch_iobp_update(SATA_IOBP_SP0G3IR, 0, - config->sata_port0_gen3_tx); - - if (config->sata_port1_gen3_tx) - pch_iobp_update(SATA_IOBP_SP1G3IR, 0, - config->sata_port1_gen3_tx); - /* Additional Programming Requirements */ sir_write(dev, 0x04, 0x00000000); sir_write(dev, 0x28, 0x0a000033); @@ -208,9 +199,6 @@ static void sata_init(struct device *dev) sir_write(dev, 0xc4, 0x0c0c0c0c); sir_write(dev, 0xc8, 0x0c0c0c0c); sir_write(dev, 0xd4, 0x10000000); - - pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000); - pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); } static void sata_enable(struct device *dev) diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index 95cac8123c..d31fd7028c 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -68,8 +68,8 @@ static void usb_ehci_init(struct device *dev) printk(BIOS_DEBUG, "done.\n"); } -static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { u8 access_cntl; diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 67e20be11f..2c28940c3b 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -27,6 +27,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_PMCLIB + select SOUTHBRIDGE_INTEL_COMMON_PMBASE select IOAPIC select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index 8d4c4e6e84..83c455f012 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -74,7 +74,7 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt) /* Fill the SSDT header */ memset((void *)ssdt, 0, sizeof(acpi_header_t)); memcpy(&ssdt->signature, "SSDT", 4); - ssdt->revision = 2; + ssdt->revision = get_acpi_table_revision(SSDT); memcpy(&ssdt->oem_id, OEM_ID, 6); memcpy(&ssdt->oem_table_id, "SERIALIO", 8); ssdt->oem_revision = 43; diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index b677e6a543..ddd5a2f53d 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -83,7 +83,7 @@ Device (LPCB) Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -106,15 +106,15 @@ Device (LPCB) If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) } If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) } If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } } diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index 90ff02d1f1..a21cd2d819 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -93,7 +93,7 @@ Scope(\) #include "sata.asl" // SMBus 0:1f.3 -#include "smbus.asl" +#include // Serial IO #if CONFIG(INTEL_LYNXPOINT_LP) diff --git a/src/southbridge/intel/lynxpoint/acpi/platform.asl b/src/southbridge/intel/lynxpoint/acpi/platform.asl deleted file mode 100644 index e37066887b..0000000000 --- a/src/southbridge/intel/lynxpoint/acpi/platform.asl +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} diff --git a/src/southbridge/intel/lynxpoint/acpi/sleepstates.asl b/src/southbridge/intel/lynxpoint/acpi/sleepstates.asl deleted file mode 100644 index 4d1d0b3ea2..0000000000 --- a/src/southbridge/intel/lynxpoint/acpi/sleepstates.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -// Name(\_S1, Package(){0x1,0x1,0x0,0x0}) -Name(\_S3, Package(){0x5,0x5,0x0,0x0}) -Name(\_S4, Package(){0x6,0x6,0x0,0x0}) -Name(\_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/southbridge/intel/lynxpoint/acpi/smbus.asl b/src/southbridge/intel/lynxpoint/acpi/smbus.asl deleted file mode 100644 index 268298fb4c..0000000000 --- a/src/southbridge/intel/lynxpoint/acpi/smbus.asl +++ /dev/null @@ -1,236 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Intel SMBus Controller 0:1f.3 - -Device (SBUS) -{ - Name (_ADR, 0x001f0003) - -#ifdef ENABLE_SMBUS_METHODS - OperationRegion (SMBP, PCI_Config, 0x00, 0x100) - Field(SMBP, DWordAcc, NoLock, Preserve) - { - Offset(0x40), - , 2, - I2CE, 1 - } - - OperationRegion (SMBI, SystemIO, SMBUS_IO_BASE, 0x20) - Field (SMBI, ByteAcc, NoLock, Preserve) - { - HSTS, 8, // Host Status - , 8, - HCNT, 8, // Host Control - HCMD, 8, // Host Command - TXSA, 8, // Transmit Slave Address - DAT0, 8, // Host Data 0 - DAT1, 8, // Host Data 1 - HBDB, 8, // Host Block Data Byte - PECK, 8, // Packet Error Check - RXSA, 8, // Receive Slave Address - RXDA, 16, // Receive Slave Data - AUXS, 8, // Auxiliary Status - AUXC, 8, // Auxiliary Control - SLPC, 8, // SMLink Pin Control - SBPC, 8, // SMBus Pin Control - SSTS, 8, // Slave Status - SCMD, 8, // Slave Command - NADR, 8, // Notify Device Address - NDLB, 8, // Notify Data Low Byte - NDLH, 8, // Notify Data High Byte - } - - // Kill all SMBus communication - Method (KILL, 0, Serialized) - { - Or (HCNT, 0x02, HCNT) // Send Kill - Or (HSTS, 0xff, HSTS) // Clean Status - } - - // Check if last operation completed - // return Failure = 0, Success = 1 - Method (CMPL, 0, Serialized) - { - Store (4000, Local0) // Timeout 200ms in 50us steps - While (Local0) { - If (And(HSTS, 0x02)) { // Completion Status? - Return (1) // Operation Completed - } Else { - Stall (50) - Decrement (Local0) - If (LEqual(Local0, 0)) { - KILL() - } - } - } - - Return (0) // Failure - } - - - // Wait for SMBus to become ready - Method (SRDY, 0, Serialized) - { - Store (200, Local0) // Timeout 200ms - While (Local0) { - If (And(HSTS, 0x40)) { // IN_USE? - Sleep(1) // Wait 1ms - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - Return (1) - } - } Else { - Store (0, Local0) // We're ready - } - } - - Store (4000, Local0) // Timeout 200ms (50us * 4000) - While (Local0) { - If (And (HSTS, 0x01)) { // Host Busy? - Stall(50) // Wait 50us - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - KILL() - } - } Else { - Return (0) // Success - } - } - - Return (1) // Failure - } - - // SMBus Send Byte - // Arg0: Address - // Arg1: Data - // Return: 1 = Success, 0=Failure - - Method (SSXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Data - - Store (0x48, HCNT) // Start + Byte Data Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Receive Byte - // Arg0: Address - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - - Store (0x44, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } - - - // SMBus Write Byte - // Arg0: Address - // Arg1: Command - // Arg2: Data - // Return: 1 = Success, 0=Failure - - Method (SWRB, 3, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Command - Store (Arg2, DAT0) // Write Data - - Store (0x48, HCNT) // Start + Byte Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Read Byte - // Arg0: Address - // Arg1: Command - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRDB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - Store (Arg1, HCMD) // Command - - Store (0x48, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } -#endif -} diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index d3847a5018..f5700401be 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -51,7 +51,7 @@ void enable_smbus(void) printk(BIOS_DEBUG, "SMBus controller enabled.\n"); } -int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(unsigned int device, unsigned int address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index bc8d8a1630..1919d58998 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -127,11 +127,11 @@ int get_gpio(int gpio_num) * get a number comprised of multiple GPIO values. gpio_num_array points to * the array of gpio pin numbers to scan, terminated by -1. */ -unsigned get_gpios(const int *gpio_num_array) +unsigned int get_gpios(const int *gpio_num_array) { int gpio; - unsigned bitmask = 1; - unsigned vector = 0; + unsigned int bitmask = 1; + unsigned int vector = 0; while (bitmask && ((gpio = *gpio_num_array++) != -1)) { diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index fa6d700fd9..8436243f59 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -169,7 +169,7 @@ int get_gpio(int gpio_num); * get a number comprised of multiple GPIO values. gpio_num_array points to * the array of gpio pin numbers to scan, terminated by -1. */ -unsigned get_gpios(const int *gpio_num_array); +unsigned int get_gpios(const int *gpio_num_array); void set_gpio(int gpio_num, int value); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 28e3544910..a1e026200b 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -403,7 +403,7 @@ static void enable_hpet(struct device *const dev) reg32 &= ~(3 << 0); RCBA32(HPTC) = reg32; /* Read it back to stick. It's affected by posted write syndrome. */ - reg32 = RCBA32(HPTC); + RCBA32(HPTC); } static void enable_clock_gating(struct device *dev) @@ -981,7 +981,7 @@ static struct device_operations device_ops = { .init = lpc_init, .final = lpc_final, .enable = pch_lpc_enable, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 8d86e68227..59a8666547 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -34,6 +34,7 @@ #include #include #include +#include #include "chip.h" #include "me.h" @@ -161,7 +162,7 @@ static inline u32 read_cb(void) static int mei_wait_for_me_ready(void) { struct mei_csr me; - unsigned try = ME_RETRY; + unsigned int try = ME_RETRY; while (try--) { read_me_csr(&me); @@ -201,7 +202,7 @@ static void mei_reset(void) static int mei_send_packet(struct mei_header *mei, void *req_data) { struct mei_csr host; - unsigned ndata, n; + unsigned int ndata, n; u32 *data; /* Number of dwords to write */ @@ -305,8 +306,8 @@ static int mei_recv_msg(void *header, int header_bytes, { struct mei_header mei_rsp; struct mei_csr me, host; - unsigned ndata, n; - unsigned expected; + unsigned int ndata, n; + unsigned int expected; u32 *data; /* Total number of dwords to read from circular buffer */ diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index a57bae311d..dc7b9580d9 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -197,7 +197,7 @@ void pch_disable_devfn(struct device *dev) #define IOBP_RETRY 1000 static inline int iobp_poll(void) { - unsigned try; + unsigned int try; for (try = IOBP_RETRY; try > 0; try--) { u16 status = RCBA16(IOBPS); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index be4285b1da..d83dd17275 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -177,7 +177,7 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void enable_smbus(void); #if ENV_ROMSTAGE -int smbus_read_byte(unsigned device, unsigned address); +int smbus_read_byte(unsigned int device, unsigned int address); #endif void enable_usb_bar(void); diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 1eb8e4bcc4..92dd02e2ed 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -168,7 +168,7 @@ static void root_port_init_config(struct device *dev) static void pch_pcie_device_set_func(int index, int pci_func) { struct device *dev; - unsigned new_devfn; + unsigned int new_devfn; dev = rpc.ports[index]; diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index aae48e7426..75bfbde2dd 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -144,7 +144,7 @@ static void sata_init(struct device *dev) /* Setup register 9Ch */ reg16 = 0; /* Disable alternate ID */ - reg16 = 1 << 5; /* BWG step 12 */ + reg16 |= (1 << 5); /* BWG step 12 */ pci_write_config16(dev, 0x9c, reg16); /* SATA Initialization register */ diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c index 02d70a694d..2293392d46 100644 --- a/src/southbridge/nvidia/ck804/ck804.c +++ b/src/southbridge/nvidia/ck804/ck804.c @@ -22,7 +22,7 @@ static u32 final_reg; -static struct device *find_lpc_dev(struct device *dev, unsigned devfn) +static struct device *find_lpc_dev(struct device *dev, unsigned int devfn) { struct device *lpc_dev; @@ -54,7 +54,7 @@ static struct device *find_lpc_dev(struct device *dev, unsigned devfn) static void ck804_enable(struct device *dev) { struct device *lpc_dev; - unsigned index = 0, index2 = 0, deviceid, vendorid, devfn; + unsigned int index = 0, index2 = 0, deviceid, vendorid, devfn; u32 reg_old, reg; u8 byte; @@ -179,8 +179,8 @@ static void ck804_enable(struct device *dev) } } -static void ck804_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void ck804_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h index 6812b5b653..c4c4c4f91a 100644 --- a/src/southbridge/nvidia/ck804/ck804.h +++ b/src/southbridge/nvidia/ck804/ck804.h @@ -26,6 +26,6 @@ #define CK804B_BUSN 0x80 #define CK804B_DEVN_BASE (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) ? CK804_DEVN_BASE : 1) -void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); +void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn); #endif diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index e2cc40a986..bbd8210d21 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -17,7 +17,6 @@ */ #include -#include #include #include #include @@ -25,20 +24,20 @@ #include "ck804.h" /* Someone messed up and snuck in some K8-specific code */ -static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val) { return 0; /* stub */}; +static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned int vendorid, unsigned int val) { return 0; /* stub */}; static int set_ht_link_ck804(u8 ht_c_num) { - unsigned vendorid = 0x10de; - unsigned val = 0x01610169; + unsigned int vendorid = 0x10de; + unsigned int val = 0x01610169; return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); } -static void setup_ss_table(unsigned index, unsigned where, unsigned control, +static void setup_ss_table(unsigned int index, unsigned int where, unsigned int control, const unsigned int *register_values, int max) { int i; - unsigned val; + unsigned int val; val = inl(control); val &= 0xfffffffe; @@ -78,8 +77,8 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, */ #define CK804_DEV(d, f, r) PCI_ADDR(0, d, f, r) -static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, - unsigned *io_base) +static void ck804_early_set_port(unsigned int ck804_num, unsigned int *busn, + unsigned int *io_base) { static const unsigned int ctrl_devport_conf[] = { CK804_DEV(0x1, 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, @@ -98,8 +97,8 @@ static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, } } -static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, - unsigned *io_base) +static void ck804_early_clear_port(unsigned int ck804_num, unsigned int *busn, + unsigned int *io_base) { static const unsigned int ctrl_devport_conf_clear[] = { CK804_DEV(0x1, 0, ANACTRL_REG_POS), ~(0x0000ff01), 0, @@ -118,8 +117,8 @@ static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, } } -static void ck804_early_setup(unsigned ck804_num, unsigned *busn, - unsigned *io_base) +static void ck804_early_setup(unsigned int ck804_num, unsigned int *busn, + unsigned int *io_base) { static const unsigned int ctrl_conf_master[] = { RES_PCI_IO, CK804_DEV(1, 2, 0x8c), 0xffff0000, 0x00009880, @@ -338,7 +337,7 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, static int ck804_early_setup_x(void) { - unsigned busn[4], io_base[4]; + unsigned int busn[4], io_base[4]; int i, ck804_num = 0; for (i = 0; i < 4; i++) { @@ -381,7 +380,7 @@ void do_soft_reset(void) outb(0x06, 0x0cf9); } -void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn) { /* The default value for CK804 is good. */ /* Set VFSMAF (VID/FID System Management Action Field) to 2. */ diff --git a/src/southbridge/nvidia/ck804/early_smbus.c b/src/southbridge/nvidia/ck804/early_smbus.c index a310422d91..8997ef0da6 100644 --- a/src/southbridge/nvidia/ck804/early_smbus.c +++ b/src/southbridge/nvidia/ck804/early_smbus.c @@ -55,23 +55,23 @@ void enable_smbus(void) printk(BIOS_DEBUG, "SMBus controller enabled\n"); } -int ck804_smbus_read_byte(unsigned bus, unsigned device, unsigned address) +int ck804_smbus_read_byte(unsigned int bus, unsigned int device, unsigned int address) { return do_smbus_read_byte(SMBUS_BASE(bus), device, address); } -int ck804_smbus_write_byte(unsigned bus, unsigned device, unsigned address, +int ck804_smbus_write_byte(unsigned int bus, unsigned int device, unsigned int address, unsigned char val) { return do_smbus_write_byte(SMBUS_BASE(bus), device, address, val); } -int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(unsigned int device, unsigned int address) { return ck804_smbus_read_byte(0, device, address); } -int smbus_write_byte(unsigned device, unsigned address, unsigned char val) +int smbus_write_byte(unsigned int device, unsigned int address, unsigned char val) { return ck804_smbus_write_byte(0, device, address, val); } diff --git a/src/southbridge/nvidia/ck804/early_smbus.h b/src/southbridge/nvidia/ck804/early_smbus.h index 5aacd93214..30c4b02fa5 100644 --- a/src/southbridge/nvidia/ck804/early_smbus.h +++ b/src/southbridge/nvidia/ck804/early_smbus.h @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -int ck804_smbus_read_byte(unsigned int, unsigned int, unsigned); +int ck804_smbus_read_byte(unsigned int, unsigned int, unsigned int); int ck804_smbus_write_byte(unsigned int, unsigned int, unsigned int, unsigned char); void enable_smbus(void); int smbus_read_byte(unsigned int, unsigned int); diff --git a/src/southbridge/nvidia/ck804/fadt.c b/src/southbridge/nvidia/ck804/fadt.c index 713a51ea0a..55f98bffce 100644 --- a/src/southbridge/nvidia/ck804/fadt.c +++ b/src/southbridge/nvidia/ck804/fadt.c @@ -22,7 +22,7 @@ #include #include -extern unsigned pm_base; /* pm_base should be set in sb acpi */ +extern unsigned int pm_base; /* pm_base should be set in sb acpi */ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 8caa8ed1ee..b8aec2667d 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -97,7 +97,7 @@ static void rom_dummy_write(struct device *dev) pci_write_config8(dev, 0x6d, new); } -unsigned pm_base = 0; +unsigned int pm_base = 0; static void lpc_init(struct device *dev) { @@ -314,7 +314,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &ck804_pci_ops, }; diff --git a/src/southbridge/nvidia/ck804/sata.c b/src/southbridge/nvidia/ck804/sata.c index c5dc56e83e..9abd6d26ba 100644 --- a/src/southbridge/nvidia/ck804/sata.c +++ b/src/southbridge/nvidia/ck804/sata.c @@ -27,7 +27,7 @@ #endif #if CK804_SATA_RESET_FOR_ATAPI -static void sata_com_reset(struct device *dev, unsigned reset) +static void sata_com_reset(struct device *dev, unsigned int reset) // reset = 1 : reset // reset = 0 : clear { diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index b96dc6e6d4..9737d0070f 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -23,7 +23,7 @@ static int lsmbus_recv_byte(struct device *dev) { - unsigned device; + unsigned int device; struct resource *res; struct bus *pbus; @@ -37,7 +37,7 @@ static int lsmbus_recv_byte(struct device *dev) static int lsmbus_send_byte(struct device *dev, u8 val) { - unsigned device; + unsigned int device; struct resource *res; struct bus *pbus; @@ -51,7 +51,7 @@ static int lsmbus_send_byte(struct device *dev, u8 val) static int lsmbus_read_byte(struct device *dev, u8 address) { - unsigned device; + unsigned int device; struct resource *res; struct bus *pbus; @@ -65,7 +65,7 @@ static int lsmbus_read_byte(struct device *dev, u8 address) static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) { - unsigned device; + unsigned int device; struct resource *res; struct bus *pbus; diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h index bf0ff3c719..9aad5e14f0 100644 --- a/src/southbridge/nvidia/ck804/smbus.h +++ b/src/southbridge/nvidia/ck804/smbus.h @@ -35,7 +35,7 @@ static inline void smbus_delay(void) outb(0x80, 0x80); } -static int smbus_wait_until_done(unsigned smbus_io_base) +static int smbus_wait_until_done(unsigned int smbus_io_base) { unsigned long loops; loops = SMBUS_TIMEOUT; @@ -52,7 +52,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base) /* Platform has severe issues placing non-inlined functions in headers. */ #if ENV_RAMSTAGE -static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) +static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device) { unsigned char global_status_register, byte; @@ -85,10 +85,10 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) return byte; } -static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, +static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device, unsigned char val) { - unsigned global_status_register; + unsigned int global_status_register; outb(val, smbus_io_base + SMBHSTDAT0); smbus_delay(); @@ -118,8 +118,8 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, } #endif /* ENV_RAMSTAGE */ -static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, - unsigned address) +static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device, + unsigned int address) { unsigned char global_status_register, byte; @@ -152,10 +152,10 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, return byte; } -static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, - unsigned address, unsigned char val) +static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device, + unsigned int address, unsigned char val) { - unsigned global_status_register; + unsigned int global_status_register; outb(val, smbus_io_base + SMBHSTDAT0); smbus_delay(); diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index 092280b4af..042dfa0b0f 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -38,7 +38,7 @@ void do_board_reset(void) outb(0x0e, 0x0cf9); } -void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn) { /* The default value for MCP55 is good. */ /* Set VFSMAF (VID/FID System Management Action Field) to 2. */ diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 69d12bfad7..85198ad7c3 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -21,21 +21,21 @@ #include #ifdef UNUSED_CODE -int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val); +int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned int vendorid, unsigned int val); static int set_ht_link_mcp55(u8 ht_c_num) { - unsigned vendorid = 0x10de; - unsigned val = 0x01610109; + unsigned int vendorid = 0x10de; + unsigned int val = 0x01610109; /* NVIDIA MCP55 hardcode, hardware can not set it automatically. */ return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); } -static void setup_ss_table(unsigned index, unsigned where, unsigned control, +static void setup_ss_table(unsigned int index, unsigned int where, unsigned int control, const unsigned int *register_values, int max) { int i; - unsigned val; + unsigned int val; val = inl(control); val &= 0xfffffffe; @@ -82,8 +82,8 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, */ #define MCP55_DEV(d, f, r) PCI_ADDR(0, d, f, r) -static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, - unsigned *devn, unsigned *io_base) +static void mcp55_early_set_port(unsigned int mcp55_num, unsigned int *busn, + unsigned int *devn, unsigned int *io_base) { static const unsigned int ctrl_devport_conf[] = { @@ -100,8 +100,8 @@ static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, } } -static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, - unsigned *devn, unsigned *io_base) +static void mcp55_early_clear_port(unsigned int mcp55_num, unsigned int *busn, + unsigned int *devn, unsigned int *io_base) { static const unsigned int ctrl_devport_conf_clear[] = { MCP55_DEV(1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0, @@ -117,8 +117,8 @@ static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, } } -static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, - unsigned anactrl_io_base, unsigned pci_e_x) +static void mcp55_early_pcie_setup(unsigned int busnx, unsigned int devnx, + unsigned int anactrl_io_base, unsigned int pci_e_x) { u32 tgio_ctrl, pll_ctrl, dword; int i; @@ -156,9 +156,9 @@ static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, mdelay(100); /* Need to wait 100ms. */ } -static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, - unsigned *devn, unsigned *io_base, - unsigned *pci_e_x) +static void mcp55_early_setup(unsigned int mcp55_num, unsigned int *busn, + unsigned int *devn, unsigned int *io_base, + unsigned int *pci_e_x) { static const unsigned int ctrl_conf_1[] = { RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000, @@ -348,21 +348,21 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, static int mcp55_early_setup_x(void) { /* Find out how many MCP55 we have. */ - unsigned busn[HT_CHAIN_NUM_MAX] = {0}; - unsigned devn[HT_CHAIN_NUM_MAX] = {0}; - unsigned io_base[HT_CHAIN_NUM_MAX] = {0}; + unsigned int busn[HT_CHAIN_NUM_MAX] = {0}; + unsigned int devn[HT_CHAIN_NUM_MAX] = {0}; + unsigned int io_base[HT_CHAIN_NUM_MAX] = {0}; /* * FIXME: May have problem if there is different MCP55 HTX card with * different PCI_E lane allocation. Need to use same trick about * pci1234 to verify node/link connection. */ - unsigned pci_e_x[HT_CHAIN_NUM_MAX] = { + unsigned int pci_e_x[HT_CHAIN_NUM_MAX] = { CONFIG_MCP55_PCI_E_X_0, CONFIG_MCP55_PCI_E_X_1, CONFIG_MCP55_PCI_E_X_2, CONFIG_MCP55_PCI_E_X_3, }; int mcp55_num = 0, ht_c_index; - unsigned busnx, devnx; + unsigned int busnx, devnx; /* FIXME: Multi PCI segment handling. */ diff --git a/src/southbridge/nvidia/mcp55/early_smbus.c b/src/southbridge/nvidia/mcp55/early_smbus.c index fe9ccdd746..1b49456a18 100644 --- a/src/southbridge/nvidia/mcp55/early_smbus.c +++ b/src/southbridge/nvidia/mcp55/early_smbus.c @@ -48,48 +48,48 @@ void enable_smbus(void) outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT); } -int smbus_recv_byte(unsigned device) +int smbus_recv_byte(unsigned int device) { return do_smbus_recv_byte(SMBUS0_IO_BASE, device); } -int smbus_send_byte(unsigned device, unsigned char val) +int smbus_send_byte(unsigned int device, unsigned char val) { return do_smbus_send_byte(SMBUS0_IO_BASE, device, val); } -int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(unsigned int device, unsigned int address) { return do_smbus_read_byte(SMBUS0_IO_BASE, device, address); } -int smbus_write_byte(unsigned device, unsigned address, +int smbus_write_byte(unsigned int device, unsigned int address, unsigned char val) { return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val); } -int smbusx_recv_byte(unsigned smb_index, unsigned device) +int smbusx_recv_byte(unsigned int smb_index, unsigned int device) { return do_smbus_recv_byte(SMBUS0_IO_BASE + (smb_index << 8), device); } -int smbusx_send_byte(unsigned smb_index, unsigned device, +int smbusx_send_byte(unsigned int smb_index, unsigned int device, unsigned char val) { return do_smbus_send_byte(SMBUS0_IO_BASE + (smb_index << 8), device, val); } -int smbusx_read_byte(unsigned smb_index, unsigned device, - unsigned address) +int smbusx_read_byte(unsigned int smb_index, unsigned int device, + unsigned int address) { return do_smbus_read_byte(SMBUS0_IO_BASE + (smb_index << 8), device, address); } -int smbusx_write_byte(unsigned smb_index, unsigned device, - unsigned address, unsigned char val) +int smbusx_write_byte(unsigned int smb_index, unsigned int device, + unsigned int address, unsigned char val) { return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index << 8), device, address, val); diff --git a/src/southbridge/nvidia/mcp55/fadt.c b/src/southbridge/nvidia/mcp55/fadt.c index 6aaa7026a5..16f0df85de 100644 --- a/src/southbridge/nvidia/mcp55/fadt.c +++ b/src/southbridge/nvidia/mcp55/fadt.c @@ -23,7 +23,7 @@ #include #include -extern unsigned pm_base; +extern unsigned int pm_base; /* Create the Fixed ACPI Description Tables (FADT) for this board. */ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) @@ -39,7 +39,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 1; + header->revision = ACPI_FADT_REV_ACPI_1_0; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 6416dd37b0..de2de5c090 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -247,7 +247,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &mcp55_pci_ops, }; static const unsigned short lpc_ids[] = { diff --git a/src/southbridge/nvidia/mcp55/mcp55.c b/src/southbridge/nvidia/mcp55/mcp55.c index bd49d9be5f..db646cd659 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.c +++ b/src/southbridge/nvidia/mcp55/mcp55.c @@ -25,7 +25,7 @@ static u32 final_reg; -static struct device *find_lpc_dev(struct device *dev, unsigned devfn) +static struct device *find_lpc_dev(struct device *dev, unsigned int devfn) { struct device *lpc_dev; @@ -55,10 +55,10 @@ static struct device *find_lpc_dev(struct device *dev, unsigned devfn) void mcp55_enable(struct device *dev) { struct device *lpc_dev = NULL, *sm_dev = NULL; - unsigned index = 0, index2 = 0; + unsigned int index = 0, index2 = 0; u32 reg_old, reg; u8 byte; - unsigned deviceid, vendorid, devfn; + unsigned int deviceid, vendorid, devfn; int i; if (dev->device == 0x0000) { @@ -217,8 +217,8 @@ void mcp55_enable(struct device *dev) } } -static void mcp55_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void mcp55_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index ac689094ca..c3e93d3714 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -30,19 +30,19 @@ void mcp55_enable(struct device *dev); extern struct pci_operations mcp55_pci_ops; #endif -void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); +void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn); void enable_smbus(void); /* Concflict declarations with . */ #if !ENV_RAMSTAGE -int smbus_recv_byte(unsigned device); -int smbus_send_byte(unsigned device, unsigned char val); -int smbus_read_byte(unsigned device, unsigned address); -int smbus_write_byte(unsigned device, unsigned address, unsigned char val); -int smbusx_recv_byte(unsigned smb_index, unsigned device); -int smbusx_send_byte(unsigned smb_index, unsigned device, unsigned char val); -int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address); -int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address, +int smbus_recv_byte(unsigned int device); +int smbus_send_byte(unsigned int device, unsigned char val); +int smbus_read_byte(unsigned int device, unsigned int address); +int smbus_write_byte(unsigned int device, unsigned int address, unsigned char val); +int smbusx_recv_byte(unsigned int smb_index, unsigned int device); +int smbusx_send_byte(unsigned int smb_index, unsigned int device, unsigned char val); +int smbusx_read_byte(unsigned int smb_index, unsigned int device, unsigned int address); +int smbusx_write_byte(unsigned int smb_index, unsigned int device, unsigned int address, unsigned char val); #endif /* !ENV_RAMSTAGE */ diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c index af4df44293..9e350dda26 100644 --- a/src/southbridge/nvidia/mcp55/nic.c +++ b/src/southbridge/nvidia/mcp55/nic.c @@ -29,10 +29,10 @@ #include "chip.h" #include "mcp55.h" -static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg) +static int phy_read(u8 *base, unsigned int phy_addr, unsigned int phy_reg) { u32 dword; - unsigned loop = 0x100; + unsigned int loop = 0x100; write32(base + 0x190, 0x8000); /* Clear MDIO lock bit. */ mdelay(1); @@ -61,7 +61,7 @@ static void phy_detect(u8 *base) { u32 dword; int i, val; - unsigned id; + unsigned int id; dword = read32(base + 0x188); dword &= ~(1 << 20); diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 37f4a1e3f1..0f8dbe3fc5 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -26,7 +26,7 @@ static int lsmbus_recv_byte(struct device *dev) { - unsigned device; + unsigned int device; struct resource *res; struct bus *pbus; @@ -40,7 +40,7 @@ static int lsmbus_recv_byte(struct device *dev) static int lsmbus_send_byte(struct device *dev, u8 val) { - unsigned device; + unsigned int device; struct resource *res; struct bus *pbus; @@ -54,7 +54,7 @@ static int lsmbus_send_byte(struct device *dev, u8 val) static int lsmbus_read_byte(struct device *dev, u8 address) { - unsigned device; + unsigned int device; struct resource *res; struct bus *pbus; @@ -68,7 +68,7 @@ static int lsmbus_read_byte(struct device *dev, u8 address) static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) { - unsigned device; + unsigned int device; struct resource *res; struct bus *pbus; @@ -87,7 +87,7 @@ static struct smbus_bus_operations lops_smbus_bus = { }; #if CONFIG(HAVE_ACPI_TABLES) -unsigned pm_base; +unsigned int pm_base; #endif static void mcp55_sm_read_resources(struct device *dev) diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h index f2704525bb..91e48ba5fe 100644 --- a/src/southbridge/nvidia/mcp55/smbus.h +++ b/src/southbridge/nvidia/mcp55/smbus.h @@ -37,7 +37,7 @@ static inline void smbus_delay(void) outb(0x80, 0x80); } -static int smbus_wait_until_done(unsigned smbus_io_base) +static int smbus_wait_until_done(unsigned int smbus_io_base) { unsigned long loops; loops = SMBUS_TIMEOUT; @@ -52,7 +52,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base) } while (--loops); return -3; } -static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) +static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device) { unsigned char global_status_register; unsigned char byte; @@ -80,9 +80,9 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) } return byte; } -static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) +static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device, unsigned char val) { - unsigned global_status_register; + unsigned int global_status_register; outb(val, smbus_io_base + SMBHSTDAT0); smbus_delay(); @@ -110,7 +110,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned } return 0; } -static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) +static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address) { unsigned char global_status_register; unsigned char byte; @@ -142,9 +142,9 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned } -static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) +static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address, unsigned char val) { - unsigned global_status_register; + unsigned int global_status_register; outb(val, smbus_io_base + SMBHSTDAT0); smbus_delay(); diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index c94722cb52..0bcf9c5f93 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -193,8 +193,8 @@ static void rl5c476_set_resources(struct device *dev) } -static void rl5c476_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void rl5c476_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { u16 miscreg = pci_read_config16(dev, 0x82); /* Enable subsystem id register writes */ diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index bfb5ab92df..1789f6e232 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -38,8 +38,8 @@ static void ti_pci1x2y_init(struct device *dev) pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02); } -static void ti_pci1x2y_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void ti_pci1x2y_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { /* * Enable change sub-vendor ID. Clear the bit 5 to enable to write diff --git a/src/southbridge/ti/pci7420/cardbus.c b/src/southbridge/ti/pci7420/cardbus.c index 2c5679b931..44a38ea05c 100644 --- a/src/southbridge/ti/pci7420/cardbus.c +++ b/src/southbridge/ti/pci7420/cardbus.c @@ -111,12 +111,6 @@ static const struct pci_driver ti_pci7620_driver __pci_driver = { .device = 0xac8d, }; -static void ti_pci7420_enable_dev(struct device *dev) -{ - /* Nothing here yet */ -} - struct chip_operations southbridge_ti_pci7420_ops = { CHIP_NAME("Texas Instruments PCI7420/7620 Cardbus Controller") - .enable_dev = ti_pci7420_enable_dev, }; diff --git a/src/southbridge/ti/pci7420/firewire.c b/src/southbridge/ti/pci7420/firewire.c index 4058540959..dac273a9e0 100644 --- a/src/southbridge/ti/pci7420/firewire.c +++ b/src/southbridge/ti/pci7420/firewire.c @@ -48,13 +48,3 @@ static const struct pci_driver ti_pci7420_driver __pci_driver = { .vendor = 0x104c, .device = 0x802e, }; - -static void ti_pci7420_firewire_enable_dev(struct device *dev) -{ - /* Nothing here yet */ -} - -struct chip_operations southbridge_ti_pci7420_firewire_ops = { - CHIP_NAME("Texas Instruments PCI7420/7620 FireWire (IEEE 1394)") - .enable_dev = ti_pci7420_firewire_enable_dev, -}; diff --git a/src/superio/acpi/pnp_generic.asl b/src/superio/acpi/pnp_generic.asl index 980404efdd..dbae2ac902 100644 --- a/src/superio/acpi/pnp_generic.asl +++ b/src/superio/acpi/pnp_generic.asl @@ -20,9 +20,9 @@ * * Controlled by the following preprocessor defines: * - * SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required) + * SUPERIO_CHIP_NAME The name of the Super I/O chip (unique, required) * SUPERIO_PNP_HID The EisaId string that identifies this device (optional) - * SUPERIO_PNP_LDN The logical device number on the super i/o + * SUPERIO_PNP_LDN The logical device number on the Super I/O * chip for this device (required) * SUPERIO_PNP_DDN A string literal that identifies the dos device * name (DDN) of this device (e.g. "COM1", optional) diff --git a/src/superio/acpi/pnp_kbc.asl b/src/superio/acpi/pnp_kbc.asl index cbcfd55910..541dce3c89 100644 --- a/src/superio/acpi/pnp_kbc.asl +++ b/src/superio/acpi/pnp_kbc.asl @@ -22,8 +22,8 @@ * * Controlled by the following preprocessor defines: * - * SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required) - * SUPERIO_KBC_LDN The logical device number on the super i/o + * SUPERIO_CHIP_NAME The name of the Super I/O chip (unique, required) + * SUPERIO_KBC_LDN The logical device number on the Super I/O * chip for this keyboard controller (required) * SUPERIO_KBC_PS2M If defined, PS/2 mouse support is included in * the KBC_LDN. Mouse irq is set at IRQ1 of the diff --git a/src/superio/acpi/pnp_uart.asl b/src/superio/acpi/pnp_uart.asl index f42cc42039..3cbe65aa05 100644 --- a/src/superio/acpi/pnp_uart.asl +++ b/src/superio/acpi/pnp_uart.asl @@ -21,8 +21,8 @@ * * Controlled by the following preprocessor defines: * - * SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required) - * SUPERIO_UART_LDN The logical device number on the super i/o + * SUPERIO_CHIP_NAME The name of the Super I/O chip (unique, required) + * SUPERIO_UART_LDN The logical device number on the Super I/O * chip for this UART (required) * SUPERIO_UART_DDN A string literal that identifies the dos device * name (DDN) of this uart (e.g. "COM1", optional) diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index 54f3f3430d..c5df8b5833 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -15,12 +15,9 @@ * GNU General Public License for more details. */ -#include #include #include #include -#include -#include #include #include #include diff --git a/src/superio/aspeed/common/Kconfig b/src/superio/aspeed/common/Kconfig index 3f0dabb853..f310f3ef98 100644 --- a/src/superio/aspeed/common/Kconfig +++ b/src/superio/aspeed/common/Kconfig @@ -20,3 +20,20 @@ config SUPERIO_ASPEED_COMMON_PRE_RAM bool default n + +config SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND + bool + default n + +config SUPERIO_ASPEED_USE_UART_DELAY_WORKAROUND + bool "Workaround for BMC serial console setup bug" + depends on CONSOLE_SERIAL && SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND + default y + help + Some mainboards with an ASPEED BMC have scrambled console output in early boot phases + because the serial output routing is not set up fast enough by the BMC. By enabling + this a delay of 500ms gets added before setting up the console and before any console + output gets printed. + + Note: this problem may disappear with future BMC firmware versions. Another approach + is using a different BMC firmware like OpenBMC, u-bmc, ... diff --git a/src/superio/aspeed/common/aspeed.h b/src/superio/aspeed/common/aspeed.h index d3774eab3e..8c54b0c750 100644 --- a/src/superio/aspeed/common/aspeed.h +++ b/src/superio/aspeed/common/aspeed.h @@ -18,7 +18,6 @@ #ifndef SUPERIO_ASPEED_COMMON_ROMSTAGE_H #define SUPERIO_ASPEED_COMMON_ROMSTAGE_H -#include #include #include diff --git a/src/superio/aspeed/common/early_serial.c b/src/superio/aspeed/common/early_serial.c index 7ac9474bcc..d2de8ed322 100644 --- a/src/superio/aspeed/common/early_serial.c +++ b/src/superio/aspeed/common/early_serial.c @@ -35,6 +35,7 @@ */ #include +#include #include #include #include @@ -67,4 +68,7 @@ void aspeed_enable_serial(pnp_devfn_t dev, u16 iobase) pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); pnp_exit_conf_state(dev); + + if (CONFIG(SUPERIO_ASPEED_USE_UART_DELAY_WORKAROUND)) + mdelay(500); } diff --git a/src/superio/common/generic.c b/src/superio/common/generic.c index 96307a3988..429ee51319 100644 --- a/src/superio/common/generic.c +++ b/src/superio/common/generic.c @@ -15,7 +15,6 @@ #include #include #include -#include #include static void generic_set_resources(struct device *dev) @@ -187,7 +186,7 @@ static void enable_dev(struct device *dev) * Need to call enable_dev() on the devices "behind" the Generic Super I/O. * coreboot's generic allocator doesn't expect them behind PnP devices. */ - scan_static_bus(dev); + enable_static_devices(dev); } struct chip_operations superio_common_ops = { diff --git a/src/superio/fintek/common/fan_control.h b/src/superio/fintek/common/fan_control.h index fbe784bfa1..c3167782be 100644 --- a/src/superio/fintek/common/fan_control.h +++ b/src/superio/fintek/common/fan_control.h @@ -18,7 +18,6 @@ #define SUPERIO_FINTEK_FAN_CONTROL_H #include -#include typedef enum { IGNORE_SENSOR = 0, diff --git a/src/superio/fintek/f71805f/Makefile.inc b/src/superio/fintek/f71805f/Makefile.inc deleted file mode 100644 index 26b23f64f3..0000000000 --- a/src/superio/fintek/f71805f/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Corey Osgood -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_FINTEK_F71805F) += superio.c diff --git a/src/superio/fintek/f71805f/f71805f.h b/src/superio/fintek/f71805f/f71805f.h deleted file mode 100644 index b4ca60a006..0000000000 --- a/src/superio/fintek/f71805f/f71805f.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_FINTEK_F71805F_H -#define SUPERIO_FINTEK_F71805F_H - -/* - * Datasheet: - * - Name: F71805F/FG Super H/W Monitor + LPC IO - * - URL: http://www.fintek.com.tw/eng/products.asp?BID=1&SID=17 - * - PDF: http://www.fintek.com.tw/files/productfiles/F71805F_V025.pdf - * - Revision: V0.25P - */ - -/* Logical Device Numbers (LDN). */ -#define F71805F_FDC 0x00 /* Floppy */ -#define F71805F_SP1 0x01 /* UART1 */ -#define F71805F_SP2 0x02 /* UART2 */ -#define F71805F_PP 0x03 /* Parallel port */ -#define F71805F_HWM 0x04 /* Hardware monitor */ -#define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */ -#define F71805F_PME 0x0a /* Power Management Events (PME) */ - -#endif /* SUPERIO_FINTEK_F71805F_H */ diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c deleted file mode 100644 index 4719923e97..0000000000 --- a/src/superio/fintek/f71805f/superio.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Corey Osgood - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "f71805f.h" - -static void f71805f_init(struct device *dev) -{ - if (!dev->enabled) - return; - - /* TODO: Might potentially need code for HWM or FDC etc. */ -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = f71805f_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - /* TODO: Some of the 0x07f8 etc. values may not be correct. */ - { NULL, F71805F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, F71805F_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, F71805F_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, F71805F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, F71805F_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, - { NULL, F71805F_GPIO, PNP_IRQ0, }, - { NULL, F71805F_PME, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_fintek_f71805f_ops = { - CHIP_NAME("Fintek F71805F/FG Super I/O") - .enable_dev = enable_dev -}; diff --git a/src/superio/fintek/f71808a/superio.c b/src/superio/fintek/f71808a/superio.c index 200b21edf2..05132cc0ea 100644 --- a/src/superio/fintek/f71808a/superio.c +++ b/src/superio/fintek/f71808a/superio.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include "f71808a.h" diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c index da998d0197..2cd1bb1d81 100644 --- a/src/superio/fintek/f71859/superio.c +++ b/src/superio/fintek/f71859/superio.c @@ -18,7 +18,6 @@ #include #include #include -#include #include "f71859.h" static void f71859_init(struct device *dev) diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index a5cd632e49..5a33a716cd 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -17,8 +17,8 @@ #include #include #include -#include #include + #include "f71863fg.h" static void f71863fg_init(struct device *dev) diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 15fdf3ef22..67b39ef066 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include "fintek_internal.h" diff --git a/src/superio/fintek/f71872/Kconfig b/src/superio/fintek/f71872/Kconfig deleted file mode 100644 index 516ff0944d..0000000000 --- a/src/superio/fintek/f71872/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_FINTEK_F71872 - bool - select SUPERIO_FINTEK_COMMON_PRE_RAM diff --git a/src/superio/fintek/f71872/Makefile.inc b/src/superio/fintek/f71872/Makefile.inc deleted file mode 100644 index 7237d0b6bf..0000000000 --- a/src/superio/fintek/f71872/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Corey Osgood -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_FINTEK_F71872) += superio.c diff --git a/src/superio/fintek/f71872/f71872.h b/src/superio/fintek/f71872/f71872.h deleted file mode 100644 index afd238c12e..0000000000 --- a/src/superio/fintek/f71872/f71872.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_FINTEK_F71872_H -#define SUPERIO_FINTEK_F71872_H - -/* Logical Device Numbers (LDN). */ -#define F71872_FDC 0x00 /* Floppy */ -#define F71872_SP1 0x01 /* UART1 */ -#define F71872_SP2 0x02 /* UART2 */ -#define F71872_PP 0x03 /* Parallel Port */ -#define F71872_HWM 0x04 /* Hardware Monitor */ -#define F71872_KBC 0x05 /* Keyboard/Mouse */ -#define F71872_GPIO 0x06 /* GPIO */ -#define F71872_VID 0x07 /* VID */ -#define F71872_PM 0x0a /* ACPI/PME */ - -#endif /* SUPERIO_FINTEK_F71872_H */ diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c deleted file mode 100644 index 3316ee2e3c..0000000000 --- a/src/superio/fintek/f71872/superio.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Corey Osgood - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "f71872.h" - -static void f71872_init(struct device *dev) -{ - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - /* TODO: Might potentially need code for HWM or FDC etc. */ - case F71872_KBC: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = f71872_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - /* TODO: Some of the 0x07f8 etc. values may not be correct. */ - { NULL, F71872_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, F71872_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, F71872_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, F71872_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, F71872_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, - { NULL, F71872_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, }, - { NULL, F71872_GPIO, PNP_IRQ0, }, - { NULL, F71872_VID, PNP_IO0, 0x0ff8, }, - { NULL, F71872_PM, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_fintek_f71872_ops = { - CHIP_NAME("Fintek F71872 Super I/O") - .enable_dev = enable_dev -}; diff --git a/src/superio/fintek/f81216h/superio.c b/src/superio/fintek/f81216h/superio.c index e55ec5776b..106ab0ea42 100644 --- a/src/superio/fintek/f81216h/superio.c +++ b/src/superio/fintek/f81216h/superio.c @@ -19,7 +19,6 @@ #include #include #include -#include #include "chip.h" #include "f81216h.h" diff --git a/src/superio/fintek/f81803a/fan_control.c b/src/superio/fintek/f81803a/fan_control.c index 17ae9c6a20..41fd0d3d50 100644 --- a/src/superio/fintek/f81803a/fan_control.c +++ b/src/superio/fintek/f81803a/fan_control.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include "../common/fan_control.h" #include "f81803a_hwm.h" diff --git a/src/superio/fintek/f81803a/superio.c b/src/superio/fintek/f81803a/superio.c index a07b69e97e..1cb31bfa9b 100644 --- a/src/superio/fintek/f81803a/superio.c +++ b/src/superio/fintek/f81803a/superio.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include "f81803a.h" diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c index b6156ee8c3..d62fc82793 100644 --- a/src/superio/fintek/f81865f/superio.c +++ b/src/superio/fintek/f81865f/superio.c @@ -17,8 +17,8 @@ #include #include #include -#include #include + #include "f81865f.h" static void f81865f_init(struct device *dev) diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c index 53a5aacb8d..c66bf27745 100644 --- a/src/superio/fintek/f81866d/superio.c +++ b/src/superio/fintek/f81866d/superio.c @@ -19,8 +19,8 @@ #include #include #include -#include #include + #include "f81866d.h" #include "fintek_internal.h" diff --git a/src/superio/intel/i8900/Makefile.inc b/src/superio/intel/i8900/Makefile.inc deleted file mode 100644 index 562d5d1128..0000000000 --- a/src/superio/intel/i8900/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Arastra, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-$(CONFIG_SUPERIO_INTEL_I8900) += early_serial.c -romstage-$(CONFIG_SUPERIO_INTEL_I8900) += early_serial.c -ramstage-$(CONFIG_SUPERIO_INTEL_I8900) += superio.c diff --git a/src/superio/intel/i8900/early_serial.c b/src/superio/intel/i8900/early_serial.c deleted file mode 100644 index 681b22599d..0000000000 --- a/src/superio/intel/i8900/early_serial.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "i8900.h" - -static void pnp_enter_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - - outb(0x80, port); - outb(0x86, port); -} - -static void pnp_exit_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - - outb(0x68, port); - outb(0x08, port); -} - -/* Enable device interrupts, set UART_CLK predivide. */ -void i8900_configure_uart_clk(pnp_devfn_t dev, u8 predivide) -{ - pnp_enter_ext_func_mode(dev); - pnp_write_config(dev, I8900_SIW_CONFIGURATION, - (predivide << 2) | I8900_ENABLE_SIRQ); - pnp_exit_ext_func_mode(dev); -} - -void i8900_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} - -void i8900_enable_wdt(pnp_devfn_t dev, u16 iobase) -{ - /* Enable WDT */ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/intel/i8900/i8900.h b/src/superio/intel/i8900/i8900.h deleted file mode 100644 index 348d3c4a2f..0000000000 --- a/src/superio/intel/i8900/i8900.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_INTEL_I8900_I8900_H -#define SUPERIO_INTEL_I8900_I8900_H - -#include - -/* - * The SIW ("Serial I/O and Watchdog Timer") integrated into the i8900 is - * very similar to a Super I/O, both in functionality and config mechanism. - * - * The SIW contains: - * - UART(s) - * - Serial interrupt controller - * - Watchdog timer (WDT) - * - LPC interface - */ - -/* Logical device numbers (LDNs). */ -#define I8900_SP1 0x04 /* Com1 */ -#define I8900_SP2 0x05 /* Com2 */ -#define I8900_WDT 0x06 /* Watchdog timer */ - -/* Registers and bit definitions: */ - -#define I8900_SIW_CONFIGURATION 0x29 - -/* - * SIW_CONFIGURATION[3:2] = UART_CLK predivide - * 00: divide by 1 - * 01: divide by 8 - * 10: divide by 26 - * 11: reserved - */ -#define I8900_UART_CLK_PREDIVIDE_1 0x00 -#define I8900_UART_CLK_PREDIVIDE_8 0x01 -#define I8900_UART_CLK_PREDIVIDE_26 0x02 -#define I8900_ENABLE_SIRQ 0x01 - -void i8900_configure_uart_clk(pnp_devfn_t dev, u8 predivide); -void i8900_enable_serial(pnp_devfn_t dev, u16 iobase); -void i8900_enable_wdt(pnp_devfn_t dev, u16 iobase); - -#endif diff --git a/src/superio/intel/i8900/superio.c b/src/superio/intel/i8900/superio.c deleted file mode 100644 index 24805bcf43..0000000000 --- a/src/superio/intel/i8900/superio.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "i8900.h" -#include - -static void pnp_enter_ext_func_mode(struct device *dev) -{ - outb(0x80, dev->path.pnp.port); - outb(0x86, dev->path.pnp.port); -} - -static void pnp_exit_ext_func_mode(struct device *dev) -{ - outb(0x68, dev->path.pnp.port); - outb(0x08, dev->path.pnp.port); -} - -static void i8900_init(struct device *dev) -{ - if (!dev->enabled) - return; -} - -static void i8900_pnp_set_resources(struct device *dev) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_resources(dev); - pnp_exit_ext_func_mode(dev); -} - -static void i8900_pnp_enable_resources(struct device *dev) -{ - pnp_enter_ext_func_mode(dev); - pnp_enable_resources(dev); - pnp_exit_ext_func_mode(dev); -} - -static void i8900_pnp_enable(struct device *dev) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, !!dev->enabled); - pnp_exit_ext_func_mode(dev); -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = i8900_pnp_set_resources, - .enable_resources = i8900_pnp_enable_resources, - .enable = i8900_pnp_enable, - .init = i8900_init, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, I8900_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, I8900_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, I8900_WDT, PNP_IO0 | PNP_IRQ0, 0x07f8, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_intel_i8900_ops = { - CHIP_NAME("Intel 8900 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 1b93036845..9d7594fc42 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -17,26 +17,14 @@ * GNU General Public License for more details. */ -#include -#include #include #include +#include +#include #include "env_ctrl.h" #include "env_ctrl_chip.h" -static inline u8 ite_ec_read(const u16 base, const u8 addr) -{ - outb(addr, base + 5); - return inb(base + 6); -} - -static inline void ite_ec_write(const u16 base, const u8 addr, const u8 value) -{ - outb(addr, base + 5); - outb(value, base + 6); -} - static void extemp_force_idle_status(const u16 base) { u8 reg; @@ -44,7 +32,7 @@ static void extemp_force_idle_status(const u16 base) /* Wait up to 10ms for non-busy state. */ while (retries > 0) { - reg = ite_ec_read(base, ITE_EC_EXTEMP_STATUS); + reg = pnp_read_hwm5_index(base, ITE_EC_EXTEMP_STATUS); if ((reg & ITE_EC_EXTEMP_STATUS_HOST_BUSY) == 0x0) break; @@ -59,9 +47,8 @@ static void extemp_force_idle_status(const u16 base) * SIO is busy due to unfinished peci transaction. * Re-configure Register 0x8E to terminate processes. */ - ite_ec_write(base, ITE_EC_EXTEMP_CONTROL, - ITE_EC_EXTEMP_CTRL_AUTO_4HZ | - ITE_EC_EXTEMP_CTRL_AUTO_START); + pnp_write_hwm5_index(base, ITE_EC_EXTEMP_CONTROL, + ITE_EC_EXTEMP_CTRL_AUTO_4HZ | ITE_EC_EXTEMP_CTRL_AUTO_START); } } @@ -71,22 +58,16 @@ static void extemp_force_idle_status(const u16 base) static void enable_peci(const u16 base) { /* Enable PECI interface */ - ite_ec_write(base, ITE_EC_INTERFACE_SELECT, - ITE_EC_INTERFACE_SEL_PECI | - ITE_EC_INTERFACE_SPEED_TOLERANCE); + pnp_write_hwm5_index(base, ITE_EC_INTERFACE_SELECT, + ITE_EC_INTERFACE_SEL_PECI | ITE_EC_INTERFACE_SPEED_TOLERANCE); /* Setup External Temperature using PECI GetTemp */ - ite_ec_write(base, ITE_EC_EXTEMP_ADDRESS, - PECI_CLIENT_ADDRESS); - ite_ec_write(base, ITE_EC_EXTEMP_COMMAND, - PECI_GETTEMP_COMMAND); - ite_ec_write(base, ITE_EC_EXTEMP_WRITE_LENGTH, - PECI_GETTEMP_WRITE_LENGTH); - ite_ec_write(base, ITE_EC_EXTEMP_READ_LENGTH, - PECI_GETTEMP_READ_LENGTH); - ite_ec_write(base, ITE_EC_EXTEMP_CONTROL, - ITE_EC_EXTEMP_CTRL_AUTO_4HZ | - ITE_EC_EXTEMP_CTRL_AUTO_START); + pnp_write_hwm5_index(base, ITE_EC_EXTEMP_ADDRESS, PECI_CLIENT_ADDRESS); + pnp_write_hwm5_index(base, ITE_EC_EXTEMP_COMMAND, PECI_GETTEMP_COMMAND); + pnp_write_hwm5_index(base, ITE_EC_EXTEMP_WRITE_LENGTH, PECI_GETTEMP_WRITE_LENGTH); + pnp_write_hwm5_index(base, ITE_EC_EXTEMP_READ_LENGTH, PECI_GETTEMP_READ_LENGTH); + pnp_write_hwm5_index(base, ITE_EC_EXTEMP_CONTROL, + ITE_EC_EXTEMP_CTRL_AUTO_4HZ | ITE_EC_EXTEMP_CTRL_AUTO_START); } /* @@ -98,7 +79,7 @@ static void enable_tmpin(const u16 base, const u8 tmpin, { u8 reg; - reg = ite_ec_read(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE); + reg = pnp_read_hwm5_index(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE); switch (conf->mode) { case THERMAL_PECI: @@ -122,26 +103,25 @@ static void enable_tmpin(const u16 base, const u8 tmpin, return; } - ite_ec_write(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE, reg); + pnp_write_hwm5_index(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE, reg); /* Set temperature offsets */ if (conf->mode != THERMAL_RESISTOR) { - reg = ite_ec_read(base, ITE_EC_BEEP_ENABLE); + reg = pnp_read_hwm5_index(base, ITE_EC_BEEP_ENABLE); reg |= ITE_EC_TEMP_ADJUST_WRITE_ENABLE; - ite_ec_write(base, ITE_EC_BEEP_ENABLE, reg); - ite_ec_write(base, ITE_EC_TEMP_ADJUST[tmpin-1], conf->offset); + pnp_write_hwm5_index(base, ITE_EC_BEEP_ENABLE, reg); + pnp_write_hwm5_index(base, ITE_EC_TEMP_ADJUST[tmpin-1], conf->offset); } /* Set temperature limits */ u8 max = conf->max; - ite_ec_write(base, ITE_EC_HIGH_TEMP_LIMIT(tmpin), - max ? max : 127); - ite_ec_write(base, ITE_EC_LOW_TEMP_LIMIT(tmpin), conf->min); + pnp_write_hwm5_index(base, ITE_EC_HIGH_TEMP_LIMIT(tmpin), max ? max : 127); + pnp_write_hwm5_index(base, ITE_EC_LOW_TEMP_LIMIT(tmpin), conf->min); /* Enable the startup of monitoring operation */ - reg = ite_ec_read(base, ITE_EC_CONFIGURATION); + reg = pnp_read_hwm5_index(base, ITE_EC_CONFIGURATION); reg |= ITE_EC_CONFIGURATION_START; - ite_ec_write(base, ITE_EC_CONFIGURATION, reg); + pnp_write_hwm5_index(base, ITE_EC_CONFIGURATION, reg); } static void fan_smartconfig(const u16 base, const u8 fan, @@ -177,20 +157,19 @@ static void fan_smartconfig(const u16 base, const u8 fan, if (conf->smoothing) pwm_auto |= ITE_EC_FAN_CTL_AUTO_SMOOTHING_EN; - ite_ec_write(base, ITE_EC_FAN_CTL_TEMP_LIMIT_OFF(fan), - conf->tmp_off); - ite_ec_write(base, ITE_EC_FAN_CTL_TEMP_LIMIT_START(fan), - conf->tmp_start); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_TEMP_LIMIT_OFF(fan), conf->tmp_off); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_TEMP_LIMIT_START(fan), + conf->tmp_start); /* Full speed above 127°C by default */ - ite_ec_write(base, ITE_EC_FAN_CTL_TEMP_LIMIT_FULL(fan), - conf->tmp_full ? conf->tmp_full : 127); - ite_ec_write(base, ITE_EC_FAN_CTL_DELTA_TEMP(fan), - ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(conf->tmp_delta)); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_TEMP_LIMIT_FULL(fan), + conf->tmp_full ? conf->tmp_full : 127); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_DELTA_TEMP(fan), + ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(conf->tmp_delta)); } - ite_ec_write(base, ITE_EC_FAN_CTL_PWM_CONTROL(fan), pwm_ctrl); - ite_ec_write(base, ITE_EC_FAN_CTL_PWM_START(fan), pwm_start); - ite_ec_write(base, ITE_EC_FAN_CTL_PWM_AUTO(fan), pwm_auto); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_PWM_CONTROL(fan), pwm_ctrl); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_PWM_START(fan), pwm_start); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_PWM_AUTO(fan), pwm_auto); } static void enable_fan(const u16 base, const u8 fan, @@ -205,39 +184,39 @@ static void enable_fan(const u16 base, const u8 fan, /* FAN_CTL2 might have its own frequency setting */ if (CONFIG(SUPERIO_ITE_ENV_CTRL_PWM_FREQ2) && fan == 2) { - reg = ite_ec_read(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE); + reg = pnp_read_hwm5_index(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE); reg &= ~ITE_EC_FAN_PWM_CLOCK_MASK; reg |= ITE_EC_FAN_PWM_DEFAULT_CLOCK; - ite_ec_write(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE, reg); + pnp_write_hwm5_index(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE, reg); } if (conf->mode >= FAN_SMART_SOFTWARE) { fan_smartconfig(base, fan, conf->mode, &conf->smart); } else { - reg = ite_ec_read(base, ITE_EC_FAN_CTL_MODE); + reg = pnp_read_hwm5_index(base, ITE_EC_FAN_CTL_MODE); if (conf->mode == FAN_MODE_ON) reg |= ITE_EC_FAN_CTL_ON(fan); else reg &= ~ITE_EC_FAN_CTL_ON(fan); - ite_ec_write(base, ITE_EC_FAN_CTL_MODE, reg); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_MODE, reg); } if (CONFIG(SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) && conf->mode >= FAN_MODE_ON) { - reg = ite_ec_read(base, ITE_EC_FAN_TAC_COUNTER_ENABLE); + reg = pnp_read_hwm5_index(base, ITE_EC_FAN_TAC_COUNTER_ENABLE); reg |= ITE_EC_FAN_TAC_16BIT_ENABLE(fan); - ite_ec_write(base, ITE_EC_FAN_TAC_COUNTER_ENABLE, reg); + pnp_write_hwm5_index(base, ITE_EC_FAN_TAC_COUNTER_ENABLE, reg); } if (CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS) && fan > 3) { - reg = ite_ec_read(base, ITE_EC_FAN_SEC_CTL); + reg = pnp_read_hwm5_index(base, ITE_EC_FAN_SEC_CTL); if (conf->mode >= FAN_MODE_ON) reg |= ITE_EC_FAN_SEC_CTL_TAC_EN(fan); else reg &= ~ITE_EC_FAN_SEC_CTL_TAC_EN(fan); - ite_ec_write(base, ITE_EC_FAN_SEC_CTL, reg); + pnp_write_hwm5_index(base, ITE_EC_FAN_SEC_CTL, reg); } else { - reg = ite_ec_read(base, ITE_EC_FAN_MAIN_CTL); + reg = pnp_read_hwm5_index(base, ITE_EC_FAN_MAIN_CTL); if (conf->mode >= FAN_MODE_ON) reg |= ITE_EC_FAN_MAIN_CTL_TAC_EN(fan); else @@ -250,7 +229,7 @@ static void enable_fan(const u16 base, const u8 fan, else reg &= ~ITE_EC_FAN_MAIN_CTL_SMART(fan); } - ite_ec_write(base, ITE_EC_FAN_MAIN_CTL, reg); + pnp_write_hwm5_index(base, ITE_EC_FAN_MAIN_CTL, reg); } } @@ -261,20 +240,20 @@ static void enable_beeps(const u16 base, const struct ite_ec_config *const conf) if (conf->tmpin_beep) { reg |= ITE_EC_BEEP_ON_TMP_LIMIT; - ite_ec_write(base, ITE_EC_BEEP_FREQ_DIV_OF_TMPIN, freq); + pnp_write_hwm5_index(base, ITE_EC_BEEP_FREQ_DIV_OF_TMPIN, freq); } if (conf->fan_beep) { reg |= ITE_EC_BEEP_ON_FAN_LIMIT; - ite_ec_write(base, ITE_EC_BEEP_FREQ_DIV_OF_FAN, freq); + pnp_write_hwm5_index(base, ITE_EC_BEEP_FREQ_DIV_OF_FAN, freq); } if (conf->vin_beep) { reg |= ITE_EC_BEEP_ON_VIN_LIMIT; - ite_ec_write(base, ITE_EC_BEEP_FREQ_DIV_OF_VIN, freq); + pnp_write_hwm5_index(base, ITE_EC_BEEP_FREQ_DIV_OF_VIN, freq); } if (reg) { - reg |= ite_ec_read(base, ITE_EC_BEEP_ENABLE); - ite_ec_write(base, ITE_EC_BEEP_ENABLE, reg); + reg |= pnp_read_hwm5_index(base, ITE_EC_BEEP_ENABLE); + pnp_write_hwm5_index(base, ITE_EC_BEEP_ENABLE, reg); } } @@ -283,11 +262,11 @@ void ite_ec_init(const u16 base, const struct ite_ec_config *const conf) size_t i; /* Configure 23.43kHz PWM active high output */ - u8 fan_ctl = ite_ec_read(base, ITE_EC_FAN_CTL_MODE); + u8 fan_ctl = pnp_read_hwm5_index(base, ITE_EC_FAN_CTL_MODE); fan_ctl &= ~ITE_EC_FAN_PWM_CLOCK_MASK; fan_ctl |= ITE_EC_FAN_PWM_DEFAULT_CLOCK; fan_ctl |= ITE_EC_FAN_CTL_POLARITY_HIGH; - ite_ec_write(base, ITE_EC_FAN_CTL_MODE, fan_ctl); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_MODE, fan_ctl); /* Enable HWM if configured */ for (i = 0; i < ITE_EC_TMPIN_CNT; ++i) @@ -295,13 +274,13 @@ void ite_ec_init(const u16 base, const struct ite_ec_config *const conf) /* Enable External Sensor SMBus Host if configured */ if (conf->smbus_en) { - ite_ec_write(base, ITE_EC_INTERFACE_SELECT, - ite_ec_read(base, ITE_EC_INTERFACE_SELECT) | + pnp_write_hwm5_index(base, ITE_EC_INTERFACE_SELECT, + pnp_read_hwm5_index(base, ITE_EC_INTERFACE_SELECT) | ITE_EC_INTERFACE_SMB_ENABLE); } /* Enable reading of voltage pins */ - ite_ec_write(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask); + pnp_write_hwm5_index(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask); /* Enable FANx if configured */ for (i = 0; i < ITE_EC_FAN_CNT; ++i) diff --git a/src/superio/ite/it8528e/superio.c b/src/superio/ite/it8528e/superio.c index 1ed8fe0cb5..d7169e6d4e 100644 --- a/src/superio/ite/it8528e/superio.c +++ b/src/superio/ite/it8528e/superio.c @@ -19,7 +19,6 @@ #include #include -#include #include #include "it8528e.h" diff --git a/src/superio/ite/it8623e/superio.c b/src/superio/ite/it8623e/superio.c index 5fdfceff41..044883267f 100644 --- a/src/superio/ite/it8623e/superio.c +++ b/src/superio/ite/it8623e/superio.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include diff --git a/src/superio/ite/it8671f/Kconfig b/src/superio/ite/it8671f/Kconfig deleted file mode 100644 index ba632243af..0000000000 --- a/src/superio/ite/it8671f/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_ITE_IT8671F - bool - select SUPERIO_ITE_COMMON_PRE_RAM diff --git a/src/superio/ite/it8671f/Makefile.inc b/src/superio/ite/it8671f/Makefile.inc deleted file mode 100644 index f625bc19a6..0000000000 --- a/src/superio/ite/it8671f/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 Uwe Hermann -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-$(CONFIG_SUPERIO_ITE_IT8671F) += early_serial.c -romstage-$(CONFIG_SUPERIO_ITE_IT8671F) += early_serial.c -ramstage-$(CONFIG_SUPERIO_ITE_IT8671F) += superio.c diff --git a/src/superio/ite/it8671f/early_serial.c b/src/superio/ite/it8671f/early_serial.c deleted file mode 100644 index b5b94df2fa..0000000000 --- a/src/superio/ite/it8671f/early_serial.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "it8671f.h" - -/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ -#define SIO_BASE 0x3f0 -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8671F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8671F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8671F_CONFIG_REG_LDE 0x23 /* PnP Logical Device Enable. */ -#define IT8671F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */ - -#define IT8671F_CONFIGURATION_PORT 0x0279 /* Write-only. */ - -/* - * Special values used for entering MB PnP mode. The first four bytes of - * each line determine the address port, the last four are data. - */ -static const u8 init_values[] = { - 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, - 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, - 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1, - 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, -}; - -static void it8671f_sio_write(u8 ldn, u8 index, u8 value) -{ - outb(IT8671F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -/* Enter the configuration state (MB PnP mode). */ -static void it8671f_enter_conf(void) -{ - int i; - - /* Perform MB PnP setup to put the SIO chip at 0x3f0. */ - /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ - /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */ - /* Base address 0x370: 0x86 0x80 0xaa 0x55. */ - outb(0x86, IT8671F_CONFIGURATION_PORT); - outb(0x80, IT8671F_CONFIGURATION_PORT); - outb(0x55, IT8671F_CONFIGURATION_PORT); - outb(0x55, IT8671F_CONFIGURATION_PORT); - - /* Sequentially write the 32 special values. */ - for (i = 0; i < 32; i++) - outb(init_values[i], SIO_BASE); -} - -/* Exit the configuration state (MB PnP mode). */ -static void it8671f_exit_conf(void) -{ - it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02); -} - -/* Select 48MHz CLKIN (24MHz is the default). */ -void it8671f_48mhz_clkin(void) -{ - it8671f_enter_conf(); - it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, (1 << 6)); - it8671f_exit_conf(); -} - -/* Enable the serial port(s). */ -void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - it8671f_enter_conf(); - - /* - * Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), - * PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). - */ - it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f); - - /* Enable serial port(s). */ - it8671f_sio_write(IT8671F_SP1, 0x30, 0x01); /* Serial port 1 */ - it8671f_sio_write(IT8671F_SP2, 0x30, 0x01); /* Serial port 2 */ - - it8671f_exit_conf(); -} diff --git a/src/superio/ite/it8671f/it8671f.h b/src/superio/ite/it8671f/it8671f.h deleted file mode 100644 index 5fe74bccba..0000000000 --- a/src/superio/ite/it8671f/it8671f.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_ITE_IT8671F_H -#define SUPERIO_ITE_IT8671F_H - -#include -#include - -/* Datasheet: Not available online, got it from ITE per request. */ - -#define IT8671F_FDC 0x00 /* Floppy */ -#define IT8671F_SP1 0x01 /* Com1 */ -#define IT8671F_SP2 0x02 /* Com2 */ -#define IT8671F_PP 0x03 /* Parallel port */ -#define IT8671F_KBCK 0x05 /* PS/2 keyboard */ -#define IT8671F_KBCM 0x06 /* PS/2 mouse */ - -void it8671f_48mhz_clkin(void); -void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase); - -#endif /* SUPERIO_ITE_IT8671F_H */ diff --git a/src/superio/ite/it8671f/superio.c b/src/superio/ite/it8671f/superio.c deleted file mode 100644 index 70da2ab4e4..0000000000 --- a/src/superio/ite/it8671f/superio.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "it8671f.h" - -static void init(struct device *dev) -{ - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case IT8671F_FDC: /* TODO. */ - break; - case IT8671F_PP: /* TODO. */ - break; - case IT8671F_KBCK: - pc_keyboard_init(NO_AUX_DEVICE); - break; - case IT8671F_KBCM: /* TODO. */ - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, - .ops_pnp_mode = &pnp_conf_mode_870155_aa, -}; - -/* TODO: FDC, PP, KBCM. */ -static struct pnp_info pnp_dev_info[] = { - { NULL, IT8671F_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, IT8671F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, - 0x07f8, }, - { NULL, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_ite_it8671f_ops = { - CHIP_NAME("ITE IT8671F Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index 6f096b09aa..2004236396 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include "it8712f.h" diff --git a/src/superio/ite/it8716f/Makefile.inc b/src/superio/ite/it8716f/Makefile.inc deleted file mode 100644 index 612506850d..0000000000 --- a/src/superio/ite/it8716f/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 Uwe Hermann -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_ITE_IT8716F) += superio.c diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h deleted file mode 100644 index 726c4cc548..0000000000 --- a/src/superio/ite/it8716f/it8716f.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_ITE_IT8716F_H -#define SUPERIO_ITE_IT8716F_H - -#include - -/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */ - -/* Logical device numbers (LDNs). */ -#define IT8716F_FDC 0x00 /* Floppy */ -#define IT8716F_SP1 0x01 /* Com1 */ -#define IT8716F_SP2 0x02 /* Com2 */ -#define IT8716F_PP 0x03 /* Parallel port */ -#define IT8716F_EC 0x04 /* Environment controller */ -#define IT8716F_KBCK 0x05 /* PS/2 keyboard */ -#define IT8716F_KBCM 0x06 /* PS/2 mouse */ -#define IT8716F_GPIO 0x07 /* GPIO */ -#define IT8716F_MIDI 0x08 /* MIDI port */ -#define IT8716F_GAME 0x09 /* GAME port */ -#define IT8716F_IR 0x0a /* Consumer IR */ - -/* Provided by mainboard, called by IT8716F superio.c. */ -void init_ec(u16 base); - -#endif /* SUPERIO_ITE_IT8716F_H */ diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c deleted file mode 100644 index de1ef0d73e..0000000000 --- a/src/superio/ite/it8716f/superio.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * Copyright (C) 2007 AMD - * (Written by Yinghai Lu for AMD) - * Copyright (C) 2007 Ward Vandewege - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include "it8716f.h" - -#if !CONFIG(SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) - -void init_ec(u16 base) -{ - u8 value; - - /* Read out current value of FAN_CTL (0x14). */ - value = pnp_read_index(base, 0x14); - printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\n", - base + 0x14, value); - - /* Set FAN_CTL (0x14) polarity to high, activate fans 1, 2 and 3. */ - pnp_write_index(base, 0x14, value | 0x87); - printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\n", - base + 0x14, value | 0x87); -} -#endif - -static void it8716f_init(struct device *dev) -{ - struct resource *res0; - - if (!dev->enabled) - return; - - /* TODO: FDC, PP, KBCM, MIDI, GAME, IR. */ - switch (dev->path.pnp.device) { - case IT8716F_EC: - res0 = find_resource(dev, PNP_IDX_IO0); -#define EC_INDEX_PORT 5 - init_ec(res0->base + EC_INDEX_PORT); - break; - case IT8716F_KBCK: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = it8716f_init, - .ops_pnp_mode = &pnp_conf_mode_870155_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, }, - { NULL, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, - { NULL, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, - { NULL, IT8716F_PP, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0, - 0x0ff8, 0x0ffc, }, - { NULL, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ff8, 0x0ff8, }, - { NULL, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0fff, 0x0fff, }, - { NULL, IT8716F_KBCM, PNP_IRQ0, }, - { NULL, IT8716F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2, - 0x0ff8, 0x0ff8, 0x0ff8, }, - { NULL, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, - { NULL, IT8716F_GAME, PNP_IO0, 0x0ff8, }, - { NULL, IT8716F_IR, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_ite_it8716f_ops = { - CHIP_NAME("ITE IT8716F Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/ite/it8718f/superio.c b/src/superio/ite/it8718f/superio.c index ed15955426..297aead5fb 100644 --- a/src/superio/ite/it8718f/superio.c +++ b/src/superio/ite/it8718f/superio.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include diff --git a/src/superio/ite/it8721f/superio.c b/src/superio/ite/it8721f/superio.c index cf3ca3f99f..5426992ce2 100644 --- a/src/superio/ite/it8721f/superio.c +++ b/src/superio/ite/it8721f/superio.c @@ -18,8 +18,8 @@ #include #include #include -#include #include + #include "it8721f.h" static void init(struct device *dev) diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c index 7107bb4e4a..58a837ea8f 100644 --- a/src/superio/ite/it8728f/superio.c +++ b/src/superio/ite/it8728f/superio.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include "chip.h" diff --git a/src/superio/ite/it8772f/early_init.c b/src/superio/ite/it8772f/early_init.c index 95be01c111..d605fb1a9e 100644 --- a/src/superio/ite/it8772f/early_init.c +++ b/src/superio/ite/it8772f/early_init.c @@ -21,26 +21,6 @@ /* NOTICE: This file is deprecated, use ite/common instead */ -/* RAMstage equiv */ -/* u8 pnp_read_config(pnp_devfn_t dev, u8 reg) */ -u8 it8772f_sio_read(pnp_devfn_t dev, u8 reg) -{ - u16 port = dev >> 8; - - outb(reg, port); - return inb(port + 1); -} - -/* RAMstage equiv */ -/* void pnp_write_config(pnp_devfn_t dev, u8 reg, u8 value) */ -void it8772f_sio_write(pnp_devfn_t dev, u8 reg, u8 value) -{ - u16 port = dev >> 8; - - outb(reg, port); - outb(value, port + 1); -} - void it8772f_enter_conf(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -53,15 +33,15 @@ void it8772f_enter_conf(pnp_devfn_t dev) void it8772f_exit_conf(pnp_devfn_t dev) { - it8772f_sio_write(dev, IT8772F_CONFIG_REG_CC, 0x02); + pnp_write_config(dev, IT8772F_CONFIG_REG_CC, 0x02); } /* Set AC resume to be up to the Southbridge */ void it8772f_ac_resume_southbridge(pnp_devfn_t dev) { it8772f_enter_conf(dev); - it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC); - it8772f_sio_write(dev, 0xf4, 0x60); + pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC); + pnp_write_config(dev, 0xf4, 0x60); it8772f_exit_conf(dev); } @@ -71,14 +51,14 @@ void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity, { set--; /* Set 1 is offset 0 */ it8772f_enter_conf(dev); - it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); if (set < 5) { - it8772f_sio_write(dev, GPIO_REG_SELECT(set), select); - it8772f_sio_write(dev, GPIO_REG_ENABLE(set), enable); - it8772f_sio_write(dev, GPIO_REG_POLARITY(set), polarity); + pnp_write_config(dev, GPIO_REG_SELECT(set), select); + pnp_write_config(dev, GPIO_REG_ENABLE(set), enable); + pnp_write_config(dev, GPIO_REG_POLARITY(set), polarity); } - it8772f_sio_write(dev, GPIO_REG_OUTPUT(set), output); - it8772f_sio_write(dev, GPIO_REG_PULLUP(set), pullup); + pnp_write_config(dev, GPIO_REG_OUTPUT(set), output); + pnp_write_config(dev, GPIO_REG_PULLUP(set), pullup); it8772f_exit_conf(dev); } @@ -88,15 +68,15 @@ void it8772f_gpio_led(pnp_devfn_t dev,int set, u8 select, u8 polarity, u8 pullup { set--; /* Set 1 is offset 0 */ it8772f_enter_conf(dev); - it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); if (set < 5) { - it8772f_sio_write(dev, IT8772F_GPIO_LED_BLINK1_PINMAP, led_pin_map); - it8772f_sio_write(dev, IT8772F_GPIO_LED_BLINK1_CONTROL, led_freq); - it8772f_sio_write(dev, GPIO_REG_SELECT(set), select); - it8772f_sio_write(dev, GPIO_REG_ENABLE(set), enable); - it8772f_sio_write(dev, GPIO_REG_POLARITY(set), polarity); + pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_PINMAP, led_pin_map); + pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_CONTROL, led_freq); + pnp_write_config(dev, GPIO_REG_SELECT(set), select); + pnp_write_config(dev, GPIO_REG_ENABLE(set), enable); + pnp_write_config(dev, GPIO_REG_POLARITY(set), polarity); } - it8772f_sio_write(dev, GPIO_REG_OUTPUT(set), output); - it8772f_sio_write(dev, GPIO_REG_PULLUP(set), pullup); + pnp_write_config(dev, GPIO_REG_OUTPUT(set), output); + pnp_write_config(dev, GPIO_REG_PULLUP(set), pullup); it8772f_exit_conf(dev); } diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 14d76acc77..8e8836def0 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -129,8 +129,6 @@ enum thermal_mode { #include #include -u8 it8772f_sio_read(pnp_devfn_t dev, u8 reg); -void it8772f_sio_write(pnp_devfn_t dev, u8 reg, u8 value); void it8772f_ac_resume_southbridge(pnp_devfn_t dev); void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity, u8 pullup, u8 output, u8 enable); diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index ed46e73559..bf6726412d 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -20,23 +20,13 @@ #include #include #include -#include #include +#include #include "chip.h" /* FIXME */ #include "it8772f.h" -static inline u8 it8772f_envc_read(struct resource *res, u8 addr) -{ - outb(addr, res->base + 5); - return inb(res->base + 6); -} - -static inline void it8772f_envc_write(struct resource *res, u8 addr, u8 value) -{ - outb(addr, res->base + 5); - outb(value, res->base + 6); -} +/* FIXME: see if the common ITE environment controller code can be used here */ static void it8772f_extemp_force_idle_status(struct resource *res) { @@ -45,7 +35,7 @@ static void it8772f_extemp_force_idle_status(struct resource *res) /* Wait up to 10ms for non-busy state. */ while (retries > 0) { - reg = it8772f_envc_read(res, IT8772F_EXTEMP_STATUS); + reg = pnp_read_hwm5_index(res->base, IT8772F_EXTEMP_STATUS); if ((reg & IT8772F_EXTEMP_STATUS_HOST_BUSY) == 0x0) break; @@ -60,7 +50,7 @@ static void it8772f_extemp_force_idle_status(struct resource *res) * SIO is busy due to unfinished peci transaction. * Re-configure Register 0x8E to terminate processes. */ - it8772f_envc_write(res, IT8772F_EXTEMP_CONTROL, + pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_CONTROL, IT8772F_EXTEMP_CONTROL_AUTO_4HZ | IT8772F_EXTEMP_CONTROL_AUTO_START); } @@ -75,25 +65,25 @@ static void it8772f_enable_peci(struct resource *res, int tmpin) return; /* Enable PECI interface */ - it8772f_envc_write(res, IT8772F_INTERFACE_SELECT, + pnp_write_hwm5_index(res->base, IT8772F_INTERFACE_SELECT, IT8772F_INTERFACE_SEL_PECI | IT8772F_INTERFACE_SPEED_TOLERANCE); /* Setup External Temperature using PECI GetTemp */ - it8772f_envc_write(res, IT8772F_EXTEMP_ADDRESS, + pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_ADDRESS, PECI_CLIENT_ADDRESS); - it8772f_envc_write(res, IT8772F_EXTEMP_COMMAND, + pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_COMMAND, PECI_GETTEMP_COMMAND); - it8772f_envc_write(res, IT8772F_EXTEMP_WRITE_LENGTH, + pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_WRITE_LENGTH, PECI_GETTEMP_WRITE_LENGTH); - it8772f_envc_write(res, IT8772F_EXTEMP_READ_LENGTH, + pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_READ_LENGTH, PECI_GETTEMP_READ_LENGTH); - it8772f_envc_write(res, IT8772F_EXTEMP_CONTROL, + pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_CONTROL, IT8772F_EXTEMP_CONTROL_AUTO_4HZ | IT8772F_EXTEMP_CONTROL_AUTO_START); /* External Temperature reported in TMPINx register */ - it8772f_envc_write(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE, + pnp_write_hwm5_index(res->base, IT8772F_ADC_TEMP_CHANNEL_ENABLE, (tmpin & 3) << 6); } @@ -109,17 +99,17 @@ static void it8772f_enable_tmpin(struct resource *res, int tmpin, if (tmpin != 1 && tmpin != 2) return; - reg = it8772f_envc_read(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE); + reg = pnp_read_hwm5_index(res->base, IT8772F_ADC_TEMP_CHANNEL_ENABLE); switch (mode) { case THERMAL_DIODE: /* Thermal Diode Mode */ - it8772f_envc_write(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE, + pnp_write_hwm5_index(res->base, IT8772F_ADC_TEMP_CHANNEL_ENABLE, reg | tmpin); break; case THERMAL_RESISTOR: /* Thermal Resistor Mode */ - it8772f_envc_write(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE, + pnp_write_hwm5_index(res->base, IT8772F_ADC_TEMP_CHANNEL_ENABLE, reg | (tmpin << 3)); break; default: @@ -128,10 +118,10 @@ static void it8772f_enable_tmpin(struct resource *res, int tmpin, return; } - reg = it8772f_envc_read(res, IT8772F_CONFIGURATION); + reg = pnp_read_hwm5_index(res->base, IT8772F_CONFIGURATION); /* Enable the startup of monitoring operation */ - it8772f_envc_write(res, IT8772F_CONFIGURATION, reg | 0x01); + pnp_write_hwm5_index(res->base, IT8772F_CONFIGURATION, reg | 0x01); } /* @@ -145,41 +135,41 @@ static void it8772f_enable_fan(struct resource *res, int fan, u8 fan_speed) return; /* Enable 6MHz (23.43kHz PWM) active high output */ - reg = it8772f_envc_read(res, IT8772F_FAN_CTL_MODE); + reg = pnp_read_hwm5_index(res->base, IT8772F_FAN_CTL_MODE); reg |= IT8772F_FAN_CTL_ON(fan) | IT8772F_FAN_PWM_CLOCK_6MHZ | IT8772F_FAN_CTL_POLARITY_HIGH; - it8772f_envc_write(res, IT8772F_FAN_CTL_MODE, reg); + pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL_MODE, reg); /* Enable output in smart mode */ - reg = it8772f_envc_read(res, IT8772F_FAN_MAIN_CTL); + reg = pnp_read_hwm5_index(res->base, IT8772F_FAN_MAIN_CTL); reg |= IT8772F_FAN_MAIN_CTL_TAC_SMART(fan); reg |= IT8772F_FAN_MAIN_CTL_TAC_EN(fan); - it8772f_envc_write(res, IT8772F_FAN_MAIN_CTL, reg); + pnp_write_hwm5_index(res->base, IT8772F_FAN_MAIN_CTL, reg); switch (fan) { case 2: /* Enable software operation */ - it8772f_envc_write(res, IT8772F_FAN_CTL2_PWM_MODE, + pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL2_PWM_MODE, IT8772F_FAN_CTL_PWM_MODE_SOFTWARE); /* Disable Smoothing */ - it8772f_envc_write(res, IT8772F_FAN_CTL2_AUTO_MODE, + pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL2_AUTO_MODE, IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS); /* Set a default fan speed */ if (fan_speed) - it8772f_envc_write(res, IT8772F_FAN_CTL2_PWM_START, + pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL2_PWM_START, fan_speed); break; case 3: /* Enable software operation */ - it8772f_envc_write(res, IT8772F_FAN_CTL3_PWM_MODE, + pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL3_PWM_MODE, IT8772F_FAN_CTL_PWM_MODE_SOFTWARE); /* Disable Smoothing */ - it8772f_envc_write(res, IT8772F_FAN_CTL3_AUTO_MODE, + pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL3_AUTO_MODE, IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS); /* Set a default fan speed */ if (fan_speed) - it8772f_envc_write(res, IT8772F_FAN_CTL3_PWM_START, + pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL3_PWM_START, fan_speed); break; } diff --git a/src/superio/nsc/pc87309/Kconfig b/src/superio/nsc/pc87309/Kconfig deleted file mode 100644 index ff72706b34..0000000000 --- a/src/superio/nsc/pc87309/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_NSC_PC87309 - bool - select SUPERIO_NSC_COMMON_PRE_RAM diff --git a/src/superio/nsc/pc87309/Makefile.inc b/src/superio/nsc/pc87309/Makefile.inc deleted file mode 100644 index 6c7a8ab367..0000000000 --- a/src/superio/nsc/pc87309/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_NSC_PC87309) += superio.c diff --git a/src/superio/nsc/pc87309/pc87309.h b/src/superio/nsc/pc87309/pc87309.h deleted file mode 100644 index 3b912ea455..0000000000 --- a/src/superio/nsc/pc87309/pc87309.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87309_H -#define SUPERIO_NSC_PC87309_H - -/* Datasheet: PC87309 SuperI/O Plug and Play Compatible Chip. */ - -#define PC87309_FDC 0x00 /* Floppy */ -#define PC87309_PP 0x01 /* Parallel port */ -#define PC87309_SP2 0x02 /* Com2 / IR */ -#define PC87309_SP1 0x03 /* Com1 */ -#define PC87309_PM 0x04 /* Power management */ -#define PC87309_KBCM 0x05 /* Mouse */ -#define PC87309_KBCK 0x06 /* Keyboard */ - -#endif /* SUPERIO_NSC_PC87309_H */ diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c deleted file mode 100644 index 4f8f967d61..0000000000 --- a/src/superio/nsc/pc87309/superio.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "pc87309.h" - -static void init(struct device *dev) -{ - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case PC87309_KBCK: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, PC87309_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, - 0x07f8, }, - { NULL, PC87309_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - /* TODO: PM. */ - { NULL, PC87309_KBCM, PNP_IRQ0, }, - { NULL, PC87309_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_nsc_pc87309_ops = { - CHIP_NAME("NSC PC87309 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/nsc/pc87360/Kconfig b/src/superio/nsc/pc87360/Kconfig deleted file mode 100644 index b70b935cb9..0000000000 --- a/src/superio/nsc/pc87360/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_NSC_PC87360 - bool - select SUPERIO_NSC_COMMON_PRE_RAM diff --git a/src/superio/nsc/pc87360/Makefile.inc b/src/superio/nsc/pc87360/Makefile.inc deleted file mode 100644 index 81e2d3d197..0000000000 --- a/src/superio/nsc/pc87360/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2000 AG Electronics Ltd. -## Copyright (C) 2003-2004 Linux Networx -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_NSC_PC87360) += superio.c diff --git a/src/superio/nsc/pc87360/pc87360.h b/src/superio/nsc/pc87360/pc87360.h deleted file mode 100644 index c9697464d2..0000000000 --- a/src/superio/nsc/pc87360/pc87360.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87360_H -#define SUPERIO_NSC_PC87360_H - -#define PC87360_FDC 0x00 /* Floppy */ -#define PC87360_PP 0x01 /* Parallel port */ -#define PC87360_SP2 0x02 /* Com2 */ -#define PC87360_SP1 0x03 /* Com1 */ -#define PC87360_SWC 0x04 -#define PC87360_KBCM 0x05 /* Mouse */ -#define PC87360_KBCK 0x06 /* Keyboard */ -#define PC87360_GPIO 0x07 -#define PC87360_ACB 0x08 -#define PC87360_FSCM 0x09 -#define PC87360_WDT 0x0A - -#endif /* SUPERIO_NSC_PC87360_H */ diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c deleted file mode 100644 index 33f27e154c..0000000000 --- a/src/superio/nsc/pc87360/superio.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "pc87360.h" - -static void init(struct device *dev) -{ - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case PC87360_KBCK: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, - 0x07f8, }, - { NULL, PC87360_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87360_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87360_KBCM, PNP_IRQ0, }, - { NULL, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_nsc_pc87360_ops = { - CHIP_NAME("NSC PC87360 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/nsc/pc87366/Kconfig b/src/superio/nsc/pc87366/Kconfig deleted file mode 100644 index bf17117812..0000000000 --- a/src/superio/nsc/pc87366/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_NSC_PC87366 - bool - select SUPERIO_NSC_COMMON_PRE_RAM diff --git a/src/superio/nsc/pc87366/Makefile.inc b/src/superio/nsc/pc87366/Makefile.inc deleted file mode 100644 index f432530f35..0000000000 --- a/src/superio/nsc/pc87366/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2000 AG Electronics Ltd. -## Copyright (C) 2003-2004 Linux Networx -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_NSC_PC87366) += superio.c diff --git a/src/superio/nsc/pc87366/pc87366.h b/src/superio/nsc/pc87366/pc87366.h deleted file mode 100644 index b1df69f355..0000000000 --- a/src/superio/nsc/pc87366/pc87366.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87366_H -#define SUPERIO_NSC_PC87366_H - -#define PC87366_FDC 0x00 /* Floppy */ -#define PC87366_PP 0x01 /* Parallel port */ -#define PC87366_SP2 0x02 /* Com2 */ -#define PC87366_SP1 0x03 /* Com1 */ -#define PC87366_SWC 0x04 -#define PC87366_KBCM 0x05 /* Mouse */ -#define PC87366_KBCK 0x06 /* Keyboard */ -#define PC87366_GPIO 0x07 -#define PC87366_ACB 0x08 -#define PC87366_FSCM 0x09 -#define PC87366_WDT 0x0A -#define PC87366_GMP 0x0b -#define PC87366_MIDI 0x0C -#define PC87366_VLM 0x0D -#define PC87366_TMS 0x0E - -#endif /* SUPERIO_NSC_PC87366_H */ diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c deleted file mode 100644 index 6d8c66e907..0000000000 --- a/src/superio/nsc/pc87366/superio.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "pc87366.h" - -static void init(struct device *dev) -{ - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case PC87366_KBCK: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, - 0x07f8, }, - { NULL, PC87366_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87366_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87366_KBCM, PNP_IRQ0, }, - { NULL, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_nsc_pc87366_ops = { - CHIP_NAME("NSC PC87366 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 7c04023670..c90ebd9b83 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -16,7 +16,7 @@ #include #include -#include + #include "pc87382.h" static void init(struct device *dev) diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c index cef7ff7ee0..87dd265182 100644 --- a/src/superio/nsc/pc87384/superio.c +++ b/src/superio/nsc/pc87384/superio.c @@ -16,7 +16,7 @@ #include #include -#include + #include "pc87384.h" static struct device_operations ops = { diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index a15d0a2aad..4a5bed29af 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -16,7 +16,7 @@ #include #include -#include + #include "pc87392.h" static void init(struct device *dev) diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index f867ff3e62..f98ba843ad 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -19,7 +19,7 @@ #include #include #include -#include + #include "pc87417.h" static void init(struct device *dev) diff --git a/src/superio/nsc/pc97317/Kconfig b/src/superio/nsc/pc97317/Kconfig deleted file mode 100644 index 38f6d34594..0000000000 --- a/src/superio/nsc/pc97317/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_NSC_PC97317 - bool diff --git a/src/superio/nsc/pc97317/Makefile.inc b/src/superio/nsc/pc97317/Makefile.inc deleted file mode 100644 index 2f8ee76908..0000000000 --- a/src/superio/nsc/pc97317/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2000 AG Electronics Ltd. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-$(CONFIG_SUPERIO_NSC_PC97317) += early_serial.c -romstage-$(CONFIG_SUPERIO_NSC_PC97317) += early_serial.c -ramstage-$(CONFIG_SUPERIO_NSC_PC97317) += superio.c diff --git a/src/superio/nsc/pc97317/early_serial.c b/src/superio/nsc/pc97317/early_serial.c deleted file mode 100644 index 74489faf37..0000000000 --- a/src/superio/nsc/pc97317/early_serial.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "pc97317.h" - -#define PM_DEV PNP_DEV(0x2e, PC97317_PM) -#define PM_BASE 0xe8 - -/* The PC97317 needs clocks to be set up before the serial port will operate. */ -void pc97317_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - /* Set base address of power management unit. */ - pnp_set_logical_device(PM_DEV); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, PM_BASE); - pnp_set_enable(dev, 1); - - /* Use on-chip clock multiplier. */ - outb(0x03, PM_BASE); - outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1); - - /* Wait for the clock to stabilise. */ - while(!(inb(PM_BASE + 1) & 0x80)) - ; - - /* Set the base address of the port. */ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/nsc/pc97317/pc97317.h b/src/superio/nsc/pc97317/pc97317.h deleted file mode 100644 index 76717fa0df..0000000000 --- a/src/superio/nsc/pc97317/pc97317.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC97317_H -#define SUPERIO_NSC_PC97317_H - -#define PC97317_KBCK 0x00 /* Keyboard */ -#define PC97317_KBCM 0x01 /* Mouse */ -#define PC97317_RTC 0x02 /* Real-Time Clock */ -#define PC97317_FDC 0x03 /* Floppy */ -#define PC97317_PP 0x04 /* Parallel port */ -#define PC97317_SP2 0x05 /* Com2 */ -#define PC97317_SP1 0x06 /* Com1 */ -#define PC97317_GPIO 0x07 -#define PC97317_PM 0x08 /* Power Management */ - -#include -#include - -void pc97317_enable_serial(pnp_devfn_t dev, u16 iobase); - -#endif /* SUPERIO_NSC_PC97317_H */ diff --git a/src/superio/nsc/pc97317/superio.c b/src/superio/nsc/pc97317/superio.c deleted file mode 100644 index 42f54347e8..0000000000 --- a/src/superio/nsc/pc97317/superio.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "pc97317.h" - -static void init(struct device *dev) -{ - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case PC97317_KBCK: - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); /* Disable keyboard */ - pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 MHz. */ - pnp_set_enable(dev, 1); /* Enable keyboard */ - pc_keyboard_init(NO_AUX_DEVICE); - break; - default: - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, PC97317_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0fff, 0x0fff, }, - { NULL, PC97317_KBCM, PNP_IRQ0, }, - { NULL, PC97317_RTC, PNP_IO0 | PNP_IRQ0, 0xfffe, }, - { NULL, PC97317_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0xfff8, }, - { NULL, PC97317_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x03fc, }, - { NULL, PC97317_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, - 0xfff8, }, - { NULL, PC97317_SP1, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC97317_GPIO, PNP_IO0, 0xfff8, }, - { NULL, PC97317_PM, PNP_IO0, 0xfffe, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_nsc_pc97317_ops = { - CHIP_NAME("NSC PC97317 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index 40d1200336..493e0cef57 100644 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -16,7 +16,7 @@ #include #include -#include + #include "nct5104d.h" #include "chip.h" diff --git a/src/superio/nuvoton/nct5539d/acpi/superio.asl b/src/superio/nuvoton/nct5539d/acpi/superio.asl new file mode 100644 index 0000000000..e259b0146d --- /dev/null +++ b/src/superio/nuvoton/nct5539d/acpi/superio.asl @@ -0,0 +1,172 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz + * Copyright (C) 2013, 2016 secunet Security Networks AG + * Copyright (C) 2017 Tobias Diedrich + * Copyright (C) 2019 Pavel Sayekat + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the NCT5539D SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices. + * + * LDN State + * 0x2 SP1 Implemented, untested + * 0x5 KBC Implemented, untested + * 0x8 GPIO Implemented, untested + * 0xb HWM Implemented, untested + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * NCT5539D_SHOW_SP1 If defined, Serial Port 1 will be exposed. + * NCT5539D_SHOW_KBC If defined, the Keyboard Controller will be exposed. + * NCT5539D_SHOW_GPIO If defined, GPIO support will be exposed. + * NCT5539D_SHOW_HWM If defined, the Environment Controller will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME NCT5539D +#include + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Nuvoton NCT5539D Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8, + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + ACT1, 1, /* Logical device activation */ + ACT2, 1, /* Logical device activation */ + ACT3, 1, /* Logical device activation */ + ACT4, 1, /* Logical device activation */ + ACT5, 1, /* Logical device activation */ + ACT6, 1, /* Logical device activation */ + ACT7, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + Offset (0x64), + PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */ + PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + Offset (0x72), + PNP_IRQ1, 8, /* Second IRQ */ + Offset (0x74), + PNP_DMA0, 8, /* DRQ */ + } + + Method (_CRS) + { + /* Announce the used I/O ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x87 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include + + +#ifdef NCT5539D_SHOW_SP1 + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #include +#endif + +#ifdef NCT5539D_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 5 + #define SUPERIO_KBC_PS2M + #include +#endif + +#ifdef NCT5539D_SHOW_HWM + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #define SUPERIO_PNP_LDN 11 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #define SUPERIO_PNP_IO1 0x08, 0x08 + #define SUPERIO_PNP_IRQ0 + #include +#endif + +#ifdef NCT5539D_SHOW_GPIO + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #undef PNP_DEVICE_ACTIVE + #define PNP_DEVICE_ACTIVE ACT3 + #define SUPERIO_PNP_LDN 8 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #include +#endif +} diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index e8249d4e69..30846872a0 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include diff --git a/src/superio/nuvoton/nct6776/superio.c b/src/superio/nuvoton/nct6776/superio.c index e399c0a703..78e07b66d6 100644 --- a/src/superio/nuvoton/nct6776/superio.c +++ b/src/superio/nuvoton/nct6776/superio.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include "nct6776.h" diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c index 49e630635e..7ef3488b8c 100644 --- a/src/superio/nuvoton/nct6779d/superio.c +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include "nct6779d.h" diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c index 3a6d74043f..23d5a6f824 100644 --- a/src/superio/nuvoton/nct6791d/superio.c +++ b/src/superio/nuvoton/nct6791d/superio.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include "nct6791d.h" diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index c1f557ebed..f11e75a550 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include diff --git a/src/superio/nuvoton/wpcm450/superio.c b/src/superio/nuvoton/wpcm450/superio.c index c666818530..aeb394acca 100644 --- a/src/superio/nuvoton/wpcm450/superio.c +++ b/src/superio/nuvoton/wpcm450/superio.c @@ -17,7 +17,7 @@ #include #include #include -#include + #include "wpcm450.h" static void init(struct device *dev) diff --git a/src/superio/renesas/m3885x/superio.c b/src/superio/renesas/m3885x/superio.c index 522d64796a..4bc590f79c 100644 --- a/src/superio/renesas/m3885x/superio.c +++ b/src/superio/renesas/m3885x/superio.c @@ -16,8 +16,6 @@ #include #include #include -#include -#include #include void m3885_configure_multikey(void); diff --git a/src/superio/smsc/dme1737/Kconfig b/src/superio/smsc/dme1737/Kconfig deleted file mode 100644 index 20cb12c0f0..0000000000 --- a/src/superio/smsc/dme1737/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_SMSC_DME1737 - bool diff --git a/src/superio/smsc/dme1737/Makefile.inc b/src/superio/smsc/dme1737/Makefile.inc deleted file mode 100644 index e106a02aa4..0000000000 --- a/src/superio/smsc/dme1737/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2000 AG Electronics Ltd. -## Copyright (C) 2003-2004 Linux Networx -## Copyright (C) 2004 Tyan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-$(CONFIG_SUPERIO_SMSC_DME1737) += early_serial.c -romstage-$(CONFIG_SUPERIO_SMSC_DME1737) += early_serial.c -ramstage-$(CONFIG_SUPERIO_SMSC_DME1737) += superio.c diff --git a/src/superio/smsc/dme1737/dme1737.h b/src/superio/smsc/dme1737/dme1737.h deleted file mode 100644 index f40cc35488..0000000000 --- a/src/superio/smsc/dme1737/dme1737.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_SMSC_DME1737_H -#define SUPERIO_SMSC_DME1737_H - -#define DME1737_FDC 0 /* Floppy */ -#define DME1737_PP 3 /* Parallel Port */ -#define DME1737_SP1 4 /* Com1 */ -#define DME1737_SP2 5 /* Com2 */ -#define DME1737_KBC 7 /* Keyboard & Mouse */ -#define DME1737_RT 10 /* Runtime reg*/ - -#include -#include - -void dme1737_enable_serial(pnp_devfn_t dev, u16 iobase); - -#endif /* SUPERIO_SMSC_DME1737_H */ diff --git a/src/superio/smsc/dme1737/early_serial.c b/src/superio/smsc/dme1737/early_serial.c deleted file mode 100644 index 58ad177641..0000000000 --- a/src/superio/smsc/dme1737/early_serial.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "dme1737.h" - -static void pnp_enter_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void dme1737_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/dme1737/superio.c b/src/superio/smsc/dme1737/superio.c deleted file mode 100644 index 0bfd3b811e..0000000000 --- a/src/superio/smsc/dme1737/superio.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "dme1737.h" - -static void dme1737_init(struct device *dev) -{ - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case DME1737_KBC: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = dme1737_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, DME1737_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, DME1737_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, DME1737_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, DME1737_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, DME1737_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, - 0x07ff, 0x07ff, }, - { NULL, DME1737_RT, PNP_IO0, 0x0780, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_smsc_dme1737_ops = { - CHIP_NAME("SMSC DME1737 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/smsc/fdc37n972/superio.c b/src/superio/smsc/fdc37n972/superio.c index 0ee9850c2e..3706dec762 100644 --- a/src/superio/smsc/fdc37n972/superio.c +++ b/src/superio/smsc/fdc37n972/superio.c @@ -17,7 +17,6 @@ #include #include #include -#include #include "fdc37n972.h" diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index e43e791516..9de88e2733 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -18,9 +18,8 @@ #include #include #include -#include #include -#include + #include "kbc1100.h" /* Forward declarations */ diff --git a/src/superio/smsc/lpc47b272/Kconfig b/src/superio/smsc/lpc47b272/Kconfig deleted file mode 100644 index 07e64728ee..0000000000 --- a/src/superio/smsc/lpc47b272/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_SMSC_LPC47B272 - bool diff --git a/src/superio/smsc/lpc47b272/Makefile.inc b/src/superio/smsc/lpc47b272/Makefile.inc deleted file mode 100644 index 51d77d4f10..0000000000 --- a/src/superio/smsc/lpc47b272/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2005 Digital Design Corporation -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-$(CONFIG_SUPERIO_SMSC_LPC47B272) += early_serial.c -romstage-$(CONFIG_SUPERIO_SMSC_LPC47B272) += early_serial.c -ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B272) += superio.c diff --git a/src/superio/smsc/lpc47b272/early_serial.c b/src/superio/smsc/lpc47b272/early_serial.c deleted file mode 100644 index 26fdfafbc6..0000000000 --- a/src/superio/smsc/lpc47b272/early_serial.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Pre-RAM driver for SMSC LPC47B272 Super I/O chip. */ - -#include -#include -#include -#include -#include "lpc47b272.h" - -static void pnp_enter_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -/** - * Configure the base I/O port of the specified serial device and enable the - * serial device. - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param iobase Processor I/O port address to assign to this serial device. - */ -void lpc47b272_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/lpc47b272/lpc47b272.h b/src/superio/smsc/lpc47b272/lpc47b272.h deleted file mode 100644 index 3fbd043364..0000000000 --- a/src/superio/smsc/lpc47b272/lpc47b272.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_SMSC_LPC47B272_H -#define SUPERIO_SMSC_LPC47B272_H - -#define LPC47B272_FDC 0 /* Floppy */ -#define LPC47B272_PP 3 /* Parallel Port */ -#define LPC47B272_SP1 4 /* Com1 */ -#define LPC47B272_SP2 5 /* Com2 */ -#define LPC47B272_KBC 7 /* Keyboard & Mouse */ -#define LPC47B272_RT 10 /* Runtime reg*/ - -#define LPC47B272_MAX_CONFIG_REGISTER 0x5F - -#include -#include - -void lpc47b272_enable_serial(pnp_devfn_t dev, u16 iobase); - -#endif /* SUPERIO_SMSC_LPC47B272_H */ diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c deleted file mode 100644 index 6ac2d6dbf4..0000000000 --- a/src/superio/smsc/lpc47b272/superio.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* RAM driver for SMSC LPC47B272 Super I/O chip. */ - -#include -#include -#include -#include -#include -#include -#include "lpc47b272.h" - -/** - * Initialize the specified Super I/O device. - * - * Devices other than COM ports and the keyboard controller are ignored. - * For COM ports, we configure the baud rate. - * - * @param dev Pointer to structure describing a Super I/O device. - */ -static void lpc47b272_init(struct device *dev) -{ - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case LPC47B272_KBC: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = lpc47b272_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, LPC47B272_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, LPC47B272_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, LPC47B272_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, LPC47B272_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, - 0x07ff, 0x07ff, }, - { NULL, LPC47B272_RT, PNP_IO0, 0x0780, }, -}; - -/** - * Create device structures and allocate resources to devices specified in the - * pnp_dev_info array (above). - * - * @param dev Pointer to structure describing a Super I/O device. - */ -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_smsc_lpc47b272_ops = { - CHIP_NAME("SMSC LPC47B272 Super I/O") - .enable_dev = enable_dev -}; diff --git a/src/superio/smsc/lpc47b397/Kconfig b/src/superio/smsc/lpc47b397/Kconfig deleted file mode 100644 index 80264c4fa3..0000000000 --- a/src/superio/smsc/lpc47b397/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_SMSC_LPC47B397 - bool diff --git a/src/superio/smsc/lpc47b397/Makefile.inc b/src/superio/smsc/lpc47b397/Makefile.inc deleted file mode 100644 index ddb251d023..0000000000 --- a/src/superio/smsc/lpc47b397/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2000 AG Electronics Ltd. -## Copyright (C) 2003-2004 Linux Networx -## Copyright (C) 2004 Tyan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-$(CONFIG_SUPERIO_SMSC_LPC47B397) += early_serial.c -romstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += early_serial.c -ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += superio.c diff --git a/src/superio/smsc/lpc47b397/early_serial.c b/src/superio/smsc/lpc47b397/early_serial.c deleted file mode 100644 index a07cd99d32..0000000000 --- a/src/superio/smsc/lpc47b397/early_serial.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "lpc47b397.h" - -static void pnp_enter_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/lpc47b397/lpc47b397.h b/src/superio/smsc/lpc47b397/lpc47b397.h deleted file mode 100644 index 5f3a5045ab..0000000000 --- a/src/superio/smsc/lpc47b397/lpc47b397.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_SMSC_LPC47B397_H -#define SUPERIO_SMSC_LPC47B397_H - -#define LPC47B397_FDC 0 /* Floppy */ -#define LPC47B397_PP 3 /* Parallel Port */ -#define LPC47B397_SP1 4 /* Com1 */ -#define LPC47B397_SP2 5 /* Com2 */ -#define LPC47B397_KBC 7 /* Keyboard & Mouse */ -#define LPC47B397_HWM 8 /* HW Monitor */ -#define LPC47B397_RT 10 /* Runtime reg*/ - -#include -#include - -void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase); - -#endif /* SUPERIO_SMSC_LPC47B397_H */ diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c deleted file mode 100644 index 4b9e345145..0000000000 --- a/src/superio/smsc/lpc47b397/superio.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "lpc47b397.h" - -static void enable_hwm_smbus(struct device *dev) -{ - /* Enable SensorBus register access. */ - u8 reg8; - - reg8 = pnp_read_config(dev, 0xf0); - reg8 |= (1 << 1); - pnp_write_config(dev, 0xf0, reg8); -} - -static void lpc47b397_init(struct device *dev) -{ - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case LPC47B397_KBC: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static void lpc47b397_pnp_enable_resources(struct device *dev) -{ - pnp_enable_resources(dev); - - pnp_enter_conf_mode(dev); - switch (dev->path.pnp.device) { - case LPC47B397_HWM: - printk(BIOS_DEBUG, "LPC47B397 SensorBus register access enabled\n"); - pnp_set_logical_device(dev); - enable_hwm_smbus(dev); - break; - } - /* dump_pnp_device(dev); */ - pnp_exit_conf_mode(dev); -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = lpc47b397_pnp_enable_resources, - .enable = pnp_alt_enable, - .init = lpc47b397_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, -}; - -#define HWM_INDEX 0 -#define HWM_DATA 1 -#define SB_INDEX 0x0b -#define SB_DATA0 0x0c -#define SB_DATA1 0x0d -#define SB_DATA2 0x0e -#define SB_DATA3 0x0f - -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - unsigned int device; - struct resource *res; - int result; - - device = dev->path.i2c.device; - - res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); - - pnp_write_index(res->base + HWM_INDEX, 0, device); /* Why 0? */ - - /* We only read it one byte one time. */ - result = pnp_read_index(res->base + SB_INDEX, address); - - return result; -} - -static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) -{ - unsigned int device; - struct resource *res; - - device = dev->path.i2c.device; - res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); - - pnp_write_index(res->base+HWM_INDEX, 0, device); /* Why 0? */ - - /* We only write it one byte one time. */ - pnp_write_index(res->base+SB_INDEX, address, val); - - return 0; -} - -static struct smbus_bus_operations lops_smbus_bus = { - /* .recv_byte = lsmbus_recv_byte, */ - /* .send_byte = lsmbus_send_byte, */ - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static struct device_operations ops_hwm = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = lpc47b397_pnp_enable_resources, - .enable = pnp_alt_enable, - .init = lpc47b397_init, - .ops_smbus_bus = &lops_smbus_bus, - .ops_pnp_mode = &pnp_conf_mode_55_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, - 0x07ff, 0x07ff, }, - { &ops_hwm, LPC47B397_HWM, PNP_IO0, 0x07f0, }, - { NULL, LPC47B397_RT, PNP_IO0, 0x0780, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_smsc_lpc47b397_ops = { - CHIP_NAME("SMSC LPC47B397 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index cd13854128..a4e3799cd8 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -21,9 +21,8 @@ #include #include #include -#include #include -#include + #include "lpc47m10x.h" /** diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index 80ed456ee4..40eb7d25b1 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -18,9 +18,8 @@ #include #include #include -#include #include -#include + #include "lpc47m15x.h" /* Forward declarations */ diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c index b8e5c0b549..9bda334b84 100644 --- a/src/superio/smsc/lpc47n207/early_serial.c +++ b/src/superio/smsc/lpc47n207/early_serial.c @@ -16,7 +16,7 @@ #include #include #include -#include + #include "lpc47n207.h" /* diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c index b10e8a1b28..1b34bec27c 100644 --- a/src/superio/smsc/lpc47n217/superio.c +++ b/src/superio/smsc/lpc47n217/superio.c @@ -23,9 +23,8 @@ #include #include #include -#include #include -#include + #include "lpc47n217.h" /* Forward declarations */ diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c index 610f685e43..57297aba5b 100644 --- a/src/superio/smsc/lpc47n227/superio.c +++ b/src/superio/smsc/lpc47n227/superio.c @@ -19,9 +19,7 @@ #include #include #include -#include #include -#include #include #include diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index 74b8b2e3ca..106b8ad500 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -18,9 +18,8 @@ #include #include #include -#include #include -#include + #include "mec1308.h" static void mec1308_init(struct device *dev) diff --git a/src/superio/smsc/sch4037/Kconfig b/src/superio/smsc/sch4037/Kconfig deleted file mode 100644 index ce87f75b2f..0000000000 --- a/src/superio/smsc/sch4037/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_SMSC_SCH4037 - bool diff --git a/src/superio/smsc/sch4037/Makefile.inc b/src/superio/smsc/sch4037/Makefile.inc deleted file mode 100644 index ac7d7de652..0000000000 --- a/src/superio/smsc/sch4037/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -bootblock-$(CONFIG_SUPERIO_SMSC_SCH4037) += sch4037_early_init.c -romstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += sch4037_early_init.c -ramstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += superio.c diff --git a/src/superio/smsc/sch4037/sch4037.h b/src/superio/smsc/sch4037/sch4037.h deleted file mode 100644 index f0fa3cda0f..0000000000 --- a/src/superio/smsc/sch4037/sch4037.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_SCH_4037_H -#define SUPERIO_SCH_4037_H - -#define SCH4037_FDD 0 /* FDD */ -#define SCH4037_LPT 3 /* LPT */ -#define SMSCSUPERIO_SP1 4 /* Com1 */ -#define SMSCSUPERIO_SP2 5 /* Com2 */ -#define SCH4037_RTC 6 /* RTC */ -#define SCH4037_KBC 7 /* KBC */ -#define SCH4037_HWM 8 /* HWM */ -#define SCH4037_RUNTIME 0x0A /* Runtime */ -#define SCH4037_XBUS 0x0B /* X-BUS */ - -void sch4037_early_init(unsigned port); - -#endif /* SUPERIO_SCH_4037_H */ diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c deleted file mode 100644 index a416ab8358..0000000000 --- a/src/superio/smsc/sch4037/sch4037_early_init.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include -#include -#include -#include - -#include "sch4037.h" - -static void pnp_enter_conf_state(pnp_devfn_t dev) -{ - unsigned port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(pnp_devfn_t dev) -{ - unsigned port = dev >> 8; - outb(0xaa, port); -} - -void sch4037_early_init(unsigned port) -{ - pnp_devfn_t dev; - - dev = PNP_DEV(port, SMSCSUPERIO_SP1); - pnp_enter_conf_state(dev); - - /* Auto power management */ - pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */ - pnp_write_config(dev, 0x23, 0); - - /* Enable SMSC UART 0 */ - dev = PNP_DEV(port, SMSCSUPERIO_SP1); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); - pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); - - /* Enabled High speed, disabled MIDI support. */ - pnp_write_config(dev, 0xF0, 0x02); - pnp_set_enable(dev, 1); - - /* Enable keyboard */ - dev = PNP_DEV(port, SCH4037_KBC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ - pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ - pnp_set_enable(dev, 1); - - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c deleted file mode 100644 index 5e49aa73c5..0000000000 --- a/src/superio/smsc/sch4037/superio.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* RAM driver for the SMSC KBC1100 Super I/O chip */ - -#include -#include -#include -#include -#include - -#include "sch4037.h" - -static void sch4037_init(struct device *dev) -{ - if (!dev->enabled) { - return; - } - - switch (dev->path.pnp.device) { - case SCH4037_KBC: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = sch4037_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, - 0x7ff, 0x7ff, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_smsc_sch4037_ops = { - CHIP_NAME("SMSC SCH4037 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index 47f317f042..26a2a3eb4b 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -23,21 +23,21 @@ static inline void sio1036_enter_conf_state(pnp_devfn_t dev) { - unsigned port = dev >> 8; + u8 port = dev >> 8; outb(0x55, port); } static inline void sio1036_exit_conf_state(pnp_devfn_t dev) { - unsigned port = dev >> 8; + u8 port = dev >> 8; outb(0xaa, port); } /* Detect SMSC SIO1036 LPC Debug Card status */ -static u8 detect_sio1036_chip(unsigned port) +static u8 detect_sio1036_chip(unsigned int port) { pnp_devfn_t dev = PNP_DEV(port, SIO1036_SP1); - unsigned data; + u8 data; sio1036_enter_conf_state(dev); data = pnp_read_config(dev, 0x0D); @@ -47,15 +47,14 @@ static u8 detect_sio1036_chip(unsigned port) if (data == 0x82) { /* Found SMSC SIO1036 chip */ return 0; - } - else { + } else { return 1; }; } void sio1036_enable_serial(pnp_devfn_t dev, u16 iobase) { - unsigned port = dev >> 8; + unsigned int port = dev >> 8; if (detect_sio1036_chip(port) != 0) return; diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c index a192831bcd..c39d0970c6 100644 --- a/src/superio/smsc/sio1036/superio.c +++ b/src/superio/smsc/sio1036/superio.c @@ -18,15 +18,13 @@ #include #include #include -#include #include "sio1036.h" static void sio1036_init(struct device *dev) { - if (!dev->enabled) { + if (!dev->enabled) return; - } } static struct device_operations ops = { diff --git a/src/superio/smsc/sio10n268/superio.c b/src/superio/smsc/sio10n268/superio.c index b8243ece51..cf432a09b8 100644 --- a/src/superio/smsc/sio10n268/superio.c +++ b/src/superio/smsc/sio10n268/superio.c @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ -#include #include #include #include + #include "sio10n268.h" static void init(struct device *dev) diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index 4ce006dc34..aa5af38250 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -35,7 +35,6 @@ #include #include #include -#include /* The following Super I/O chips are currently supported by this driver: */ #define LPC47M172 0x14 diff --git a/src/superio/via/vt1211/Kconfig b/src/superio/via/vt1211/Kconfig deleted file mode 100644 index b2de1d3134..0000000000 --- a/src/superio/via/vt1211/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_VIA_VT1211 - bool diff --git a/src/superio/via/vt1211/Makefile.inc b/src/superio/via/vt1211/Makefile.inc deleted file mode 100644 index d3044afd11..0000000000 --- a/src/superio/via/vt1211/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2004 Nick Barker -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_VIA_VT1211) += superio.c diff --git a/src/superio/via/vt1211/superio.c b/src/superio/via/vt1211/superio.c deleted file mode 100644 index 4d7c8dedfc..0000000000 --- a/src/superio/via/vt1211/superio.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Nick Barker - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "vt1211.h" - -static u8 hwm_io_regs[] = { - 0x10,0x03, 0x11,0x10, 0x12,0x0d, 0x13,0x7f, - 0x14,0x21, 0x15,0x81, 0x16,0xbd, 0x17,0x8a, - 0x18,0x00, 0x19,0x00, 0x1a,0x00, 0x1b,0x00, - 0x1d,0xff, 0x1e,0x00, 0x1f,0x73, 0x20,0x67, - 0x21,0xc1, 0x22,0xca, 0x23,0x74, 0x24,0xc2, - 0x25,0xc7, 0x26,0xc9, 0x27,0x7f, 0x29,0x00, - 0x2a,0x00, 0x2b,0xff, 0x2c,0x00, 0x2d,0xff, - 0x2e,0x00, 0x2f,0xff, 0x30,0x00, 0x31,0xff, - 0x32,0x00, 0x33,0xff, 0x34,0x00, 0x39,0xff, - 0x3a,0x00, 0x3b,0xff, 0x3c,0xff, 0x3d,0xff, - 0x3e,0x00, 0x3f,0xb0, 0x43,0xff, 0x44,0xff, - 0x46,0xff, 0x47,0x50, 0x4a,0x03, 0x4b,0xc0, - 0x4c,0x00, 0x4d,0x00, 0x4e,0x0f, 0x5d,0x77, - 0x5c,0x00, 0x5f,0x33, 0x40,0x01, -}; - -static void vt1211_set_iobase(struct device *dev, u8 index, u16 iobase) -{ - switch (dev->path.pnp.device) { - case VT1211_FDC: - case VT1211_PP: - case VT1211_SP1: - case VT1211_SP2: - pnp_write_config(dev, index + 0, (iobase >> 2) & 0xff); - break; - case VT1211_ROM: - /* TODO: Error. VT1211_ROM doesn't have an I/O base. */ - break; - case VT1211_MIDI: - case VT1211_GAME: - case VT1211_GPIO: - case VT1211_WDG: - case VT1211_WUC: - case VT1211_HWM: - case VT1211_FIR: - default: - pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); - pnp_write_config(dev, index + 1, iobase & 0xff); - break; - } -} - -/* Initialize VT1211 hardware monitor registers, which are at 0xECXX. */ -static void init_hwm(u16 base) -{ - int i; - - for (i = 0; i < sizeof(hwm_io_regs); i += 2) - outb(hwm_io_regs[i + 1], base + hwm_io_regs[i]); -} - -static void vt1211_init(struct device *dev) -{ - struct resource *res0; - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case VT1211_HWM: - res0 = find_resource(dev, PNP_IDX_IO0); - init_hwm(res0->base); - break; - case VT1211_FDC: - case VT1211_PP: - case VT1211_MIDI: - case VT1211_GAME: - case VT1211_GPIO: - case VT1211_WDG: - case VT1211_WUC: - case VT1211_FIR: - case VT1211_ROM: - /* TODO: Any init needed for these LDNs? */ - break; - default: - printk(BIOS_INFO, "VT1211: Cannot init unknown device!\n"); - } -} - -static void vt1211_pnp_enable_resources(struct device *dev) -{ - printk(BIOS_DEBUG, "%s - enabling\n", dev_path(dev)); - pnp_enable_resources(dev); -} - -static void vt1211_pnp_set_resources(struct device *dev) -{ - struct resource *res; - -#if CONFIG(CONSOLE_SERIAL) && CONFIG(DRIVERS_UART_8250IO) - /* TODO: Do the same for SP2? */ - if (dev->path.pnp.device == VT1211_SP1) { - for (res = dev->resource_list; res; res = res->next) { - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } - return; - } -#endif - - pnp_enter_conf_mode(dev); - - pnp_set_logical_device(dev); - - /* Paranoia says I should disable the device here... */ - for (res = dev->resource_list; res; res = res->next) { - if (!(res->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010Lx " - "not assigned\n", dev_path(dev), res->index, - resource_type(res), res->size); - continue; - } - - /* Now store the resource. */ - if (res->flags & IORESOURCE_IO) { - vt1211_set_iobase(dev, res->index, res->base); - } else if (res->flags & IORESOURCE_DRQ) { - pnp_set_drq(dev, res->index, res->base); - } else if (res->flags & IORESOURCE_IRQ) { - pnp_set_irq(dev, res->index, res->base); - } else { - printk(BIOS_ERR, "ERROR: %s %02lx unknown resource " - "type\n", dev_path(dev), res->index); - return; - } - res->flags |= IORESOURCE_STORED; - - report_resource_stored(dev, res, ""); - } - - pnp_exit_conf_mode(dev); -} - -struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = vt1211_pnp_set_resources, - .enable_resources = vt1211_pnp_enable_resources, - .enable = pnp_alt_enable, - .init = vt1211_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, -}; - -/* TODO: Check if 0x07f8 is correct for FDC/PP/SP1/SP2, the rest is correct. */ -static struct pnp_info pnp_dev_info[] = { - { NULL, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, VT1211_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, VT1211_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, VT1211_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, VT1211_MIDI, PNP_IO0 | PNP_IRQ0, 0xfffc, }, - { NULL, VT1211_GAME, PNP_IO0, 0xfff8, }, - { NULL, VT1211_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, VT1211_WDG, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, VT1211_WUC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, VT1211_HWM, PNP_IO0 | PNP_IRQ0, 0xff00, }, - { NULL, VT1211_FIR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0xff00, }, - { NULL, VT1211_ROM, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_via_vt1211_ops = { - CHIP_NAME("VIA VT1211 Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/via/vt1211/vt1211.h b/src/superio/via/vt1211/vt1211.h deleted file mode 100644 index 9f0a1ef8cd..0000000000 --- a/src/superio/via/vt1211/vt1211.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Nick Barker - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_VIA_VT1211_VT1211_H -#define SUPERIO_VIA_VT1211_VT1211_H - -/* Logical device numbers (LDNs). */ -#define VT1211_FDC 0x00 /* Floppy */ -#define VT1211_PP 0x01 /* Parallel port */ -#define VT1211_SP1 0x02 /* COM1 */ -#define VT1211_SP2 0x03 /* COM2 */ -#define VT1211_MIDI 0x06 /* MIDI */ -#define VT1211_GAME 0x07 /* Game port (GMP) */ -#define VT1211_GPIO 0x08 /* GPIO */ -#define VT1211_WDG 0x09 /* Watchdog timer (WDG) */ -#define VT1211_WUC 0x0a /* Wake-up control (WUC) */ -#define VT1211_HWM 0x0b /* Hardware monitor (HM) */ -#define VT1211_FIR 0x0c /* Very fast IR (VFIR/FIR) */ -#define VT1211_ROM 0x0d /* Flash ROM */ - -#endif diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 9e15037277..bd9900ba14 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -17,7 +17,7 @@ #include #include #include -#include + #include "w83627dhg.h" static void w83627dhg_enable_UR2(struct device *dev) diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 88fbc314a9..da501739f6 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -20,10 +20,11 @@ #include #include #include +#include #include #include #include -#include + #include "w83627ehg.h" static void enable_hwm_smbus(struct device *dev) @@ -65,12 +66,12 @@ static void init_hwm(u16 base) for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) { reg = hwm_reg_values[i]; - value = pnp_read_index(base, reg); + value = pnp_read_hwm5_index(base, reg); value &= 0xff & (~(hwm_reg_values[i + 1])); value |= 0xff & hwm_reg_values[i + 2]; printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, " "value = 0x%02x\n", base, reg, value); - pnp_write_index(base, reg, value); + pnp_write_hwm5_index(base, reg, value); } } @@ -87,8 +88,7 @@ static void w83627ehg_init(struct device *dev) break; case W83627EHG_HWM: res0 = find_resource(dev, PNP_IDX_IO0); -#define HWM_INDEX_PORT 5 - init_hwm(res0->base + HWM_INDEX_PORT); + init_hwm(res0->base); break; case W83627EHG_ACPI: init_acpi(dev); diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 318eaa4b03..a4d734fa47 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -20,10 +20,11 @@ #include #include #include +#include #include #include #include -#include + #include "w83627hf.h" static void enable_hwm_smbus(struct device *dev) @@ -72,12 +73,12 @@ static void init_hwm(u16 base) for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) { reg = hwm_reg_values[i]; - value = pnp_read_index(base, reg); + value = pnp_read_hwm5_index(base, reg); value &= 0xff & hwm_reg_values[i + 1]; value |= 0xff & hwm_reg_values[i + 2]; printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, " "value = 0x%02x\n", base, reg, value); - pnp_write_index(base, reg, value); + pnp_write_hwm5_index(base, reg, value); } } @@ -94,8 +95,7 @@ static void w83627hf_init(struct device *dev) break; case W83627HF_HWM: res0 = find_resource(dev, PNP_IDX_IO0); -#define HWM_INDEX_PORT 5 - init_hwm(res0->base + HWM_INDEX_PORT); + init_hwm(res0->base); break; case W83627HF_ACPI: init_acpi(dev); diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index 82974ba056..e78374076e 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -18,8 +18,8 @@ #include #include #include -#include #include + #include "w83627uhg.h" /* diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index 0735f045ad..4a995d6b5d 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include diff --git a/src/superio/winbond/w83697hf/Kconfig b/src/superio/winbond/w83697hf/Kconfig deleted file mode 100644 index 6ca03fec59..0000000000 --- a/src/superio/winbond/w83697hf/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_WINBOND_W83697HF - bool - select SUPERIO_WINBOND_COMMON_PRE_RAM diff --git a/src/superio/winbond/w83697hf/Makefile.inc b/src/superio/winbond/w83697hf/Makefile.inc deleted file mode 100644 index d1ef2b082a..0000000000 --- a/src/superio/winbond/w83697hf/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Sean Nelson -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_WINBOND_W83697HF) += superio.c diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h deleted file mode 100644 index f7fc7985dd..0000000000 --- a/src/superio/winbond/w83697hf/chip.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Sean Nelson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_WINBOND_W83697HF_CHIP_H -#define SUPERIO_WINBOND_W83697HF_CHIP_H - - -struct superio_winbond_w83697hf_config { - unsigned int hwmon_fan1_divisor; - unsigned int hwmon_fan2_divisor; -}; - -#endif /* SUPERIO_WINBOND_W83697HF_CHIP_H */ diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c deleted file mode 100644 index a3c132ccee..0000000000 --- a/src/superio/winbond/w83697hf/superio.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Sean Nelson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" -#include "w83697hf.h" - -static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { - unsigned char enc, buf; - - if (divisor) { - enc = log2(divisor); - if (1 << enc != divisor || enc > 7) - die("invalid fan divisor"); - outb(0x4e, base + 5); - outb(0x00, base + 6); - outb(0x47, base + 5); - outb((inb(base + 6) & ~(0x30 << (num * 2))) | ((enc & 3) << (4 + num * 2)), base + 6); - outb(0x5d, base + 5); - buf = inb(base + 6); - /* the above inb() auto-increments the address pointer ... */ - outb(0x5d, base + 5); - outb((buf & ~(0x20 << num)) | ((enc & 4) << (3 + num)), base + 6); - } -} - -static void w83697hf_init(struct device *dev) -{ - struct resource *res0; - struct superio_winbond_w83697hf_config *cfg; - - if (!dev->enabled) - return; - - cfg = dev->chip_info; - - switch (dev->path.pnp.device) { - case W83697HF_HWM: - if (cfg) { - res0 = find_resource(dev, PNP_IDX_IO0); - hwmon_set_fan_divisor(res0->base, 0, cfg->hwmon_fan1_divisor); - hwmon_set_fan_divisor(res0->base, 1, cfg->hwmon_fan2_divisor); - } - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = w83697hf_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, W83697HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, W83697HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, W83697HF_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, W83697HF_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, W83697HF_CIR, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, W83697HF_GAME_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, - 0x07ff, 0x07fe, }, - { NULL, W83697HF_MIDI_GPIO5, }, - { NULL, W83697HF_GPIO234, }, - { NULL, W83697HF_ACPI, }, - { NULL, W83697HF_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_winbond_w83697hf_ops = { - CHIP_NAME("Winbond W83697HF Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h deleted file mode 100644 index 52466a8e96..0000000000 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Sean Nelson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_WINBOND_W83697HF_H -#define SUPERIO_WINBOND_W83697HF_H - -#define W83697HF_FDC 0 /* Floppy */ -#define W83697HF_PP 1 /* Parallel port */ -#define W83697HF_SP1 2 /* Com1 */ -#define W83697HF_SP2 3 /* Com2 */ -#define W83697HF_CIR 6 /* Consumer IR */ -#define W83697HF_GAME_GPIO1 7 /* Game port, GPIO 1 */ -#define W83697HF_MIDI_GPIO5 8 /* MIDI, GPIO 5 */ -#define W83697HF_GPIO234 9 /* GPIO 2, 3, 4 */ -#define W83697HF_ACPI 10 /* ACPI */ -#define W83697HF_HWM 11 /* Hardware monitor */ - -#endif /* SUPERIO_WINBOND_W83697HF_H */ diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index b4f316ba75..b11e5be577 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -20,7 +20,7 @@ #include #include #include -#include + #include "w83977tf.h" static void w83977tf_init(struct device *dev) diff --git a/src/superio/winbond/wpcd376i/Kconfig b/src/superio/winbond/wpcd376i/Kconfig deleted file mode 100644 index 57cce7bbdc..0000000000 --- a/src/superio/winbond/wpcd376i/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_WINBOND_WPCD376I - bool - select SUPERIO_WINBOND_COMMON_PRE_RAM diff --git a/src/superio/winbond/wpcd376i/Makefile.inc b/src/superio/winbond/wpcd376i/Makefile.inc deleted file mode 100644 index cebd175d80..0000000000 --- a/src/superio/winbond/wpcd376i/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2000 AG Electronics Ltd. -## Copyright (C) 2003-2004 Linux Networx -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-$(CONFIG_SUPERIO_WINBOND_WPCD376I) += early_serial.c -romstage-$(CONFIG_SUPERIO_WINBOND_WPCD376I) += early_serial.c -ramstage-$(CONFIG_SUPERIO_WINBOND_WPCD376I) += superio.c diff --git a/src/superio/winbond/wpcd376i/early_serial.c b/src/superio/winbond/wpcd376i/early_serial.c deleted file mode 100644 index 9f9ff6b227..0000000000 --- a/src/superio/winbond/wpcd376i/early_serial.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Marc Jones - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Pre-RAM driver for the Winbond WPCD376I Super I/O chip. */ - - -#include -#include -#include "wpcd376i.h" - -void wpcd376i_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/winbond/wpcd376i/superio.c b/src/superio/winbond/wpcd376i/superio.c deleted file mode 100644 index ae4fce4d0b..0000000000 --- a/src/superio/winbond/wpcd376i/superio.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "chip.h" -#include "wpcd376i.h" - -static void init(struct device *dev) -{ - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case WPCD376I_KBCK: - pc_keyboard_init(NO_AUX_DEVICE); - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, WPCD376I_FDC, - PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC8, - 0x07f8, }, - { NULL, WPCD376I_LPT, - PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0 | PNP_MSC8, - 0x03f8, }, - { NULL, WPCD376I_SP1, - PNP_IO0 | PNP_IRQ0 | PNP_MSC0, - 0x07f8, }, - { NULL, WPCD376I_SWC, - PNP_IO0 | PNP_IO1 | PNP_IRQ0, - 0xfff0, 0xfff0, }, - { NULL, WPCD376I_KBCM, - PNP_IRQ0, }, - { NULL, WPCD376I_KBCK, - PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, - 0x07f8, 0x07f8, }, - { NULL, WPCD376I_GPIO, - PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | - PNP_MSC8, - 0xffe0, }, - { NULL, WPCD376I_ECIR, - PNP_IO0 | PNP_IO1 | PNP_IRQ0, - 0xfff0, 0xfff0, }, - { NULL, WPCD376I_IR, - PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1 | PNP_MSC0, - 0xfff8, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_winbond_wpcd376i_ops = { - CHIP_NAME("Winbond WPCD376I Super I/O") - .enable_dev = enable_dev, -}; diff --git a/src/superio/winbond/wpcd376i/wpcd376i.h b/src/superio/winbond/wpcd376i/wpcd376i.h deleted file mode 100644 index a90b13bad7..0000000000 --- a/src/superio/winbond/wpcd376i/wpcd376i.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_WINBOND_WPCD376I_WPCD376I_H -#define SUPERIO_WINBOND_WPCD376I_WPCD376I_H - -#include - -/* Logical Device Numbers (LDN). */ -#define WPCD376I_FDC 0x00 /* Floppy */ -#define WPCD376I_LPT 0x01 /* Parallel port */ -/* 0x02 Undefined */ -#define WPCD376I_SP1 0x03 /* UART1 */ -#define WPCD376I_SWC 0x04 /* System wake-up control */ -#define WPCD376I_KBCM 0x05 /* PS/2 mouse */ -#define WPCD376I_KBCK 0x06 /* PS/2 keyboard */ -#define WPCD376I_GPIO 0x07 /* General Purpose I/O */ -#define WPCD376I_ECIR 0x15 /* Enhanced Consumer Infrared Functions (ECIR) */ -#define WPCD376I_IR 0x16 /* UART3 & Infrared port */ - -void wpcd376i_enable_serial(pnp_devfn_t dev, u16 iobase); - -#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c index 856a21af33..2f919d76e2 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c @@ -716,7 +716,7 @@ MemFGetDctInterleavedLimit ( UINT8 i; DctMemLimit = 0; - if (DctInterleavedMemSize == NBPtr->DCTPtr->Timings.DctMemSize << 6) { + if (DctInterleavedMemSize == (UINT64)(NBPtr->DCTPtr->Timings.DctMemSize) << 6) { // The whole memory range is interleaved for the DCTs with the minimum memory size for (i = 0; i < NBPtr->DctCount; i++) { DctMemLimit += DctInterleavedMemSize; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c index 08c773080c..9bb94408c5 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c @@ -260,8 +260,7 @@ MemTAmdRdDqs2DTraining ( // IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tProgramming Final Vref for channel\n\n"); MemT2DProgramVref (TechPtr, NBPtr->ChannelPtr->MaxVref); - Status = TRUE; - } else { + } else { SetMemError (AGESA_ERROR, NBPtr->MCTPtr); PutEventLog (AGESA_ERROR, MEM_ERROR_2D_DQS_VREF_MARGIN_ERROR, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); } diff --git a/src/vendorcode/amd/fsp/picasso/FspUpd.h b/src/vendorcode/amd/fsp/picasso/FspUpd.h new file mode 100644 index 0000000000..dba4dca03f --- /dev/null +++ b/src/vendorcode/amd/fsp/picasso/FspUpd.h @@ -0,0 +1,22 @@ +/** @file + * + * This file is automatically generated. + * + */ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#ifdef EFI32 +# include +# include +#else +# include +#endif + +#define FSPM_UPD_SIGNATURE 0x4D5F4f5341434950 /* 'PICASO_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4f5341434950 /* 'PICASO_S' */ + + +#endif diff --git a/src/vendorcode/amd/fsp/picasso/FspmUpd.h b/src/vendorcode/amd/fsp/picasso/FspmUpd.h new file mode 100644 index 0000000000..aa85adc766 --- /dev/null +++ b/src/vendorcode/amd/fsp/picasso/FspmUpd.h @@ -0,0 +1,39 @@ +/** @file + * + * This file is automatically generated. + * + */ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include + +#pragma pack(1) + + +/** Fsp M Configuration +**/ +typedef struct { + /** Offset 0x0040**/ uint32_t pci_express_base_addr; + /** Offset 0x0044**/ uint32_t serial_port_base; + /** Offset 0x0048**/ uint32_t serial_port_use_mmio; + /** Offset 0x004C**/ uint32_t serial_port_stride; + /** Offset 0x0050**/ uint32_t serial_port_baudrate; + /** Offset 0x0054**/ uint32_t serial_port_refclk; + /** Offset 0x0058**/ uint8_t UnusedUpdSpace0[168]; + /** Offset 0x0100**/ uint16_t Reserved100; + /** Offset 0x0102**/ uint16_t UpdTerminator; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + /** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader; + /** Offset 0x0020**/ FSPM_ARCH_UPD FspmArchUpd; + /** Offset 0x0040**/ FSP_M_CONFIG FspmConfig; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h new file mode 100644 index 0000000000..5a154358d9 --- /dev/null +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -0,0 +1,44 @@ +/** @file + * + * This file is automatically generated. + * + */ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include + +#pragma pack(1) + + +typedef struct { + /** Offset 0x0020**/ uint32_t pcie_port0_topology; + /** Offset 0x0024**/ uint32_t pcie_port1_topology; + /** Offset 0x0028**/ uint32_t pcie_port2_topology; + /** Offset 0x002C**/ uint32_t pcie_port3_topology; + /** Offset 0x0030**/ uint32_t pcie_port4_topology; + /** Offset 0x0034**/ uint32_t pcie_port5_topology; + /** Offset 0x0038**/ uint32_t pcie_port6_topology; + /** Offset 0x003C**/ uint32_t pcie_sata_topology; + /** Offset 0x0040**/ uint32_t pcie_xgbe1_topology; + /** Offset 0x0044**/ uint32_t pcie_xgbe2_topology; + /** Offset 0x0048**/ uint32_t dp0_connector_type; + /** Offset 0x004C**/ uint32_t dp1_connector_type; + /** Offset 0x0050**/ uint32_t dp2_connector_type; + /** Offset 0x0054**/ uint32_t dp3_connector_type; + /** Offset 0x0058**/ uint32_t emmc0_mode; + /** Offset 0x005C**/ uint8_t UnusedUpdSpace0[196]; + /** Offset 0x0120**/ uint16_t UpdTerminator; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + /** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader; + /** Offset 0x0020**/ FSP_S_CONFIG FspsConfig; +} FSPS_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/amd/fsp/picasso/fsp_h_c99.h b/src/vendorcode/amd/fsp/picasso/fsp_h_c99.h new file mode 100644 index 0000000000..dc3f94608f --- /dev/null +++ b/src/vendorcode/amd/fsp/picasso/fsp_h_c99.h @@ -0,0 +1,51 @@ +/** @file + * + * C99 common FSP definitions from + * Intel Firmware Support Package External Architecture Specification v2.0 + * + * These definitions come in a format that is usable outside an EFI environment. + **/ +#ifndef FSP_H_C99_H +#define FSP_H_C99_H + +#include + +enum { + FSP_STATUS_RESET_REQUIRED_COLD = 0x40000001, + FSP_STATUS_RESET_REQUIRED_WARM = 0x40000002, + FSP_STATUS_RESET_REQUIRED_3 = 0x40000003, + FSP_STATUS_RESET_REQUIRED_4 = 0x40000004, + FSP_STATUS_RESET_REQUIRED_5 = 0x40000005, + FSP_STATUS_RESET_REQUIRED_6 = 0x40000006, + FSP_STATUS_RESET_REQUIRED_7 = 0x40000007, + FSP_STATUS_RESET_REQUIRED_8 = 0x40000008, +}; + +typedef enum { + EnumInitPhaseAfterPciEnumeration = 0x20, + EnumInitPhaseReadyToBoot = 0x40, + EnumInitPhaseEndOfFirmware = 0xF0 +} FSP_INIT_PHASE; + +typedef struct { + uint64_t Signature; + uint8_t Revision; + uint8_t Reserved[23]; +} FSP_UPD_HEADER; + +_Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed"); + +typedef struct { + uint8_t Revision; + uint8_t Reserved[3]; + void *NvsBufferPtr; + void *StackBase; + uint32_t StackSize; + uint32_t BootLoaderTolumSize; + uint32_t BootMode; + uint8_t Reserved1[8]; +} FSPM_ARCH_UPD; + +_Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed"); + +#endif /* FSP_H_C99_H */ diff --git a/src/vendorcode/eltan/Kconfig b/src/vendorcode/eltan/Kconfig index 731dd2cea3..30bb8b8ab8 100644 --- a/src/vendorcode/eltan/Kconfig +++ b/src/vendorcode/eltan/Kconfig @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2014-2018 Eltan B.V. +## Copyright (C) 2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -13,5 +13,9 @@ ## GNU General Public License for more details. ## -source src/vendorcode/eltan/security/mboot/Kconfig -source src/vendorcode/eltan/security/verified_boot/Kconfig +config USE_VENDORCODE_ELTAN + bool + +if USE_VENDORCODE_ELTAN +source src/vendorcode/eltan/security/Kconfig +endif diff --git a/src/vendorcode/eltan/security/Kconfig b/src/vendorcode/eltan/security/Kconfig index 2af58080da..6b93d2a97a 100644 --- a/src/vendorcode/eltan/security/Kconfig +++ b/src/vendorcode/eltan/security/Kconfig @@ -1,6 +1,6 @@ ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Eltan B.V. +## Copyright (C) 2018-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -12,5 +12,7 @@ ## GNU General Public License for more details. ## +menu "Eltan Security Settings" source src/vendorcode/eltan/security/mboot/Kconfig source src/vendorcode/eltan/security/verified_boot/Kconfig +endmenu diff --git a/src/vendorcode/eltan/security/include/cb_sha.h b/src/vendorcode/eltan/security/include/cb_sha.h index 4d087f40c9..9a231d8a1e 100644 --- a/src/vendorcode/eltan/security/include/cb_sha.h +++ b/src/vendorcode/eltan/security/include/cb_sha.h @@ -20,14 +20,7 @@ #include #include -/* Supported Algorithm types for hash */ -enum endian_algorithm { - NO_ENDIAN_ALGORITHM = 0, - BIG_ENDIAN_ALGORITHM = 1, - LITTLE_ENDIAN_ALGORITHM = 2, -}; +vb2_error_t cb_sha_little_endian(enum vb2_hash_algorithm hash_alg, const uint8_t *data, + uint32_t len, uint8_t *digest); -int cb_sha_endian(enum vb2_hash_algorithm hash_alg, const uint8_t *data, uint32_t len, - uint8_t *digest, enum endian_algorithm endian); - -#endif \ No newline at end of file +#endif diff --git a/src/vendorcode/eltan/security/lib/cb_sha.c b/src/vendorcode/eltan/security/lib/cb_sha.c index 47cd10a47c..20a84afacc 100644 --- a/src/vendorcode/eltan/security/lib/cb_sha.c +++ b/src/vendorcode/eltan/security/lib/cb_sha.c @@ -15,42 +15,24 @@ #include -int cb_sha_endian(enum vb2_hash_algorithm hash_alg, const uint8_t *data, uint32_t len, - uint8_t *digest, enum endian_algorithm endian) +vb2_error_t cb_sha_little_endian(enum vb2_hash_algorithm hash_alg, const uint8_t *data, + uint32_t len, uint8_t *digest) { int i; int rv; - uint32_t digest_size; - uint8_t *result_ptr; + uint32_t digest_size = vb2_digest_size(hash_alg); uint8_t result[VB2_MAX_DIGEST_SIZE]; - switch (hash_alg) { - case VB2_HASH_SHA1: - digest_size = VB2_SHA1_DIGEST_SIZE; - break; - case VB2_HASH_SHA256: - digest_size = VB2_SHA256_DIGEST_SIZE; - break; - case VB2_HASH_SHA512: - digest_size = VB2_SHA512_DIGEST_SIZE; - break; - default: + if (!digest_size) return VB2_ERROR_SHA_INIT_ALGORITHM; - } - result_ptr = result; - rv = vb2_digest_buffer(data, len, hash_alg, result_ptr, digest_size); - if (rv || (endian == NO_ENDIAN_ALGORITHM)) + rv = vb2_digest_buffer(data, len, hash_alg, (uint8_t *)&result, digest_size); + if (rv) return rv; for (i = 0; i < digest_size; ++i) { - if (endian == BIG_ENDIAN_ALGORITHM) { - /* use big endian */ - digest[i] = *result_ptr++; - } else { - /* use little endian */ - digest[digest_size - i - 1] = *result_ptr++; - } + /* use little endian */ + digest[digest_size - i - 1] = result[i]; } return rv; } diff --git a/src/superio/ite/it8716f/Kconfig b/src/vendorcode/eltan/security/mboot/Kconfig similarity index 57% rename from src/superio/ite/it8716f/Kconfig rename to src/vendorcode/eltan/security/mboot/Kconfig index 969e7882d9..c4e8dbabee 100644 --- a/src/superio/ite/it8716f/Kconfig +++ b/src/vendorcode/eltan/security/mboot/Kconfig @@ -1,8 +1,6 @@ -## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan +## Copyright (C) 2018-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -14,12 +12,17 @@ ## GNU General Public License for more details. ## -config SUPERIO_ITE_IT8716F - bool - select SUPERIO_ITE_COMMON_PRE_RAM +menu "Measured Boot (mboot)" -config SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL - bool - depends on SUPERIO_ITE_IT8716F +config VENDORCODE_ELTAN_MBOOT + bool "Measure firmware with mboot." default n - select SUPERIO_ITE_COMMON_PRE_RAM + help + Enabling MBOOT will use mboot to measure the components of the firmware + (stages, payload, etc). + +config VENDORCODE_ELTAN_CRTM_VERSION_STRING + string "default CRTM version" + default "default CRTM version" + +endmenu # Measured Boot (mboot) diff --git a/src/superio/fintek/f71805f/Kconfig b/src/vendorcode/eltan/security/mboot/Makefile.inc similarity index 53% rename from src/superio/fintek/f71805f/Kconfig rename to src/vendorcode/eltan/security/mboot/Makefile.inc index 7f06f55128..68b38586b1 100644 --- a/src/superio/fintek/f71805f/Kconfig +++ b/src/vendorcode/eltan/security/mboot/Makefile.inc @@ -1,8 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan +## Copyright (C) 2018-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -14,6 +13,17 @@ ## GNU General Public License for more details. ## -config SUPERIO_FINTEK_F71805F - bool - select SUPERIO_FINTEK_COMMON_PRE_RAM +ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) +CPPFLAGS_common += -I$(src)/security/mboot +endif + +ifeq ($(CONFIG_VENDORCODE_ELTAN_MBOOT),y) +postcar-y += mboot.c + +ramstage-y += mboot.c +ramstage-y += mboot_func.c + +romstage-y += mboot.c +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) + +endif # CONFIG_VENDORCODE_ELTAN_VBOOT or CONFIG_VENDORCODE_ELTAN_MBOOT diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c new file mode 100644 index 0000000000..b24bf3d480 --- /dev/null +++ b/src/vendorcode/eltan/security/mboot/mboot.c @@ -0,0 +1,545 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +/* + * Get the list of currently active PCR banks in TPM. + * + * @retval A map of active PCR banks. + */ +EFI_TCG2_EVENT_ALGORITHM_BITMAP tpm2_get_active_pcrs(void) +{ + int status; + TPML_PCR_SELECTION Pcrs; + EFI_TCG2_EVENT_ALGORITHM_BITMAP tpmHashAlgorithmBitmap = 0; + uint32_t activePcrBanks = 0; + uint32_t index; + + status = tpm2_get_capability_pcrs(&Pcrs); + if (status != TPM_SUCCESS) { + tpmHashAlgorithmBitmap = EFI_TCG2_BOOT_HASH_ALG_SHA1; + activePcrBanks = EFI_TCG2_BOOT_HASH_ALG_SHA1; + } else { + for (index = 0; index < Pcrs.count; index++) { + switch (Pcrs.pcrSelections[index].hash) { + case TPM_ALG_SHA1: + tpmHashAlgorithmBitmap |= + EFI_TCG2_BOOT_HASH_ALG_SHA1; + if (!is_zero_buffer(Pcrs.pcrSelections[index].pcrSelect, + Pcrs.pcrSelections[index].sizeofSelect)) + activePcrBanks |= + EFI_TCG2_BOOT_HASH_ALG_SHA1; + break; + case TPM_ALG_SHA256: + tpmHashAlgorithmBitmap |= + EFI_TCG2_BOOT_HASH_ALG_SHA256; + if (!is_zero_buffer(Pcrs.pcrSelections[index].pcrSelect, + Pcrs.pcrSelections[index].sizeofSelect)) + activePcrBanks |= + EFI_TCG2_BOOT_HASH_ALG_SHA256; + break; + case TPM_ALG_SHA384: + case TPM_ALG_SHA512: + case TPM_ALG_SM3_256: + default: + printk(BIOS_DEBUG, "%s: unsupported algorithm " + "reported - 0x%x\n", __func__, + Pcrs.pcrSelections[index].hash); + break; + } + } + } + printk(BIOS_DEBUG, "Tcg2 Capability values from TPM\n"); + printk(BIOS_DEBUG, "tpmHashAlgorithmBitmap - 0x%08x\n", + tpmHashAlgorithmBitmap); + printk(BIOS_DEBUG, "activePcrBanks - 0x%08x\n", + activePcrBanks); + + return activePcrBanks; +} + +/* + * tpm2_get_capability_pcrs + * + * Return the TPM PCR information. + * + * This function parses the data got from tlcl_get_capability and returns the + * PcrSelection. + * + * @param[out] Pcrs The Pcr Selection + * + * @retval TPM_SUCCESS Operation completed successfully. + * @retval TPM_E_IOERROR The command was unsuccessful. + */ +int tpm2_get_capability_pcrs(TPML_PCR_SELECTION *Pcrs) +{ + TPMS_CAPABILITY_DATA TpmCap; + int status; + int index; + + status = tlcl_get_capability(TPM_CAP_PCRS, 0, 1, &TpmCap); + if (status == TPM_SUCCESS) { + Pcrs->count = TpmCap.data.assignedPCR.count; + printk(BIOS_DEBUG, "Pcrs->count = %d\n", Pcrs->count); + for (index = 0; index < Pcrs->count; index++) { + Pcrs->pcrSelections[index].hash = + swab16(TpmCap.data.assignedPCR.pcrSelections[index].hash); + printk(BIOS_DEBUG, "Pcrs->pcrSelections[%d].hash = 0x%x\n", index, + Pcrs->pcrSelections[index].hash); + Pcrs->pcrSelections[index].sizeofSelect = + TpmCap.data.assignedPCR.pcrSelections[index].sizeofSelect; + memcpy(Pcrs->pcrSelections[index].pcrSelect, + TpmCap.data.assignedPCR.pcrSelections[index].pcrSelect, + Pcrs->pcrSelections[index].sizeofSelect); + } + } + return status; +} + +/* + * mboot_hash_extend_log + * + * Calculates the hash over the data and extends it in active PCR banks and + * then logs them in the event log. + * + * @param[in] activePcr bitmap of active PCR banks in TPM. + * @param[in] flags flags associated with hash data. Currently + * unused. + * @param[in] hashData data to be hashed. + * @param[in] hashDataLen length of the data to be hashed. + * @param[in] newEventHdr event header in TCG_PCR_EVENT2 format. + * @param[in] eventLog description of the event. + * @param[in] invalid invalidate the pcr + * + * @retval TPM_SUCCESS Operation completed successfully. + * @retval TPM_E_IOERROR Unexpected device behavior. + */ +int mboot_hash_extend_log(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, + uint64_t flags, uint8_t *hashData, uint32_t hashDataLen, + TCG_PCR_EVENT2_HDR *newEventHdr, uint8_t *eventLog, uint8_t invalid) +{ + int status; + TPMT_HA *digest = NULL; + int digest_num = 0; + + printk(BIOS_DEBUG, "%s: Hash Data Length: %zu bytes\n", __func__, + (size_t)hashDataLen); + + if (invalid) { + digest = &(newEventHdr->digest.digests[digest_num]); + digest->hashAlg = TPM_ALG_ERROR; + digest_num++; + } else { + /* + * Generate SHA1 hash if SHA1 PCR bank is active in TPM + * currently + */ + if (activePcr & EFI_TCG2_BOOT_HASH_ALG_SHA1) { + digest = &(newEventHdr->digest.digests[digest_num]); + if (flags & MBOOT_HASH_PROVIDED) { + /* The hash is provided as data */ + memcpy(digest->digest.sha1, (void *)hashData, + VB2_SHA1_DIGEST_SIZE); + } else { + if (cb_sha_little_endian(VB2_HASH_SHA1, hashData, + hashDataLen, digest->digest.sha1)) + return TPM_E_IOERROR; + } + + digest->hashAlg = TPM_ALG_SHA1; + digest_num++; + + printk(BIOS_DEBUG, "%s: SHA1 Hash Digest:\n", __func__); + mboot_print_buffer(digest->digest.sha1, + VB2_SHA1_DIGEST_SIZE); + } + + /* + * Generate SHA256 hash if SHA256 PCR bank is active in TPM + * currently + */ + if (activePcr & EFI_TCG2_BOOT_HASH_ALG_SHA256) { + digest = &(newEventHdr->digest.digests[digest_num]); + if (flags & MBOOT_HASH_PROVIDED) { + /* The hash is provided as data */ + memcpy(digest->digest.sha256, + (void *)hashData, hashDataLen); + } else { + + if (cb_sha_little_endian(VB2_HASH_SHA256, hashData, + hashDataLen, digest->digest.sha256)) + return TPM_E_IOERROR; + } + digest->hashAlg = TPM_ALG_SHA256; + digest_num++; + + printk(BIOS_DEBUG, "%s: SHA256 Hash Digest:\n", + __func__); + mboot_print_buffer(digest->digest.sha256, + VB2_SHA256_DIGEST_SIZE); + } + } + + newEventHdr->digest.count = digest_num; + + status = tlcl_extend(newEventHdr->pcrIndex, (uint8_t *)&(newEventHdr->digest), + NULL); + if (status != TPM_SUCCESS) + printk(BIOS_DEBUG, "%s: returned 0x%x\n", __func__, status); + + return status; +} + +/* + * invalidate_pcrs + * + * Invalidate PCRs 0-7 with extending 1 after tpm failure. + */ +void invalidate_pcrs(void) +{ + int status, pcr; + TCG_PCR_EVENT2_HDR tcgEventHdr; + EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrs; + uint8_t invalidate; + + ActivePcrs = tpm2_get_active_pcrs(); + invalidate = 1; + + for (pcr = 0; pcr < 8; pcr++) { + printk(BIOS_DEBUG, "%s: Invalidating PCR %d\n", __func__, pcr); + memset(&tcgEventHdr, 0, sizeof(tcgEventHdr)); + tcgEventHdr.pcrIndex = pcr; + tcgEventHdr.eventType = EV_NO_ACTION; + tcgEventHdr.eventSize = (uint32_t) sizeof(invalidate); + + status = mboot_hash_extend_log(ActivePcrs, 0, + (uint8_t *)&invalidate, tcgEventHdr.eventSize, + &tcgEventHdr, (uint8_t *)"Invalidate PCR", invalidate); + + if (status != TPM_SUCCESS) + printk(BIOS_DEBUG, "%s: invalidating pcr %d returned" + " 0x%x\n", __func__, pcr, status); + } +} + +/* + * is_zero_buffer + * + * Check if buffer is all zero. + * + * @param[in] buffer Buffer to be checked. + * @param[in] size Size of buffer to be checked. + * + * @retval TRUE buffer is all zero. + * @retval FALSE buffer is not all zero. + */ +int is_zero_buffer(void *buffer, unsigned int size) +{ + uint8_t *ptr; + + ptr = buffer; + while (size--) { + if (*(ptr++) != 0) + return false; + } + return true; +} + +/* + * Prints command or response buffer for debugging purposes. + * + * @param[in] Buffer Buffer to print. + * @param[in] BufferSize Buffer data length. + * + * @retval None + */ +void mboot_print_buffer(uint8_t *buffer, uint32_t bufferSize) +{ + uint32_t index; + + printk(BIOS_DEBUG, "Buffer Address: 0x%08x, Size: 0x%08x, Value:\n", + (unsigned int)*buffer, bufferSize); + for (index = 0; index < bufferSize; index++) { + printk(BIOS_DEBUG, "%02x ", *(buffer + index)); + if ((index+1) % 16 == 0) + printk(BIOS_DEBUG, "\n"); + } + printk(BIOS_DEBUG, "\n"); +} + +/* + * measures and logs the specified cbfs file. + * + * @param[in] activePcr bitmap of active PCR banks in TPM. + * @param[in] name name of the cbfs file to measure + * @param[in] type data type of the cbfs file. + * @param[in] pcr pcr to extend. + * @param[in] evenType tcg event type. + * @param[in] event_msg description of the event. + * + * @retval TPM_SUCCESS Operation completed successfully. + * @retval TPM_E_IOERROR Unexpected device behavior. + */ +int mb_measure_log_worker(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, + const char *name, uint32_t type, uint32_t pcr, + TCG_EVENTTYPE eventType, const char *event_msg) +{ + int status; + TCG_PCR_EVENT2_HDR tcgEventHdr; + uint8_t *base; + size_t size; + + printk(BIOS_DEBUG, "%s: Measure %s\n", __func__, name); + base = cbfs_boot_map_with_leak(name, type, &size); + + if (base == NULL) { + printk(BIOS_DEBUG, "%s: CBFS locate fail: %s\n", __func__, + name); + return VB2_ERROR_READ_FILE_OPEN; + } + + printk(BIOS_DEBUG, "%s: CBFS locate success: %s\n", + __func__, name); + memset(&tcgEventHdr, 0, sizeof(tcgEventHdr)); + tcgEventHdr.pcrIndex = pcr; + tcgEventHdr.eventType = eventType; + if (event_msg) + tcgEventHdr.eventSize = (uint32_t) strlen(event_msg); + + status = mboot_hash_extend_log(activePcr, 0, base, size, &tcgEventHdr, + (uint8_t *)event_msg, 0); + return status; +} + +#ifdef __PRE_RAM__ +/* + * Called from early romstage + * + *mb_entry + * + * initializes measured boot mechanism, initializes the tpm library and starts the tpm called + * by mb_measure + * + * The function can be overridden at the mainboard level my simply creating a function with the + * same name there. + * + * @param[in] wake_from_s3 1 if we are waking from S3, 0 standard boot + * + * @retval TPM_SUCCESS Operation completed successfully. + * @retval TPM_E_IOERROR Unexpected device behavior. +**/ + +int __attribute__((weak)) mb_entry(int wake_from_s3) +{ + int status; + + /* Initialize TPM driver. */ + printk(BIOS_DEBUG, "%s: tlcl_lib_init\n", __func__); + if (tlcl_lib_init() != VB2_SUCCESS) { + printk(BIOS_ERR, "%s: TPM driver initialization failed.\n", __func__); + return TPM_E_IOERROR; + } + + if (wake_from_s3) { + printk(BIOS_DEBUG, "%s: tlcl_resume\n", __func__); + status = tlcl_resume(); + } else { + printk(BIOS_DEBUG, "%s: tlcl_startup\n", __func__); + status = tlcl_startup(); + } + + if (status) + printk(BIOS_ERR, "%s: StartUp failed 0x%x!\n", __func__, status); + + return status; +} + +/* + * + * mb_measure + * + * initial call to the measured boot mechanism, initializes the + * tpm library, starts the tpm and performs the measurements defined by + * the coreboot platform. + * + * The pcrs will be invalidated if the measurement fails + * + * The function can be overridden at the mainboard level my simply creating a + * function with the same name there. + * + * @param[in] wake_from_s3 1 if we are waking from S3, 0 standard boot + * + * @retval TPM_SUCCESS Operation completed successfully. + * @retval TPM_E_IOERROR Unexpected device behavior. + */ + +int __attribute__((weak))mb_measure(int wake_from_s3) +{ + uint32_t status; + + status = mb_entry(wake_from_s3); + if (status == TPM_SUCCESS) { + printk(BIOS_DEBUG, "%s: StartUp, successful!\n", __func__); + status = mb_measure_log_start(); + if (status == TPM_SUCCESS) { + printk(BIOS_DEBUG, "%s: Measuring, successful!\n", __func__); + } else { + invalidate_pcrs(); + printk(BIOS_ERR, "%s: Measuring returned 0x%x unsuccessful! PCRs invalidated.\n", + __func__, status); + } + } else { + invalidate_pcrs(); + printk(BIOS_ERR, "%s: StartUp returned 0x%x, unsuccessful! PCRs invalidated.\n", __func__, + status); + } + return status; +} + +/* + * + * mb_measure_log_start + * + * performs the measurements defined by the the board routines. + * + * The logging is defined by the mb_log_list structure + * + * These items need to be defined in the mainboard part of the mboot + * implementation + * + * The function can be overridden at the mainboard level my simply creating a + * function with the same name there. + * + * @param[in] none + * + * @retval TPM_SUCCESS Operation completed successfully. + * @retval TPM_E_IOERROR Unexpected device behavior. + */ +int __attribute__((weak))mb_measure_log_start(void) +{ + int status; + EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrs; + uint32_t i; + + ActivePcrs = tpm2_get_active_pcrs(); + + if (ActivePcrs == 0x0) { + printk(BIOS_DEBUG, "%s: No Active PCR Bank in TPM.\n", + __func__); + return TPM_E_IOERROR; + } + + status = mb_crtm(ActivePcrs); + if (status != TPM_SUCCESS) { + printk(BIOS_DEBUG, "%s: Fail! CRTM Version can't be measured." + " ABORTING!!!\n", __func__); + return status; + } + printk(BIOS_DEBUG, "%s: Success! CRTM Version measured.\n", __func__); + + /* Log the items defined by the mainboard */ + for (i = 0; i < ARRAY_SIZE(mb_log_list); i++) { + status = mb_measure_log_worker( + ActivePcrs, mb_log_list[i].cbfs_name, + mb_log_list[i].cbfs_type, mb_log_list[i].pcr, + mb_log_list[i].eventType, + mb_log_list[i].event_msg); + if (status != TPM_SUCCESS) { + printk(BIOS_DEBUG, "%s: Fail! %s can't be measured." + "ABORTING!!!\n", __func__, + mb_log_list[i].cbfs_name); + return status; + } + printk(BIOS_DEBUG, "%s: Success! %s measured to pcr" + "%d.\n", __func__, mb_log_list[i].cbfs_name, + mb_log_list[i].pcr); + } + return status; +} + +static const uint8_t crtm_version[] = + CONFIG_VENDORCODE_ELTAN_CRTM_VERSION_STRING\ + COREBOOT_VERSION COREBOOT_EXTRA_VERSION " " COREBOOT_BUILD; + +/* + * + * mb_crtm + * + * measures the crtm version. this consists of a string than can be + * defined using make menuconfig and automatically generated version + * information. + * + * The function can be overridden at the mainboard level my simply creating a + * function with the same name there. + * + * @param[in] activePcr bitmap of the support + * + * @retval TPM_SUCCESS Operation completed successfully. + * @retval TPM_E_IOERROR Unexpected device behavior. +**/ +int __attribute__((weak))mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr) +{ + int status; + TCG_PCR_EVENT2_HDR tcgEventHdr; + uint8_t hash[VB2_SHA256_DIGEST_SIZE]; + uint8_t *msgPtr; + + /* Use FirmwareVersion string to represent CRTM version. */ + printk(BIOS_DEBUG, "%s: Measure CRTM Version\n", __func__); + memset(&tcgEventHdr, 0, sizeof(tcgEventHdr)); + tcgEventHdr.pcrIndex = MBOOT_PCR_INDEX_0; + tcgEventHdr.eventType = EV_S_CRTM_VERSION; + tcgEventHdr.eventSize = sizeof(crtm_version); + printk(BIOS_DEBUG, "%s: EventSize - %u\n", __func__, + tcgEventHdr.eventSize); + + status = mboot_hash_extend_log(activePcr, 0, (uint8_t *)crtm_version, + tcgEventHdr.eventSize, &tcgEventHdr, (uint8_t *)crtm_version, + 0); + if (status) { + printk(BIOS_DEBUG, "Measure CRTM Version returned 0x%x\n", status); + return status; + } + + status = get_intel_me_hash(hash); + if (status) { + printk(BIOS_DEBUG, "get_intel_me_hash returned 0x%x\n", status); + status = TPM_E_IOERROR; + return status; + } + + /* Add the me hash */ + printk(BIOS_DEBUG, "%s: Add the hash returned by the ME\n", + __func__); + memset(&tcgEventHdr, 0, sizeof(tcgEventHdr)); + tcgEventHdr.pcrIndex = MBOOT_PCR_INDEX_0; + tcgEventHdr.eventType = EV_S_CRTM_CONTENTS; + + msgPtr = NULL; + tcgEventHdr.eventSize = 0; + status = mboot_hash_extend_log(activePcr, MBOOT_HASH_PROVIDED, hash, + sizeof(hash), &tcgEventHdr, msgPtr, 0); + if (status) + printk(BIOS_DEBUG, "Add ME hash returned 0x%x\n", status); + + return status; +} +#endif // __PRE_RAM__ diff --git a/src/vendorcode/eltan/security/mboot/mboot.h b/src/vendorcode/eltan/security/mboot/mboot.h new file mode 100644 index 0000000000..96375aba5b --- /dev/null +++ b/src/vendorcode/eltan/security/mboot/mboot.h @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MBOOT_H +#define MBOOT_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* TPM2 interface */ +#define EFI_TPM2_ACPI_TABLE_START_METHOD_TIS 6 +#define TPM_SHA1_160_HASH_LEN 0x14 + +/* Part 2, section 5.4: TPM_DIGEST */ + +/* Index to a PCR register */ +typedef uint32_t TPM_PCRINDEX; +typedef uint32_t TCG_EVENTTYPE; +typedef TPM_PCRINDEX TCG_PCRINDEX; +typedef int8_t TCG_DIGEST; + +/* TCG_PCR_EVENT_HDR */ +typedef struct { + TCG_PCRINDEX pcrIndex; + TCG_EVENTTYPE eventType; + TCG_DIGEST digest[TPM_SHA1_160_HASH_LEN]; + uint32_t eventSize; +} __packed TCG_PCR_EVENT_HDR; + +/* TCG_PCR_EVENT2_HDR */ +typedef struct { + TCG_PCRINDEX pcrIndex; + TCG_EVENTTYPE eventType; + TPML_DIGEST_VALUES digest; + uint32_t eventSize; +} __packed TCG_PCR_EVENT2_HDR; + +typedef uint32_t EFI_TCG2_EVENT_ALGORITHM_BITMAP; + +#define EFI_TCG2_BOOT_HASH_ALG_SHA1 0x00000001 +#define EFI_TCG2_BOOT_HASH_ALG_SHA256 0x00000002 +#define EFI_TCG2_BOOT_HASH_ALG_SHA384 0x00000004 +#define EFI_TCG2_BOOT_HASH_ALG_SHA512 0x00000008 +#define EFI_TCG2_BOOT_HASH_ALG_SM3_256 0x00000010 + +/* Standard event types */ +#define EV_POST_CODE ((TCG_EVENTTYPE) 0x00000001) +#define EV_NO_ACTION ((TCG_EVENTTYPE) 0x00000003) +#define EV_SEPARATOR ((TCG_EVENTTYPE) 0x00000004) +#define EV_S_CRTM_CONTENTS ((TCG_EVENTTYPE) 0x00000007) +#define EV_S_CRTM_VERSION ((TCG_EVENTTYPE) 0x00000008) +#define EV_CPU_MICROCODE ((TCG_EVENTTYPE) 0x00000009) +#define EV_TABLE_OF_DEVICES ((TCG_EVENTTYPE) 0x0000000B) + +#define MBOOT_PCR_INDEX_0 0x0 +#define MBOOT_PCR_INDEX_1 0x1 +#define MBOOT_PCR_INDEX_2 0x2 +#define MBOOT_PCR_INDEX_3 0x3 +#define MBOOT_PCR_INDEX_4 0x4 +#define MBOOT_PCR_INDEX_5 0x5 +#define MBOOT_PCR_INDEX_6 0x6 +#define MBOOT_PCR_INDEX_7 0x7 + +/* + * used to indicate a hash is provide so there is no need to perform the + * measurement + */ +#define MBOOT_HASH_PROVIDED (0x00000001) + + +int is_zero_buffer(void *buffer, unsigned int size); + +int mboot_hash_extend_log(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, + uint64_t flags, uint8_t *hashData, uint32_t hashDataLen, + TCG_PCR_EVENT2_HDR *newEventHdr, uint8_t *eventLog, uint8_t invalid); + +void mboot_print_buffer(uint8_t *buffer, uint32_t bufferSize); + +int mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr); + +typedef struct { + const char *cbfs_name; + uint32_t cbfs_type; + uint32_t pcr; + TCG_EVENTTYPE eventType; + const char *event_msg; +} mboot_measure_item_t; + +int mb_measure_log_worker(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, + const char *name, uint32_t type, uint32_t pcr, + TCG_EVENTTYPE eventType, const char *event_msg); + +int mb_measure_log_start(void); +void invalidate_pcrs(void); + +EFI_TCG2_EVENT_ALGORITHM_BITMAP tpm2_get_active_pcrs(void); + +int tpm2_get_capability_pcrs(TPML_PCR_SELECTION *Pcrs); + +int mb_measure(int wake_from_s3); +int mb_entry(int wake_from_s3); + +int log_efi_specid_event(EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrs); +int log_event_tcg_20_format(TCG_PCR_EVENT2_HDR *EventHdr, uint8_t *EventLog); +int log_event_tcg_12_format(TCG_PCR_EVENT2_HDR *EventHdr, uint8_t *EventLog); + +int get_intel_me_hash(uint8_t *hash); + +#endif /* MBOOT_H */ diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/vendorcode/eltan/security/mboot/mboot_func.c similarity index 59% rename from src/soc/intel/skylake/include/fsp11/soc/romstage.h rename to src/vendorcode/eltan/security/mboot/mboot_func.c index 386931043d..ec66d345d0 100644 --- a/src/soc/intel/skylake/include/fsp11/soc/romstage.h +++ b/src/vendorcode/eltan/security/mboot/mboot_func.c @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,14 +13,16 @@ * GNU General Public License for more details. */ -#ifndef _SOC_ROMSTAGE_H_ -#define _SOC_ROMSTAGE_H_ +#include -#include +int log_efi_specid_event(EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrs) { + return TPM_SUCCESS; +} -void systemagent_early_init(void); -void intel_early_me_status(void); -void enable_smbus(void); -int smbus_read_byte(unsigned int device, unsigned int address); +int log_event_tcg_12_format(TCG_PCR_EVENT2_HDR *EventHdr, uint8_t *EventLog) { + return TPM_SUCCESS; +} -#endif /* _SOC_ROMSTAGE_H_ */ +int log_event_tcg_20_format(TCG_PCR_EVENT2_HDR *EventHdr, uint8_t *EventLog) { + return TPM_SUCCESS; +} diff --git a/src/vendorcode/eltan/security/verified_boot/Kconfig b/src/vendorcode/eltan/security/verified_boot/Kconfig new file mode 100644 index 0000000000..ab254c48d9 --- /dev/null +++ b/src/vendorcode/eltan/security/verified_boot/Kconfig @@ -0,0 +1,67 @@ +## This file is part of the coreboot project. +## +## Copyright (C) 2018-2019 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +menu "Verified Boot (verified_boot)" + +config VENDORCODE_ELTAN_VBOOT + bool "Enable Verified Boot" + depends on !VBOOT + default n + +config VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST + bool "Enable Signed Manifest" + depends on VENDORCODE_ELTAN_VBOOT + default n + +config VENDORCODE_ELTAN_VBOOT_USE_SHA512 + bool "SHA512 hashes" + depends on VENDORCODE_ELTAN_VBOOT + default n + help + Use SHA512 for the vboot operations, this applies to the digest in + the manifest and the manifest digest. + +config VENDORCODE_ELTAN_OEM_MANIFEST_LOC + hex "Manifest Location" + default 0xFFFFF840 + +config VENDORCODE_ELTAN_VBOOT_MANIFEST + string "Verified boot manifest file" + default "mainboard/$(MAINBOARD_DIR)/manifest.h" + +config VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS + int "Manifest Items" + default 12 + +config VENDORCODE_ELTAN_OEM_MANIFEST_ITEM_SIZE + int + default 64 if VENDORCODE_ELTAN_VBOOT_USE_SHA512 + default 32 + +config VENDORCODE_ELTAN_VBOOT_KEY_LOCATION + hex "Verified boot Key Location" + depends on VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST + default 0xFFFFF500 + +config VENDORCODE_ELTAN_VBOOT_KEY_FILE + string "Verified boot Key File" + depends on VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST + default "3rdparty/eltan/verified_boot/Keys/key.vbpubk2" + +config VENDORCODE_ELTAN_VBOOT_KEY_SIZE + int + default 610 if VENDORCODE_ELTAN_VBOOT_USE_SHA512 + default 576 + +endmenu # Verified Boot (verified_boot) diff --git a/src/vendorcode/eltan/security/verified_boot/Makefile.inc b/src/vendorcode/eltan/security/verified_boot/Makefile.inc new file mode 100644 index 0000000000..357e520298 --- /dev/null +++ b/src/vendorcode/eltan/security/verified_boot/Makefile.inc @@ -0,0 +1,47 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018-2019 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) + +CPPFLAGS_common += -I$(src)/security/vboot + +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += vboot_check.c +postcar-y += vboot_check.c +romstage-y += vboot_check.c +ramstage-y += vboot_check.c + +ifeq ($(CONFIG_VENDORCODE_ELTAN_VBOOT),y) +cbfs-files-y += oemmanifest.bin +oemmanifest.bin-file := $(obj)/oemmanifest.bin +oemmanifest.bin-position := $(CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC) +oemmanifest.bin-type := raw + +$(obj)/oemmanifest.bin: +ifeq ($(CONFIG_VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST),y) + dd if=/dev/zero of=$@ seek=8 bs=$(CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEM_SIZE) count=$(CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS) +else # ($(CONFIG_VERIFIED_BOOT_SIGNED_MANIFEST),y) + dd if=/dev/zero of=$@ bs=$(CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEM_SIZE) count=$(CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS) +endif # ($(CONFIG_VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST),y) + +ifeq ($(CONFIG_VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST),y) +cbfs-files-y += vboot_public_key.bin +vboot_public_key.bin-file := $(call strip_quotes, $(CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_FILE)) +vboot_public_key.bin-position := $(CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION) +vboot_public_key.bin-type := raw + +endif # ($(CONFIG_VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST),y) +endif # CONFIG_VENDORCODE_ELTAN_VBOOT + +endif # CONFIG_VENDORCODE_ELTAN_VBOOT or CONFIG_VENDORCODE_ELTAN_MBOOT diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c new file mode 100644 index 0000000000..88519bdd78 --- /dev/null +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -0,0 +1,431 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2017-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include "fmap_config.h" + +#define RSA_PUBLICKEY_FILE_NAME "vboot_public_key.bin" + +#if CONFIG(VENDORCODE_ELTAN_VBOOT_USE_SHA512) +#define DIGEST_SIZE VB2_SHA512_DIGEST_SIZE +#define HASH_ALG VB2_HASH_SHA512 +#else +#define DIGEST_SIZE VB2_SHA256_DIGEST_SIZE +#define HASH_ALG VB2_HASH_SHA256 +#endif + +int verified_boot_check_manifest(void) +{ + uint8_t *buffer; + uint8_t sig_buffer[1024]; /* used to build vb21_signature */ + size_t size = 0; + struct vb2_public_key key; + struct vb2_workbuf wb; + struct vb21_signature *vb2_sig_hdr = (struct vb21_signature *)sig_buffer; + uint8_t wb_buffer[1024]; + + buffer = cbfs_boot_map_with_leak(RSA_PUBLICKEY_FILE_NAME, CBFS_TYPE_RAW, &size); + if (!buffer || !size) { + printk(BIOS_ERR, "ERROR: Public key not found!\n"); + goto fail; + } + + if ((size != CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_SIZE) || + (buffer != (void *)CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION)) { + printk(BIOS_ERR, "ERROR: Illegal public key!\n"); + goto fail; + } + + if (vb21_unpack_key(&key, buffer, size)) { + printk(BIOS_ERR, "ERROR: Invalid public key!\n"); + goto fail; + } + + cbfs_boot_map_with_leak("oemmanifest.bin", CBFS_TYPE_RAW, &size); + if (size != (CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE) + + vb2_rsa_sig_size(VB2_SIG_RSA2048)) { + printk(BIOS_ERR, "ERROR: Incorrect manifest size!\n"); + goto fail; + } + + /* prepare work buffer structure */ + wb.buf = (uint8_t *)&wb_buffer; + wb.size = sizeof(wb_buffer); + + /* Build vb2_sig_hdr buffer */ + vb2_sig_hdr->sig_offset = sizeof(struct vb21_signature) + + (CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE); + vb2_sig_hdr->sig_alg = VB2_SIG_RSA2048; + vb2_sig_hdr->sig_size = vb2_rsa_sig_size(VB2_SIG_RSA2048); + vb2_sig_hdr->hash_alg = HASH_ALG; + vb2_sig_hdr->data_size = CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE; + memcpy(&sig_buffer[sizeof(struct vb21_signature)], + (uint8_t *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC, size); + + if (vb21_verify_data(&sig_buffer[sizeof(struct vb21_signature)], vb2_sig_hdr->data_size, + (struct vb21_signature *)&sig_buffer, &key, &wb)) { + printk(BIOS_ERR, "ERROR: Signature verification failed for hash table\n"); + goto fail; + } + + printk(BIOS_INFO, "%s: Successfully verified hash_table signature.\n", __func__); + return 0; + +fail: + die("HASH table verification failed!\n"); + return -1; +} + +static int vendor_secure_locate(struct cbfs_props *props) +{ + struct cbfs_header header; + const struct region_device *bdev; + int32_t rel_offset; + size_t offset; + + bdev = boot_device_ro(); + + if (bdev == NULL) + return -1; + + size_t fmap_top = ___FMAP__COREBOOT_BASE + ___FMAP__COREBOOT_SIZE; + + /* Find location of header using signed 32-bit offset from + * end of CBFS region. */ + offset = fmap_top - sizeof(int32_t); + if (rdev_readat(bdev, &rel_offset, offset, sizeof(int32_t)) < 0) + return -1; + + offset = fmap_top + rel_offset; + if (rdev_readat(bdev, &header, offset, sizeof(header)) < 0) + return -1; + + header.magic = ntohl(header.magic); + header.romsize = ntohl(header.romsize); + header.offset = ntohl(header.offset); + + if (header.magic != CBFS_HEADER_MAGIC) + return -1; + + props->offset = header.offset; + props->size = header.romsize; + props->size -= props->offset; + + printk(BIOS_SPEW, "CBFS @ %zx size %zx\n", props->offset, props->size); + + return 0; +} + +#ifndef __BOOTBLOCK__ + +/* + * + * measure_item + * + * extends the defined pcr using the hash calculated by the verified boot + * routines. + * + * @param[in] pcr PCR to extend + * @param[in] *hashData Pointer to the hash data + * @param[in] hashDataLen Length of the hash data + * @param[in] *event_msg Message to log or display + * @param[in] eventType Event type to use when logging + + * @retval TPM_SUCCESS Operation completed successfully. + * @retval TPM_E_IOERROR Unexpected device behavior. + */ +static int measure_item(uint32_t pcr, uint8_t *hashData, uint32_t hashDataLen, + int8_t *event_msg, TCG_EVENTTYPE eventType) +{ + int status = TPM_SUCCESS; + TCG_PCR_EVENT2_HDR tcgEventHdr; + + memset(&tcgEventHdr, 0, sizeof(tcgEventHdr)); + tcgEventHdr.pcrIndex = pcr; + tcgEventHdr.eventType = eventType; + if (event_msg) { + status = mboot_hash_extend_log(MBOOT_HASH_PROVIDED, hashData, + hashDataLen, &tcgEventHdr, + (uint8_t *)event_msg); + if (status == TPM_SUCCESS) + printk(BIOS_INFO, "%s: Success! %s measured to pcr %d.\n", __func__, + event_msg, pcr); + } + return status; +} +#endif + +static void verified_boot_check_buffer(const char *name, void *start, size_t size, + uint32_t hash_index, int32_t pcr) +{ + uint8_t digest[DIGEST_SIZE]; + int hash_algorithm; + vb2_error_t status; + + printk(BIOS_DEBUG, "%s: %s HASH verification buffer %p size %d\n", __func__, name, + start, (int)size); + + if (start && size) { + if (CONFIG(VENDORCODE_ELTAN_VBOOT_USE_SHA512)) + hash_algorithm = VB2_HASH_SHA512; + else + hash_algorithm = VB2_HASH_SHA256; + + status = cb_sha_little_endian(hash_algorithm, (const uint8_t *)start, size, digest); + if ((CONFIG(VENDORCODE_ELTAN_VBOOT) && memcmp((void *)( + (uint8_t *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC + + sizeof(digest) * hash_index), digest, sizeof(digest))) || status) { + printk(BIOS_DEBUG, "%s: buffer hash\n", __func__); + hexdump(digest, sizeof(digest)); + printk(BIOS_DEBUG, "%s: manifest hash\n", __func__); + hexdump((void *)( (uint8_t *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC + + sizeof(digest) * hash_index), sizeof(digest)); + printk(BIOS_EMERG, "%s ", name); + die("HASH verification failed!\n"); + } else { +#ifndef __BOOTBLOCK__ + if (CONFIG(VENDORCODE_ELTAN_MBOOT)) { + if (pcr != -1) { + printk(BIOS_DEBUG, "%s: measuring %s\n", __func__, name); + if (measure_item(pcr, digest, sizeof(digest), + (int8_t *)name, 0)) + printk(BIOS_DEBUG, "%s: measuring failed!\n", + __func__); + } + } +#endif + if (CONFIG(VENDORCODE_ELTAN_VBOOT)) + printk(BIOS_DEBUG, "%s HASH verification success\n", name); + } + } else { + printk(BIOS_EMERG, "Invalid buffer\n"); + die("HASH verification failed!\n"); + } +} + +void verified_boot_check_cbfsfile(const char *name, uint32_t type, uint32_t hash_index, + void **buffer, uint32_t *filesize, int32_t pcr) +{ + void *start; + size_t size; + + start = cbfs_boot_map_with_leak(name, type & ~VERIFIED_BOOT_COPY_BLOCK, &size); + if (start && size) { + /* Speed up processing by copying the file content to memory first */ +#ifndef __PRE_RAM__ + if ((type & VERIFIED_BOOT_COPY_BLOCK) && (buffer) && (*buffer) && + ((uint32_t) start > (uint32_t)(~(CONFIG_CBFS_SIZE-1)))) { + printk(BIOS_DEBUG, "%s: move buffer to memory\n", __func__); + /* Move the file to a memory bufferof which we know it doesn't harm */ + memcpy(*buffer, start, size); + start = *buffer; + printk(BIOS_DEBUG, "%s: done\n", __func__); + } +#endif // __PRE_RAM__ + verified_boot_check_buffer(name, start, size, hash_index, pcr); + } else { + printk(BIOS_EMERG, "CBFS Failed to get file content for %s\n", name); + die("HASH verification failed!\n"); + } + if (buffer) + *buffer = start; + if (filesize) + *filesize = size; +} + +void process_verify_list(const verify_item_t list[]) +{ + int i = 0; + + while (list[i].type != VERIFY_TERMINATOR) { + switch (list[i].type) { + case VERIFY_FILE: + verified_boot_check_cbfsfile(list[i].name, list[i].data.file.cbfs_type, + list[i].hash_index, NULL, NULL, list[i].pcr); + if (list[i].data.file.related_items) { + printk(BIOS_SPEW, "process related items\n"); + process_verify_list( + (verify_item_t *)list[i].data.file.related_items); + } + break; + case VERIFY_BLOCK: + verified_boot_check_buffer(list[i].name, + (void *)list[i].data.block.start, + list[i].data.block.size, + list[i].hash_index, list[i].pcr); + break; + default: + printk(BIOS_EMERG, "INVALID TYPE IN VERIFY LIST 0x%x\n", list[i].type); + die("HASH verification failed!\n"); + } + i++; + } +} +#ifdef __BOOTBLOCK__ +/* + * BOOTBLOCK + */ + +extern verify_item_t bootblock_verify_list[]; + +void verified_boot_bootblock_check(void) +{ + printk(BIOS_SPEW, "%s: processing bootblock items\n", __func__); + + if (CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST)) { + printk(BIOS_SPEW, "%s: check the manifest\n", __func__); + if (verified_boot_check_manifest() != 0) + die("invalid manifest"); + } + printk(BIOS_SPEW, "%s: process bootblock verify list\n", __func__); + process_verify_list(bootblock_verify_list); +} + +static void vendor_secure_prepare(void) +{ + printk(BIOS_SPEW, "%s: bootblock\n", __func__); + verified_boot_bootblock_check(); +} +#endif //__BOOTBLOCK__ + +#ifdef __ROMSTAGE__ +/* + * ROMSTAGE + */ + +extern verify_item_t romstage_verify_list[]; + +void verified_boot_early_check(void) +{ + printk(BIOS_SPEW, "%s: processing early items\n", __func__); + + if (!CONFIG(C_ENVIRONMENT_BOOTBLOCK) && + CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST)) { + printk(BIOS_SPEW, "%s: check the manifest\n", __func__); + if (verified_boot_check_manifest() != 0) + die("invalid manifest"); + } + + if (CONFIG(VENDORCODE_ELTAN_MBOOT)) { + printk(BIOS_DEBUG, "mb_measure returned 0x%x\n", + mb_measure(vboot_platform_is_resuming())); + } + + printk(BIOS_SPEW, "%s: process early verify list\n", __func__); + process_verify_list(romstage_verify_list); +} + +static int prepare_romstage = 0; + +static void vendor_secure_prepare(void) +{ + printk(BIOS_SPEW, "%s: romstage\n", __func__); + if (!prepare_romstage) { + verified_boot_early_check(); + prepare_romstage = 1; + } +} +#endif //__ROMSTAGE__ + +#ifdef __POSTCAR__ +/* + * POSTCAR + */ + +extern verify_item_t postcar_verify_list[]; + +static void vendor_secure_prepare(void) +{ + printk(BIOS_SPEW, "%s: postcar\n", __func__); + process_verify_list(postcar_verify_list); +} +#endif //__POSTCAR__ + +#ifdef __RAMSTAGE__ +/* + * RAM STAGE + */ + +static int process_oprom_list(const verify_item_t list[], + struct rom_header *rom_header) +{ + int i = 0; + struct pci_data *rom_data; + uint32_t viddevid = 0; + + if (le32_to_cpu(rom_header->signature) != PCI_ROM_HDR) { + printk(BIOS_ERR, "Incorrect expansion ROM header signature %04x DONT START\n", + le32_to_cpu(rom_header->signature)); + return 0; + } + + rom_data = (((void *)rom_header) + le32_to_cpu(rom_header->data)); + + viddevid |= (rom_data->vendor << 16); + viddevid |= rom_data->device; + + while (list[i].type != VERIFY_TERMINATOR) { + switch (list[i].type) { + case VERIFY_OPROM: + if (viddevid == list[i].data.oprom.viddev) { + verified_boot_check_buffer(list[i].name, + (void *)rom_header, + rom_header->size * 512, + list[i].hash_index, list[i].pcr); + if (list[i].data.oprom.related_items) { + printk(BIOS_SPEW, "%s: process related items\n", + __func__); + process_verify_list( + (verify_item_t *)list[i].data.oprom.related_items); + } + printk(BIOS_SPEW, "%s: option rom can be started\n", __func__); + return 1; + } + break; + default: + printk(BIOS_EMERG, "%s: INVALID TYPE IN OPTION ROM LIST 0x%x\n", + __func__, list[i].type); + die("HASH verification failed!\n"); + } + i++; + } + printk(BIOS_ERR, "%s: option rom not in list DONT START\n", __func__); + return 0; +} + +extern verify_item_t payload_verify_list[]; + +extern verify_item_t oprom_verify_list[]; + +int verified_boot_should_run_oprom(struct rom_header *rom_header) +{ + return process_oprom_list(oprom_verify_list, rom_header); +} + +static void vendor_secure_prepare(void) +{ + printk(BIOS_SPEW, "%s: ramstage\n", __func__); + process_verify_list(payload_verify_list); +} +#endif //__RAMSTAGE__ + +const struct cbfs_locator cbfs_master_header_locator = { + .name = "Vendorcode Header Locator", + .prepare = vendor_secure_prepare, + .locate = vendor_secure_locate +}; diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.h b/src/vendorcode/eltan/security/verified_boot/vboot_check.h new file mode 100644 index 0000000000..22f1edf948 --- /dev/null +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.h @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2017-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VBOOT_CHECK_H +#define VBOOT_CHECK_H + +#include +#include +#include +#include +#include CONFIG_VENDORCODE_ELTAN_VBOOT_MANIFEST +#include +#include +#include +#include +#include + +#define VERIFIED_BOOT_COPY_BLOCK 0x80000000 +/* These method verifies the SHA256 hash over the 'named' CBFS component. + * 'type' denotes the type of CBFS component i.e. stage, payload or fsp. + */ +#ifdef __BOOTBLOCK__ +void verified_boot_bootblock_check(void); +#endif +#ifdef __ROMSTAGE__ +void verified_boot_early_check(void); +#endif + +int verified_boot_check_manifest(void); + +void verified_boot_check_cbfsfile(const char *name, uint32_t type, + uint32_t hash_index, void **buffer, uint32_t *filesize, int32_t pcr); + +typedef enum { + VERIFY_TERMINATOR = 0, + VERIFY_FILE, + VERIFY_BLOCK, + VERIFY_OPROM + +} verify_type; + +typedef struct { + verify_type type; + const char *name; + union { + struct { + const void *related_items; + uint32_t cbfs_type; + } file; + struct { + const void *start; + uint32_t size; + } block; + struct { + const void *related_items; + uint32_t viddev; + } oprom; + } data; + uint32_t hash_index; + int32_t pcr; +} verify_item_t; + +void process_verify_list(const verify_item_t list[]); + +#endif //VBOOT_CHECK_H diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 2ff7ec70b8..cdb4305fdd 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -95,5 +95,14 @@ config CHROMEOS_USE_EC_WATCHDOG_FLAG help Use the AP watchdog flag stored in EC. +config CHROMEOS_DSM_CALIB + bool + default n + help + On some boards, there are calibrated parameters for Dynamic Speaker Management(DSM) + stored in VPD. Enable this config to read and parse these VPD values and write them + to ACPI DSD table in device driver. These parameters will be applied by kernel driver + through device property at boot. + endif # CHROMEOS endmenu diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 000d056509..05acdeec9a 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -21,6 +21,7 @@ ramstage-y += vpd_mac.c vpd_serialno.c vpd_calibration.c ramstage-$(CONFIG_CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME) += tpm2.c ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c ramstage-$(CONFIG_USE_SAR) += sar.c +ramstage-$(CONFIG_CHROMEOS_DSM_CALIB) += dsm_calib.c ramstage-$(CONFIG_TPM_CR50) += cr50_enable_update.c ifeq ($(CONFIG_ARCH_MIPS),) bootblock-y += watchdog.c diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index e5420ac099..a40c4c9a88 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -23,6 +23,7 @@ #include #include #include +#include #if CONFIG(CHROMEOS) /* functions implemented in watchdog.c */ @@ -58,6 +59,16 @@ static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {} void cbmem_add_vpd_calibration_data(void); +/** + * get_dsm_calibration_from_key - Gets value related to DSM calibration from VPD + * @key: The key in RO_VPD. The valid prefix is "dsm_calib_". The valid keys are + * documented in https://chromeos.google.com/partner/dlm/docs/factory/vpd.html. + * @value: Output value. The value read from VPD parsed into uint64_t integer. + * + * Returns CB_SUCCESS on success or CB_ERR on failure. + */ +enum cb_err get_dsm_calibration_from_key(const char *key, uint64_t *value); + /* * Create the OIPG package containing the Chrome OS gpios described by * the chromeos_gpio array. diff --git a/src/vendorcode/google/chromeos/dsm_calib.c b/src/vendorcode/google/chromeos/dsm_calib.c new file mode 100644 index 0000000000..d3b14cb03c --- /dev/null +++ b/src/vendorcode/google/chromeos/dsm_calib.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#define DSM_BUF_LEN 128 +#define DSM_PREFIX "dsm_calib_" + +enum cb_err get_dsm_calibration_from_key(const char *key, uint64_t *value) +{ + static char buf[DSM_BUF_LEN]; + char *ret; + long value_from_vpd; + + if (strncmp(key, DSM_PREFIX, strlen(DSM_PREFIX))) { + printk(BIOS_ERR, "got invalid dsm_calib key: %s\n", key); + return CB_ERR; + } + + ret = vpd_gets(key, buf, DSM_BUF_LEN, VPD_RO); + if (!ret) { + printk(BIOS_ERR, "failed to find key in VPD: %s\n", key); + return CB_ERR; + } + + value_from_vpd = atol(buf); + if (value_from_vpd <= 0) { + printk(BIOS_ERR, "got invalid dsm_calib from VPD: %ld\n", value_from_vpd); + return CB_ERR; + } + + *value = value_from_vpd; + + return CB_SUCCESS; +} diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h index 0df3063e5c..f56cba9b5c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h @@ -37,49 +37,49 @@ are permitted provided that the following conditions are met: #pragma pack(1) - -/// -/// Azalia Header structure -/// -typedef struct { - UINT16 VendorId; ///< Codec Vendor ID - UINT16 DeviceId; ///< Codec Device ID - UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. - UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. - UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. - UINT32 Reserved; ///< Reserved for future use. Must be set to 0. -} AZALIA_HEADER; - -/// -/// Audio Azalia Verb Table structure -/// -typedef struct { - AZALIA_HEADER Header; ///< AZALIA PCH header - UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header -} AUDIO_AZALIA_VERB_TABLE; - -/// -/// Refer to the definition of PCH_INT_PIN -/// -typedef enum { - SiPchNoInt, ///< No Interrupt Pin - SiPchIntA, - SiPchIntB, - SiPchIntC, - SiPchIntD -} SI_PCH_INT_PIN; -/// -/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. -/// -typedef struct { - UINT8 Device; ///< Device number - UINT8 Function; ///< Device function - UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) - UINT8 Irq; ///< IRQ to be set for device. -} SI_PCH_DEVICE_INTERRUPT_CONFIG; - -#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + /** Fsp S Configuration **/ @@ -3621,7 +3621,17 @@ typedef struct { **/ UINT32 SdCardRxCmdDataDelay2RegValue; -/** Offset 0x0ABC +/** Offset 0x0ABC - Enforce Enhanced Debug Mode + Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 EnforceEDebugMode; + +/** Offset 0x0ABD +**/ + UINT8 UnusedUpdSpace31[7]; + +/** Offset 0x0AC4 **/ UINT8 ReservedFspsTestUpd[12]; } FSP_S_TEST_CONFIG; @@ -3642,11 +3652,11 @@ typedef struct { **/ FSP_S_TEST_CONFIG FspsTestConfig; -/** Offset 0x0AC8 +/** Offset 0x0AD0 **/ - UINT8 UnusedUpdSpace31[6]; + UINT8 UnusedUpdSpace32[6]; -/** Offset 0x0ACE +/** Offset 0x0AD6 **/ UINT16 UpdTerminator; } FSPS_UPD; diff --git a/src/vendorcode/siemens/Kconfig b/src/vendorcode/siemens/Kconfig index 8bbab62268..6684b8af97 100644 --- a/src/vendorcode/siemens/Kconfig +++ b/src/vendorcode/siemens/Kconfig @@ -16,5 +16,3 @@ config USE_SIEMENS_HWILIB bool default n - -source "src/vendorcode/siemens/*/Kconfig" diff --git a/util/abuild/abuild b/util/abuild/abuild index 4a62cfa045..23b22aaa9b 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -471,13 +471,14 @@ function build_config required_arches=$(grep -E "^CONFIG_ARCH_(BOOTBLOCK|R.MSTAGE|VERSTAGE)" "$TARGET/${BUILD_NAME}/config.build" | \ sed "s,^CONFIG_ARCH_[^_]*_\([^=]*\)=.*$,\1," |sort -u |tr 'A-Z\n\r' 'a-z ') - missing_arches="$($MAKE --no-print-directory -f - \ - REQUIRED_ARCHES="$required_arches" <<'EOF' + missing_arches="$($MAKE --no-print-directory -f Makefile -f - \ + REQUIRED_ARCHES="$required_arches" obj="${build_dir}" <<'EOF' include .xcompile .PHONY: missing_arches missing_arches: $(if $(XCOMPILE_COMPLETE),,$(error .xcompile is invalid.)) @echo $(foreach arch,$(REQUIRED_ARCHES),$(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch))) +.DEFAULT_GOAL := missing_arches EOF )" # shellcheck disable=SC2181 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 4c5b2163d4..02564cf5ba 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -357,7 +357,11 @@ static amd_fw_entry amd_fw_table[] = { }; static amd_bios_entry amd_bios_table[] = { - { .type = AMD_BIOS_APCB, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 3, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 4, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB_BK, .level = BDT_BOTH }, { .type = AMD_BIOS_APOB, .level = BDT_BOTH }, { .type = AMD_BIOS_BIN, @@ -387,6 +391,8 @@ typedef struct _embedded_firmware { uint32_t comboable; uint32_t bios0_entry; /* todo: add way to select correct entry */ uint32_t bios1_entry; + uint32_t bios2_entry; + uint32_t reserved[0x2c]; /* 0x24 - 0x4f */ } __attribute__((packed, aligned(16))) embedded_firmware; typedef struct _psp_directory_header { diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index b082d8c783..4bc95ab4da 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -106,6 +106,7 @@ struct cbfs_file_attribute { #define CBFS_FILE_ATTR_TAG_POSITION 0x42435350 /* PSCB */ #define CBFS_FILE_ATTR_TAG_ALIGNMENT 0x42434c41 /* ALCB */ #define CBFS_FILE_ATTR_TAG_PADDING 0x47444150 /* PDNG */ +#define CBFS_FILE_ATTR_TAG_IBB 0x32494242 /* Initial BootBlock */ struct cbfs_file_attr_compression { uint32_t tag; diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 5cbe1f185a..452c9d9a04 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -3,6 +3,8 @@ * * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. * Copyright (C) 2016 Siemens AG. All rights reserved. + * Copyright (C) 2019 9elements Agency GmbH + * Copyright (C) 2019 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -656,7 +658,8 @@ static int cbfs_add_entry_at(struct cbfs_image *image, struct cbfs_file *entry, const void *data, uint32_t content_offset, - const struct cbfs_file *header) + const struct cbfs_file *header, + const size_t len_align) { struct cbfs_file *next = cbfs_find_next_entry(image, entry); uint32_t addr = cbfs_get_entry_addr(image, entry), @@ -708,6 +711,13 @@ static int cbfs_add_entry_at(struct cbfs_image *image, memcpy(CBFS_SUBHEADER(entry), data, ntohl(entry->len)); if (verbose > 1) cbfs_print_entry_info(image, entry, stderr); + // Align the length to a multiple of len_align + if (len_align && + ((ntohl(entry->offset) + ntohl(entry->len)) % len_align)) { + size_t off = (ntohl(entry->offset) + ntohl(entry->len)) % len_align; + entry->len = htonl(ntohl(entry->len) + len_align - off); + } + // Process buffer AFTER entry. entry = cbfs_find_next_entry(image, entry); addr = cbfs_get_entry_addr(image, entry); @@ -738,7 +748,8 @@ static int cbfs_add_entry_at(struct cbfs_image *image, int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, uint32_t content_offset, - struct cbfs_file *header) + struct cbfs_file *header, + const size_t len_align) { assert(image); assert(buffer); @@ -812,7 +823,7 @@ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, addr, addr_next - addr, content_offset); if (cbfs_add_entry_at(image, entry, buffer->data, - content_offset, header) == 0) { + content_offset, header, len_align) == 0) { return 0; } break; diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 1f8b162d7c..1bb3c686e5 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -106,7 +106,8 @@ int cbfs_export_entry(struct cbfs_image *image, const char *entry_name, * Never pass this function a top-aligned address: convert it to an offset. * Returns 0 on success, otherwise non-zero. */ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, - uint32_t content_offset, struct cbfs_file *header); + uint32_t content_offset, struct cbfs_file *header, + const size_t len_align); /* Removes an entry from CBFS image. Returns 0 on success, otherwise non-zero. */ int cbfs_remove_entry(struct cbfs_image *image, const char *name); diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 54b5f6549c..65c5e08871 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -5,6 +5,8 @@ * written by Patrick Georgi * Copyright (C) 2012 Google, Inc. * Copyright (C) 2016 Siemens AG + * Copyright (C) 2019 9elements Agency GmbH + * Copyright (C) 2019 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -83,6 +85,7 @@ static struct param { bool autogen_attr; bool machine_parseable; bool unprocessed; + bool ibb; enum comp_algo compression; int precompression; enum vb2_hash_algorithm hash; @@ -249,7 +252,7 @@ static int cbfs_add_integer_component(const char *name, header = cbfs_create_file_header(CBFS_COMPONENT_RAW, buffer.size, name); - if (cbfs_add_entry(&image, &buffer, offset, header) != 0) { + if (cbfs_add_entry(&image, &buffer, offset, header, 0) != 0) { ERROR("Failed to add %llu into ROM image as '%s'.\n", (long long unsigned)u64val, name); goto done; @@ -364,7 +367,7 @@ static int cbfs_add_master_header(void) header = cbfs_create_file_header(CBFS_COMPONENT_CBFSHEADER, buffer_size(&buffer), name); - if (cbfs_add_entry(&image, &buffer, 0, header) != 0) { + if (cbfs_add_entry(&image, &buffer, 0, header, 0) != 0) { ERROR("Failed to add cbfs master header into ROM image.\n"); goto done; } @@ -448,6 +451,8 @@ static int cbfs_add_component(const char *filename, uint32_t headeroffset, convert_buffer_t convert) { + size_t len_align = 0; + if (!filename) { ERROR("You need to specify -f/--filename.\n"); return 1; @@ -539,6 +544,17 @@ static int cbfs_add_component(const char *filename, } } + if (param.ibb) { + /* Mark as Initial Boot Block */ + struct cbfs_file_attribute *attrs = cbfs_add_file_attr(header, + CBFS_FILE_ATTR_TAG_IBB, + sizeof(struct cbfs_file_attribute)); + if (attrs == NULL) + return -1; + /* For Intel TXT minimum align is 16 */ + len_align = 16; + } + if (param.padding) { const uint32_t hs = sizeof(struct cbfs_file_attribute); uint32_t size = MAX(hs, param.padding); @@ -554,7 +570,7 @@ static int cbfs_add_component(const char *filename, if (IS_TOP_ALIGNED_ADDRESS(offset)) offset = convert_to_from_top_aligned(param.image_region, -offset); - if (cbfs_add_entry(&image, &buffer, offset, header) != 0) { + if (cbfs_add_entry(&image, &buffer, offset, header, len_align) != 0) { ERROR("Failed to add '%s' into ROM image.\n", filename); free(header); buffer_delete(&buffer); @@ -1277,6 +1293,11 @@ static const struct command commands[] = { {"truncate", "r:h?", cbfs_truncate, true, true}, }; +enum { + /* begin after ASCII characters */ + LONGOPT_IBB = 256, +}; + static struct option long_options[] = { {"alignment", required_argument, 0, 'a' }, {"base-address", required_argument, 0, 'b' }, @@ -1315,6 +1336,7 @@ static struct option long_options[] = { {"gen-attribute", no_argument, 0, 'g' }, {"mach-parseable",no_argument, 0, 'k' }, {"unprocessed", no_argument, 0, 'U' }, + {"ibb", no_argument, 0, LONGOPT_IBB }, {NULL, 0, 0, 0 } }; @@ -1388,7 +1410,7 @@ static void usage(char *name) " add [-r image,regions] -f FILE -n NAME -t TYPE [-A hash] \\\n" " [-c compression] [-b base-address | -a alignment] \\\n" " [-p padding size] [-y|--xip if TYPE is FSP] \\\n" - " [-j topswap-size] (Intel CPUs only) " + " [-j topswap-size] (Intel CPUs only) [--ibb] " "Add a component\n" " " " -j valid size: 0x10000 0x20000 0x40000 0x80000 0x100000 \n" @@ -1398,7 +1420,7 @@ static void usage(char *name) "Add a payload to the ROM\n" " add-stage [-r image,regions] -f FILE -n NAME [-A hash] \\\n" " [-c compression] [-b base] [-S section-to-ignore] \\\n" - " [-a alignment] [-y|--xip] [-P page-size] " + " [-a alignment] [-y|--xip] [-P page-size] [--ibb] " "Add a stage to the ROM\n" " add-flat-binary [-r image,regions] -f FILE -n NAME \\\n" " [-A hash] -l load-address -e entry-point \\\n" @@ -1709,6 +1731,9 @@ int main(int argc, char **argv) case 'U': param.unprocessed = true; break; + case LONGOPT_IBB: + param.ibb = true; + break; case 'h': case '?': usage(argv[0]); diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh index 9d2ca84aa9..dc33fac8ce 100755 --- a/util/chromeos/crosfirmware.sh +++ b/util/chromeos/crosfirmware.sh @@ -76,7 +76,7 @@ extract_partition() SIZE=$(( $( echo $ROOTP | cut -f4 -d\ | tr -d "B" ) )) dd if=$FILE of=$ROOTFS bs=$_bs skip=$(( $START / $_bs )) \ - count=$(( $SIZE / $_bs )) > /dev/null 2>&1 + count=$(( $SIZE / $_bs )) > /dev/null } extract_shellball() diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 6c378ac7fd..b75b90a877 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -861,9 +861,9 @@ build_IASL() { test "$UNAME" = "Cygwin" && HOST="_CYGWIN" HOST="$HOST" CFLAGS="$CFLAGS" \ OPT_CFLAGS="-O -D_FORTIFY_SOURCE=2 -D COREBOOT_TOOLCHAIN_VERSION='\"coreboot toolchain v$CROSSGCC_VERSION $CROSSGCC_DATE\"' " \ - $MAKE CC="$(hostcc host)" iasl || touch "$RDIR/.failed" - rm -f "$DESTDIR$TARGETDIR/bin/iasl" || touch "$RDIR/.failed" - cp bin/iasl "$DESTDIR$TARGETDIR/bin" || touch "$RDIR/.failed" + $MAKE $JOBS CC="$(hostcc host)" iasl acpibin acpidump acpiexec acpihelp acpinames acpisrc acpixtract + rm -f "$DESTDIR$TARGETDIR/bin/{iasl,acpibin,acpidump,acpiexec,acpihelp,acpinames,acpisrc,acpixtract}" || touch "$RDIR/.failed" + cp bin/{iasl,acpibin,acpidump,acpiexec,acpihelp,acpinames,acpisrc,acpixtract} "$DESTDIR$TARGETDIR/bin" || touch "$RDIR/.failed" } build_LLVM() { diff --git a/util/crossgcc/patches/binutils-2.32_as-ipxe.patch b/util/crossgcc/patches/binutils-2.32_as-ipxe.patch new file mode 100644 index 0000000000..4d2c00a17f --- /dev/null +++ b/util/crossgcc/patches/binutils-2.32_as-ipxe.patch @@ -0,0 +1,36 @@ +From 6984bd861cc595e56d26ea033851d9174e855129 Mon Sep 17 00:00:00 2001 +From: Himanshu Sahdev aka CunningLearner +Date: Mon, 26 Aug 2019 16:57:13 +0530 +Subject: [PATCH] as: facilitate tests based on /dev/null + +Signed-off-by: Himanshu Sahdev + +--- + gas/as.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/gas/as.c b/gas/as.c +index 728811bc..78b4802c 100644 +--- a/gas/as.c ++++ b/gas/as.c +@@ -1203,7 +1203,7 @@ main (int argc, char ** argv) + { + char ** argv_orig = argv; + struct stat sob; +- ++ const char *dev_null_file="/dev/null"; + int macro_strip_at; + + start_time = get_run_time (); +@@ -1252,7 +1252,7 @@ main (int argc, char ** argv) + so that switches like --hash-size can be honored. */ + parse_args (&argc, &argv); + +- if (argc > 1 && stat (out_file_name, &sob) == 0) ++ if (argc > 1 && stat (out_file_name, &sob) == 0 && strcmp(out_file_name,dev_null_file)!=0) + { + int i; + +-- +2.17.1 + diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 0e83c760d8..a6d0ffa778 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -216,6 +216,7 @@ static int is_platform_ifd_2(void) PLATFORM_GLK, PLATFORM_CNL, PLATFORM_ICL, + PLATFORM_TGL, }; unsigned int i; @@ -921,6 +922,7 @@ static void set_chipdensity(const char *filename, char *image, int size, unsigned int density) { fcba_t *fcba = find_fcba(image, size); + uint8_t mask, chip2_offset; if (!fcba) exit(EXIT_FAILURE); @@ -937,12 +939,13 @@ static void set_chipdensity(const char *filename, char *image, int size, printf("error: Selected density not supported in IFD version 1.\n"); exit(EXIT_FAILURE); } + mask = 0x7; + chip2_offset = 3; break; case IFD_VERSION_2: - /* I do not have a version 2 IFD nor do i have the docs. */ - printf("error: Changing the chip density for IFD version 2 has not been" - " implemented yet.\n"); - exit(EXIT_FAILURE); + mask = 0xf; + chip2_offset = 4; + break; default: printf("error: Unknown IFD version\n"); exit(EXIT_FAILURE); @@ -952,13 +955,13 @@ static void set_chipdensity(const char *filename, char *image, int size, /* clear chip density for corresponding chip */ switch (selected_chip) { case 1: - fcba->flcomp &= ~(0x7); + fcba->flcomp &= ~mask; break; case 2: - fcba->flcomp &= ~(0x7 << 3); + fcba->flcomp &= ~(mask << chip2_offset); break; default: /*both chips*/ - fcba->flcomp &= ~(0x3F); + fcba->flcomp &= ~(mask | (mask << chip2_offset)); break; } @@ -966,7 +969,7 @@ static void set_chipdensity(const char *filename, char *image, int size, if (selected_chip == 1 || selected_chip == 0) fcba->flcomp |= (density); /* first chip */ if (selected_chip == 2 || selected_chip == 0) - fcba->flcomp |= (density << 3); /* second chip */ + fcba->flcomp |= (density << chip2_offset); /* second chip */ write_image(filename, image, size); } @@ -1024,6 +1027,7 @@ static void lock_descriptor(const char *filename, char *image, int size) case PLATFORM_CNL: case PLATFORM_ICL: case PLATFORM_SKLKBL: + case PLATFORM_TGL: /* CPU/BIOS can read descriptor and BIOS. */ fmba->flmstr1 |= (1 << REGION_DESC) << rd_shift; fmba->flmstr1 |= (1 << REGION_BIOS) << rd_shift; @@ -1403,30 +1407,30 @@ static void print_usage(const char *name) { printf("usage: %s [-vhdix?] \n", name); printf("\n" - " -d | --dump: dump intel firmware descriptor\n" - " -f | --layout dump regions into a flashrom layout file\n" - " -t | --validate Validate that the firmware descriptor layout matches the fmap layout\n" - " -x | --extract: extract intel fd modules\n" - " -i | --inject : inject file into region \n" - " -n | --newlayout update regions using a flashrom layout file\n" - " -s | --spifreq <17|20|30|33|48|50> set the SPI frequency\n" - " -D | --density <512|1|2|4|8|16> set chip density (512 in KByte, others in MByte)\n" - " -C | --chip <0|1|2> select spi chip on which to operate\n" - " can only be used once per run:\n" - " 0 - both chips (default), 1 - first chip, 2 - second chip\n" - " -e | --em100 set SPI frequency to 20MHz and disable\n" - " Dual Output Fast Read Support\n" - " -l | --lock Lock firmware descriptor and ME region\n" - " -u | --unlock Unlock firmware descriptor and ME region\n" - " -M | --altmedisable <0|1> Set the AltMeDisable (or HAP for skylake or newer platform)\n" - " bit to disable ME\n" - " -p | --platform Add platform-specific quirks\n" - " aplk - Apollo Lake\n" - " cnl - Cannon Lake\n" - " glk - Gemini Lake\n" - " sklkbl - Skylake/Kaby Lake\n" - " -v | --version: print the version\n" - " -h | --help: print this help\n\n" + " -d | --dump: dump intel firmware descriptor\n" + " -f | --layout dump regions into a flashrom layout file\n" + " -t | --validate Validate that the firmware descriptor layout matches the fmap layout\n" + " -x | --extract: extract intel fd modules\n" + " -i | --inject : inject file into region \n" + " -n | --newlayout update regions using a flashrom layout file\n" + " -s | --spifreq <17|20|30|33|48|50> set the SPI frequency\n" + " -D | --density <512|1|2|4|8|16|32|64> set chip density (512 in KByte, others in MByte)\n" + " -C | --chip <0|1|2> select spi chip on which to operate\n" + " can only be used once per run:\n" + " 0 - both chips (default), 1 - first chip, 2 - second chip\n" + " -e | --em100 set SPI frequency to 20MHz and disable\n" + " Dual Output Fast Read Support\n" + " -l | --lock Lock firmware descriptor and ME region\n" + " -u | --unlock Unlock firmware descriptor and ME region\n" + " -M | --altmedisable <0|1> Set the AltMeDisable (or HAP for skylake or newer platform)\n" + " bit to disable ME\n" + " -p | --platform Add platform-specific quirks\n" + " aplk - Apollo Lake\n" + " cnl - Cannon Lake\n" + " glk - Gemini Lake\n" + " sklkbl - Skylake/Kaby Lake\n" + " -v | --version: print the version\n" + " -h | --help: print this help\n\n" " is one of Descriptor, BIOS, ME, GbE, Platform\n" "\n"); } @@ -1635,6 +1639,8 @@ int main(int argc, char *argv[]) platform = PLATFORM_ICL; } else if (!strcmp(optarg, "sklkbl")) { platform = PLATFORM_SKLKBL; + } else if (!strcmp(optarg, "tgl")) { + platform = PLATFORM_TGL; } else { fprintf(stderr, "Unknown platform: %s\n", optarg); exit(EXIT_FAILURE); @@ -1659,7 +1665,7 @@ int main(int argc, char *argv[]) if ((mode_dump + mode_layout + mode_extract + mode_inject + mode_newlayout + (mode_spifreq | mode_em100 | mode_unlocked | - mode_locked) + mode_altmedisable + mode_layout) > 1) { + mode_locked) + mode_altmedisable + mode_validate) > 1) { fprintf(stderr, "You may not specify more than one mode.\n\n"); print_usage(argv[0]); exit(EXIT_FAILURE); diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 195a09cce4..2f5b3c3f2e 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -58,6 +58,7 @@ enum platform { PLATFORM_GLK, PLATFORM_ICL, PLATFORM_SKLKBL, + PLATFORM_TGL, }; #define LAYOUT_LINELEN 80 diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index d2c8ede2ca..e322e81028 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -160,6 +160,11 @@ static int get_number_of_cpus(void) return sysconf(_SC_NPROCESSORS_ONLN); } +static int get_number_of_cores(void) +{ + return sysconf(_SC_NPROCESSORS_CONF); +} + static int is_sgx_supported(int cpunum) { cpuid_result_t cpuid_regs; @@ -221,7 +226,7 @@ int print_sgx(void) int print_intel_core_msrs(void) { - unsigned int i, core, id; + unsigned int i, core, id, core_num = get_number_of_cores(); msr_t msr; #define IA32_PLATFORM_ID 0x0017 @@ -1539,7 +1544,7 @@ int print_intel_core_msrs(void) */ static const msr_entry_t model96ex_global_msrs[] = { - { 0x0000, "IA32_PLATFORM_ID"}, + { 0x0017, "IA32_PLATFORM_ID"}, { 0x0080, "MSR_TRACE_HUB_STH_ACPIBAR_BASE"}, { 0x00CE, "MSR_PLATFORM_INFO"}, { 0x0198, "IA32_PERF_STATUS"}, @@ -1634,7 +1639,6 @@ int print_intel_core_msrs(void) { 0x01F3, "IA32_SMRR_PHYSMASK"}, { 0x01F4, "MSR_PRMRR_PHYS_BASE"}, { 0x01F5, "MSR_PRMRR_PHYS_MASK"}, - { 0x01F4, "MSR_PRMRR_PHYS_BASE"}, { 0x01FB, "MSR_PRMRR_VALID_CONFIG"}, { 0x01FC, "MSR_POWER_CTL"}, { 0x0200, "IA32_MTRR_PHYSBASE0"}, @@ -1739,22 +1743,6 @@ int print_intel_core_msrs(void) { 0x0600, "IA32_DS_AREA" }, { 0x064E, "MSR_PPERF"}, { 0x0653, "MSR_CORE_HDC_RESIDENCY"}, - { 0x0680, "MSR_LASTBRANCH_0_FROM_IP" }, - { 0x0681, "MSR_LASTBRANCH_1_FROM_IP" }, - { 0x0682, "MSR_LASTBRANCH_2_FROM_IP" }, - { 0x0683, "MSR_LASTBRANCH_3_FROM_IP" }, - { 0x0684, "MSR_LASTBRANCH_4_FROM_IP" }, - { 0x0685, "MSR_LASTBRANCH_5_FROM_IP" }, - { 0x0686, "MSR_LASTBRANCH_6_FROM_IP" }, - { 0x0687, "MSR_LASTBRANCH_7_FROM_IP" }, - { 0x0688, "MSR_LASTBRANCH_8_FROM_IP" }, - { 0x0689, "MSR_LASTBRANCH_9_FROM_IP" }, - { 0x068a, "MSR_LASTBRANCH_10_FROM_IP" }, - { 0x068b, "MSR_LASTBRANCH_11_FROM_IP" }, - { 0x068c, "MSR_LASTBRANCH_12_FROM_IP" }, - { 0x068d, "MSR_LASTBRANCH_13_FROM_IP" }, - { 0x068e, "MSR_LASTBRANCH_14_FROM_IP" }, - { 0x068f, "MSR_LASTBRANCH_15_FROM_IP" }, { 0x0690, "MSR_LASTBRANCH_16_FROM_IP" }, { 0x0691, "MSR_LASTBRANCH_17_FROM_IP" }, { 0x0692, "MSR_LASTBRANCH_18_FROM_IP" }, @@ -1771,38 +1759,22 @@ int print_intel_core_msrs(void) { 0x069D, "MSR_LASTBRANCH_29_FROM_IP" }, { 0x069E, "MSR_LASTBRANCH_30_FROM_IP" }, { 0x069F, "MSR_LASTBRANCH_31_FROM_IP" }, - { 0x06c0, "MSR_LASTBRANCH_0_TO_IP" }, - { 0x06c1, "MSR_LASTBRANCH_1_TO_IP" }, - { 0x06c2, "MSR_LASTBRANCH_2_TO_IP" }, - { 0x06c3, "MSR_LASTBRANCH_3_TO_IP" }, - { 0x06c4, "MSR_LASTBRANCH_4_TO_IP" }, - { 0x06c5, "MSR_LASTBRANCH_5_TO_IP" }, - { 0x06c6, "MSR_LASTBRANCH_6_TO_IP" }, - { 0x06c7, "MSR_LASTBRANCH_7_TO_IP" }, - { 0x06c8, "MSR_LASTBRANCH_8_TO_IP" }, - { 0x06c9, "MSR_LASTBRANCH_9_TO_IP" }, - { 0x06ca, "MSR_LASTBRANCH_10_TO_IP" }, - { 0x06cb, "MSR_LASTBRANCH_11_TO_IP" }, - { 0x06cc, "MSR_LASTBRANCH_12_TO_IP" }, - { 0x06cd, "MSR_LASTBRANCH_13_TO_IP" }, - { 0x06ce, "MSR_LASTBRANCH_14_TO_IP" }, - { 0x06cf, "MSR_LASTBRANCH_15_TO_IP" }, - { 0x06d0, "MSR_LASTBRANCH_16_FROM_IP" }, - { 0x06d1, "MSR_LASTBRANCH_17_FROM_IP" }, - { 0x06d2, "MSR_LASTBRANCH_18_FROM_IP" }, - { 0x06d3, "MSR_LASTBRANCH_19_FROM_IP" }, - { 0x06d4, "MSR_LASTBRANCH_20_FROM_IP" }, - { 0x06d5, "MSR_LASTBRANCH_21_FROM_IP" }, - { 0x06d6, "MSR_LASTBRANCH_22_FROM_IP" }, - { 0x06d7, "MSR_LASTBRANCH_23_FROM_IP" }, - { 0x06d8, "MSR_LASTBRANCH_24_FROM_IP" }, - { 0x06d9, "MSR_LASTBRANCH_25_FROM_IP" }, - { 0x06da, "MSR_LASTBRANCH_26_FROM_IP" }, - { 0x06db, "MSR_LASTBRANCH_27_FROM_IP" }, - { 0x06dc, "MSR_LASTBRANCH_28_FROM_IP" }, - { 0x06dd, "MSR_LASTBRANCH_29_FROM_IP" }, - { 0x06de, "MSR_LASTBRANCH_30_FROM_IP" }, - { 0x06df, "MSR_LASTBRANCH_31_FROM_IP" }, + { 0x06d0, "MSR_LASTBRANCH_16_TO_IP" }, + { 0x06d1, "MSR_LASTBRANCH_17_TO_IP" }, + { 0x06d2, "MSR_LASTBRANCH_18_TO_IP" }, + { 0x06d3, "MSR_LASTBRANCH_19_TO_IP" }, + { 0x06d4, "MSR_LASTBRANCH_20_TO_IP" }, + { 0x06d5, "MSR_LASTBRANCH_21_TO_IP" }, + { 0x06d6, "MSR_LASTBRANCH_22_TO_IP" }, + { 0x06d7, "MSR_LASTBRANCH_23_TO_IP" }, + { 0x06d8, "MSR_LASTBRANCH_24_TO_IP" }, + { 0x06d9, "MSR_LASTBRANCH_25_TO_IP" }, + { 0x06da, "MSR_LASTBRANCH_26_TO_IP" }, + { 0x06db, "MSR_LASTBRANCH_27_TO_IP" }, + { 0x06dc, "MSR_LASTBRANCH_28_TO_IP" }, + { 0x06dd, "MSR_LASTBRANCH_29_TO_IP" }, + { 0x06de, "MSR_LASTBRANCH_30_TO_IP" }, + { 0x06df, "MSR_LASTBRANCH_31_TO_IP" }, { 0x06E0, "IA32_TSC_DEADLINE"}, { 0x0771, "IA32_HWP_CAPABILITIES"}, { 0x0773, "IA32_HWP_INTERRUPT"}, @@ -1846,6 +1818,379 @@ int print_intel_core_msrs(void) { 0x0DDF, "IA32_LBR_INFO_31"}, }; +/* + * Intel® 64 and IA-32 Architecture Software Developer’s Manual + * Volume 4: Model-Specific Registers + * Order Number: 335592-070US + * page 2-265 ... 2-286 + * page 2-297 ... 2-308 + * + * The following two tables are for the Intel(R) Xeon(R) Processor Scalable + * Family based on Skylake microarchitecture, 2nd generation Intel(R) Xeon(R) + * Processor Scalable Family based on Cascade Lake product, and future Cooper + * Lake product + * family 6 model 85 (06_55h) + */ + static const msr_entry_t model565x_global_msrs[] = { + { 0x004e, "MSR_PPIN_CTL" }, + { 0x004f, "MSR_PPIN" }, + { 0x00ce, "MSR_PLATFORM_INFO" }, + { 0x0198, "IA32_PERF_STATUS" }, + { 0x019c, "IA32_THERM_STATUS" }, + { 0x01a2, "MSR_TEMPERATURE_TARGET" }, + { 0x01ad, "MSR_TURBO_RATIO_LIMIT" }, + { 0x01ae, "MSR_TURBO_RATIO_LIMIT_CORES" }, + { 0x0284, "IA32_MC4_CTL2" }, + { 0x0285, "IA32_MC5_CTL2" }, + { 0x0286, "IA32_MC6_CTL2" }, + { 0x0287, "IA32_MC7_CTL2" }, + { 0x0288, "IA32_MC8_CTL2" }, + { 0x0289, "IA32_MC9_CTL2" }, + { 0x028a, "IA32_MC10_CTL2" }, + { 0x028b, "IA32_MC11_CTL2" }, + { 0x028c, "IA32_MC12_CTL2" }, + { 0x028d, "IA32_MC13_CTL2" }, + { 0x028e, "IA32_MC14_CTL2" }, + { 0x028f, "IA32_MC15_CTL2" }, + { 0x0290, "IA32_MC16_CTL2" }, + { 0x0291, "IA32_MC17_CTL2" }, + { 0x0292, "IA32_MC18_CTL2" }, + { 0x0293, "IA32_MC19_CTL2" }, + { 0x0300, "MSR_SGXOWNEREPOCH0" }, + { 0x0301, "MSR_SGXOWNEREPOCH1" }, + { 0x0410, "IA32_MC4_CTL" }, + { 0x0411, "IA32_MC4_STATUS" }, + { 0x0412, "IA32_MC4_ADDR" }, + { 0x0413, "IA32_MC4_MISC" }, + { 0x0414, "IA32_MC5_CTL" }, + { 0x0415, "IA32_MC5_STATUS" }, + { 0x0416, "IA32_MC5_ADDR" }, + { 0x0417, "IA32_MC5_MISC" }, + { 0x0418, "IA32_MC6_CTL" }, + { 0x0419, "IA32_MC6_STATUS" }, + { 0x041a, "IA32_MC6_ADDR" }, + { 0x041b, "IA32_MC6_MISC" }, + { 0x041c, "IA32_MC7_CTL" }, + { 0x041d, "IA32_MC7_STATUS" }, + { 0x041e, "IA32_MC7_ADDR" }, + { 0x041f, "IA32_MC7_MISC" }, + { 0x0420, "IA32_MC8_CTL" }, + { 0x0421, "IA32_MC8_STATUS" }, + { 0x0422, "IA32_MC8_ADDR" }, + { 0x0423, "IA32_MC8_MISC" }, + { 0x0424, "IA32_MC9_CTL" }, + { 0x0425, "IA32_MC9_STATUS" }, + { 0x0426, "IA32_MC9_ADDR" }, + { 0x0427, "IA32_MC9_MISC" }, + { 0x0428, "IA32_MC10_CTL" }, + { 0x0429, "IA32_MC10_STATUS" }, + { 0x042a, "IA32_MC10_ADDR" }, + { 0x042b, "IA32_MC10_MISC" }, + { 0x042c, "IA32_MC11_CTL" }, + { 0x042d, "IA32_MC11_STATUS" }, + { 0x042e, "IA32_MC11_ADDR" }, + { 0x042f, "IA32_MC11_MISC" }, + { 0x0430, "IA32_MC12_CTL" }, + { 0x0431, "IA32_MC12_STATUS" }, + { 0x0432, "IA32_MC12_ADDR" }, + { 0x0433, "IA32_MC12_MISC" }, + { 0x0434, "IA32_MC13_CTL" }, + { 0x0435, "IA32_MC13_STATUS" }, + { 0x0436, "IA32_MC13_ADDR" }, + { 0x0437, "IA32_MC13_MISC" }, + { 0x0438, "IA32_MC14_CTL" }, + { 0x0439, "IA32_MC14_STATUS" }, + { 0x043a, "IA32_MC14_ADDR" }, + { 0x043b, "IA32_MC14_MISC" }, + { 0x043c, "IA32_MC15_CTL" }, + { 0x043d, "IA32_MC15_STATUS" }, + { 0x043e, "IA32_MC15_ADDR" }, + { 0x043f, "IA32_MC15_MISC" }, + { 0x0440, "IA32_MC16_CTL" }, + { 0x0441, "IA32_MC16_STATUS" }, + { 0x0442, "IA32_MC16_ADDR" }, + { 0x0443, "IA32_MC16_MISC" }, + { 0x0444, "IA32_MC17_CTL" }, + { 0x0445, "IA32_MC17_STATUS" }, + { 0x0446, "IA32_MC17_ADDR" }, + { 0x0447, "IA32_MC17_MISC" }, + { 0x0448, "IA32_MC18_CTL" }, + { 0x0449, "IA32_MC18_STATUS" }, + { 0x044a, "IA32_MC18_ADDR" }, + { 0x044b, "IA32_MC18_MISC" }, + { 0x044c, "IA32_MC19_CTL" }, + { 0x044b, "IA32_MC19_STATUS" }, + { 0x044e, "IA32_MC19_ADDR" }, + { 0x044f, "IA32_MC19_MISC" }, + { 0x0606, "MSR_RAPL_POWER_UNIT" }, + { 0x0618, "MSR_DRAM_POWER_LIMIT" }, + { 0x0619, "MSR_DRAM_ENERGY_STATUS" }, + { 0x061b, "MSR_DRAM_PERF_STATUS" }, + { 0x061c, "MSR_DRAM_POWER_INFO" }, + { 0x0620, "MSR_UNCORE_RATIO_LIMIT" }, + { 0x0639, "MSR_PP0_ENERGY_STATUS" }, + { 0x0638, "MSR_PP0_POWER_LIMIT" }, + { 0x064d, "MSR_PLATFORM_ENERGY_COUNTER" }, + { 0x064f, "MSR_CORE_PERF_LIMIT_REASONS" }, + { 0x0652, "MSR_PKG_HDC_CONFIG" }, + { 0x0655, "MSR_PKG_HDC_SHALLOW_RESIDENCY" }, + { 0x0656, "MSR_PKG_HDC_DEEP_RESIDENCY" }, + { 0x0658, "MSR_WEIGHTED_CORE_C0" }, + { 0x0659, "MSR_ANY_CORE_C0" }, + { 0x065a, "MSR_ANY_GFXE_C0" }, + { 0x065b, "MSR_CORE_GFXE_OVERLAP_C0" }, + { 0x065c, "MSR_PLATFORM_POWER_LIMIT" }, + { 0x06b0, "MSR_GRAPHICS_PERF_LIMIT_REASONS" }, + { 0x06b1, "MSR_RING_PERF_LIMIT_REASONS" }, + { 0x0770, "IA32_PM_ENABLE" }, + { 0x0db0, "IA32_PKG_HDC_CTL" }, + { 0x0c90, "IA32_L3_QOS_MASK_0" }, + { 0x0c91, "IA32_L3_QOS_MASK_1" }, + { 0x0c92, "IA32_L3_QOS_MASK_2" }, + { 0x0c93, "IA32_L3_QOS_MASK_3" }, + { 0x0c94, "IA32_L3_QOS_MASK_4" }, + { 0x0c95, "IA32_L3_QOS_MASK_5" }, + { 0x0c96, "IA32_L3_QOS_MASK_6" }, + { 0x0c97, "IA32_L3_QOS_MASK_7" }, + { 0x0c98, "IA32_L3_QOS_MASK_8" }, + { 0x0c99, "IA32_L3_QOS_MASK_9" }, + { 0x0c9a, "IA32_L3_QOS_MASK_10" }, + { 0x0c9b, "IA32_L3_QOS_MASK_11" }, + { 0x0c9c, "IA32_L3_QOS_MASK_12" }, + { 0x0c9d, "IA32_L3_QOS_MASK_13" }, + { 0x0c9e, "IA32_L3_QOS_MASK_14" }, + { 0x0c9f, "IA32_L3_QOS_MASK_15" }, + }; + + static const msr_entry_t model565x_per_core_msrs[] = { + { 0x0000, "IA32_P5_MC_ADDR" }, + { 0x0001, "IA32_P5_MC_TYPE" }, + { 0x0006, "IA32_MONITOR_FILTER_SIZE" }, + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x0017, "IA32_PLATFORM_ID" }, + { 0x001b, "IA32_APIC_BASE" }, + { 0x0034, "MSR_SMI_COUNT" }, + { 0x003a, "IA32_FEATURE_CONTROL" }, + { 0x008b, "IA32_BIOS_SIGN_ID" }, + { 0x00c1, "IA32_PMC0" }, + { 0x00c2, "IA32_PMC1" }, + { 0x00c3, "IA32_PMC2" }, + { 0x00c4, "IA32_PMC3" }, + { 0x00e2, "MSR_PKG_CST_CONFIG_CONTROL" }, + { 0x00e4, "MSR_PMG_IO_CAPTURE_BASE" }, + { 0x00e7, "IA32_MPERF" }, + { 0x00e8, "IA32_APERF" }, + { 0x00fe, "IA32_MTRRCAP" }, + { 0x013c, "MSR_FEATURE_CONFIG" }, + { 0x0174, "IA32_SYSENTER_CS" }, + { 0x0175, "IA32_SYSENTER_ESP" }, + { 0x0176, "IA32_SYSENTER_EIP" }, + { 0x0179, "IA32_MCG_CAP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x017d, "MSR_SMM_MCA_CAP" }, + { 0x0186, "IA32_PERFEVTSEL0" }, + { 0x0187, "IA32_PERFEVTSEL1" }, + { 0x0188, "IA32_PERFEVTSEL2" }, + { 0x0189, "IA32_PERFEVTSEL3" }, + { 0x019b, "IA32_THERM_INTERRUPT" }, + { 0x0199, "IA32_PERF_CTL" }, + { 0x019a, "IA32_CLOCK_MODULATION" }, + { 0x01a0, "IA32_MISC_ENABLE" }, + { 0x01a4, "IA32_MISC_FEATURE_CONTROL" }, + { 0x01a6, "MSR_OFFCORE_RSP_0" }, + { 0x01a7, "MSR_OFFCORE_RSP_1" }, + { 0x01c8, "MSR_LBR_SELECT" }, + { 0x01c9, "MSR_LASTBRANCH_TOS" }, + { 0x01d9, "IA32_DEBUGCTL" }, + { 0x01dd, "MSR_LER_FROM_LIP" }, + { 0x01de, "MSR_LER_TO_LIP" }, + { 0x01f2, "IA32_SMRR_PHYSBASE" }, + { 0x01f3, "IA32_SMRR_PHYSMASK" }, + { 0x01fc, "MSR_POWER_CTL" }, + { 0x0200, "IA32_MTRR_PHYSBASE0" }, + { 0x0201, "IA32_MTRR_PHYSBASE0" }, + { 0x0202, "IA32_MTRR_PHYSBASE1" }, + { 0x0203, "IA32_MTRR_PHYSBASE1" }, + { 0x0204, "IA32_MTRR_PHYSBASE2" }, + { 0x0205, "IA32_MTRR_PHYSBASE2" }, + { 0x0206, "IA32_MTRR_PHYSBASE3" }, + { 0x0207, "IA32_MTRR_PHYSBASE3" }, + { 0x0208, "IA32_MTRR_PHYSBASE4" }, + { 0x0209, "IA32_MTRR_PHYSBASE4" }, + { 0x020a, "IA32_MTRR_PHYSBASE5" }, + { 0x020b, "IA32_MTRR_PHYSBASE5" }, + { 0x020c, "IA32_MTRR_PHYSBASE6" }, + { 0x020d, "IA32_MTRR_PHYSBASE6" }, + { 0x020e, "IA32_MTRR_PHYSBASE7" }, + { 0x020f, "IA32_MTRR_PHYSBASE7" }, + { 0x0210, "IA32_MTRR_PHYSBASE8" }, + { 0x0211, "IA32_MTRR_PHYSBASE8" }, + { 0x0212, "IA32_MTRR_PHYSBASE9" }, + { 0x0213, "IA32_MTRR_PHYSBASE9" }, + { 0x0250, "IA32_MTRR_FIX64K_00000" }, + { 0x0258, "IA32_MTRR_FIX16K_80000" }, + { 0x0259, "IA32_MTRR_FIX16K_A0000" }, + { 0x0268, "IA32_MTRR_FIX4K_C0000" }, + { 0x0269, "IA32_MTRR_FIX4K_C8000" }, + { 0x026a, "IA32_MTRR_FIX4K_D0000" }, + { 0x026b, "IA32_MTRR_FIX4K_D8000" }, + { 0x026c, "IA32_MTRR_FIX4K_E0000" }, + { 0x026d, "IA32_MTRR_FIX4K_E8000" }, + { 0x026e, "IA32_MTRR_FIX4K_F0000" }, + { 0x026f, "IA32_MTRR_FIX4K_F8000" }, + { 0x0277, "IA32_PAT" }, + { 0x0280, "IA32_MC0_CTL2" }, + { 0x0281, "IA32_MC1_CTL2" }, + { 0x0282, "IA32_MC2_CTL2" }, + { 0x0283, "IA32_MC3_CTL2" }, + { 0x02ff, "IA32_MTRR_DEF_TYPE" }, + { 0x0309, "IA32_FIXED_CTR0" }, + { 0x030a, "IA32_FIXED_CTR1" }, + { 0x030b, "IA32_FIXED_CTR2" }, + { 0x0345, "IA32_PERF_CAPABILITIES" }, + { 0x038d, "IA32_FIXED_CTR_CTRL" }, + { 0x038e, "IA32_PERF_GLOBAL_STATUS" }, + { 0x038f, "IA32_PERF_GLOBAL_CTRL" }, + { 0x0390, "IA32_PERF_GLOBAL_STATUS_RESET" }, + { 0x0391, "IA32_PERF_GLOBAL_STATUS_SET" }, + { 0x0392, "IA32_PERF_GLOBAL_INUSE" }, + { 0x03f1, "MSR_PEBS_ENABLE" }, + { 0x03f6, "MSR_PEBS_LD_LAT" }, + { 0x03f7, "MSR_PEBS_FRONTEND" }, + { 0x03fc, "MSR_CORE_C3_RESIDENCY" }, + { 0x03fd, "MSR_CORE_C6_RESIDENCY" }, + { 0x03fe, "MSR_CORE_C7_RESIDENCY" }, + { 0x0400, "IA32_MC0_CTL" }, + { 0x0401, "IA32_MC0_STATUS" }, + { 0x0402, "IA32_MC0_ADDR" }, + { 0x0403, "IA32_MC0_MISC" }, + { 0x0404, "IA32_MC1_CTL" }, + { 0x0405, "IA32_MC1_STATUS" }, + { 0x0406, "IA32_MC1_ADDR" }, + { 0x0407, "IA32_MC1_MISC" }, + { 0x0408, "IA32_MC2_CTL" }, + { 0x0409, "IA32_MC2_STATUS" }, + { 0x040a, "IA32_MC2_ADDR" }, + { 0x040b, "IA32_MC2_MISC" }, + { 0x040c, "IA32_MC3_CTL" }, + { 0x040d, "IA32_MC3_STATUS" }, + { 0x040e, "IA32_MC3_ADDR" }, + { 0x040f, "IA32_MC3_MISC" }, + { 0x0480, "IA32_VMX_BASIC" }, + { 0x0481, "IA32_VMX_PINBASED_CTLS" }, + { 0x0482, "IA32_VMX_PROCBASED_CTLS" }, + { 0x0483, "IA32_VMX_EXIT_CTLS" }, + { 0x0484, "IA32_VMX_ENTRY_CTLS" }, + { 0x0485, "IA32_VMX_MISC" }, + { 0x0486, "IA32_VMX_CR0_FIXED0" }, + { 0x0487, "IA32_VMX_CR0_FIXED1" }, + { 0x0488, "IA32_VMX_CR4_FIXED0" }, + { 0x0489, "IA32_VMX_CR4_FIXED1" }, + { 0x048a, "IA32_VMX_VMCS_ENUM" }, + { 0x048b, "IA32_VMX_PROCBASED_CTLS2" }, + { 0x048c, "IA32_VMX_EPT_VPID_ENUM" }, + { 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" }, + { 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" }, + { 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" }, + { 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" }, + { 0x04c1, "IA32_A_PMC0" }, + { 0x04c2, "IA32_A_PMC1" }, + { 0x04c3, "IA32_A_PMC2" }, + { 0x04c4, "IA32_A_PMC3" }, + { 0x04c5, "IA32_A_PMC4" }, + { 0x04c6, "IA32_A_PMC5" }, + { 0x04c7, "IA32_A_PMC6" }, + { 0x04c8, "IA32_A_PMC7" }, + { 0x0500, "IA32_SGX_SVN_STATUS" }, + { 0x0560, "IA32_RTIT_OUTPUT_BASE" }, + { 0x0561, "IA32_RTIT_OUTPUT_MASK_PTRS" }, + { 0x0570, "IA32_RTIT_CTL" }, + { 0x0571, "IA32_RTIT_STATUS" }, + { 0x0572, "IA32_RTIT_CR3_MATCH" }, + { 0x0580, "IA32_RTIT_ADDR0_A" }, + { 0x0581, "IA32_RTIT_ADDR0_B" }, + { 0x0582, "IA32_RTIT_ADDR1_A" }, + { 0x0583, "IA32_RTIT_ADDR1_B" }, + { 0x0600, "IA32_DS_AREA" }, + { 0x064e, "MSR_PPERF" }, + { 0x0653, "MSR_CORE_HDC_RESIDENCY" }, + { 0x0690, "MSR_LASTBRANCH_16_FROM_IP" }, + { 0x0691, "MSR_LASTBRANCH_17_FROM_IP" }, + { 0x0692, "MSR_LASTBRANCH_18_FROM_IP" }, + { 0x0693, "MSR_LASTBRANCH_19_FROM_IP" }, + { 0x0694, "MSR_LASTBRANCH_20_FROM_IP" }, + { 0x0695, "MSR_LASTBRANCH_21_FROM_IP" }, + { 0x0696, "MSR_LASTBRANCH_22_FROM_IP" }, + { 0x0697, "MSR_LASTBRANCH_23_FROM_IP" }, + { 0x0698, "MSR_LASTBRANCH_24_FROM_IP" }, + { 0x0699, "MSR_LASTBRANCH_25_FROM_IP" }, + { 0x069a, "MSR_LASTBRANCH_26_FROM_IP" }, + { 0x069b, "MSR_LASTBRANCH_27_FROM_IP" }, + { 0x069c, "MSR_LASTBRANCH_28_FROM_IP" }, + { 0x069d, "MSR_LASTBRANCH_29_FROM_IP" }, + { 0x069e, "MSR_LASTBRANCH_30_FROM_IP" }, + { 0x069f, "MSR_LASTBRANCH_31_FROM_IP" }, + { 0x06d0, "MSR_LASTBRANCH_16_TO_IP" }, + { 0x06d1, "MSR_LASTBRANCH_17_TO_IP" }, + { 0x06d2, "MSR_LASTBRANCH_18_TO_IP" }, + { 0x06d3, "MSR_LASTBRANCH_19_TO_IP" }, + { 0x06d4, "MSR_LASTBRANCH_20_TO_IP" }, + { 0x06d5, "MSR_LASTBRANCH_21_TO_IP" }, + { 0x06d6, "MSR_LASTBRANCH_22_TO_IP" }, + { 0x06d7, "MSR_LASTBRANCH_23_TO_IP" }, + { 0x06d8, "MSR_LASTBRANCH_24_TO_IP" }, + { 0x06d9, "MSR_LASTBRANCH_25_TO_IP" }, + { 0x06da, "MSR_LASTBRANCH_26_TO_IP" }, + { 0x06db, "MSR_LASTBRANCH_27_TO_IP" }, + { 0x06dc, "MSR_LASTBRANCH_28_TO_IP" }, + { 0x06dd, "MSR_LASTBRANCH_29_TO_IP" }, + { 0x06de, "MSR_LASTBRANCH_30_TO_IP" }, + { 0x06df, "MSR_LASTBRANCH_31_TO_IP" }, + { 0x06e0, "IA32_TSC_DEADLINE" }, + { 0x0771, "IA32_HWP_CAPABILITIES" }, + { 0x0773, "IA32_HWP_INTERRUPT" }, + { 0x0774, "IA32_HWP_REQUEST" }, + { 0x0777, "IA32_HWP_STATUS" }, + { 0x0c8d, "IA32_QM_EVTSEL" }, + { 0x0c8f, "IA32_PQR_ASSOC" }, + { 0x0d90, "IA32_BNDCFGS" }, + { 0x0da0, "IA32_XSS" }, + { 0x0db1, "IA32_PM_CTL1" }, + { 0x0db2, "IA32_THREAD_STALL" }, + { 0x0dc0, "MSR_LBR_INFO_0" }, + { 0x0dc1, "MSR_LBR_INFO_1" }, + { 0x0dc2, "MSR_LBR_INFO_2" }, + { 0x0dc3, "MSR_LBR_INFO_3" }, + { 0x0dc4, "MSR_LBR_INFO_4" }, + { 0x0dc5, "MSR_LBR_INFO_5" }, + { 0x0dc6, "MSR_LBR_INFO_6" }, + { 0x0dc7, "MSR_LBR_INFO_7" }, + { 0x0dc8, "MSR_LBR_INFO_8" }, + { 0x0dc9, "MSR_LBR_INFO_9" }, + { 0x0dca, "MSR_LBR_INFO_10" }, + { 0x0dcb, "MSR_LBR_INFO_11" }, + { 0x0dcc, "MSR_LBR_INFO_12" }, + { 0x0dcd, "MSR_LBR_INFO_13" }, + { 0x0dce, "MSR_LBR_INFO_14" }, + { 0x0dcf, "MSR_LBR_INFO_15" }, + { 0x0dd0, "MSR_LBR_INFO_16" }, + { 0x0dd1, "MSR_LBR_INFO_17" }, + { 0x0dd2, "MSR_LBR_INFO_18" }, + { 0x0dd3, "MSR_LBR_INFO_19" }, + { 0x0dd4, "MSR_LBR_INFO_20" }, + { 0x0dd5, "MSR_LBR_INFO_21" }, + { 0x0dd6, "MSR_LBR_INFO_22" }, + { 0x0dd7, "MSR_LBR_INFO_23" }, + { 0x0dd8, "MSR_LBR_INFO_24" }, + { 0x0dd9, "MSR_LBR_INFO_25" }, + { 0x0ddA, "MSR_LBR_INFO_26" }, + { 0x0ddB, "MSR_LBR_INFO_27" }, + { 0x0ddc, "MSR_LBR_INFO_28" }, + { 0x0ddd, "MSR_LBR_INFO_29" }, + { 0x0dde, "MSR_LBR_INFO_30" }, + { 0x0ddf, "MSR_LBR_INFO_31" }, + }; + typedef struct { unsigned int model; const msr_entry_t *global_msrs; @@ -1865,6 +2210,7 @@ int print_intel_core_msrs(void) { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) }, { 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) }, { 0x906e0, model96ex_global_msrs, ARRAY_SIZE(model96ex_global_msrs), model96ex_per_core_msrs, ARRAY_SIZE(model96ex_per_core_msrs) }, + { 0x50650, model565x_global_msrs, ARRAY_SIZE(model565x_global_msrs), model565x_per_core_msrs, ARRAY_SIZE(model565x_per_core_msrs) }, { CPUID_BAYTRAIL, silvermont_global_msrs, ARRAY_SIZE(silvermont_global_msrs), silvermont_per_core_msrs, ARRAY_SIZE(silvermont_per_core_msrs) }, /* Baytrail */ @@ -1908,7 +2254,7 @@ int print_intel_core_msrs(void) close(fd_msr); - for (core = 0; core < 8; core++) { + for (core = 0; core < core_num; core++) { #ifndef __DARWIN__ char msrfilename[64]; memset(msrfilename, 0, 64); diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index db80bd26b1..830cdcdeaf 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -502,15 +502,55 @@ static void print_usage(const char *name) exit(1); } +static void print_system_info(struct pci_dev *nb, struct pci_dev *sb, struct pci_dev *gfx) +{ + unsigned int id, i; + char *sbname = "unknown", *nbname = "unknown", *gfxname = "unknown"; + + id = cpuid(1); + + /* Determine names */ + for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) { + if (nb->device_id == supported_chips_list[i].device_id) + nbname = supported_chips_list[i].name; + } + for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) { + if (sb->device_id == supported_chips_list[i].device_id) + sbname = supported_chips_list[i].name; + } + if (gfx) { + for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) + if (gfx->device_id == supported_chips_list[i].device_id) + gfxname = supported_chips_list[i].name; + } + + /* Intel has suggested applications to display the family of a CPU as + * the sum of the "Family" and the "Extended Family" fields shown + * above, and the model as the sum of the "Model" and the 4-bit + * left-shifted "Extended Model" fields. + * http://download.intel.com/design/processor/applnots/24161832.pdf + */ + printf("CPU: ID 0x%x, Processor Type 0x%x, Family 0x%x, Model 0x%x, Stepping 0x%x\n", + id, (id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff), + ((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf)); + + printf("Northbridge: %04x:%04x (%s)\n", + nb->vendor_id, nb->device_id, nbname); + + printf("Southbridge: %04x:%04x (%s)\n", + sb->vendor_id, sb->device_id, sbname); + + if (gfx) + printf("IGD: %04x:%04x (%s)\n", + gfx->vendor_id, gfx->device_id, gfxname); +} + int main(int argc, char *argv[]) { struct pci_access *pacc; struct pci_dev *sb = NULL, *nb, *gfx = NULL, *ahci = NULL, *dev; const char *dump_spd_file = NULL; int opt, option_index = 0; - unsigned int id, i; - - char *sbname = "unknown", *nbname = "unknown", *gfxname = "unknown"; int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0; int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0; @@ -737,43 +777,9 @@ int main(int argc, char *argv[]) ahci = NULL; } - id = cpuid(1); - - /* Intel has suggested applications to display the family of a CPU as - * the sum of the "Family" and the "Extended Family" fields shown - * above, and the model as the sum of the "Model" and the 4-bit - * left-shifted "Extended Model" fields. - * http://download.intel.com/design/processor/applnots/24161832.pdf - */ - printf("CPU: ID 0x%x, Processor Type 0x%x, Family 0x%x, Model 0x%x, Stepping 0x%x\n", - id, (id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff), - ((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf)); - - /* Determine names */ - for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) - if (nb->device_id == supported_chips_list[i].device_id) - nbname = supported_chips_list[i].name; - for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) - if (sb->device_id == supported_chips_list[i].device_id) - sbname = supported_chips_list[i].name; - if (gfx) { - for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) - if (gfx->device_id == supported_chips_list[i].device_id) - gfxname = supported_chips_list[i].name; - } - - printf("Northbridge: %04x:%04x (%s)\n", - nb->vendor_id, nb->device_id, nbname); - - printf("Southbridge: %04x:%04x (%s)\n", - sb->vendor_id, sb->device_id, sbname); - - if (gfx) - printf("IGD: %04x:%04x (%s)\n", - gfx->vendor_id, gfx->device_id, gfxname); + print_system_info(nb, sb, gfx); /* Now do the deed */ - if (dump_gpios) { print_gpios(sb, 1, show_gpio_diffs); printf("\n\n"); diff --git a/util/mainboard/google/hatch/create_coreboot_variant.sh b/util/mainboard/google/hatch/create_coreboot_variant.sh index 569143f795..184e54c810 100755 --- a/util/mainboard/google/hatch/create_coreboot_variant.sh +++ b/util/mainboard/google/hatch/create_coreboot_variant.sh @@ -13,11 +13,14 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. +VERSION="1.0.0" +SCRIPT=$(basename -- "${0}") + export LC_ALL=C if [[ "$#" -lt 1 ]]; then - echo "Usage: $0 variant_name [b:bug_number]" - echo "e.g. $0 kohaku b:140261109" + echo "Usage: ${SCRIPT} variant_name [b:bug_number]" + echo "e.g. ${SCRIPT} kohaku b:140261109" echo "Adds a new variant of Hatch to Kconfig and Kconfig.name, creates the" echo "skeleton files for acpi, ec, and gpio, copies the makefile for" echo "SPD sources, and sets up a basic overridetree" @@ -56,7 +59,7 @@ fi # Start a branch. Use YMD timestamp to avoid collisions. DATE=$(date +%Y%m%d) -git checkout -b "create_${VARIANT}_${DATE}" || exit 1 +git checkout -b "coreboot_${VARIANT}_${DATE}" || exit 1 # Copy the template tree to the target. mkdir -p "variants/${VARIANT}/" @@ -75,6 +78,8 @@ git add Kconfig Kconfig.name # Now commit the files. git commit -sm "${BASE}: Create ${VARIANT} variant +(Auto-Generated by ${SCRIPT} version ${VERSION}). + BUG=${BUG} TEST=util/abuild/abuild -p none -t google/${BASE} -x -a make sure the build includes GOOGLE_${VARIANT_UPPER}" diff --git a/util/mainboard/google/hatch/template/include/variant/gpio.h b/util/mainboard/google/hatch/template/include/variant/gpio.h index 1322233ad0..3b07c1ba20 100644 --- a/util/mainboard/google/hatch/template/include/variant/gpio.h +++ b/util/mainboard/google/hatch/template/include/variant/gpio.h @@ -16,4 +16,11 @@ #include +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_F20 +#define GPIO_MEM_CONFIG_1 GPP_F21 +#define GPIO_MEM_CONFIG_2 GPP_F11 +#define GPIO_MEM_CONFIG_3 GPP_F22 + #endif diff --git a/util/pgtblgen/Makefile.inc b/util/pgtblgen/Makefile.inc new file mode 100644 index 0000000000..c4f3ef37b6 --- /dev/null +++ b/util/pgtblgen/Makefile.inc @@ -0,0 +1,19 @@ +ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_64),y) + +PGTBLGEN:= $(obj)/pgtblgen + +cbfs-files-y += pagetables +pagetables-file := $(obj)/mainboard/$(MAINBOARDDIR)/pagetables +pagetables-type := raw +pagetables-compression := none +pagetables-COREBOOT-position := $(CONFIG_ARCH_X86_64_PGTBL_LOC) + +$(obj)/mainboard/$(MAINBOARDDIR)/pagetables: $(PGTBLGEN) $(obj)/config.h + printf " TOOL Creating page tables\n" + $(PGTBLGEN) -b $(CONFIG_ARCH_X86_64_PGTBL_LOC) -a x86_64 -o $@ + +$(PGTBLGEN): util/pgtblgen/pgtblgen.c + printf " MAKE Creating PGTBLGEN tool\n" + $(HOSTCC) $< -I$(obj) -o $@ + +endif diff --git a/util/pgtblgen/description.md b/util/pgtblgen/description.md new file mode 100644 index 0000000000..f2e4763d75 --- /dev/null +++ b/util/pgtblgen/description.md @@ -0,0 +1 @@ +Generates page tables based on fixed physical address. `C` diff --git a/util/pgtblgen/pgtblgen.c b/util/pgtblgen/pgtblgen.c new file mode 100644 index 0000000000..efbad55204 --- /dev/null +++ b/util/pgtblgen/pgtblgen.c @@ -0,0 +1,168 @@ +/* + * This file is part of pgtblgen. + * + * Copyright (c) 2019 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void usage(char *argv[]) +{ + printf("usage: %s -b -a -o \n", argv[0]); + printf(" -a\t architecure. Supported: x86_64\n"); + printf(" -b\t base address\n"); + printf(" -b\t the file to write to\n"); + printf(" -h\t show this help text\n"); +} + +/* + * For reference see "AMD64 ArchitectureProgrammer's Manual Volume 2", + * Document 24593-Rev. 3.31-July 2019 Chapter 5.3.4 + * + * Page table attributes: WB, User+Supervisor, Present, Writeable + */ +#define PRES (1ULL << 0) +#define RW (1ULL << 1) +#define US (1ULL << 2) +#define PS (1ULL << 7) +#define _GEN_DIR(a) (PRES | RW | US | (a)) +#define _GEN_PAGE(a) (PRES | RW | US | PS | (a)) + +/* + * Generate x86_64 page tables. + * The page tables needs to be placed at @base_address, and identity map + * the first @size_gib GiB of physical memory. + */ +static int gen_pgtbl_x86_64(const uint64_t base_address, + const size_t size_gib, + void **out_buf, + size_t *out_size) +{ + uint64_t *entry; + + if (!out_size || !out_buf) + return 1; + + *out_size = (size_gib + 2) * 4096; + *out_buf = malloc(*out_size); + if (!*out_buf) + return 1; + + memset(*out_buf, 0, *out_size); + entry = (uint64_t *)*out_buf; + + /* Generate one PM4LE entry - point to PDPE */ + entry[0] = _GEN_DIR(base_address + 4096); + entry += 512; + + /* PDPE table - point to PDE */ + for (size_t i = 0; i < size_gib; i++) + entry[i] = _GEN_DIR(base_address + 4096 * (i + 2)); + entry += 512; + + /* PDE tables - identity map 2MiB pages */ + for (size_t g = 0; g < size_gib; g++) { + for (size_t i = 0; i < 512; i++) { + uint64_t addr = ((1ULL << (12 + 9)) * i) | ((1ULL << (12 + 9 + 9)) * g); + entry[i] = _GEN_PAGE(addr); + } + entry += 512; + } + + return 0; +} + +int main(int argc, char *argv[]) +{ + int ret = 1; + uint64_t base_address = 0; + char *filename = NULL; + char *arch = NULL; + void *buf = NULL; + size_t buf_size = 0; + int c; + + while ((c = getopt(argc, argv, "ho:a:b:")) != -1) + switch (c) { + case '?': /* falltrough */ + case 'h': + usage(argv); + return 0; + case 'o': + filename = optarg; + break; + case 'a': + arch = optarg; + break; + case 'b': + base_address = strtoull(optarg, NULL, 0); + break; + default: + break; + } + + if (!filename) { + fprintf(stderr, "E: Missing filename.\n"); + goto done; + } + if (!arch) { + fprintf(stderr, "E: Missing architecture.\n"); + goto done; + } else if (strcmp(arch, "x86_64") != 0) { + fprintf(stderr, "E: Unsupported architecture.\n"); + goto done; + } + if (base_address & 4095) { + fprintf(stderr, "E: Base address not 4 KiB aligned\n"); + goto done; + } + + /* FIXME: Identity map 4GiB for now, increase if necessary */ + if (strcmp(arch, "x86_64") == 0) + ret = gen_pgtbl_x86_64(base_address, 4, &buf, &buf_size); + + if (ret) { + fprintf(stderr, "Failed to generate page tables\n"); + goto done; + } + + // write the table + FILE *fd = fopen(filename, "wb"); + if (!fd) { + fprintf(stderr, "%s open failed: %s\n", filename, strerror(errno)); + goto done; + } + + if (fwrite(buf, 1, buf_size, fd) != buf_size) { + fprintf(stderr, "%s write failed: %s\n", filename, strerror(errno)); + fclose(fd); + goto done; + } + + if (fclose(fd)) { + fprintf(stderr, "%s close failed: %s\n", filename, strerror(errno)); + goto done; + } + + ret = 0; +done: + free(buf); + return ret; +} diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 6b421ec3d6..5c2333309b 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -696,7 +696,7 @@ static int dev_has_children(struct device *dev) return 0; } -static void pass0(FILE *fil, struct device *ptr, struct device *next) +static void pass0(FILE *fil, FILE *head, struct device *ptr, struct device *next) { if (ptr == &base_root_dev) { fprintf(fil, "STORAGE struct bus %s_links[];\n", @@ -781,7 +781,7 @@ static void emit_dev_links(FILE *fil, struct device *ptr) fprintf(fil, "\t};\n"); } -static void pass1(FILE *fil, struct device *ptr, struct device *next) +static void pass1(FILE *fil, FILE *head, struct device *ptr, struct device *next) { int pin; struct chip_instance *chip_ins = ptr->chip_instance; @@ -883,16 +883,22 @@ static void pass1(FILE *fil, struct device *ptr, struct device *next) emit_dev_links(fil, ptr); } -static void expose_device_names(FILE *fil, struct device *ptr, struct device *next) +static void expose_device_names(FILE *fil, FILE *head, struct device *ptr, struct device *next) { /* Only devices on root bus here. */ - if (ptr->bustype == PCI && ptr->parent->dev->bustype == DOMAIN) + if (ptr->bustype == PCI && ptr->parent->dev->bustype == DOMAIN) { + fprintf(head, "extern DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d;\n", + ptr->path_a, ptr->path_b); fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d = &%s;\n", ptr->path_a, ptr->path_b, ptr->name); + } - if (ptr->bustype == PNP) + if (ptr->bustype == PNP) { + fprintf(head, "extern DEVTREE_CONST struct device *DEVTREE_CONST __pnp_%04x_%02x;\n", + ptr->path_a, ptr->path_b); fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pnp_%04x_%02x = &%s;\n", ptr->path_a, ptr->path_b, ptr->name); + } } static void add_siblings_to_queue(struct queue_entry **bfs_q_head, @@ -916,8 +922,8 @@ static void add_children_to_queue(struct queue_entry **bfs_q_head, } } -static void walk_device_tree(FILE *fil, struct device *ptr, - void (*func)(FILE *, struct device *, +static void walk_device_tree(FILE *fil, FILE *head, struct device *ptr, + void (*func)(FILE *, FILE *, struct device *, struct device *)) { struct queue_entry *bfs_q_head = NULL; @@ -926,7 +932,7 @@ static void walk_device_tree(FILE *fil, struct device *ptr, while ((ptr = dequeue_head(&bfs_q_head))) { add_children_to_queue(&bfs_q_head, ptr); - func(fil, ptr, peek_queue_head(bfs_q_head)); + func(fil, head, ptr, peek_queue_head(bfs_q_head)); } } @@ -995,7 +1001,7 @@ static void emit_chips(FILE *fil) } } -static void inherit_subsystem_ids(FILE *file, struct device *dev, +static void inherit_subsystem_ids(FILE *file, FILE *head, struct device *dev, struct device *next) { struct device *p; @@ -1020,17 +1026,18 @@ static void inherit_subsystem_ids(FILE *file, struct device *dev, static void usage(void) { - printf("usage: sconfig devicetree_file output_file [override_devicetree_file]\n"); + printf("usage: sconfig devicetree_file output_file header_file [override_devicetree_file]\n"); exit(1); } enum { DEVICEFILE_ARG = 1, OUTPUTFILE_ARG, + HEADERFILE_ARG, OVERRIDE_DEVICEFILE_ARG, }; -#define MANDATORY_ARG_COUNT 3 +#define MANDATORY_ARG_COUNT 4 #define OPTIONAL_ARG_COUNT 1 #define TOTAL_ARG_COUNT (MANDATORY_ARG_COUNT + OPTIONAL_ARG_COUNT) @@ -1365,6 +1372,7 @@ int main(int argc, char **argv) const char *base_devtree = argv[DEVICEFILE_ARG]; const char *outputc = argv[OUTPUTFILE_ARG]; + const char *outputh = argv[HEADERFILE_ARG]; const char *override_devtree; parse_devicetree(base_devtree, &base_root_bus); @@ -1389,18 +1397,31 @@ int main(int argc, char **argv) exit(1); } + FILE *autohead = fopen(outputh, "w"); + if (!autohead) { + fprintf(stderr, "Could not open file '%s' for writing: ", outputh); + perror(NULL); + fclose(autogen); + exit(1); + } + fprintf(autohead, "#ifndef __STATIC_DEVICE_TREE_H\n"); + fprintf(autohead, "#define __STATIC_DEVICE_TREE_H\n\n"); + fprintf(autohead, "#include \n\n"); + emit_chips(autogen); - walk_device_tree(autogen, &base_root_dev, inherit_subsystem_ids); + walk_device_tree(autogen, autohead, &base_root_dev, inherit_subsystem_ids); fprintf(autogen, "\n/* pass 0 */\n"); - walk_device_tree(autogen, &base_root_dev, pass0); + walk_device_tree(autogen, autohead, &base_root_dev, pass0); fprintf(autogen, "\n/* pass 1 */\n"); - walk_device_tree(autogen, &base_root_dev, pass1); + walk_device_tree(autogen, autohead, &base_root_dev, pass1); /* Expose static devicenames to global namespace. */ fprintf(autogen, "\n/* expose_device_names */\n"); - walk_device_tree(autogen, &base_root_dev, expose_device_names); + walk_device_tree(autogen, autohead, &base_root_dev, expose_device_names); + fprintf(autohead, "\n#endif /* __STATIC_DEVICE_TREE_H */\n"); + fclose(autohead); fclose(autogen); return 0;