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tree/acpi: Replace Not(a) with ASL 2.0 syntax

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Replace `Not (a)` with `~a`.

Change-Id: I53993fb7b46b3614d18ee001323f17efacbf04c1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71513
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer
2022-12-25 16:25:06 +01:00
committed by Elyes Haouas
parent 25b717ad84
commit c87c1abffb
4 changed files with 4 additions and 4 deletions
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2
src/ec/google/chromeec/acpi/battery.asl
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@@ -44,7 +44,7 @@ Method (BSTA, 1, Serialized)
Return (Zero)
}
If (Not(BTSW (Arg0)) & BTEX) {
If (~BTSW (Arg0) & BTEX) {
Local0 = 0x1F
} Else {
Local0 = 0x0F

2
src/ec/google/chromeec/acpi/ec.asl
View File

@@ -630,7 +630,7 @@ Device (EC0)
*/
Method (UPPC, 1, Serialized)
{
USPP &= Not (1 << Arg0)
USPP &= ~(1 << Arg0)
}
#endif

2
src/ec/quanta/it8518/acpi/ec.asl
View File

@@ -547,7 +547,7 @@ Device (EC0)
\PWRS = ACPW
// Initialize LID switch state
\LIDS = NOT(HPLD)
\LIDS = ~HPLD
// Enable OS control of fan speed
// TODO FCOS = One

2
src/soc/intel/cannonlake/acpi/gpio.asl
View File

@@ -138,7 +138,7 @@ Method (CGPM, 2, Serialized)
Local0 = GPID (Arg0)
If (Local0 != 0) {
/* Mask off current PM bits */
PCRA (Local0, GPIO_MISCCFG, Not (MISCCFG_GPIO_PM_CONFIG_BITS))
PCRA (Local0, GPIO_MISCCFG, ~MISCCFG_GPIO_PM_CONFIG_BITS)
/* Mask in requested bits */
PCRO (Local0, GPIO_MISCCFG, Arg1 & MISCCFG_GPIO_PM_CONFIG_BITS)
}