broadwell: add new intel SOC
broadwell: Import files from haswell/lynxpoint into soc/broadwell Reviewed-on: https://chromium-review.googlesource.com/198425 (cherry picked from commit 178400e5709d676dd41e6a75df06faa829e0e3af) broadwell: Unify and clean up license Reviewed-on: https://chromium-review.googlesource.com/198426 (cherry picked from commit 30d3c25a0abc76be68477c39a654b95a5975f55d) broadwell: pch.h: split PM into new header Reviewed-on: https://chromium-review.googlesource.com/198427 (cherry picked from commit 97a8d0b051f476d0edc06301f57326a718df1373) broadwell: pch.h: split RCBA into new header Reviewed-on: https://chromium-review.googlesource.com/198428 (cherry picked from commit fa217361b28fdb8d3a3e85f070dfaf13c0d48135) broadwell: pch.h: split SATA into new header Reviewed-on: https://chromium-review.googlesource.com/198429 (cherry picked from commit bf8795ca92f9f0467e7869c701038abb4529ac71) broadwell: pch.h: split SPI into new header Reviewed-on: https://chromium-review.googlesource.com/198550 (cherry picked from commit 099af14676a2654ca3e24e66d7b9f0b4ab13cd14) broadwell: pch.h: split SerialIO into new header Reviewed-on: https://chromium-review.googlesource.com/198551 (cherry picked from commit 4f3c028686aed78fb07b8792dcf46aebd2268ea6) broadwell: pch.h: split LPC into new header Reviewed-on: https://chromium-review.googlesource.com/198552 (cherry picked from commit 10bad5bbb6739c0277fd5330d26a89d60fd5c102) broadwell: pch.h: split GPIO into new header and clean up Reviewed-on: https://chromium-review.googlesource.com/198553 (cherry picked from commit 9c97532460562215b78e10b011a29e092a07f3e5) broadwell: pch.h: split USB into new headers Reviewed-on: https://chromium-review.googlesource.com/198554 (cherry picked from commit 86ef1a45a2e5f307467b3be48e377569f37b3068) broadwell: Split IOBP into separate files Reviewed-on: https://chromium-review.googlesource.com/198734 (cherry picked from commit f93b8bda71728f1383937ad675d2d5fb5a927600) broadwell: smbus: Extract common code and split header Reviewed-on: https://chromium-review.googlesource.com/198735 (cherry picked from commit 8052030a9d6b22e8a19938fa9b93e90d08f0057d) broadwell: Create iomap.h header with platform base addresses Reviewed-on: https://chromium-review.googlesource.com/198736 (cherry picked from commit b35947d070b28871637dfe2b930a9f2be80958ee) broadwell: Add header for platform PCI devices Reviewed-on: https://chromium-review.googlesource.com/198737 (cherry picked from commit 6ac4e56db6e489bb9eaf91a0c3c543399f691500) broadwell: Split SMM related defines/prototypes to new header Reviewed-on: https://chromium-review.googlesource.com/198738 (cherry picked from commit 2a2595067077cd918bfd48cad79a684b8e1ff0f4) broadwell: cpu.h: Split MSR defines to separate header Reviewed-on: https://chromium-review.googlesource.com/198739 (cherry picked from commit 01148cd2c9edd97cd0c8ef3cfed58bc8c33eb805) broadwell: Create romstage header file Reviewed-on: https://chromium-review.googlesource.com/198740 (cherry picked from commit 31c91e811b9e07e7bcba6b9f8f5720a31322eb21) broadwell: Create ram stage header file Reviewed-on: https://chromium-review.googlesource.com/198741 (cherry picked from commit 93dde85f98d43d4a1886b59004d1bab4924ad621) broadwell: Add reference code data interface Reviewed-on: https://chromium-review.googlesource.com/198743 (cherry picked from commit 9059b8e2308892a48c838c3099404c9cf450df95) broadwell: Clean up ACPI NVS region Reviewed-on: https://chromium-review.googlesource.com/198897 (cherry picked from commit d83cc82c36661556eb1e2e437b7ac51d5b8e4a14) broadwell: Move CTDP ACPI methods to new file Reviewed-on: https://chromium-review.googlesource.com/198898 (cherry picked from commit fc1e711290df304d18c558d697eea8a5e57061b2) broadwell: Split EHCI and XHCI ACPI devices Reviewed-on: https://chromium-review.googlesource.com/198899 (cherry picked from commit 26f437b27e00dbd5c92ea22e76404633a62fb7ca) broadwell: ACPI: Clean up SerialIO ACPI code Reviewed-on: https://chromium-review.googlesource.com/198910 (cherry picked from commit ea3cd39566c1bb2ead463a6253b6204a62545d35) broadwell: ACPI: Remove special handling of LPT-LP chipset Reviewed-on: https://chromium-review.googlesource.com/198911 (cherry picked from commit 2c54df159bf6759c8f866628e83541de6f4e28f6) broadwell: ACPI: Clean up use of base address defines Reviewed-on: https://chromium-review.googlesource.com/198912 (cherry picked from commit 34e4788955bceff01631fd0b4dbf0aa24cf56b75) broadwell: ACPI: Clean up and fix formatting Reviewed-on: https://chromium-review.googlesource.com/198913 (cherry picked from commit bc0f7c6d2f95681eb987bb6ff6baf2d16cc77050) broadwell: Add header for ACPI defines and prototypes Reviewed-on: https://chromium-review.googlesource.com/198914 (cherry picked from commit 9951e7931942d2921f92f6e094b1cc32c190eab9) broadwell: Add reset_system function and header Reviewed-on: https://chromium-review.googlesource.com/198915 (cherry picked from commit 6d1efb94bd39bcd6f7e3e0de2f3299a384b109ef) broadwell: Move PCODE MMIO defines to systemagent.h Reviewed-on: https://chromium-review.googlesource.com/198916 (cherry picked from commit abb5f87e548fbde3a08e14a18714b4e4391c955f) broadwell: Unify chip.h and add chip.c Reviewed-on: https://chromium-review.googlesource.com/198917 (cherry picked from commit a9c2d7ff3afa1e2a10be85ccc72b7db0f2aaafe1) broadwell: Rename HASWELL_BCLK to CPU_BCLK Reviewed-on: https://chromium-review.googlesource.com/198918 (cherry picked from commit 65ac1a07abaf14eb42fec6c5df67d2d3688ad5a1) broadwell: Clean up broadwell/cpu.h Reviewed-on: https://chromium-review.googlesource.com/198919 (cherry picked from commit 17353803babc8ace279e105c012130678226144e) broadwell: Clean up broadwell/systemagent.h Reviewed-on: https://chromium-review.googlesource.com/198920 (cherry picked from commit 49d7a023f3ff04a65d16622aa9b2fa6004b693ae) broadwell: Clean up broadwell/pch.h Reviewed-on: https://chromium-review.googlesource.com/198921 (cherry picked from commit 17da652b4408a91fcfea99dd35fe9f9e1bdcf03b) broadwell: Clean up management engine driver Reviewed-on: https://chromium-review.googlesource.com/198922 (cherry picked from commit 4fce5fbb56dc4f31b77e5ada05463c043ad5be72) broadwell: Add common CPUID and PCI Device ID defines Reviewed-on: https://chromium-review.googlesource.com/198923 (cherry picked from commit c6bf20309f33168ea2cc4634cbda5ec242824ba8) broadwell: Clean up and expand report_platform Reviewed-on: https://chromium-review.googlesource.com/198924 (cherry picked from commit 5082d4824db149e867a2cd8be34c932b03754022) broadwell: Clean up the bootblock code Reviewed-on: https://chromium-review.googlesource.com/198925 (cherry picked from commit ba0206ab76fe0b6834a14dc57f400d139094623c) broadwell: Clean up ramstage device and driver operations Reviewed-on: https://chromium-review.googlesource.com/199180 (cherry picked from commit d8fc9daf129738713a5059286b7ead004f3b7569) broadwell: Clean up XHCI and EHCI ramstage drivers Reviewed-on: https://chromium-review.googlesource.com/199181 (cherry picked from commit d355247333a828a146ce7cf9b92a63da74119c1d) broadwell: Clean up gpio handling code Reviewed-on: https://chromium-review.googlesource.com/199182 (cherry picked from commit d62cef1970fe75f8166315016b3d8415cddcab20) broadwell: Clean up the PCH generic code Reviewed-on: https://chromium-review.googlesource.com/199183 (cherry picked from commit 3b93b3ea79965d5ac831bf9015e49330f157b0ff) broadwell: Move get_top_of_ram() and cbmem_top() to memmap.c Reviewed-on: https://chromium-review.googlesource.com/199184 (cherry picked from commit 68955ba4ff8b49ff466d7badaa934bd143026ba7) broadwell: Clean up pmutil.c Reviewed-on: https://chromium-review.googlesource.com/199185 (cherry picked from commit b6fb672ae879e17422f7449f70c3669055096f84) broadwell: pmutil: Add new acpi_sci_irq() function Reviewed-on: https://chromium-review.googlesource.com/199186 (cherry picked from commit 80ad8bb9bdc75f180e667861fed42a3844226bc5) broadwell: Clean up HDA ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199187 (cherry picked from commit b4962acd706eaa66c1c3ef4d22eba313642fbb2d) broadwell: Clean up cache_as_ram assembly Reviewed-on: https://chromium-review.googlesource.com/199188 (cherry picked from commit 8a457b82610b604ae7f69e2500815ce411c2d02d) broadwell: romstage: Separate stack helper functions Reviewed-on: https://chromium-review.googlesource.com/199189 (cherry picked from commit c220383c90466fc2dbf4b6107679b08ecb4aadad) broadwell: Add function to read WPSR from SPI Reviewed-on: https://chromium-review.googlesource.com/199190 (cherry picked from commit 935404da1157d606b913eff6c2635ae898e9980a) broadwell: Clean up SMBUS code in romstage and ramstage Reviewed-on: https://chromium-review.googlesource.com/199191 (cherry picked from commit 6ae9d93c1a6f14da6429a4e5b01619c9ccaefdaa) broadwell: SPI: Clean up romstage and ramstage code Reviewed-on: https://chromium-review.googlesource.com/199192 (cherry picked from commit 28ffd71a416aee2ab54bc5d782cfeef31d4d30bf) broadwell: Clean up PCIe root port ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199193 (cherry picked from commit 781f3a1b72c72f0bb05f5524edec471ad13ec90e) broadwell: Clean up minihd ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199194 (cherry picked from commit a52d275e41fdcbf9895d07350725609d9be1ff0e) broadwell: Update romstage main to follow baytrail format Reviewed-on: https://chromium-review.googlesource.com/199361 (cherry picked from commit 0678c739af84c871922ffba5594132b25e471ddd) broadwell: Add CPU set_max_freq function for romstage Reviewed-on: https://chromium-review.googlesource.com/199362 (cherry picked from commit 68b0122472af27f38502d42a8a6c80678ddbbba6) broadwell: romstage: Add chipset_power_state implementation Reviewed-on: https://chromium-review.googlesource.com/199363 (cherry picked from commit 761cec3b6bb9bde579c3214f3f1196f65700757c) broadwell: romstage: Convert systemagent init to reg_script Reviewed-on: https://chromium-review.googlesource.com/199364 (cherry picked from commit c2ea2d3a0c7555a353fb9a1d4a63e773ac8961b2) broadwell: romstage: Convert pch init to reg_script Reviewed-on: https://chromium-review.googlesource.com/199365 (cherry picked from commit 4383de5846e97ca5aee6dd210459d8dba0af981c) broadwell: elog: Use chipset_power_state for events Reviewed-on: https://chromium-review.googlesource.com/199366 (cherry picked from commit 0ef5961ebe3a7037d5fbe361fbc70a87ac2edad9) broadwell: Clean up SATA ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199367 (cherry picked from commit ffa5743f74551bd48aa7e5445ce7cd9dc7b07ce8) broadwell: Update ramstage graphics driver to support broadwell Reviewed-on: https://chromium-review.googlesource.com/199368 (cherry picked from commit bb01deb8bbed56f15e1143504e4cf012ecf5a281) broadwell: Update raminit to follow baytrail layout Reviewed-on: https://chromium-review.googlesource.com/199369 (cherry picked from commit 3f25c23dc58f85d2521916cd6edbe9deeeb8d523) broadwell: Update and unify the finalize steps Reviewed-on: https://chromium-review.googlesource.com/199390 (cherry picked from commit ddc4c116b42d38dfdfc45ef4388fbfab32ca48fa) broadwell: Clean up SMM code Reviewed-on: https://chromium-review.googlesource.com/199391 (cherry picked from commit 8295e56c9b643fd4b9267d70b5efd0cf94dd67dd) broadwell: Clean up LPC ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199392 (cherry picked from commit 28326aeaaf304c9262866588d91b79b37d1d9a2e) broadwell: Clean up systemagent ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199393 (cherry picked from commit 749988fff07eab8d2c9ebc731e3ed9e427b3f7b3) broadwell: Move C-state configuration information to acpi.c Reviewed-on: https://chromium-review.googlesource.com/199394 (cherry picked from commit 198a3cd5cbd009be406298cbb53163f075fe9990) broadwell: Clean up CPU ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199395 (cherry picked from commit 8159689bba479bab6fd2e949e3e1c3f817088969) broadwell: Do not reserve SMM relocation region Reviewed-on: https://chromium-review.googlesource.com/199402 (cherry picked from commit e2ab52340e3d3a97a3f8dbdad8fac9f7769d1b4c) broadwell: Add an early ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199403 (cherry picked from commit c7a8c867101b49a7f9f17ec1a8777a8db145f3e3) broadwell: Support for second reference code binary Reviewed-on: https://chromium-review.googlesource.com/199404 (cherry picked from commit abb99b36e97c4f739b23abed6146fea370bbbec2) broadwell: Clean up serialio init code Reviewed-on: https://chromium-review.googlesource.com/199405 (cherry picked from commit e09a1f8520a7b72451a1e2068b200f7c5451f489) broadwell: acpi: Add function to fill out FADT Reviewed-on: https://chromium-review.googlesource.com/199406 (cherry picked from commit 7e58f43e46d4382cf4541057f81fe6be3e4d6e74) broadwell: Update C-state table creation Reviewed-on: https://chromium-review.googlesource.com/199407 (cherry picked from commit 68b1f70e32e1d0c6fc4332dce402ad78334e0063) broadwell: acpi: Clean up acpi table creation code Reviewed-on: https://chromium-review.googlesource.com/199408 (cherry picked from commit 49088b312b159bb17a9330eda6a88d6f324ea146) broadwell: acpi: Add ACPI table create helper functions Reviewed-on: https://chromium-review.googlesource.com/199409 (cherry picked from commit 344c3c511d0341457525ef4d6eb70201404fc62c) broadwell: Add soc/intel/broadwell Makefiles Reviewed-on: https://chromium-review.googlesource.com/199410 (cherry picked from commit ea8f97738eadd3b0b6a642754df7a7d22e547ffc) broadwell: Add Kconfig for broadwell soc Reviewed-on: https://chromium-review.googlesource.com/199411 (cherry picked from commit 8c99038a5c20812497619134c66d45bc4f21c8fe) Squashed 78 commits for broadwell that form a solid code base. Change-Id: I365ca9a45978b5e0cc5237f884e20a44f62a0e63 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6964 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Duncan Laurie
committed by
Marc Jones
Marc Jones
parent
f0aaa29989
commit
c88c54c667
440
src/soc/intel/broadwell/systemagent.c
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src/soc/intel/broadwell/systemagent.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <stdlib.h>
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#include <string.h>
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#include <cbmem.h>
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#include <romstage_handoff.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <broadwell/cpu.h>
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#include <broadwell/iomap.h>
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#include <broadwell/ramstage.h>
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#include <broadwell/systemagent.h>
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static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
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{
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u32 pciexbar_reg;
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*base = 0;
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*len = 0;
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pciexbar_reg = pci_read_config32(dev, index);
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if (!(pciexbar_reg & (1 << 0)))
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return 0;
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switch ((pciexbar_reg >> 1) & 3) {
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case 0: // 256MB
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*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
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(1 << 28));
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*len = 256 * 1024 * 1024;
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return 1;
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case 1: // 128M
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*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
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(1 << 28)|(1 << 27));
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*len = 128 * 1024 * 1024;
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return 1;
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case 2: // 64M
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*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|
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(1 << 28)|(1 << 27)|(1 << 26));
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*len = 64 * 1024 * 1024;
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return 1;
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}
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return 0;
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}
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static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
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{
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u32 bar;
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bar = pci_read_config32(dev, index);
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/* If not enabled don't report it. */
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if (!(bar & 0x1))
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return 0;
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/* Knock down the enable bit. */
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*base = bar & ~1;
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return 1;
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}
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/* There are special BARs that actually are programmed in the MCHBAR. These
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* Intel special features, but they do consume resources that need to be
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* accounted for. */
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static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base,
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u32 *len)
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{
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u32 bar;
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bar = MCHBAR32(index);
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/* If not enabled don't report it. */
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if (!(bar & 0x1))
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return 0;
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/* Knock down the enable bit. */
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*base = bar & ~1;
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return 1;
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}
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struct fixed_mmio_descriptor {
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unsigned int index;
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u32 size;
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int (*get_resource)(device_t dev, unsigned int index,
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u32 *base, u32 *size);
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const char *description;
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};
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struct fixed_mmio_descriptor mc_fixed_resources[] = {
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{ PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" },
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{ MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" },
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{ DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" },
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{ EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" },
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{ GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" },
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{ EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" },
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};
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/*
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* Add all known fixed MMIO ranges that hang off the host bridge/memory
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* controller device.
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*/
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static void mc_add_fixed_mmio_resources(device_t dev)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) {
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u32 base;
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u32 size;
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struct resource *resource;
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unsigned int index;
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size = mc_fixed_resources[i].size;
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index = mc_fixed_resources[i].index;
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if (!mc_fixed_resources[i].get_resource(dev, index,
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&base, &size))
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continue;
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resource = new_resource(dev, mc_fixed_resources[i].index);
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resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
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IORESOURCE_STORED | IORESOURCE_RESERVE |
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IORESOURCE_ASSIGNED;
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resource->base = base;
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resource->size = size;
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printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
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__func__, mc_fixed_resources[i].description, index,
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(unsigned long)base, (unsigned long)(base + size - 1));
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}
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}
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/* Host Memory Map:
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*
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* +--------------------------+ TOUUD
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* | |
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* +--------------------------+ 4GiB
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* | PCI Address Space |
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* +--------------------------+ TOLUD (also maps into MC address space)
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* | iGD |
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* +--------------------------+ BDSM
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* | GTT |
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* +--------------------------+ BGSM
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* | TSEG |
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* +--------------------------+ TSEGMB
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* | Usage DRAM |
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* +--------------------------+ 0
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*
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* Some of the base registers above can be equal making the size of those
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* regions 0. The reason is because the memory controller internally subtracts
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* the base registers from each other to determine sizes of the regions. In
|
||||
* other words, the memory map is in a fixed order no matter what.
|
||||
*/
|
||||
|
||||
struct map_entry {
|
||||
int reg;
|
||||
int is_64_bit;
|
||||
int is_limit;
|
||||
const char *description;
|
||||
};
|
||||
|
||||
static void read_map_entry(device_t dev, struct map_entry *entry,
|
||||
uint64_t *result)
|
||||
{
|
||||
uint64_t value;
|
||||
uint64_t mask;
|
||||
|
||||
/* All registers are on a 1MiB granularity. */
|
||||
mask = ((1ULL<<20)-1);
|
||||
mask = ~mask;
|
||||
|
||||
value = 0;
|
||||
|
||||
if (entry->is_64_bit) {
|
||||
value = pci_read_config32(dev, entry->reg + 4);
|
||||
value <<= 32;
|
||||
}
|
||||
|
||||
value |= pci_read_config32(dev, entry->reg);
|
||||
value &= mask;
|
||||
|
||||
if (entry->is_limit)
|
||||
value |= ~mask;
|
||||
|
||||
*result = value;
|
||||
}
|
||||
|
||||
#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \
|
||||
{ \
|
||||
.reg = reg_, \
|
||||
.is_64_bit = is_64_, \
|
||||
.is_limit = is_limit_, \
|
||||
.description = desc_, \
|
||||
}
|
||||
|
||||
#define MAP_ENTRY_BASE_64(reg_, desc_) \
|
||||
MAP_ENTRY(reg_, 1, 0, desc_)
|
||||
#define MAP_ENTRY_LIMIT_64(reg_, desc_) \
|
||||
MAP_ENTRY(reg_, 1, 1, desc_)
|
||||
#define MAP_ENTRY_BASE_32(reg_, desc_) \
|
||||
MAP_ENTRY(reg_, 0, 0, desc_)
|
||||
|
||||
enum {
|
||||
TOM_REG,
|
||||
TOUUD_REG,
|
||||
MESEG_BASE_REG,
|
||||
MESEG_LIMIT_REG,
|
||||
REMAP_BASE_REG,
|
||||
REMAP_LIMIT_REG,
|
||||
TOLUD_REG,
|
||||
BGSM_REG,
|
||||
BDSM_REG,
|
||||
TSEG_REG,
|
||||
// Must be last.
|
||||
NUM_MAP_ENTRIES
|
||||
};
|
||||
|
||||
static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
|
||||
[TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"),
|
||||
[TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
|
||||
[MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"),
|
||||
[MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"),
|
||||
[REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"),
|
||||
[REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"),
|
||||
[TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
|
||||
[BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"),
|
||||
[BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"),
|
||||
[TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"),
|
||||
};
|
||||
|
||||
static void mc_read_map_entries(device_t dev, uint64_t *values)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < NUM_MAP_ENTRIES; i++) {
|
||||
read_map_entry(dev, &memory_map[i], &values[i]);
|
||||
}
|
||||
}
|
||||
|
||||
static void mc_report_map_entries(device_t dev, uint64_t *values)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < NUM_MAP_ENTRIES; i++) {
|
||||
printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
|
||||
memory_map[i].description, values[i]);
|
||||
}
|
||||
/* One can validate the BDSM and BGSM against the GGC. */
|
||||
printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
|
||||
}
|
||||
|
||||
static void mc_add_dram_resources(device_t dev)
|
||||
{
|
||||
unsigned long base_k, size_k;
|
||||
unsigned long touud_k;
|
||||
unsigned long index;
|
||||
struct resource *resource;
|
||||
uint64_t mc_values[NUM_MAP_ENTRIES];
|
||||
|
||||
/* Read in the MAP registers and report their values. */
|
||||
mc_read_map_entries(dev, &mc_values[0]);
|
||||
mc_report_map_entries(dev, &mc_values[0]);
|
||||
|
||||
/*
|
||||
* These are the host memory ranges that should be added:
|
||||
* - 0 -> 0xa0000: cacheable
|
||||
* - 0xc0000 -> TSEG : cacheable
|
||||
* - TESG -> BGSM: cacheable with standard MTRRs and reserved
|
||||
* - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved
|
||||
* - 4GiB -> TOUUD: cacheable
|
||||
*
|
||||
* The default SMRAM space is reserved so that the range doesn't
|
||||
* have to be saved during S3 Resume. Once marked reserved the OS
|
||||
* cannot use the memory. This is a bit of an odd place to reserve
|
||||
* the region, but the CPU devices don't have dev_ops->read_resources()
|
||||
* called on them.
|
||||
*
|
||||
* The range 0xa0000 -> 0xc0000 does not have any resources
|
||||
* associated with it to handle legacy VGA memory. If this range
|
||||
* is not omitted the mtrr code will setup the area as cacheable
|
||||
* causing VGA access to not work.
|
||||
*
|
||||
* The TSEG region is mapped as cacheable so that one can perform
|
||||
* SMRAM relocation faster. Once the SMRR is enabled the SMRR takes
|
||||
* precedence over the existing MTRRs covering this region.
|
||||
*
|
||||
* It should be noted that cacheable entry types need to be added in
|
||||
* order. The reason is that the current MTRR code assumes this and
|
||||
* falls over itself if it isn't.
|
||||
*
|
||||
* The resource index starts low and should not meet or exceed
|
||||
* PCI_BASE_ADDRESS_0.
|
||||
*/
|
||||
index = 0;
|
||||
|
||||
/* 0 - > 0xa0000 */
|
||||
base_k = 0;
|
||||
size_k = (0xa0000 >> 10) - base_k;
|
||||
ram_resource(dev, index++, base_k, size_k);
|
||||
|
||||
/* 0xc0000 -> TSEG */
|
||||
base_k = 0xc0000 >> 10;
|
||||
size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k;
|
||||
ram_resource(dev, index++, base_k, size_k);
|
||||
|
||||
/* TSEG -> BGSM */
|
||||
resource = new_resource(dev, index++);
|
||||
resource->base = mc_values[TSEG_REG];
|
||||
resource->size = mc_values[BGSM_REG] - resource->base;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
|
||||
IORESOURCE_STORED | IORESOURCE_RESERVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
|
||||
|
||||
/* BGSM -> TOLUD */
|
||||
resource = new_resource(dev, index++);
|
||||
resource->base = mc_values[BGSM_REG];
|
||||
resource->size = mc_values[TOLUD_REG] - resource->base;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
|
||||
IORESOURCE_STORED | IORESOURCE_RESERVE |
|
||||
IORESOURCE_ASSIGNED;
|
||||
|
||||
/* 4GiB -> TOUUD */
|
||||
base_k = 4096 * 1024; /* 4GiB */
|
||||
touud_k = mc_values[TOUUD_REG] >> 10;
|
||||
size_k = touud_k - base_k;
|
||||
if (touud_k > base_k)
|
||||
ram_resource(dev, index++, base_k, size_k);
|
||||
|
||||
/* Reserve everything between A segment and 1MB:
|
||||
*
|
||||
* 0xa0000 - 0xbffff: legacy VGA
|
||||
* 0xc0000 - 0xfffff: RAM
|
||||
*/
|
||||
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
|
||||
reserved_ram_resource(dev, index++, (0xc0000 >> 10),
|
||||
(0x100000 - 0xc0000) >> 10);
|
||||
|
||||
chromeos_reserve_ram_oops(dev, index++);
|
||||
}
|
||||
|
||||
static void systemagent_read_resources(device_t dev)
|
||||
{
|
||||
/* Read standard PCI resources. */
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
/* Add all fixed MMIO resources. */
|
||||
mc_add_fixed_mmio_resources(dev);
|
||||
|
||||
/* Calculate and add DRAM resources. */
|
||||
mc_add_dram_resources(dev);
|
||||
}
|
||||
|
||||
static void systemagent_init(struct device *dev)
|
||||
{
|
||||
u8 bios_reset_cpl, pair;
|
||||
|
||||
/* Enable Power Aware Interrupt Routing */
|
||||
pair = MCHBAR8(MCH_PAIR);
|
||||
pair &= ~0x7; /* Clear 2:0 */
|
||||
pair |= 0x4; /* Fixed Priority */
|
||||
MCHBAR8(MCH_PAIR) = pair;
|
||||
|
||||
/*
|
||||
* Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
|
||||
* that BIOS has initialized memory and power management
|
||||
*/
|
||||
bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
|
||||
bios_reset_cpl |= 3;
|
||||
MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
|
||||
printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
|
||||
|
||||
/* Configure turbo power limits 1ms after reset complete bit */
|
||||
mdelay(1);
|
||||
set_power_limits(28);
|
||||
}
|
||||
|
||||
static void systemagent_enable(device_t dev)
|
||||
{
|
||||
#if CONFIG_HAVE_ACPI_RESUME
|
||||
struct romstage_handoff *handoff;
|
||||
|
||||
handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
|
||||
|
||||
if (handoff == NULL) {
|
||||
printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
|
||||
acpi_slp_type = 0;
|
||||
} else if (handoff->s3_resume) {
|
||||
printk(BIOS_DEBUG, "S3 Resume.\n");
|
||||
acpi_slp_type = 3;
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "Normal boot.\n");
|
||||
acpi_slp_type = 0;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static struct device_operations systemagent_ops = {
|
||||
.read_resources = &systemagent_read_resources,
|
||||
.set_resources = &pci_dev_set_resources,
|
||||
.enable_resources = &pci_dev_enable_resources,
|
||||
.init = &systemagent_init,
|
||||
.enable = &systemagent_enable,
|
||||
.ops_pci = &broadwell_pci_ops,
|
||||
};
|
||||
|
||||
static const unsigned short systemagent_ids[] = {
|
||||
0x0a04, /* Haswell ULT */
|
||||
0x1604, /* Broadwell-U/Y */
|
||||
0x1610, /* Broadwell-H Desktop */
|
||||
0x1614, /* Broadwell-H Mobile */
|
||||
0
|
||||
};
|
||||
|
||||
static const struct pci_driver systemagent_driver __pci_driver = {
|
||||
.ops = &systemagent_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.devices = systemagent_ids
|
||||
};
|
||||
Reference in New Issue
Block a user